Manufacturing method of image sensor

Abstract

The invention relates to the technical field of semiconductor integrated circuit manufacturing, in particular to a manufacturing method of an image sensor. Comprising the following steps: forming a first photoresist layer on a semiconductor substrate, forming a logic region injection window in the first photoresist layer, and exposing a logic region from the logic region injection window; performing ion implantation on the semiconductor substrate with the first photoresist layer, and forming source and drain electrodes of the logic region in the semiconductor substrate at two sides of the polysilicon gate of the logic region; a space fusion barrier layer is deposited in a blanket mode, the semiconductor substrate is covered with the space fusion barrier layer, and gaps between part of the polysilicon gates in the pixel area are filled with the space fusion barrier layer to form a fusion structure; forming a second photoresist layer on the semiconductor substrate, forming a pixel region injection window in the second photoresist layer, and exposing the pixel region from the pixel region injection window; and performing ion implantation on the semiconductor substrate with the second photoresist layer, and forming an ion implantation region in a gap between the polysilicon gates of the pixel region where the fusion structure is not formed.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing an image sensor. Background Art

[0002] Existing image sensors mainly include pixel arrays and peripheral circuits, among which the pixel array is the core part for realizing the photoelectric conversion function. The pixel array is composed of a certain number of pixel units, which usually include photosensitive areas and active areas. These active areas include a variety of MOS tubes, such as reset transistors, row selection transistors, signal amplifiers, control switch transistors and other MOS tubes. The photosensitive area, active area, and active area need to be isolated from each other.

[0003] Related technologies usually form an isolation sidewall fusion structure as an injection barrier by injection to achieve the effect of self-aligned injection. However, in new small-size processes, the sidewall fusion structure is no longer suitable for self-aligned injection. Summary of the invention

[0004] The present application provides a method for manufacturing an image sensor, which can solve the problem that the sidewall fusion structure is no longer suitable for self-aligned injection in a new small-size process.

[0005] In order to solve the technical problem in the background technology, the present application provides a method for manufacturing an image sensor, and the method for manufacturing an image sensor comprises the following steps:

[0006] Providing a semiconductor substrate, the semiconductor substrate comprising a pixel region and a logic region, a plurality of spaced pixel region polysilicon gates are formed on the semiconductor substrate of the pixel region, and a plurality of spaced logic region polysilicon gates are formed on the semiconductor substrate of the logic region;

[0007] Forming a first photoresist layer on the semiconductor substrate through a photolithography process, wherein a logic area injection window is formed in the first photoresist layer, and the logic area is exposed from the logic area injection window;

[0008] Performing ion implantation on the semiconductor substrate with the first photoresist layer to form source and drain electrodes of the logic region in the semiconductor substrate on both sides of the polysilicon gate of the logic region;

[0009] Blanket depositing a space fusion barrier layer, wherein the space fusion barrier layer covers the semiconductor substrate, and the space fusion barrier layer fills the gap between the polysilicon gates in a part of the pixel area to form a fusion structure;

[0010] Forming a second photoresist layer on the semiconductor substrate through a photolithography process, wherein a pixel region injection window is formed in the second photoresist layer, and the pixel region is exposed from the pixel region injection window;

[0011] Ion implantation is performed on the semiconductor substrate with the second photoresist layer to form an ion implantation region in the gap between the polysilicon gates in the pixel region where the fusion structure is not formed.

[0012] Optionally, the step of blanket depositing a space fusion barrier layer, the space fusion barrier layer covering the semiconductor substrate, and the space fusion barrier layer filling a gap between polysilicon gates in a part of the pixel area to form a fusion structure includes:

[0013] Determine a size of a target fusion interval, wherein the target fusion interval is an interval between polysilicon gates in a portion of pixel regions, and the interval between polysilicon gates in a portion of pixel regions is less than a first threshold;

[0014] A spatial fusion barrier layer having a thickness matching the size of the target fusion interval is deposited, so that the spatial fusion barrier layers are fused with each other at the target fusion interval to form the fusion structure.

[0015] Optionally, the thickness of the spatial fusion barrier layer is 200A to 800A.

[0016] Optionally, the spatial fusion barrier layer is a metal silicide barrier layer.

[0017] Optionally, the step of performing ion implantation on the semiconductor substrate with the second photoresist layer to form an ion implantation region in the gap between polysilicon gates in the pixel region where the fusion structure is not formed includes:

[0018] When ion implantation is performed on the semiconductor substrate with the second photoresist layer, the implanted ions pass through the injection window of the pixel area and are injected into the spatial fusion barrier layer of the pixel area, and the fusion structure of the spatial fusion barrier layer blocks the implanted ions from being implanted into the semiconductor substrate of the target fusion interval; the spatial fusion barrier layer in the non-target fusion interval is thinner, and the ions can still pass through the spatial fusion barrier layer in the non-target fusion interval and be injected into the semiconductor substrate of the non-target fusion interval to form the ion implantation area.

[0019] Optionally, in the step of providing a semiconductor substrate, wherein the semiconductor substrate includes a pixel area and a logic area, a plurality of pixel area polysilicon gates are formed on the semiconductor substrate of the pixel area, and a plurality of logic area polysilicon gates are formed on the semiconductor substrate of the logic area, the interval between two adjacent pixel area polysilicon gates includes a target fusion interval and a non-target fusion interval, and an interval having a size less than or equal to a first threshold is determined as a target fusion interval, and an interval having a size greater than the first threshold is determined as a non-target fusion interval.

[0020] The technical solution of the present application includes at least the following advantages: the present application implements ion implantation in the logic area before forming the space fusion barrier layer, and then implants ion implantation in the pixel area after the space fusion barrier layer, thereby realizing partitioned implantation in the logic area and the pixel area, so that the ion implantation process in the logic area and the ion implantation process in the pixel area can be adjusted in a partitioned manner, thereby avoiding the adverse effects of implanted elements such as Ge / C in the ion implantation in the logic area on the performance of the pixel area. When ion implantation is performed in the pixel area, the gap where the fusion structure is formed can block the ion implantation, and the implanted ions enter the substrate at the gap position where the fusion structure is not formed, and an ion implantation area is formed in the substrate in this area. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A flow chart of a method for manufacturing an image sensor provided by an embodiment of the present application is shown;

[0023] Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor substrate provided in step S1 is shown;

[0024] Figure 3 A schematic diagram of a cross-sectional structure of the device during step S3 is shown;

[0025] Figure 4 A schematic diagram of the cross-sectional structure of the device after step S4 is completed is shown;

[0026] Figure 5 A schematic diagram of a cross-sectional structure of the device during step S6 is shown;

[0027] Figure 6 A schematic diagram of a cross-sectional structure of a device after etching the spatial fusion barrier layer in other embodiments is shown. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0029] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0030] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0031] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0032] Figure 1 A flowchart of a method for manufacturing an image sensor provided by an embodiment of the present application is shown. Figure 1 It can be seen that the manufacturing method of the image sensor includes the following steps:

[0033] Step S1: providing a semiconductor substrate, the semiconductor substrate comprising a pixel region and a logic region, a plurality of spaced pixel region polysilicon gates are formed on the semiconductor substrate of the pixel region, and a plurality of spaced logic region polysilicon gates are formed on the semiconductor substrate of the logic region.

[0034] Figure 2 The schematic diagram of the cross-sectional structure of the semiconductor substrate provided in step S1 is shown. Figure 2 As can be seen in the figure, the semiconductor substrate 100 includes a pixel region 110 and a logic region 120. The pixel region 110 is used to form a photodiode of the image sensor, and the logic region 120 is used to form a logic device of the image sensor. A plurality of pixel region polysilicon gates 111 spaced apart are formed in the pixel region 110, and a plurality of logic region polysilicon gates 121 spaced apart are formed in the logic region 120.

[0035] Exemplarily, the interval between two adjacent pixel region polysilicon gates includes a target fusion interval and a non-target fusion interval, and the interval with a size less than or equal to a first threshold is determined as the target fusion interval, and the interval with a size greater than the first threshold is determined as the non-target fusion interval.

[0036] Step S2: forming a first photoresist layer on the semiconductor substrate through a photolithography process, wherein a logic area injection window is formed in the first photoresist layer, and the logic area is exposed from the logic area injection window.

[0037] Step S3: performing ion implantation on the semiconductor substrate with the first photoresist layer to form source and drain electrodes of the logic region in the semiconductor substrate on both sides of the polysilicon gate of the logic region.

[0038] Reference Figure 3 , which shows a schematic diagram of the device cross-sectional structure when step S3 is performed, from Figure 3 It can be seen that the pixel area 110 is covered by the first photoresist 200 , the logic area 120 is exposed from the logic area injection window 210 , and the injected ions pass through the logic area injection window 210 and are driven into the semiconductor substrate 100 of the logic area 120 .

[0039] Step S4: blanket depositing a space fusion barrier layer, wherein the space fusion barrier layer covers the semiconductor substrate, and the space fusion barrier layer fills the gaps between the polysilicon gates in a part of the pixel area to form a fusion structure.

[0040] Exemplarily, the deposition of the spatial fusion barrier layer may be a deposition process of a metal silicide barrier layer required to be performed in a subsequent process, thereby eliminating the need for additional process steps.

[0041] The implementation process of step S4 includes the following steps S41 and S42:

[0042] Step S41: determining the size of a target fusion interval, where the target fusion interval is the interval between polysilicon gates in a portion of pixel regions, and the interval between polysilicon gates in a portion of pixel regions is smaller than a first threshold.

[0043] Step S42: depositing a spatial fusion barrier layer with a thickness matching the size of the target fusion interval, so that the spatial fusion barrier layers fuse with each other at the target fusion interval to form the fusion structure.

[0044] Reference Figure 4 , which shows a schematic diagram of the cross-sectional structure of the device after step S4 is completed, from Figure 4It can be seen that the pixel area 110 and the logic area 120 are covered with a space fusion barrier layer 300, and the space fusion barrier layer 300 covers the pixel area polysilicon gate 111, the logic area polysilicon gate 121, the gap between two adjacent pixel area polysilicon gates 111, and the gap between two adjacent logic area polysilicon gates 121. Among them, the gap between the two adjacent pixel area polysilicon gates 111 is divided into a target fusion interval and a non-target fusion interval. The space fusion barrier layer 300 covered on the side wall of the polysilicon gate 111 of one pixel area and the space fusion barrier layer 300 covered on the side wall of the polysilicon gate 111 of another pixel area are fused at the target fusion interval to form a fusion structure 400. At the non-target fusion interval, the space fusion barrier layer 300 covered on the side wall of the polysilicon gate 111 of one pixel area is spaced from the space fusion barrier layer 300 covered on the side wall of the polysilicon gate 111 of another pixel area.

[0045] from Figure 4 It can be seen that for Figure 4 In the structure shown, the gap between two adjacent pixel region polysilicon gates 111 in region A is the target fusion gap, and the gap between two adjacent pixel region polysilicon gates 111 in region B is the non-target fusion gap. In region A, the spatial fusion barrier layer 300 covering the sidewall of the polysilicon gate 111 in one pixel region and the spatial fusion barrier layer 300 covering the sidewall of the polysilicon gate 111 in another pixel region are fused at the target fusion gap to form a fusion structure 400. In region B, the spatial fusion barrier layer 300 covering the sidewall of the polysilicon gate 111 in one pixel region and the spatial fusion barrier layer 300 covering the sidewall of the polysilicon gate 111 in another pixel region are spaced apart.

[0046] Step S5: forming a second photoresist layer on the semiconductor substrate through a photolithography process, wherein a pixel region injection window is formed in the second photoresist layer, and the pixel region is exposed from the pixel region injection window.

[0047] Step S6: performing ion implantation on the semiconductor substrate with the second photoresist layer to form an ion implantation region in the gap between the polysilicon gates in the pixel region where the fusion structure is not formed.

[0048] Exemplarily, the ion implantation region may be a super junction that plays an isolation role, or may be a source or drain of a pixel region.

[0049] When ion implantation is performed on the semiconductor substrate with the second photoresist layer, the implanted ions pass through the pixel region implantation window and are injected into the spatial fusion barrier layer of the pixel region, and the fusion structure of the spatial fusion barrier layer blocks the implanted ions from being implanted into the semiconductor substrate of the target fusion interval. The spatial fusion barrier layer in the non-target fusion interval is thinner, and the ions can still pass through the spatial fusion barrier layer in the non-target fusion interval and be injected into the semiconductor substrate of the non-target fusion interval to form the ion implantation area.

[0050] Reference Figure 5 , which shows a schematic diagram of the device cross-sectional structure when step S6 is performed, from Figure 5 It can be seen that when ion implantation is performed on the semiconductor substrate 100 with the second photoresist layer 500, the implanted ions pass through the pixel area implantation window 510 in the second photoresist layer 500 and penetrate into the non-target fusion interval, i.e., the semiconductor substrate 100 in area B to form the ion implantation area 600.

[0051] In other embodiments, after completing step S5 and before performing step S6, the space fusion barrier layer 300 exposed from the pixel region injection window may be etched to remove the space fusion barrier layer 300 covering the pixel region 110. Figure 6 , which shows a schematic diagram of a cross-sectional structure of a device after etching the space fusion barrier layer in other embodiments, from Figure 6 It can be seen that the remaining spatial fusion barrier layer 300 is filled in the target fusion interval, while the semiconductor substrate at the non-target fusion interval position is exposed, and the ions injected during the subsequent step S6 can better enter the semiconductor substrate at the non-target fusion interval position to form an ion implantation area.

[0052] This embodiment implements ion implantation in the logic area before forming the space fusion barrier layer, and then implants ion implantation in the pixel area after the space fusion barrier layer, so as to realize the partitioned implantation of the logic area and the pixel area, so that the ion implantation process of the logic area and the ion implantation process of the pixel area can be adjusted by partition, and the implanted elements such as Ge / C in the ion implantation of the logic area are prevented from having an adverse effect on the performance of the pixel area. When the pixel area is implanted with ions, the gap where the fusion structure is formed can block the ion implantation, and the implanted ions enter the substrate at the gap position where the fusion structure is not formed, and an ion implantation area is formed in the substrate in this area.

[0053] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.

Claims

1. A method for manufacturing an image sensor, characterized in that: The method for manufacturing the image sensor comprises the following steps: Providing a semiconductor substrate, the semiconductor substrate comprising a pixel region and a logic region, a plurality of spaced pixel region polysilicon gates are formed on the semiconductor substrate of the pixel region, and a plurality of spaced logic region polysilicon gates are formed on the semiconductor substrate of the logic region; Forming a first photoresist layer on the semiconductor substrate through a photolithography process, wherein a logic area injection window is formed in the first photoresist layer, and the logic area is exposed from the logic area injection window; Performing ion implantation on the semiconductor substrate with the first photoresist layer to form source and drain electrodes of the logic region in the semiconductor substrate on both sides of the polysilicon gate of the logic region; Blanket depositing a space fusion barrier layer, wherein the space fusion barrier layer covers the semiconductor substrate, and the space fusion barrier layer fills the gap between the polysilicon gates in a part of the pixel area to form a fusion structure; Forming a second photoresist layer on the semiconductor substrate through a photolithography process, wherein a pixel region injection window is formed in the second photoresist layer, and the pixel region is exposed from the pixel region injection window; Ion implantation is performed on the semiconductor substrate with the second photoresist layer to form an ion implantation region in the gap between the polysilicon gates in the pixel region where the fusion structure is not formed.

2. The method for manufacturing an image sensor according to claim 1, wherein: The step of blanket depositing a space fusion barrier layer, wherein the space fusion barrier layer covers the semiconductor substrate, and the space fusion barrier layer fills the gap between the polysilicon gates in a part of the pixel area to form a fusion structure, comprises: Determine a size of a target fusion interval, wherein the target fusion interval is an interval between polysilicon gates in a portion of pixel regions, and the interval between polysilicon gates in a portion of pixel regions is less than a first threshold; A spatial fusion barrier layer having a thickness matching the size of the target fusion interval is deposited, so that the spatial fusion barrier layers are fused with each other at the target fusion interval to form the fusion structure.

3. The method for manufacturing an image sensor according to claim 1, wherein: The thickness of the space fusion barrier layer is 200A to 800A.

4. The method for manufacturing an image sensor according to claim 1, wherein: The space fusion barrier layer is a metal silicide barrier layer.

5. The method for manufacturing an image sensor according to claim 1, wherein: The step of performing ion implantation on the semiconductor substrate with the second photoresist layer to form an ion implantation region in the gap between the polysilicon gates in the pixel region where the fusion structure is not formed comprises: When ion implantation is performed on the semiconductor substrate with the second photoresist layer, the implanted ions pass through the injection window of the pixel area and are injected into the spatial fusion barrier layer of the pixel area, and the fusion structure of the spatial fusion barrier layer blocks the implanted ions from being implanted into the semiconductor substrate of the target fusion interval; the spatial fusion barrier layer in the non-target fusion interval is thinner, and the ions can still pass through the spatial fusion barrier layer in the non-target fusion interval and be injected into the semiconductor substrate of the non-target fusion interval to form the ion implantation area.

6. The method for manufacturing an image sensor according to claim 1, wherein: In the step of providing a semiconductor substrate, the semiconductor substrate includes a pixel area and a logic area, a plurality of pixel area polysilicon gates are formed on the semiconductor substrate of the pixel area, and a plurality of logic area polysilicon gates are formed on the semiconductor substrate of the logic area, wherein the interval between two adjacent pixel area polysilicon gates includes a target fusion interval and a non-target fusion interval, an interval with a size less than or equal to a first threshold is determined as the target fusion interval, and an interval with a size greater than the first threshold is determined as the non-target fusion interval.

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