Display panel and manufacturing method thereof

Abstract

The invention provides a display panel and a manufacturing method thereof. The display panel includes: a base layer; a pixel defining film on the base layer and having a light emitting opening; a partition wall having a partition wall opening overlapping the light emitting opening and including a first partition wall layer on the pixel defining film and a second partition wall layer on the first partition wall layer; a light emitting element at least partially located in the partition wall opening and including an anode, an intermediate layer, and a cathode in contact with the partition wall; and a sacrificial pattern between the first partition wall layer and the second partition wall layer and having sacrificial openings overlapping the partition wall openings.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0128803 filed in the Korean Intellectual Property Office on September 26, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display panel having improved display quality and a method for manufacturing the display panel. Background Art

[0004] Display devices (e.g., televisions, monitors, smart phones, and tablet computers) include display panels for displaying images to users. Various suitable panels (e.g., liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels) are being developed as display panels.

[0005] The organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. The light emitting pattern may be separated for each light emitting region, and the cathode may provide a common voltage to each light emitting region.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] Embodiments of the present disclosure may reside in a display panel having improved display quality among display panels in which a light emitting element is formed without using a metal mask, and a method for manufacturing the display panel.

[0008] According to one or more embodiments of the present disclosure, a display panel includes: a base layer; a pixel defining film on the base layer and having a light-emitting opening; a partition wall having a partition wall opening overlapping the light-emitting opening and including a first partition wall layer on the pixel defining film and a second partition wall layer on the first partition wall layer; a light-emitting element at least partially located in the partition wall opening and including an anode, an intermediate layer and a cathode, the cathode being in contact with the partition wall; and a sacrificial pattern between the first partition wall layer and the second partition wall layer and having a sacrificial opening overlapping the partition wall opening.

[0009] In embodiments, the sacrificial pattern may have an undercut shape with respect to the partition wall.

[0010] In an embodiment, the first partition wall layer of the partition wall may have an undercut shape with respect to the second partition wall layer.

[0011] In an embodiment, the first partition wall layer may include a first side surface of a first region defining a partition wall opening, the sacrificial pattern may include a second side surface of a second region defining a sacrificial opening, the second partition wall layer may include a third side surface of a third region defining a partition wall opening, and the first region to the third region may be integrated with each other in the thickness direction of the base layer.

[0012] In an embodiment, the second side surface of the sacrificial pattern may be more recessed than the first side surface of the first partition wall layer and the third side surface of the second partition wall layer in a direction away from the partition wall opening.

[0013] In an embodiment, the second side surface of the sacrificial pattern may overlap the first partition wall layer and the second partition wall layer in a plan view.

[0014] In an embodiment, a width of the second region in the first direction may be greater than a width of the first region in the first direction and a width of the third region in the first direction.

[0015] In an embodiment, the display panel may further include a lower sacrificial pattern between the anode and the pixel defining film and having a lower sacrificial opening overlapping the light emitting opening.

[0016] In an embodiment, the pixel defining film may include: a first pixel defining film, which is on the base layer and includes a first inner surface of a first pixel opening that defines a light-emitting opening; and a second pixel defining film, which is on the first pixel defining film and includes a second inner surface of a second pixel opening that defines a light-emitting opening.

[0017] In an embodiment, a width of the first pixel opening in the first direction may be equal to or smaller than a width of the second pixel opening in the first direction.

[0018] In embodiments, the cathode may be spaced apart from the sacrificial pattern.

[0019] According to one or more embodiments of the present disclosure, a display panel includes: a base layer; a pixel defining film on the base layer and having a light-emitting opening; a partition wall having a partition wall opening overlapping the light-emitting opening and including a first partition wall layer on the pixel defining film and a second partition wall layer on the first partition wall layer; a light-emitting element at least partially located in the partition wall opening and including an anode, an intermediate layer and a cathode, the cathode being in contact with the partition wall; a sacrificial pattern between the first partition wall layer and the second partition wall layer and including a transparent conductive oxide; and a lower sacrificial pattern between the anode and the pixel defining film and including a transparent conductive oxide.

[0020] In embodiments, the lower sacrificial pattern may have a lower sacrificial opening overlapping the light emitting opening, and the sacrificial pattern may have a sacrificial opening overlapping the partition wall opening.

[0021] In embodiments, the sacrificial pattern may have an undercut shape with respect to the partition wall.

[0022] In an embodiment, the first partition wall layer may include a first side surface defining a first region of a partition wall opening, the sacrificial pattern may have a sacrificial opening overlapping the partition wall opening and include a second side surface defining a second region of the sacrificial opening, and the second partition wall layer may include a third side surface defining a third region of the partition wall opening. The first region to the third region may be integrated with each other in a thickness direction of the base layer, and the second side surface of the sacrificial pattern may be more recessed than the first side surface of the first partition wall layer and the third side surface of the second partition wall layer in a direction away from the partition wall opening.

[0023] In an embodiment, the second side surface of the sacrificial pattern may overlap the first partition wall layer and the second partition wall layer in a plan view.

[0024] In embodiments, the cathode may be spaced apart from the sacrificial pattern.

[0025] According to one or more embodiments of the present disclosure, a method for manufacturing a display panel includes: providing a preliminary display panel, the preliminary display panel including a base layer and an anode, a lower sacrificial layer and a first preliminary pixel defining film arranged on the base layer; forming a first pixel defining film by etching the first preliminary pixel defining film; sequentially depositing a second preliminary pixel defining film, a first preliminary partition wall layer, a sacrificial layer and a second preliminary partition wall layer on the first pixel defining film; and forming a second pixel defining film, a partition wall and a sacrificial pattern by etching the second preliminary pixel defining film, the first preliminary partition wall layer, the sacrificial layer and the second preliminary partition wall layer.

[0026] In an embodiment, forming a second pixel defining film, a partition wall, and a sacrificial pattern may include: etching a second preliminary partition wall layer; etching a sacrificial layer; etching a first preliminary partition wall layer; forming a partition wall having a partition wall opening by etching the first preliminary partition wall layer and the second preliminary partition wall layer; forming a second pixel defining film by etching the second preliminary pixel defining film; and forming a sacrificial pattern by etching the sacrificial layer.

[0027] In embodiments, forming the sacrificial pattern by etching the sacrificial layer may include forming a lower sacrificial pattern by etching the lower sacrificial layer.

[0028] In an embodiment, the method may further include: forming a light emitting pattern in the partition wall opening; forming a cathode in the partition wall opening contacting the partition wall and spaced apart from the sacrificial pattern; and forming an inorganic lower encapsulation pattern contacting the sacrificial pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of exemplary, non-limiting embodiments with reference to the accompanying drawings, in which:

[0030] Figure 1A is a perspective view of a display device according to an embodiment of the present disclosure;

[0031] Figure 1B is an exploded perspective view of a display device according to an embodiment of the present disclosure;

[0032] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present disclosure;

[0033] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure;

[0034] Figure 4 is a partially enlarged plan view of a display area of ​​a display panel according to an embodiment of the present disclosure;

[0035] Figure 5 According to an embodiment of the present disclosure, Figure 3 A cross-sectional view of the display panel taken along line II' in FIG.

[0036] FIG. 6A to FIG. 6L are cross-sectional views illustrating some operations of a method for manufacturing a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always represent the same elements. However, the present disclosure can be implemented in various different forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete and will fully convey the aspects and features of the present disclosure to those skilled in the art. Therefore, processes, elements and techniques that are not necessary for a person of ordinary skill in the art to fully understand the aspects and features of the present disclosure may not be described. Unless otherwise stated, the same reference numerals throughout the attached drawings and the written description represent the same elements, and therefore, redundant descriptions thereof may not be repeated.

[0038] When a certain embodiment can be implemented differently, the process described as being performed in a specific order can be performed in an order different from the described order. For example, two processes described in succession can be performed simultaneously or substantially simultaneously, or can be performed in an order opposite to the described order.

[0039] In addition, as will be understood by those of ordinary skill in the art, considering the entirety of the present disclosure, each suitable feature of the various embodiments of the present disclosure may be partially or fully combined with each other and may be technically interlocked and operated in various suitable manners, and each embodiment may be implemented independently of each other or in combination with each other in any suitable manner, unless otherwise specified or implied.

[0040] In the accompanying drawings, for the sake of clarity, the relative sizes, thicknesses and ratios of elements, layers and regions may be exaggerated and / or simplified. Spatially relative terms, such as "below", "below", "lower", "below", "above", "upper", etc., may be used in this article for ease of explanation to describe the relationship between an element or feature and another (additional) element or feature as shown in the figure. It will be understood that, in addition to the orientations shown in the accompanying drawings, spatially relative terms are intended to also include different orientations of the device in use or in operation. For example, if the device in the figure is flipped, the element or feature described as "below" or "below" or "below" other elements or features will then be oriented to "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used in this article should be interpreted accordingly.

[0041] In the accompanying drawings, the first direction, the second direction, and the third direction are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the first direction, the second direction, and the third direction can be perpendicular or substantially perpendicular to each other, or can represent different directions that are not perpendicular to each other.

[0042] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the spirit and scope of the present disclosure, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part.

[0043] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, connected to, or coupled to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, it may be directly electrically connected to the other layer, region, or element, and / or may be indirectly electrically connected to the other layer, region, or element with one or more intervening layers, regions, or elements therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0044] The terms used herein are for the purpose of describing a particular embodiment, and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "one" and "an" are intended to also include plural meanings. It will also be understood that the terms "include", "comprise", "include", "contain", "have", "have" and "contain" when used in this specification specify the existence of the features, wholes, steps, operations, elements and / or components described, but do not exclude the existence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the statement "A and / or B" means A, B, or A and B. Statements such as "at least one of ..." modify the entire column of elements when used with a column of elements, and do not modify the individual elements in the column. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0045] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent variations in measured or calculated values ​​that one of ordinary skill in the art would recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilizing," "utilizing," and "utilized," respectively.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0047] Figure 1A is a perspective view of a display device DD according to an embodiment of the present disclosure. Figure 1B is an exploded perspective view of a display device DD according to an embodiment of the present disclosure.

[0048] In an embodiment, the display device DD may be a large electronic device, such as a television, a monitor, or a billboard. In an embodiment, the display device DD may be a small and / or medium-sized electronic device, such as a personal computer, a notebook computer, a dedicated digital terminal, a car navigation unit, a game console, a smart phone, a tablet computer, or a camera. However, the present disclosure is not limited thereto, and the display device DD may be used for other suitable display devices. Figure 1A and Figure 1B It is shown that the display device DD is a smartphone as a representative example.

[0049] Reference Figure 1A and Figure 1B , the display device DD may display an image IM toward a third direction DR3 on a display surface FS that is parallel or substantially parallel to each of the first direction DR1 and the second direction DR2. The image IM may include a static image as well as a dynamic image. Figure 1A A clock window and an icon are shown as representative examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0050] In the present embodiment, the front surface (e.g., upper surface) and the rear surface (e.g., lower surface) of each member are defined based on the direction in which the image IM is displayed. The front surface and the rear surface are opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to or substantially parallel to the third direction DR3. The directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be modified differently to other suitable directions. In the present specification, "on a plane" and "in a plan view" may mean when observed in the third direction DR3.

[0051] The display device DD may include a window WP, a display module (eg, a display or a touch display) DM, and a housing HAU. The window WP and the housing HAU may be connected to (eg, coupled to or attached to) each other to constitute the appearance of the display device DD.

[0052] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmissive area TA and a frame area BZA. The transmissive area TA may be an optically transparent area. For example, the transmissive area TA may be an area having a visible light transmittance of 90% or more.

[0053] The frame area BZA may be an area having a relatively lower transmittance than the transmittance of the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and may surround the transmission area TA (e.g., around its periphery). However, the present disclosure is not limited thereto, and the frame area BZA of the window WP may be omitted as needed or desired. The window WP may include at least any one of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, but the present disclosure is not limited to any particular embodiment.

[0054] The display module DM may be disposed on a lower portion (e.g., lower surface) of the window WP. The display module DM may be a structure that generates or substantially generates an image IM. The image IM generated by the display module DM is displayed on a display surface IS of the display module DM and may be viewed by an external user through the transmissive area TA.

[0055] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area activated in response to an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA (e.g., around its periphery). The non-display area NDA may be an area overlapping with the bezel area BZA and may not be seen from the outside.

[0056] The housing HAU may be connected to (eg, coupled to or attached to) the window WP. The housing HAU may be connected to (eg, coupled to or attached to) the window WP to provide an internal space (eg, a predetermined internal space). The display module DM may be accommodated in the internal space.

[0057] The housing HAU may include a suitable material with relatively high rigidity. For example, the housing HAU may include a plurality of frames and / or plates made of glass, plastic, or metal, or a suitable combination thereof. The housing HAU may stably protect the configuration and structure of the display device DD contained in the internal space from external impact.

[0058] Figure 2 is a cross-sectional view of a display module DM according to an embodiment of the present disclosure.

[0059] Reference Figure 2 , the display module DM may include a display panel DP and an input sensor INS. The display device DD according to an embodiment of the present disclosure (eg, see Figure 1A ) may further include a protection member disposed on a lower surface of the display panel DP, or an anti-reflection member and / or a window member disposed on an upper surface of the input sensor INS.

[0060] The display panel DP may be a light-emitting display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP may be described in more detail in the context of an organic light-emitting display panel.

[0061] The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE, wherein the circuit element layer DP-CL is disposed on the base layer BL. The input sensor INS may be directly disposed on the thin film encapsulation layer TFE. In this specification, when "configuration A is directly disposed on configuration B", no adhesive layer is disposed between configuration A and configuration B.

[0062] The base layer BL may include at least one plastic film. The base layer BL may be a flexible substrate, and may include a plastic substrate, a glass substrate, a metal substrate, an organic / inorganic composite material substrate, or the like. Figure 1B Described is a display area DA and a non-display area NDA.

[0063] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, pixel drivers, etc.

[0064] The display element layer DP-OLED may include partition walls and a light emitting element. The light emitting element may include an anode, an intermediate layer and a cathode.

[0065] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be provided to improve optical efficiency, and others of which may be provided to protect the organic light emitting diode.

[0066] The input sensor INS acquires coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single-layer or multi-layer conductive layer. In addition, the input sensor INS may be a single-layer or multi-layer insulating layer. The input sensor INS may detect the external input in a capacitive manner. However, the present disclosure is not limited thereto. For example, in an embodiment, the input sensor INS may detect the external input in an electromagnetic induction method or a pressure detection method. However, in another embodiment of the present disclosure, the input sensor INS may be omitted as needed or desired.

[0067] Figure 3 is a plan view of a display panel DP according to an embodiment of the present disclosure.

[0068] Reference Figure 3 , a display area DA and a non-display area NDA surrounding the display area DA may be defined in the display panel DP. The display panel DP may include pixels PX and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a drive circuit GDC and a pad portion PLD. The display area DA and the non-display area NDA may be distinguished from each other based on whether the pixel PX is set. The pixel PX may be set in the display area DA. The drive circuit GDC and the pad portion PLD may be set in the non-display area NDA.

[0069] The pixels PX may be arranged along the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged along the second direction DR2 and a plurality of pixel columns extending in the second direction DR2 and arranged along the first direction DR1.

[0070] The signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. The gate line GL may be connected to a corresponding pixel in the pixels PX, and the data line DL may be connected to a corresponding pixel in the pixels PX, respectively. The power line PL may be electrically connected to the pixel PX. The control signal line CSL may be connected to the driving circuit GDC to provide a control signal to the driving circuit GDC.

[0071] The driving circuit GDC may include a gate driver. The gate driver may generate a gate signal and may sequentially output the generated gate signal to the gate lines GL. The gate driver may further output another control signal to the pixel driver.

[0072] The pad portion PLD may be a portion to which the flexible circuit board is connected. The pad portion PLD may include a pixel pad D-PD, and the pixel pad D-PD may be a pad for connecting the flexible circuit board to the display panel DP. The pixel pads D-PD may be connected to corresponding signal lines in the signal lines SGL, respectively. The pixel pads D-PD may be connected to corresponding pixels PX through the signal lines SGL, respectively. In addition, one of the pixel pads D-PD may be connected to the drive circuit GDC.

[0073] In addition, the pad portion PLD may further include an input pad. The input pad may be used to connect the flexible circuit board to the input sensor INS (see, for example, Figure 2 However, the present disclosure is not limited thereto, and the input pad may be provided at the input sensor INS (eg, see Figure 2 ) to connect the pixel pad D-PD to a separate circuit board. As another example, the input sensor INS may be omitted as needed or desired (e.g., see Figure 2 ), and the input pads may be omitted as needed or desired.

[0074] Figure 4 is a partially enlarged plan view of a display area DA of a display panel DP according to an embodiment of the present disclosure. Figure 4 The display surface IS of the display module DM is shown (see, for example, Figure 1B ) is a plane of the display module DM observed on the upper side, and shows the arrangement of the light emitting areas PXA-R, PXA-G and PXA-B.

[0075] Reference Figure 4 , the display area DA may include a first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B and a peripheral area NPXA surrounding the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B (e.g., around the periphery thereof). The first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may respectively correspond to areas from which light provided from the light emitting element is emitted. The first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may be emitted to the display module DM (e.g., see Figure 2 )The colors of external light are used to distinguish them from each other.

[0076] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may respectively provide first to third color lights having different colors from each other. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, the present disclosure is not limited thereto, and examples of the first to third color lights are not limited to the above examples.

[0077] The first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be defined as regions in which the upper surface of the anode is exposed through the light-emitting opening described in more detail below, respectively. The peripheral region NPXA may define (e.g., may be provided with) a boundary of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B, and may prevent or substantially prevent color mixing between the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B.

[0078] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may each be provided in plural numbers, and may each be repeatedly provided in the display area DA in a suitable arrangement (e.g., a predetermined arrangement). For example, the first light emitting region PXA-R and the third light emitting region PXA-B may be alternately arranged along the first direction DR1 to constitute a "first group". The second light emitting region PXA-G may be arranged along the first direction DR1 to constitute a "second group". The "first group" and the "second group" may each be provided in plural numbers, and the "first group" and the "second group" may be alternately arranged along the second direction DR2.

[0079] One second light emitting region PXA-G may be disposed to be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0080] Figure 4 An exemplary arrangement form of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B is shown, but the present disclosure is not limited thereto, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be arranged in various suitable forms. Figure 4 As shown in FIG. 1 , the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have an RGBG arrangement form (eg, Arrangement form, is an officially registered trademark of Samsung Display Co., Ltd.). As another example, the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may have a stripe arrangement form or a Diamond Pixel arrangement form. TM Arrangement form.

[0081] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have various suitable shapes on a plane (e.g., in a plan view). For example, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have a suitable shape, such as a polygon, a circle, or an ellipse. Figure 4 The first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (eg, a diamond shape) and the second light emitting region PXA-G having an octagonal shape are illustrated as representative examples.

[0082] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have the same or substantially the same shape as each other on a plane (eg, in a plan view), or at least a portion thereof may have a shape different from that of the other light emitting regions. Figure 4 As representative examples, first and third light emitting regions PXA-R and PXA-B having the same or substantially the same shapes as each other and a second light emitting region PXA-G having a shape different from those of the first and third light emitting regions PXA-R and PXA-B are shown.

[0083] At least a portion of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may have an area different from other portions on a plane (e.g., in a plan view). In an embodiment, the first light-emitting region PXA-R for emitting red light may have an area larger than that of the second light-emitting region PXA-G for emitting green light, and may have an area smaller than that of the third light-emitting region PXA-B for emitting blue light. However, the present disclosure is not limited thereto, and the relative sizes of the areas of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be determined according to the display module DM (e.g., see Figure 2 ) is changed differently depending on the design of the light source, depending on the color of the light emitted thereby. In addition, the present disclosure is not limited thereto, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have the same or substantially the same area as each other on a plane (e.g., in a plan view).

[0084] The display module DM according to the present disclosure (for example, see Figure 2 The shapes, areas, and arrangements of the first light emitting regions PXA-R, the second light emitting regions PXA-G, and the third light emitting regions PXA-B of the display module DM may be variously designed according to the color of light emitted therefrom or the size or configuration of the display module DM, and therefore, the present disclosure is not limited to Figure 4 Those shown in .

[0085] Figure 5 According to an embodiment of the present disclosure, Figure 3 The cross-sectional view of the display panel DP taken along the line II' in FIG. Figure 2 Describe in more detail Figure 5 , and redundant descriptions of components denoted by the same reference numerals or symbols therebetween may not be repeated. Figure 5 The display area DA is shown in FIG. Figure 4 ) is enlarged, and Figure 5 The light emitting area PXA in may correspond to Figure 4 Any one of the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B.

[0086] Reference Figure 5 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0087] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers may be formed by coating, deposition, or the like. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching. By using this method, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed.

[0088] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, first, second, third, fourth, and fifth insulating layers 10, 20, 30, 40, and 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0089] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0090] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, but the present disclosure is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. Figure 5 Some semiconductor patterns are shown as representative examples, and the semiconductor patterns may be further provided in a plurality of light emitting regions PXA-R, PXA-G, and PXA-B (eg, see Figure 4 ). The semiconductor pattern may be arranged according to appropriate rules (e.g., specific or predetermined rules) throughout the plurality of light emitting regions PXA-R, PXA-G, and PXA-B. The semiconductor pattern may have different electrical characteristics depending on whether it is doped. The semiconductor pattern may include a first region having a larger doping concentration and a second region having a smaller doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant. The N-type transistor may include a first region doped with an N-type dopant.

[0091] The first region has a conductive property greater than that of the second region and is substantially used as an electrode or a signal line. The second region may substantially correspond to an active region (e.g., a channel) of a transistor. In other words, a portion of the semiconductor pattern may be an active region of a transistor, another portion of the semiconductor may be a source or a drain, and another portion of the semiconductor may be a conductive region.

[0092] The source S, the active region A, and the drain D of the transistor TR1 may be formed of a semiconductor pattern. Figure 5 A signal transmission region SCL formed of a semiconductor pattern is partially shown in FIG. Although not separately shown, the signal transmission region SCL may be connected to the drain D of the transistor TR1 on a plane (eg, in a plan view).

[0093] The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may be disposed on the buffer layer BFL. The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may be an inorganic layer or an organic layer.

[0094] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active region A, and the drain D of the transistor TR1 and the signal transmission region SCL disposed on the buffer layer BFL. The gate G of the transistor TR1 may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the electrode EE.

[0095] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 penetrating the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0096] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 penetrating the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0097] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a lower sacrificial pattern SP1, a capping pattern CP, a pixel defining film PDL, a partition wall PW, an upper sacrificial pattern SP2, and a dummy pattern DMP. In the present disclosure, the upper sacrificial pattern SP2 may be referred to as a sacrificial pattern SP2.

[0098] The light emitting element ED may include an anode AE ​​(eg, a first electrode), a light emitting pattern EP, and a cathode CE (eg, a second electrode). At least a portion of the light emitting element ED may be disposed in the partition wall opening OP-P.

[0099] The anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 through a contact hole CNT-3 penetrating the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transmission area SCL through the first connection electrode CNE1 and the second connection electrode CNE2 to be electrically connected to the corresponding circuit element. The anode AE ​​may include a single-layer or multi-layer structure. The anode AE ​​may include a plurality of layers containing ITO or silver (Ag). For example, the anode AE ​​may include a layer containing ITO (hereinafter referred to as a lower ITO layer), a layer containing silver (Ag) disposed on the lower ITO layer (hereinafter referred to as a silver (Ag) layer), and a layer containing ITO disposed on the silver (Ag) layer (hereinafter referred to as an upper ITO layer).

[0100] The lower sacrificial pattern SP1 may be disposed between the anode AE ​​and the pixel defining film PDL. The lower sacrificial pattern SP1 may have a lower sacrificial opening OP-S1 partially exposing the upper surface of the anode AE. The lower sacrificial opening OP-S1 may overlap with a light emitting opening OP-E described in more detail below.

[0101] The lower sacrificial pattern SP1 may include a transparent conductive oxide. For example, the lower sacrificial pattern SP1 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), aluminum zinc oxide, or zinc indium tin oxide (ZITO). In an embodiment, the lower sacrificial pattern SP1 may include (for example, may be) zinc indium tin oxide (ZITO) in which 3at% to 14at% of tin (Sn) is doped. The lower sacrificial pattern SP1 may have to Thickness.

[0102] The pixel defining film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The pixel defining film PDL may have a light emitting opening OP-E. The light emitting opening OP-E may correspond to the anode AE, and the pixel defining film PDL may at least partially expose the anode AE ​​through the light emitting opening OP-E.

[0103] In addition, the light emitting opening OP-E may correspond to the lower sacrificial opening OP-S1 of the lower sacrificial pattern SP1. According to the present embodiment, the upper surface of the anode AE ​​may be spaced apart from the pixel defining film PDL in cross section with the lower sacrificial pattern SP1 therebetween. Therefore, in the process of forming the light emitting opening OP-E, the anode AE ​​may be protected from damage.

[0104] On a plane (e.g., in a plan view), the light emitting opening OP-E may have an area smaller than that of the lower sacrificial opening OP-S1. In other words, the inner side surface of the pixel defining film PDL having the light emitting opening OP-E may be closer to the center of the anode AE ​​than the inner side surface of the lower sacrificial pattern SP1 having the lower sacrificial opening OP-S1. However, the present disclosure is not limited thereto, and the inner side surface of the lower sacrificial pattern SP1 having the lower sacrificial opening OP-S1 may be aligned or substantially aligned with the inner side surface of the pixel defining film PDL having the light emitting opening OP-E. In this case, the light emitting area PXA may be an area of ​​the anode AE ​​exposed from the lower sacrificial opening OP-S1 corresponding thereto.

[0105] The pixel defining film PDL may include a first pixel defining film PDL1 and a second pixel defining film PDL2. The light emitting opening OP-E may include a first pixel opening OP-PDL1 and a second pixel opening OP-PDL2.

[0106] The first pixel defining film PDL1 may be disposed on the circuit element layer DP-CL and may include a first inner side surface S1-PDL of the first pixel opening OP-PDL1 defining the light emitting opening OP-E (eg, see Figure 6H). The second pixel defining film PDL2 may be disposed on the first pixel defining film PDL1, and may include a second inner side surface S2-PDL of the second pixel opening OP-PDL2 defining the light emitting opening OP-E (eg, see Figure 6H ). The width of the first pixel opening OP-PDL1 in the first direction DR1 may be equal to or smaller than the width of the second pixel opening OP-PDL2 in the first direction DR1. However, the present disclosure is not limited thereto.

[0107] The first pixel defining film PDL1 and the second pixel defining film PDL2 may include an inorganic insulating material. For example, the first pixel defining film PDL1 and the second pixel defining film PDL2 may include silicon nitride (SiN x ). The first pixel defining film PDL1 and the second pixel defining film PDL2 may be disposed between the anode AE ​​and the partition wall PW to prevent the anode AE ​​and the partition wall PW from being electrically connected to each other. In addition, the second pixel defining film PDL2 may be used to protect the anode AE ​​and the lower sacrificial pattern SP1 during the formation of the light emitting opening OP-E and the lower sacrificial opening OP-S1. This will be described in more detail below.

[0108] The light emitting pattern EP may be disposed on the anode AE. The light emitting pattern EP may include a light emitting layer including a light emitting material. The light emitting pattern EP may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the anode AE ​​and the light emitting layer, and may further include an electron transport layer (ETL) and an electron injection layer (EIL) disposed on the light emitting layer. The light emitting pattern EP may be referred to as an "organic layer" or an "intermediate layer".

[0109] The light emitting pattern EP may be patterned by a tip portion defined in the partition wall PW. The light emitting pattern EP may be disposed inside the lower sacrificial opening OP-S1, the light emitting opening OP-E, and the partition wall opening OP-P. The light emitting pattern EP may partially cover the upper surface of the pixel defining film PDL exposed from the partition wall opening OP-P.

[0110] The cathode CE may be disposed on the light emitting pattern EP. The cathode CE may be patterned by a tip portion defined in the partition wall PW. At least a portion of the cathode CE may be disposed in the partition wall opening OP-P and may contact the partition wall PW in the partition wall opening OP-P. The cathode CE may be spaced apart from the upper sacrificial pattern SP2 to be described in more detail below.

[0111] The cathode CE may have a conductive property. The cathode CE may be formed of various suitable materials, such as metal, transparent conductive oxide (TCO) or conductive polymer material, as long as it has a conductive property. For example, the cathode CE may include silver (Ag), magnesium (Mg), lead (Pb), copper (Cu) or a suitable compound thereof.

[0112] The capping pattern CP may be disposed in the partition wall opening OP-P and may be disposed on the cathode CE. The capping pattern CP may be patterned by a tip portion formed in the partition wall PW. Figure 5 The capping pattern CP is shown not to contact the first side surface S1 of the first partition wall layer L1, but the present disclosure is not limited thereto. For example, the capping pattern CP may be formed to contact the first side surface S1 of the first partition wall layer L1. According to another embodiment of the present disclosure, the capping pattern CP may be omitted as needed or desired.

[0113] The partition wall PW may be disposed on the pixel definition film PDL. The partition wall PW may have a partition wall opening OP-P. The partition wall opening OP-P may correspond to the light emitting opening OP-E and may at least partially expose the anode AE. The partition wall PW may have an undercut shape in cross section. The partition wall PW may include a plurality of layers stacked sequentially, and at least one of the plurality of layers may be more recessed than the other layers.

[0114] The partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be disposed on the pixel definition film PDL, and the second partition wall layer L2 may be disposed on the first partition wall layer L1. Figure 5 As shown in FIG. 8 , the first partition wall layer L1 may have a thickness greater than that of the second partition wall layer L2 , but the present disclosure is not limited thereto.

[0115] The first partition wall layer L1 may be relatively more recessed than the second partition wall layer L2 relative to the light emitting region PXA. The first partition wall layer L1 may have an undercut shape relative to the second partition wall layer L2. A portion of the second partition wall layer L2 protruding from the first partition wall layer L1 toward the light emitting region PXA may be defined as a tip portion of the partition wall PW.

[0116] The first partition wall layer L1 and the second partition wall layer L2 may each include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a suitable combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or a suitable alloy thereof. The transparent conductive oxide (TCO) may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0117] The partition wall PW may receive the second driving voltage, and thus, the cathode CE may be electrically connected to the partition wall PW to receive the second driving voltage.

[0118] The upper sacrificial pattern SP2 may be disposed between the first partition wall layer L1 and the second partition wall layer L2 in cross section. The upper sacrificial pattern SP2 may include a transparent conductive oxide. For example, the upper sacrificial pattern SP2 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), aluminum zinc oxide, or zinc indium tin oxide (ZITO). In an embodiment, the upper sacrificial pattern SP2 may include (for example, may be) zinc indium tin oxide (ZITO) doped with 15 at % to 22 at % of tin (Sn). The upper sacrificial pattern SP2 may have to Thickness.

[0119] The upper sacrificial pattern SP2 may have an upper sacrificial opening OP-S2 overlapping the partition wall opening OP-P. The upper sacrificial opening OP-S2 may be referred to as a sacrificial opening OP-S2. The upper sacrificial pattern SP2 may be relatively more recessed than the partition wall PW relative to the light emitting area PXA. The upper sacrificial pattern SP2 may have an undercut shape relative to the partition wall PW. For example, the upper sacrificial pattern SP2 may have an undercut shape relative to the first partition wall layer L1 and the second partition wall layer L2.

[0120] According to one or more embodiments of the present disclosure, since the upper sacrificial pattern SP2 is formed between the first partition wall layer L1 and the second partition wall layer L2, a path through which impurities introduced from the side surface of the inorganic lower encapsulation pattern LIL can be extended. In addition, since the upper sacrificial pattern SP2 has an undercut shape relative to the first partition wall layer L1 and the second partition wall layer L2, the cathode CE can be spaced apart from the upper sacrificial pattern SP2. Therefore, the upper sacrificial pattern SP2 including a transparent conductive oxide can directly contact the inorganic lower encapsulation pattern LIL. Because the bonding force between the inorganic lower encapsulation pattern LIL and the partition wall PW is increased, pixel defects (e.g., dark spots, pixel shrinkage, etc.) can be reduced or removed.

[0121] The partition wall opening OP-P and the upper sacrificial opening OP-S2 may include a first area A1, a second area A2, and a third area A3. The partition wall opening OP-P may include the first area A1 and the third area A3, and the upper sacrificial opening OP-S2 may include the second area A2. The first area A1, the second area A2, and the third area A3 may be formed integrally with each other in a thickness direction (e.g., a third direction DR3) of the base layer BL. The width of the second area A2 in the first direction DR1 may be greater than the width of the first area A1 in the first direction DR1 and the width of the third area A3 in the first direction DR1.

[0122] The first partition wall layer L1 may include a first side surface S1 defining a first area A1. The upper sacrificial pattern SP2 may include a second side surface S2 defining a second area A2. The second partition wall layer L2 may include a third side surface S3 defining a third area A3. The second side surface S2 of the upper sacrificial pattern SP2 may be more recessed than the first side surface S1 of the first partition wall layer L1 and the third side surface S3 of the second partition wall layer L2 in a direction away from the partition wall opening OP-P. On a plane (e.g., in a plan view), the second side surface S2 of the upper sacrificial pattern SP2 may overlap with the first partition wall layer L1 and the second partition wall layer L2.

[0123] The dummy pattern DMP may be disposed on the partition wall PW. The dummy pattern DMP may include a first dummy pattern D1, a second dummy pattern D2, and a third dummy pattern D3. The first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may be sequentially stacked on the upper surface of the second partition wall layer L2 of the partition wall PW along the third direction DR3.

[0124] The first dummy pattern D1 may include an organic material. For example, the first dummy pattern D1 may include the same material as that of the light emitting pattern EP. The first dummy pattern D1 may be formed concurrently or substantially simultaneously with the light emitting pattern EP through one process, and may be formed separately from the light emitting pattern EP due to the undercut shape of the partition wall PW.

[0125] The second dummy pattern D2 may include a conductive material. For example, the second dummy pattern D2 may include the same material as that of the cathode CE. The second dummy pattern D2 may be formed concurrently or substantially simultaneously with the cathode CE through one process, and may be formed separately from the cathode CE due to the undercut shape of the partition wall PW.

[0126] The third dummy pattern D3 may include a conductive material. For example, the third dummy pattern D3 may include the same material as that of the capping pattern CP. The third dummy pattern D3 may be formed concurrently or substantially simultaneously with the capping pattern CP through one process, and may be formed separately from the capping pattern CP due to the undercut shape of the partition wall PW.

[0127] The dummy pattern DMP may have a dummy opening OP-D. The dummy opening OP-D may correspond to the light emitting opening OP-E. On a plane (e.g., in a plan view), the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may each have a closed line shape surrounding the light emitting area PXA (e.g., around its periphery).

[0128] Figure 5 The first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 are shown to cover the third side surface S3 of the second partition wall layer L2, but the present disclosure is not limited thereto. For example, the inner side surfaces of the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may be formed to be aligned or substantially aligned with the third side surface S3 of the second partition wall layer L2. In this case, the dummy opening OP-D may include a first area defined by the inner side surface of the first dummy pattern D1, a second area defined by the inner side surface of the second dummy pattern D2, and a third area defined by the inner side surface of the third dummy pattern D3.

[0129] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include an inorganic lower encapsulation pattern LIL, an organic encapsulation film OL, and an inorganic upper encapsulation film UIL.

[0130] The inorganic lower encapsulation pattern LIL may be disposed corresponding to the light emitting opening OP-E. For example, a portion of the inorganic lower encapsulation pattern LIL may be disposed in the partition wall opening OP-P, and another portion of the inorganic lower encapsulation pattern LIL may be disposed on the partition wall PW. A portion of the inorganic lower encapsulation pattern LIL disposed in the partition wall opening OP-P may be disposed on the cathode CE and / or the capping pattern CP to cover the cathode CE.

[0131] The organic encapsulation film OL may cover the inorganic lower encapsulation pattern LIL and may provide a flat or substantially flat upper surface. The inorganic upper encapsulation film UIL may be disposed on the organic encapsulation film OL.

[0132] The inorganic lower encapsulation pattern LIL and the inorganic upper encapsulation film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the organic encapsulation film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0133] FIG. 6A to FIG. 6L is a cross-sectional view illustrating some operations of a method for manufacturing a display panel according to an embodiment of the present disclosure. FIG. 6A to FIG. 6L The same / similar components and configurations are used as above with reference to FIGS. 1 to Figure 5 The same / similar reference numerals or symbols as those described are denoted, and thus, redundant description thereof may not be repeated.

[0134] According to one or more embodiments of the present disclosure, a method for manufacturing a display panel may include: providing a preliminary display panel, the preliminary display panel including a base layer and an anode, a lower sacrificial layer and a first preliminary pixel defining film arranged on the base layer; forming a first pixel defining film by etching the first preliminary pixel defining film; sequentially depositing a second preliminary pixel defining film, a first preliminary partition wall layer, a sacrificial layer and a second preliminary partition wall layer on the first pixel defining film; and forming a second pixel defining film, a partition wall and a sacrificial pattern by etching the second preliminary pixel defining film, the first preliminary partition wall layer, the sacrificial layer and the second preliminary partition wall layer.

[0135] Reference Fig. 6A , the method for manufacturing a display panel according to one or more embodiments of the present disclosure may include the following operations: providing a preliminary display panel DP-I.

[0136] The preliminary display panel DP-I provided in an embodiment of the present disclosure may include a base layer BL, a circuit element layer DP-CL, an anode electrode AE, a lower sacrificial layer SP1-I, and a first preliminary pixel defining film PDL1-I.

[0137] The circuit element layer DP-CL can be formed by the following process of manufacturing circuit elements: by forming an insulating layer, a semiconductor layer and a conductive layer through coating, deposition, etc. and selectively patterning the insulating layer, the semiconductor layer and the conductive layer through photolithography and etching to form a semiconductor pattern, a conductive pattern, a signal line, etc.

[0138] The anode AE ​​and the lower sacrificial layer SP1-I may be formed by the same patterning process. The lower sacrificial layer SP1-I may include a transparent conductive oxide. For example, the lower sacrificial layer SP1-I may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), aluminum zinc oxide, or zinc indium tin oxide (ZITO). In an embodiment, the lower sacrificial layer SP1-I may include (for example, may be) zinc indium tin oxide (ZITO) doped with about 14at% tin (Sn).

[0139] The first preliminary pixel defining film PDL1-I may be formed on the base layer BL. The first preliminary pixel defining film PDL1-I may cover all of the anodes AE and the lower sacrificial layer SP1-I. The first preliminary pixel defining film PDL1-I may include an inorganic material. For example, the first preliminary pixel defining film PDL1-I may include silicon nitride (SiN x ).

[0140] The method for manufacturing a display panel according to one or more embodiments of the present disclosure may include the following operations: forming a first photoresist layer PR1 on a first preliminary pixel defining film PDL1-I. The first photoresist layer PR1 may be formed by patterning the preliminary photoresist layer by using a photolithography mask after forming the preliminary photoresist layer on the first preliminary pixel defining film PDL1-I. A first photolithography opening OP-PR1 overlapping the anode AE ​​may be formed in the first photoresist layer PR1 by a patterning process.

[0141] Reference Figure 6B The method for manufacturing a display panel according to one or more embodiments of the present disclosure may include the following operations: etching a first preliminary pixel definition film PDL1-I (eg, see Fig. 6A) forms a first pixel defining film PDL1. In the operation of forming the first pixel defining film PDL1, the first preliminary pixel defining film PDL1-I may be dry-etched by using the first photoresist layer PR1 as a mask. The portion of the first preliminary pixel defining film PDL1-I that does not overlap with the first photoresist layer PR1 may be etched to be removed, and the other remaining portion of the first preliminary pixel defining film PDL1-I that is not etched and remains may be the first pixel defining film PDL1. The first pixel opening OP-PDL1 of the first pixel defining film PDL1 may be formed by the etched and removed portion. The first pixel opening OP-PDL1 may overlap with the first photolithography opening OP-PR1 of the first photoresist layer PR1.

[0142] Reference Figure 6C According to one or more embodiments of the present disclosure, the method for manufacturing a display panel may include the following operations: before removing the first photoresist layer PR1 (eg, see Figure 6B ), a second preliminary pixel defining film PDL2-I, a first preliminary partition wall layer L1-I, an upper sacrificial layer SP2-I, and a second preliminary partition wall layer L2-I are sequentially deposited on the first pixel defining film PDL1. In the present disclosure, the upper sacrificial layer SP2-I may be referred to as a sacrificial layer SP2-I.

[0143] The second preliminary pixel defining film PDL2-I may be formed on the first pixel defining film PDL1. The second preliminary pixel defining film PDL2-I may include an inorganic material. For example, the second preliminary pixel defining film PDL2-I may include silicon nitride (SiN x ).

[0144] The first preliminary partition wall layer L1-I can be formed by a process of depositing a conductive material on the second preliminary pixel definition film PDL2-I. The first preliminary partition wall layer L1-I may include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO) or a suitable combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or a suitable alloy thereof. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0145] The upper sacrificial layer SP2-I (e.g., sacrificial layer) may be formed in a process of depositing a conductive material on the first preliminary partition wall layer L1-I. The upper sacrificial layer SP2-I may include a transparent conductive oxide. For example, the upper sacrificial layer SP2-I may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), aluminum zinc oxide, or zinc indium tin oxide (ZITO). In an embodiment, the upper sacrificial layer SP2-I may include (e.g., may be) zinc indium tin oxide (ZITO) doped with about 22at% tin (Sn).

[0146] The second preliminary partition wall layer L2-1 may be formed in a process of depositing a conductive material on the upper sacrificial layer SP2-1. The second preliminary partition wall layer L2-1 may include a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (TCO), or a suitable combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or a suitable alloy thereof. The transparent conductive oxide may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide (IGZO), or aluminum zinc oxide.

[0147] The method for manufacturing a display panel according to one or more embodiments of the present disclosure may include the following operations: forming a second photoresist layer PR2 on the second preliminary partition wall layer L2-I. The second photoresist layer PR2 may be formed by: after forming the preliminary photoresist layer on the second preliminary partition wall layer L2-I, patterning the preliminary photoresist layer by using a photolithography mask. A second photolithography opening OP-PR2 overlapping the anode AE ​​may be formed in the second photoresist layer PR2 by a patterning process.

[0148] Reference FIG. 6D to FIG. 6I , the method for manufacturing a display panel according to one or more embodiments of the present disclosure may include the following operations: etching the second preliminary pixel definition film PDL2-I, the first preliminary partition wall layer L1-I, the upper sacrificial layer SP2-I, and the second preliminary partition wall layer L2-I (for example, see Figure 6C) to form a second pixel defining film PDL2, a partition wall PW, and an upper sacrificial pattern SP2. The operation of forming the second pixel defining film PDL2, the partition wall PW, and the upper sacrificial pattern SP2 may include an operation of etching the second preliminary partition wall layer L2-I, an operation of etching the upper sacrificial layer SP2-I, an operation of etching the first preliminary partition wall layer L1-I, an operation of forming a partition wall PW having a partition wall opening OP-P by etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I, an operation of forming the second pixel defining film PDL2 by etching the second preliminary pixel defining film PDL2-I, and an operation of forming the upper sacrificial pattern SP2 by etching the upper sacrificial layer SP2-I.

[0149] In more detail, Fig.6D As shown in FIG. 1 , a second pixel definition film PDL2 is formed (for example, see Fig.6I ), the partition wall PW and the upper sacrificial pattern SP2 may include etching the second preliminary partition wall layer L2-I (eg, see Figure 6C ). In the operation of etching the second preliminary partition wall layer L2-I, the second preliminary partition wall layer L2-I can be dry-etched by using the second photoresist layer PR2 as a mask. The portion of the second preliminary partition wall layer L2-I that does not overlap with the second photoresist layer PR2 can be etched to be removed. In other words, the portion of the second preliminary partition wall layer L2-I that overlaps with the second photolithography opening OP-PR2 can be etched and removed.

[0150] like Fig. 6E As shown in FIG. 1 , a second pixel definition film PDL2 is formed (for example, see Fig.6I ), the partition wall PW and the upper sacrificial pattern SP2 may include etching the upper sacrificial layer SP2-I (eg, see Fig.6D ). The operation of etching the upper sacrificial layer SP2-I may be to wet-etch the upper sacrificial layer SP2-I by using the second photoresist layer PR2 as a mask. The portion of the upper sacrificial layer SP2-I that does not overlap with the second photoresist layer PR2 may be etched to be removed. In other words, the portion of the upper sacrificial layer SP2-I that overlaps with the second photolithography opening OP-PR2 may be etched and removed.

[0151] like Fig. 6F As shown in FIG. 1 , a second pixel definition film PDL2 is formed (for example, see Fig.6I), the operation of forming the partition wall PW and the upper sacrificial pattern SP2 may include an operation of etching the first preliminary partition wall layer L1-I. In the operation of etching the first preliminary partition wall layer L1-I, the first preliminary partition wall layer L1-I may be dry-etched by using the second photoresist layer PR2 as a mask. The portion of the first preliminary partition wall layer L1-I that does not overlap with the second photoresist layer PR2 may be etched to be removed. In other words, the portion of the first preliminary partition wall layer L1-I that overlaps with the second photolithography opening OP-PR2 may be etched and removed. The inner side surface of the first preliminary partition wall layer L1-I having the preliminary opening OP-I, the inner side surface of the upper sacrificial layer SP2-I, and the inner side surface of the second preliminary partition wall layer L2-I may be aligned with each other or substantially aligned.

[0152] like Figure 6G As shown in FIG. 1 , a second pixel definition film PDL2 is formed (for example, see Fig.6I ), the partition wall PW and the upper sacrificial pattern SP2 may include etching the first preliminary partition wall layer L1-I (eg, see Fig. 6F ) and the second preliminary partition wall layer L2-I form a partition wall PW having a partition wall opening OP-P. In the operation of forming the partition wall PW having the partition wall opening OP-P by etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I, the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may be wet-etched by using the second photoresist layer PR2 as a mask. The first partition wall layer L1 and the second partition wall layer L2 formed by etching may be defined as the partition wall PW.

[0153] During the above process, the upper sacrificial layer SP2-I may also be partially etched. Figure 6G The upper sacrificial layer SP2-I is shown to be partially etched so that the side surface of the second partition wall layer L2 is aligned with the side surface of the upper sacrificial layer SP2-I, but the present disclosure is not limited thereto. For example, the side surface of the upper sacrificial layer SP2-I may be formed to be more recessed inward than the side surface of the second partition wall layer L2.

[0154] In an embodiment, when the etching selectivity of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I is large, a wet etching process may be performed. Therefore, the second partition wall layer L2 may have a shape in which the second partition wall layer L2 protrudes more toward the partition wall opening OP-P than the first partition wall layer L1. In more detail, because the etching rate of the first preliminary partition wall layer L1-I is greater than the etching rate of the second preliminary partition wall layer L2-I, the first preliminary partition wall layer L1-I may be mainly etched. Therefore, the side surface of the first partition wall layer L1 may be formed to be much more recessed inward than the side surface of the second partition wall layer L2. The portion of the second partition wall layer L2 that protrudes much more than the first partition wall layer L1 may be formed as a tip portion in the partition wall PW.

[0155] Reference Figure 6H , forming a second pixel definition film PDL2 (for example, see Fig.6I ), the partition wall PW and the upper sacrificial pattern SP2 may include etching the second preliminary pixel definition film PDL2-I (eg, see Figure 6G )An operation of forming a second pixel defining film PDL2. In the operation of forming the second pixel defining film PDL2, the second preliminary pixel defining film PDL2-I may be dry-etched by using the second photoresist layer PR2 as a mask. A portion of the second preliminary pixel defining film PDL2-I that does not overlap with the second photoresist layer PR2 may be etched to be removed, and another portion of the second preliminary pixel defining film PDL2-I that is not etched and remains may be the second pixel defining film PDL2. A second pixel opening OP-PDL2 of the second pixel defining film PDL2 may be formed by the etched and removed portion. The second pixel opening OP-PDL2 may overlap with the second photolithography opening OP-PR2 of the second photoresist layer PR2.

[0156] The first pixel defining film PDL1 and the second pixel defining film PDL2 may be defined as a pixel defining film PDL, and the first pixel opening OP-PDL1 and the second pixel opening OP-PDL2 may be defined as a light emitting opening OP-E. The first pixel defining film PDL1 may include a first inner surface S1-PDL defining the first pixel opening OP-PDL1. The second pixel defining film PDL2 may include a second inner surface S2-PDL defining the second pixel opening OP-PDL2.

[0157] Reference Fig.6I The operation of forming the second pixel defining film PDL2, the partition wall PW, and the upper sacrificial pattern SP2 may include etching the upper sacrificial layer SP2-I (eg, see Figure 6H) to form the upper sacrificial pattern SP2. In the present disclosure, the upper sacrificial pattern SP2 may be referred to as the sacrificial pattern SP2. The operation of forming the upper sacrificial pattern SP2 by etching the upper sacrificial layer SP2-I may include etching the lower sacrificial layer SP1-I (for example, see Figure 6H )An operation of forming the lower sacrificial pattern SP1.

[0158] In the operation of etching the upper sacrificial layer SP2-I, the upper sacrificial layer SP2-I may be wet-etched by using the second photoresist layer PR2 as a mask. In this case, the lower sacrificial pattern SP1 exposed by the light emitting opening OP-E may be wet-etched together. Portions of the lower sacrificial layer SP1-I and the upper sacrificial layer SP2-I that do not overlap with the second photoresist layer PR2 may be etched to be removed, and other portions of the lower sacrificial layer SP1-I and the upper sacrificial layer SP2-I that are not etched to be left may be the lower sacrificial pattern SP1 and the upper sacrificial pattern SP2, respectively. Through the etched and removed portions, the upper sacrificial pattern SP2 may have an upper sacrificial opening OP-S2, and the lower sacrificial pattern SP1 may have a lower sacrificial opening OP-S1.

[0159] In the first preliminary partition wall layer L1-I (for example, see Fig. 6F ) and the second preliminary partition wall layer L2-I are wet-etched, and the upper sacrificial layer SP2-I that is exposed and partially etched can be controlled to be etched less than the lower sacrificial layer SP1-I. For example, the upper sacrificial layer SP2-I can be zinc indium tin oxide (ZITO) doped with 3at% to 14at% of tin (Sn), and the lower sacrificial layer SP1-I can be zinc indium tin oxide (ZITO) doped with 15at% to 22at% of tin (Sn). Therefore, the etching rate of the lower sacrificial layer SP1-I can be controlled to be greater than the etching rate of the upper sacrificial layer SP2-I.

[0160] The partition wall opening OP-P and the upper sacrificial opening OP-S2 may include a first area A1, a second area A2, and a third area A3. The partition wall opening OP-P may include the first area A1 and the third area A3, and the upper sacrificial opening OP-S2 may include the second area A2. The first area A1, the second area A2, and the third area A3 may be formed integrally with each other in a thickness direction (e.g., a third direction DR3) of the base layer BL. The width of the second area A2 in the first direction DR1 may be greater than the width of the first area A1 in the first direction DR1 and the width of the third area A3 in the first direction DR1.

[0161] The first partition wall layer L1 may include a first side surface S1 (eg, see Figure 5). The upper sacrificial pattern SP2 may include a second side surface S2 defining a second area A2 (eg, see Figure 5 ). The second partition wall layer L2 may include a third side surface S3 defining a third area A3 (eg, see Figure 5 ). The second side surface S2 of the upper sacrificial pattern SP2 may be more recessed than the first side surface S1 of the first partition wall layer L1 and the third side surface S3 of the second partition wall layer L2 in a direction away from the partition wall opening OP-P. On a plane (e.g., in a plan view), the second side surface S2 of the upper sacrificial pattern SP2 may overlap with the first partition wall layer L1 and the second partition wall layer L2.

[0162] Reference Figure 6J The method for manufacturing a display panel according to one or more embodiments of the present disclosure may include, after removing the second photoresist layer PR2 , an operation of forming a light emitting pattern EP in the partition wall opening OP-P and an operation of forming a cathode CE.

[0163] The operation of forming the light emitting pattern EP may be performed by a deposition process. For example, the operation of forming the light emitting pattern EP may include a thermal evaporation process. The light emitting pattern EP may be formed on the anode AE. In the operation of forming the light emitting pattern EP, the light emitting pattern EP may be separated by a tip portion formed in the partition wall PW to be disposed in the light emitting opening OP-E and the partition wall opening OP-P. In the operation of forming the light emitting pattern EP, the first dummy layer D1-I spaced apart from the light emitting pattern EP may be formed together on the partition wall PW.

[0164] The operation of forming the cathode CE may be performed by a deposition process. For example, the operation of forming the cathode CE may include a sputtering process. The cathode CE may be formed on the light emitting pattern EP. The cathode CE may be formed so that it contacts the partition wall PW and so that it is spaced apart from the upper sacrificial pattern SP2. For example, the cathode CE may be formed so as to contact the side surface of the first partition wall layer L1 by providing it at an incident angle higher than the incident angle of the light emitting pattern EP. In the operation of forming the cathode CE, the cathode CE may be separated by a tip portion formed in the partition wall PW to be disposed in the partition wall opening OP-P. In the operation of forming the cathode CE, a second dummy layer D2-I spaced apart from the cathode CE may be formed together on the partition wall PW. The anode AE, the light emitting pattern EP, and the cathode CE may constitute a light emitting element ED.

[0165] In addition, the method for manufacturing a display panel according to an embodiment may further include an operation of forming a capping pattern CP on the cathode CE. The operation of forming the capping pattern CP may be performed by a deposition process. For example, the operation of forming the capping pattern CP may include a thermal evaporation process. In the operation of forming the capping pattern CP, the capping pattern CP may be separated by a tip portion formed in the partition wall PW to be disposed in the partition wall opening OP-P. In the operation of forming the capping pattern CP, a third dummy layer D3-I spaced apart from the capping pattern CP may be formed together on the partition wall PW. According to another embodiment of the present disclosure, the operation of forming the capping pattern CP may be omitted as needed or desired.

[0166] However, the present disclosure is not limited to the above process, and the deposition process of each of the operation of forming the light emitting pattern EP, the operation of forming the cathode CE, and the operation of forming the capping pattern CP is not limited thereto. The first dummy layer D1-I, the second dummy layer D2-I, and the third dummy layer D3-I may form a dummy layer DMP-I, and a dummy opening OP-D may be formed in the dummy layer DMP-I.

[0167] Reference Figure 6J and Figure 6K , the method for manufacturing a display panel according to one or more embodiments of the present disclosure may include an operation of forming an inorganic lower encapsulation pattern LIL.

[0168] like Figure 6J As shown in FIG. , an inorganic lower encapsulation pattern LIL is formed (for example, see Figure 6K ) may include an operation of depositing an inorganic lower encapsulation layer LIL-I. The inorganic lower encapsulation layer LIL-I may be formed by a deposition process. In an embodiment, the inorganic lower encapsulation layer LIL-I may be formed by a chemical vapor deposition (CVD) process.

[0169] The inorganic lower encapsulation layer LIL-I may be deposited on the partition wall PW and the cathode CE. In more detail, a portion of the inorganic lower encapsulation layer LIL-I may be deposited in the partition wall opening OP-P and the upper sacrificial opening OP-S2, and another portion of the inorganic lower encapsulation layer LIL-I may be deposited on the partition wall PW. The inorganic lower encapsulation layer LIL-I may be formed to contact the upper sacrificial pattern SP2.

[0170] Reference Figure 6K The method for manufacturing a display panel according to one or more embodiments of the present disclosure may include an operation of forming a third photoresist layer PR3 and an operation of forming an inorganic lower encapsulation layer LIL-I (eg, see Figure 6J ) and the dummy layer DMP-I are patterned to respectively form the inorganic lower encapsulation pattern LIL and the dummy pattern DMP.

[0171] In the operation of forming the third photoresist layer PR3, after forming the preliminary photoresist layer, the third photoresist layer PR3 may be formed by patterning the preliminary photoresist layer using a photolithography mask. Through the patterning process, the third photoresist layer PR3 may be formed in the form of a pattern corresponding to the light emitting opening OP-E.

[0172] In the operation of patterning the inorganic lower encapsulation layer LIL-I, the inorganic lower encapsulation layer LIL-I may be dry-etched to be patterned, thereby removing a portion of the inorganic lower encapsulation layer LIL-I that overlaps with the remaining portion except for the corresponding anode AE. An inorganic lower encapsulation pattern LIL that overlaps with the corresponding light-emitting opening OP-E may be formed from the patterned inorganic lower encapsulation layer LIL-I.

[0173] In the operation of patterning the dummy layer DMP-I, the first dummy layer D1-I, the second dummy layer D2-I, and the third dummy layer D3-I may be dry-etched to be patterned so as to remove portions of the first dummy layer D1-I, the second dummy layer D2-I, and the third dummy layer D3-I overlapping with the remaining portions except for the corresponding anode AE.

[0174] The first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 overlapping the corresponding light emitting opening OP-E may be formed by patterning the first dummy layer D1-I, the second dummy layer D2-I, and the third dummy layer D3-I, so that the dummy pattern DMP including the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may be formed. The first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may have a dummy pattern surrounding the corresponding light emitting area PXA (for example, see FIG. 1 ) on a plane (for example, in a plan view). Figure 4 ) (e.g., around its perimeter).

[0175] In another embodiment of the present disclosure, the method for manufacturing a display panel may further include an operation of additionally etching the dummy pattern DMP. For example, in the operation of additionally etching the dummy pattern DMP, the dummy pattern DMP may be wet-etched to be removed.

[0176] Reference Figure 6L According to one or more embodiments, the method for manufacturing a display panel may include the following operations: before removing the third photoresist layer PR3 (eg, see Figure 6K), the display panel DP is completed by forming an organic encapsulation film OL and an inorganic upper encapsulation film UIL. The organic encapsulation film OL can be formed by applying an organic material by an inkjet method, but the present disclosure is not limited thereto. The organic encapsulation film OL provides a flat or substantially flat upper surface. The inorganic upper encapsulation film UIL can be formed by depositing an inorganic material. In this way, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE can be formed.

[0177] Between the operation of forming the inorganic lower encapsulation pattern LIL and the operation of completing the display panel DP, an operation of forming a partition wall opening and a light emitting opening corresponding to a light emitting area for providing another color in the partition wall PW and the pixel definition film PDL, an operation of forming a light emitting element for providing another color, and an operation of forming an inorganic lower encapsulation pattern covering the light emitting element for providing another color may be further performed. In this way, the inorganic lower encapsulation pattern LIL including the light emitting elements respectively corresponding to the light emitting areas of the other color may be formed. Figure 4 The display panel DP includes the first to third light-emitting elements, the 1-1 to 1-3 dummy patterns, the 2-1 to 2-3 dummy patterns, the 3-1 to 3-3 dummy patterns, and the first to third inorganic lower encapsulation patterns corresponding to the multiple light-emitting areas PXA-R, PXA-G and PXA-B shown in FIG.

[0178] According to one or more embodiments described above, since an upper sacrificial pattern can be formed between the first partition wall layer and the second partition wall layer, a path through which impurities introduced from the side surface of the inorganic lower encapsulation pattern can be extended. In addition, since the upper sacrificial pattern has an undercut shape relative to the first partition wall layer and the second partition wall layer, the cathode can be spaced apart from the upper sacrificial pattern. Therefore, the upper sacrificial pattern including a transparent conductive oxide can directly contact the inorganic lower encapsulation pattern, and the bonding force between the inorganic lower encapsulation pattern and the partition wall can be improved, thereby reducing or eliminating pixel defects (e.g., dark spots, pixel shrinkage, etc.).

[0179] The above are examples of some embodiments of the present disclosure and should not be interpreted as limiting them. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications may be made to the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Therefore, as will be understood by those of ordinary skill in the art, unless otherwise specifically noted, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it is to be understood that the above are examples of various exemplary embodiments and are not to be interpreted as being limited to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the appended claims and their equivalents.

Claims

1. Display panel, including: Base layer; a pixel defining film on the base layer and having a light emitting opening; a partition wall having a partition wall opening overlapping the light emitting opening and comprising a first partition wall layer on the pixel defining film and a second partition wall layer on the first partition wall layer; a light emitting element at least partially located in the partition wall opening and comprising an anode, an intermediate layer and a cathode, the cathode being in contact with the partition wall; as well as The sacrificial pattern is between the first partition wall layer and the second partition wall layer and has a sacrificial opening overlapping the partition wall opening.

2. The display panel according to claim 1, wherein: The sacrificial pattern has an undercut shape with respect to the partition wall.

3. The display panel according to claim 1, wherein: The first partition wall layer of the partition wall has an undercut shape with respect to the second partition wall layer.

4. The display panel according to claim 1, wherein: The first partition wall layer includes a first side surface defining a first region of the partition wall opening, The sacrificial pattern includes a second side surface defining a second area of ​​the sacrificial opening, The second partition wall layer includes a third side surface defining a third region of the partition wall opening, and The first to third regions are integrated with each other in the thickness direction of the base layer.

5. The display panel according to claim 4, wherein: The second side surface of the sacrificial pattern is more recessed than the first side surface of the first partition wall layer and the third side surface of the second partition wall layer in a direction away from the partition wall opening.

6. The display panel according to claim 4, wherein: The second side surface of the sacrificial pattern overlaps the first partition wall layer and the second partition wall layer in a plan view.

7. The display panel according to claim 4, wherein: A width of the second region in the first direction is greater than a width of the first region in the first direction and a width of the third region in the first direction. 8 . The display panel of claim 1 , further comprising a lower sacrificial pattern between the anode and the pixel defining film and having a lower sacrificial opening overlapping the light emitting opening.

9. The display panel according to claim 1, wherein: The pixel definition film comprises: a first pixel defining film on the base layer and including a first inner surface defining a first pixel opening of the light emitting opening; and The second pixel defining film is on the first pixel defining film and includes a second inner surface defining a second pixel opening of the light emitting opening.

10. The display panel according to claim 9, wherein: A width of the first pixel opening in the first direction is equal to or smaller than a width of the second pixel opening in the first direction.

11. The display panel according to claim 1, wherein: The cathode is spaced apart from the sacrificial pattern.

12. Display panel, comprising: Base layer; a pixel defining film on the base layer and having a light emitting opening; a partition wall having a partition wall opening overlapping the light emitting opening and comprising a first partition wall layer on the pixel defining film and a second partition wall layer on the first partition wall layer; a light emitting element at least partially located in the partition wall opening and comprising an anode, an intermediate layer and a cathode, the cathode being in contact with the partition wall; a sacrificial pattern between the first partition wall layer and the second partition wall layer and comprising a transparent conductive oxide; as well as A lower sacrificial pattern is between the anode and the pixel defining film and includes a transparent conductive oxide.

13. The display panel according to claim 12, wherein: The lower sacrificial pattern has a lower sacrificial opening overlapping the light emitting opening, and The sacrificial pattern has a sacrificial opening overlapping the partition wall opening.

14. The display panel according to claim 12, wherein: The sacrificial pattern has an undercut shape with respect to the partition wall.

15. The display panel according to claim 12, wherein: The first partition wall layer includes a first side surface defining a first region of the partition wall opening, The sacrificial pattern has a sacrificial opening overlapping the partition wall opening and includes a second side surface defining a second area of ​​the sacrificial opening, The second partition wall layer includes a third side surface defining a third region of the partition wall opening, The first to third regions are integrated with each other in a thickness direction of the base layer, and The second side surface of the sacrificial pattern is more recessed than the first side surface of the first partition wall layer and the third side surface of the second partition wall layer in a direction away from the partition wall opening.

16. The display panel according to claim 15, wherein: The second side surface of the sacrificial pattern overlaps the first partition wall layer and the second partition wall layer in a plan view.

17. The display panel according to claim 12, wherein: The cathode is spaced apart from the sacrificial pattern.

18. A method for manufacturing a display panel, the method comprising: Providing a preliminary display panel, the preliminary display panel comprising a base layer, and an anode, a lower sacrificial layer, and a first preliminary pixel defining film disposed on the base layer; forming a first pixel defining film by etching the first preliminary pixel defining film; sequentially depositing a second preliminary pixel defining film, a first preliminary partition wall layer, a sacrificial layer, and a second preliminary partition wall layer on the first pixel defining film; as well as A second pixel defining film, a partition wall, and a sacrificial pattern are formed by etching the second preliminary pixel defining film, the first preliminary partition wall layer, the sacrificial layer, and the second preliminary partition wall layer.

19. The method according to claim 18, wherein: Forming the second pixel defining film, the partition wall and the sacrificial pattern includes: etching the second preliminary partition wall layer; etching the sacrificial layer; etching the first preliminary partition wall layer; forming the partition wall having a partition wall opening by etching the first preliminary partition wall layer and the second preliminary partition wall layer; forming the second pixel defining film by etching the second preliminary pixel defining film; and The sacrificial pattern is formed by etching the sacrificial layer.

20. The method according to claim 19, wherein: Forming the sacrificial pattern by etching the sacrificial layer includes forming a lower sacrificial pattern by etching the lower sacrificial layer.

21. The method of claim 19, further comprising: forming a light emitting pattern in the partition wall opening; forming a cathode in the partition wall opening, contacting the partition wall and spaced apart from the sacrificial pattern; as well as An inorganic lower encapsulation pattern is formed in contact with the sacrificial pattern.

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