A power control circuit for a chip and the chip itself

Abstract

This disclosure provides a power control circuit and a chip. The power control circuit includes a node voltage generation module, a comparison module, and a control module. The node voltage generation module establishes a stable first internal node voltage based on the power port voltage and a stable second internal node voltage based on the internal circuit voltage. The comparison module compares the first internal node voltage with the power port voltage to obtain a first comparison signal, and compares the second internal node voltage with the power port voltage to obtain a second comparison signal. The control module controls the switching between the power port and the power supply terminal of the internal circuit based on the first and second comparison signals to prevent ground bounce noise from external power signals from entering the internal circuit, thereby improving chip stability. This power control circuit can prevent ground bounce noise from entering the internal circuit, thus improving chip stability, and can also reduce circuit complexity, thereby reducing chip area.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of integrated circuit technology, and more particularly to a power control circuit and chip for a chip. Background Technology

[0002] To support high-power circuitry, chips typically require external capacitors for voltage regulation. The negative terminal of these capacitors is usually connected to the ideal ground of the printed circuit board (PCB). However, PCB traces and packages contain parasitic inductance, and the chip's ground is affected by ground bounce noise. Since the power supply to the chip's internal circuitry is formed by the positive terminal of the external capacitors and the chip ground, the ground bounce voltage is effectively superimposed on the internal circuitry's power supply voltage. This results in significant noise exposure to the internal circuitry, degrading critical chip performance, such as reference voltage deviation and loss of feedback loop control. Low-voltage circuits are also at risk of damage due to excessively high voltage exposure.

[0003] In existing technologies, the output signal of the power stage is typically acquired and transmitted to a power supply port. A shielding signal is then generated based on the power stage's output signal to control the power supply's on-state logic, thereby shielding the energy transfer from ground bounce noise devices. However, the acquisition and transmission of the power stage's output signal requires additional circuitry, resulting in a larger chip area. Summary of the Invention

[0004] This disclosure provides a power control circuit and chip that can prevent ground bounce noise from entering the internal circuit, thereby improving the stability of the chip and reducing circuit complexity, thus reducing the chip area.

[0005] In a first aspect, this disclosure provides a power control circuit for a chip, the chip including a power port and internal circuitry, the power control circuit including a node voltage generation module, a comparison module, and a control module.

[0006] The node voltage generation module is configured to establish a stable first internal node voltage based on the power port voltage and a stable second internal node voltage based on the internal circuit voltage. The power port voltage is the voltage of the external power signal received by the power port, and the internal circuit voltage is the power supply voltage of the internal circuit.

[0007] The comparison module is configured to compare the first internal node voltage and the power port voltage to obtain a first comparison signal; and to compare the second internal node voltage and the power port voltage to obtain a second comparison signal.

[0008] The control module is configured to control the switching between the power port and the power supply terminal of the internal circuit according to the first comparison signal and the second comparison signal, so as to prevent ground bounce noise in the external power signal from entering the internal circuit.

[0009] In some embodiments of this disclosure, the comparison module includes a positive comparison unit and a negative comparison unit. The first input terminal of the positive comparison unit is connected to the first output terminal of the node voltage generation module, the second input terminal of the positive comparison unit is connected to the power supply port, the output terminal of the positive comparison unit is connected to the first input terminal of the control module, the first input terminal of the negative comparison unit is connected to the power supply port, the second input terminal of the negative comparison unit is connected to the second output terminal of the node voltage generation module, and the output terminal of the negative comparison unit is connected to the second input terminal of the control module.

[0010] The forward comparison unit is configured to output a first level signal when the power port voltage is greater than or equal to the sum of the first internal node voltage and the first preset voltage; and to output a second level signal when the power port voltage is less than the sum of the first internal node voltage and the preset voltage.

[0011] The negative comparison unit is configured to output the first level signal when the sum of the power port voltage and the second preset voltage is less than or equal to the second internal node voltage; and to output the second level signal when the sum of the power port voltage and the second preset voltage is greater than the second internal node voltage.

[0012] In some embodiments of this disclosure, the forward comparison unit includes a first transistor and a first resistor. The control terminal of the first transistor is connected to the first output terminal of the node voltage generation module. The first terminal of the first transistor is connected to the power supply port. The second terminal of the first transistor is connected to the first input terminal of the control module and the first terminal of the first resistor. The second terminal of the first resistor is connected to the chip ground.

[0013] In some embodiments of this disclosure, the negative comparison unit includes a second transistor, a second resistor, a third resistor, and a first capacitor. The control terminal of the second transistor is connected to the first plate of the first capacitor and the first terminal of the third resistor. The second plate of the first capacitor is connected to the power supply port. The second terminal of the third resistor is connected to the power supply terminal of the internal circuit. The first terminal of the second transistor is connected to the second output terminal of the node voltage generation module. The second terminal of the second transistor is connected to the second input terminal of the control module and the first terminal of the second resistor. The second terminal of the second resistor is connected to chip ground.

[0014] In some embodiments of this disclosure, the control module includes a positive signal generation unit, a negative signal generation unit, and a control unit. The input terminal of the positive signal generation unit is connected to the first output terminal of the comparison module, the output terminal of the positive signal generation unit is connected to the first control terminal of the control unit, the input terminal of the negative signal generation unit is connected to the second output terminal of the comparison module, the output terminal of the negative signal generation unit is connected to the second control terminal of the control unit, the input terminal of the control unit is connected to the power supply port, and the output terminal of the control unit is connected to the power supply terminal of the internal circuit.

[0015] The positive signal generation unit is configured to generate a positive control signal based on the first comparison signal, the positive control signal including a positive conduction control signal and a positive disconnection control signal. The negative signal generation unit is configured to generate a negative control signal based on the second comparison signal, the negative control signal including a negative conduction control signal and a negative disconnection control signal.

[0016] The control unit is configured to connect the power port to the power supply terminal of the internal circuit when the positive control signal is the positive conduction control signal and the negative control signal is the negative conduction control signal; and to disconnect the connection between the power port and the power supply terminal of the internal circuit when the positive control signal is the positive disconnection control signal or the negative control signal is the negative disconnection control signal, so as to prevent the ground bounce noise from entering the internal circuit.

[0017] In some embodiments of this disclosure, the positive signal generation unit includes a third transistor, a fourth transistor, a fifth transistor, and a fourth resistor. The control terminals of the third transistor and the fourth transistor are connected to the first output terminal of the comparator module. The first terminals of the third transistor and the fifth transistor are connected to the power supply port. The second terminal of the third transistor is connected to the second terminal of the fourth transistor and the control terminal of the fifth transistor. The second terminal of the fifth transistor is connected to the first terminal of the fourth resistor and the first control terminal of the control unit. The second terminal of the fourth resistor and the first terminal of the fourth transistor are connected to chip ground.

[0018] In some embodiments of this disclosure, the negative signal generation unit includes a sixth transistor, a seventh transistor, an eighth transistor, and a fifth resistor. The control terminals of the sixth transistor and the seventh transistor are connected to the second output terminal of the comparator module. The first terminals of the sixth transistor and the eighth transistor are connected to the power supply terminal of the internal circuit. The second terminal of the sixth transistor is connected to the second terminal of the seventh transistor and the control terminal of the eighth transistor. The second terminal of the eighth transistor is connected to the first terminal of the fifth resistor and the second control terminal of the control unit. The second terminal of the fifth resistor and the second terminal of the seventh transistor are connected to the chip ground.

[0019] In some embodiments of this disclosure, the control unit includes a ninth transistor and a tenth transistor. The control terminal of the ninth transistor is connected to the output terminal of the positive signal generation unit, and the control terminal of the tenth transistor is connected to the output terminal of the negative signal generation unit. The first terminal of the ninth transistor is connected to the power supply port, the first terminal of the tenth transistor is connected to the power supply terminal of the internal circuit, and the second terminal of the ninth transistor is connected to the second terminal of the tenth transistor.

[0020] In some embodiments of this disclosure, the node voltage generation module includes a sixth resistor, a seventh resistor, a second capacitor, and a third capacitor. The first end of the sixth resistor is connected to the power supply port, and the second end of the sixth resistor is connected to the first plate of the second capacitor and the first input terminal of the comparison module. The first end of the seventh resistor is connected to the power supply terminal of the internal circuit, and the second end of the seventh resistor is connected to the first plate of the third capacitor and the second input terminal of the comparison module. The second plates of the second capacitor and the second plates of the third capacitor are connected to the chip ground.

[0021] In a second aspect, this disclosure provides a chip including a power port, internal circuitry, and any of the power control circuits provided in the first aspect.

[0022] This disclosure provides a power control circuit for a chip, including a node voltage generation module, a comparison module, and a control module. The node voltage generation module establishes a stable first internal node voltage based on the power port voltage and a stable second internal node voltage based on the internal circuit voltage. The power port voltage is the voltage of the external power signal received at the power port, and the internal circuit voltage is the power supply voltage of the internal circuit. The comparison module compares the first internal node voltage and the power port voltage to obtain a first comparison signal, and compares the second internal node voltage and the power port voltage to obtain a second comparison signal. The control module controls the switching between the power port and the power supply terminal of the internal circuit based on the first and second comparison signals to prevent ground bounce noise in the external power signal from entering the internal circuit, thereby improving the stability of the chip. Thus, the power control circuit can adaptively determine whether the external power signal contains ground bounce noise based on the amplitude and duration of the ground bounce noise, without needing to collect the power stage output signal. Therefore, it eliminates the need for additional circuitry to monitor the chip's power stage operating state and to monitor, collect, and transmit the power stage output signal, reducing circuit complexity and consequently reducing chip area. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. It should be understood that the accompanying drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure, wherein:

[0024] Figure 1 A schematic diagram of the structure of a switching power supply chip provided by the prior art.

[0025] Figure 2 A control timing diagram for a switching power supply chip provided for the prior art.

[0026] Figure 3 This is a schematic diagram of the structure of a chip provided in an embodiment of the present disclosure.

[0027] Figure 4 This is a schematic diagram of a power control circuit provided in an embodiment of the present disclosure.

[0028] Figure 5 This is a circuit diagram of a power control circuit provided in an embodiment of the present disclosure.

[0029] Figure 6 This is a schematic diagram of the voltage at each node in a power control circuit provided in this disclosure. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0031] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the specification and in the related art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, the statement “connecting” two or more parts together shall mean that the parts are joined directly together or joined through one or more intermediate components.

[0032] In this disclosure, the reference to "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of the phrase "embodiment" in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this disclosure can be combined with other embodiments.

[0033] Furthermore, the terms "first," "second," etc., in the specification, claims, or the accompanying drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more of the features.

[0034] In this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three possibilities: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0035] In the description of this disclosure, unless otherwise stated, "multiple" and "at least two" mean two or more (including two), and similarly, "multiple groups" and "at least two groups" mean two or more (including two groups).

[0036] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0037] Figure 1 A schematic diagram of the structure of a switching power supply chip provided for the prior art, such as... Figure 1 As shown, the chip includes a power supply port VCC and internal circuitry. The negative power supply terminal of the internal circuitry and the first plate of capacitor C are connected to the chip ground GND_CHIP. The second plate of capacitor C is connected to the positive power supply terminal AVDD of the internal circuitry. The positive power supply terminal AVDD of the internal circuitry is connected to the power supply port VCC through the first switch K1 and the second switch K2 in sequence. The power supply port VCC is also connected to the first plate of an external capacitor Co. The second plate of the external capacitor Co is connected to the PCB ground GND_PCB.

[0038] The internal circuitry includes a high-side driver, a low-side driver, an upper transistor (Hs), and a lower transistor (LS). The high-side driver receives the PWM control signal from the upper transistor, and the low-side driver receives the control signal from the lower transistor. Lower tube control signal This is the inverted signal of the PWM control signal for the upper transistor.

[0039] The PCB traces and packages contain parasitic inductance Lpar. Since the chip ground GND_CHIP is connected to the PCB ground GND_PCB through this parasitic inductance Lpar, GND_CHIP is susceptible to ground bounce noise. Because the internal circuitry's power supply consists of the power supply port VCC and the chip ground GND_CHIP, the ground bounce voltage is effectively superimposed on the internal circuitry's power supply voltage. This results in significant noise on the internal circuitry, degrading critical chip performance, such as reference voltage deviation and loss of feedback loop control. Low-voltage circuitry is also at risk of damage due to excessive voltage exposure, leading to reduced chip stability.

[0040] To solve the above problems, it is usually necessary to monitor the PWM control signal of the upper MOSFET in the power stage. When the PWM control signal is high (i.e., when the upper MOSFET HS is turned on), the BLANK shielding signal is pulled high and then pulled low after a shielding delay of Tblank. When the PWM control signal is low (i.e., when the lower MOSFET LS is turned on), the BLANK shielding signal is pulled high and then pulled low after a shielding delay of Tblank. Figure 2 As shown, Figure 2 A control timing diagram for a switching power supply chip provided for the prior art.

[0041] The control terminals of the first switch K1 and the second switch K2 receive the shielding signal BLANK. When the shielding signal BLANK is low, the power supply port VCC is connected to the power supply terminal AVDD of the internal circuit. When the shielding signal BLANK is high, the connection between the power supply port VCC and the power supply terminal AVDD of the internal circuit is disconnected to shield energy transmission during ground bounce noise.

[0042] Ground bounce noise is fast, typically on the order of 10V / ns. If the power stage output signal is used to control the conduction of the power path, the control signal needs to be acquired from the power stage and transmitted to the vicinity of the power port very quickly. However, the control signal is not easy to acquire in many cases.

[0043] For example, in Peak Current Mode (PCM), the upper transistor disconnection control signal is generated by the high-voltage circuit of the chip. Therefore, it is necessary to transfer the control signal to a low voltage through a level shifter before transmitting it to the power supply port control circuit. The delay in the level shifting process and transmission process of the control signal cannot be ignored, so it is difficult to guarantee the shielding effect of ground bounce noise.

[0044] For example, in multiphase or distributed power stage circuits, there are multiple output control signals that can generate ground bounce noise. These signals need to be logically integrated to control the conduction state of the power supply port. However, there is overlap between multiple control signals, which makes the power conduction logic more complex. Furthermore, simultaneously acquiring and transmitting the output signals of multiple power stages requires more acquisition circuits and wiring space, occupying additional chip area.

[0045] Furthermore, the waveform amplitude and duration of ground bounce noise are not fixed and are related to various factors such as load current, power stage switching speed, and parasitic inductance. The triggering timing of ground bounce noise also varies. For example, when the load current is positive, ground bounce noise is triggered when the upper transistor Hs switches, while when the load current is negative, ground bounce noise is triggered when the lower transistor Ls switches.

[0046] If the shielding time is too short and / or the shielding timing is delayed, it will be insufficient to shield ground bounce noise. If the shielding time is too long and / or the shielding timing is too early, it will shorten the charging time of the power supply within the cycle, thereby reducing the power supply voltage of the internal circuitry of the chip and weakening the chip's key performance characteristics, such as the on-resistance of the power stage. When dealing with ground bounce noise of different durations and / or different triggering times, additional circuitry is needed to monitor the sign of the load current and the switching speed of the power stage, and complex logic is also required to adjust the shielding timing for various situations.

[0047] In summary, existing ground bounce noise shielding solutions require additional circuitry to monitor, acquire, and transmit the power stage output signal; additional circuitry to monitor the positive and negative values ​​of the load current and the switching speed of the power stage; and complex logic circuitry to adjust the shielding timing for different situations, resulting in a large chip area.

[0048] In view of this, this disclosure provides a power control circuit for a chip, including a node voltage generation module, a comparison module, and a control module. The node voltage generation module establishes a stable first internal node voltage based on the power port voltage and a stable second internal node voltage based on the internal circuit voltage. The power port voltage is the voltage of the external power signal received at the power port, and the internal circuit voltage is the power supply voltage of the internal circuit. The comparison module compares the first internal node voltage and the power port voltage to obtain a first comparison signal, and compares the second internal node voltage and the power port voltage to obtain a second comparison signal. The control module controls the switching between the power port and the power supply terminal of the internal circuit based on the first and second comparison signals to prevent ground bounce noise in the external power signal from entering the internal circuit, thereby improving the stability of the chip. Thus, the power control circuit can adaptively determine whether the external power signal contains ground bounce noise based on the amplitude and duration of the ground bounce noise, without needing to collect the power stage output signal. Therefore, it eliminates the need for additional circuitry to monitor the operating state of the chip's power stage and to monitor, collect, and transmit the power stage output signal, reducing circuit complexity and consequently reducing chip area.

[0049] The technical solutions of this disclosure are described in detail below with reference to several specific embodiments.

[0050] Figure 3 This is a schematic diagram of the structure of a chip provided in an embodiment of the present disclosure, such as... Figure 3 As shown, the chip can be a switching power supply chip. The chip includes a power control circuit 100, a power port VCC, and an internal circuit 200. The power port VCC is connected to the positive power supply terminal AVDD of the internal circuit 200 through the power control circuit 100.

[0051] The external capacitor Co has its first plate connected to the power supply port VCC, and its second plate connected to the PCB ground GND_PCB to stabilize the power supply port voltage Vcc. The chip also includes an internal capacitor Ci. The first plate of the internal capacitor Ci is connected to the positive power supply terminal AVDD of the internal circuit 200, and the second plate of the internal capacitor Ci and the negative power supply terminal of the internal circuit 200 are connected to the chip ground GND_CHIP to stabilize the power supply voltage Vdd of the internal circuit 200.

[0052] Figure 4This is a schematic diagram of a power control circuit provided in an embodiment of the present disclosure, such as... Figure 4 As shown, the power control circuit 100 includes a node voltage generation module 110, a comparison module 120, and a control module 130.

[0053] The first input terminal of the node voltage generation module 110 is connected to the power supply port VCC, the second input terminal of the node voltage generation module 110 is connected to the positive power supply terminal AVDD of the internal circuit, the first output terminal of the node voltage generation module 110 is connected to the first input terminal of the comparator module 120, and the second output terminal of the node voltage generation module 110 is connected to the second input terminal of the comparator module 120.

[0054] The third input terminal of the comparator module 120 is connected to the power supply port VCC, the first output terminal of the comparator module 120 is connected to the first control terminal of the control module 130, the second output terminal of the comparator module 120 is connected to the second control terminal of the control module 130, the input terminal of the control module 130 is connected to the power supply port VCC, and the output terminal of the control module 130 is connected to the positive power supply terminal AVDD of the internal circuit.

[0055] The node voltage generation module 110 is configured to establish a stable first internal node voltage Vnode1 based on the power port voltage Vcc, and to establish a stable second internal node voltage Vnode2 based on the internal circuit voltage Vdd, wherein the power port voltage Vcc is the voltage of the external power signal received by the power port VCC, and the internal circuit voltage Vdd is the power supply voltage of the internal circuit.

[0056] The comparison module 120 is configured to compare the first internal node voltage Vnode1 and the power port voltage Vcc to obtain a first comparison signal CMP1, and compare the second internal node voltage Vnode2 and the power port voltage Vcc to obtain a second comparison signal CMP2.

[0057] The control module 130 is configured to control the switching between the power supply port VCC and the positive power supply terminal AVDD of the internal circuit according to the first comparison signal CMP1 and the second comparison signal CMP2, so as to prevent ground bounce noise in the external power supply signal from entering the internal circuit.

[0058] For example, see [link to example]. Figure 4 The node voltage generation module 110 includes a first node voltage generation unit 111 and a second node voltage generation unit 112. The input of the first node voltage generation unit 111 is connected to the power supply port VCC, and the output of the first node voltage generation unit 111 is connected to the first input of the comparison module 120. The first node voltage generation unit 111 can perform voltage regulation on the power supply port voltage Vcc to obtain the first internal node voltage Vnode1.

[0059] The input of the second node voltage generation unit 112 is connected to the positive power supply port AVDD of the internal circuit, and the output of the second node voltage generation unit 112 is connected to the second input of the comparator module 120. The second node voltage generation unit 112 can perform voltage regulation on the internal circuit voltage Vdd to obtain the second internal node voltage Vnode2.

[0060] See also Figure 4 The comparison module 120 includes a positive comparison unit 121 and a negative comparison unit 122. The first input terminal of the positive comparison unit 121 is connected to the first output terminal of the node voltage generation module 111, the second input terminal of the positive comparison unit 121 is connected to the power supply port VCC, and the output terminal of the positive comparison unit 121 is connected to the first input terminal of the control module 130.

[0061] The first input terminal of the negative comparator 122 is connected to the power supply port VCC, the second input terminal of the negative comparator 122 is connected to the second output terminal of the node voltage generation module 110, and the output terminal of the negative comparator 122 is connected to the second input terminal of the control module 130.

[0062] For example, the first input terminal of the forward comparison unit 121 is connected to the output terminal of the first node voltage generation unit 111. The forward comparison unit 121 compares the power port voltage Vcc and the first internal node voltage Vnode1 to determine whether the power port voltage Vcc is less than the sum of the first internal node voltage Vnode1 and the first preset voltage Vth1, thereby obtaining the first comparison signal CMP1.

[0063] When the external power signal received by the power port VCC contains positive ground bounce noise, the power port voltage Vcc is superimposed with the positive ground bounce noise voltage. At this time, the power port voltage Vcc is greater than or equal to the sum of the first internal node voltage Vnode1 and the first preset voltage Vth1, and the resulting first comparison signal CMP1 is the first level signal.

[0064] When the external power signal received by the power port VCC does not contain positive ground bounce noise, the power port voltage Vcc is not superimposed with the positive ground bounce noise voltage. At this time, the power port voltage Vcc is less than the sum of the first internal node voltage Vnode1 and the first preset voltage Vth1, and the resulting first comparison signal CMP1 is the second level signal. For example, the first level signal is a high level signal and the second level signal is a low level signal, or the first level signal is a low level signal and the second level signal is a high level signal.

[0065] Thus, when the power port voltage Vcc is greater than or equal to the sum of the first internal node voltage Vnode1 and the first preset voltage Vth1, the forward comparison unit 121 outputs a first level signal, and when the power port voltage Vcc is less than the sum of the first internal node voltage Vnode1 and the first preset voltage Vth1, it outputs a second level signal.

[0066] The first input terminal of the negative comparison unit 122 is connected to the output terminal of the second node voltage generation unit 112. The negative comparison unit 122 compares the power supply port voltage Vcc and the second internal node voltage Vnode2 to determine whether the sum of the power supply port voltage Vcc and the second preset voltage Vth2 is greater than the second internal node voltage Vnode2, thereby obtaining the second comparison signal CMP2.

[0067] When the external power signal received by the power port VCC contains reverse ground bounce noise, the reverse ground bounce noise voltage is superimposed on the power port voltage Vcc. At this time, the sum of the power port voltage Vcc and the second preset voltage Vth2 is less than or equal to the second internal node voltage Vnode2, and the resulting second comparison signal CMP2 is the first level signal.

[0068] When the external power signal received by the power port VCC does not contain reverse ground bounce noise, the power port voltage Vcc is not superimposed with the reverse ground bounce noise voltage. At this time, the sum of the power port voltage Vcc and the second preset voltage Vth2 is greater than the second internal node voltage Vnode2, and the resulting second comparison signal CMP2 is the second level signal.

[0069] Thus, when the sum of the power port voltage Vcc and the second preset voltage Vth2 is less than or equal to the second internal node voltage Vnode2, the negative comparison unit 122 outputs a first level signal, and when the sum of the power port voltage Vcc and the second preset voltage Vth2 is greater than the second internal node voltage Vnode2, it outputs a second level signal.

[0070] See also Figure 4 The control module 130 includes a positive signal generation unit 131, a negative signal generation unit 132, and a control unit 133. The input terminal of the positive signal generation unit 131 is connected to the first output terminal of the comparison module 120, and the output terminal of the positive signal generation unit 131 is connected to the first control terminal of the control unit 133. The input terminal of the negative signal generation unit 132 is connected to the second output terminal of the comparison module 120, and the output terminal of the negative signal generation unit 132 is connected to the second control terminal of the control unit 133. The input terminal of the control unit 133 is connected to the power supply port VCC, and the output terminal of the control unit 133 is connected to the positive power supply terminal AVDD of the internal circuit.

[0071] For example, the input terminal of the positive signal generation unit 131 is connected to the output terminal of the positive comparison unit 121. When the external power signal received by the power port VCC contains positive ground bounce noise, the first comparison signal CMP1 output by the positive comparison unit 121 is a first level signal. At this time, the positive signal generation unit 131 can generate a positive disconnection control signal according to the first comparison signal CMP1.

[0072] When the external power signal received by the power port VCC does not contain forward ground bounce noise, the first comparison signal CMP1 output by the forward comparison unit 121 is a second level signal. At this time, the forward signal generation unit 131 can generate a forward conduction control signal according to the first comparison signal CMP1.

[0073] Thus, the positive signal generation unit 131 can generate a positive control signal based on the first comparison signal CMP1, wherein the positive control signal includes a positive conduction control signal and a positive disconnection control signal.

[0074] The input terminal of the negative signal generation unit 132 is connected to the output terminal of the negative comparison unit 122. When the external power signal received by the power port VCC contains negative ground bounce noise, the second comparison signal CMP2 output by the negative comparison unit 122 is a first level signal. At this time, the negative signal generation unit 132 can generate a negative disconnection control signal according to the second comparison signal CMP2.

[0075] When the external power signal received by the power port VCC does not contain negative ground bounce noise, the second comparison signal CMP2 output by the negative comparison unit 122 is a second level signal. At this time, the negative signal generation unit 132 can generate a negative conduction control signal according to the second comparison signal CMP2.

[0076] Thus, the negative signal generation unit 132 can generate a negative control signal based on the second comparison signal CMP2, wherein the negative control signal includes a negative conduction control signal and a negative disconnection control signal.

[0077] When the external power signal received by the power port VCC contains positive ground bounce noise, the positive control signal generated by the positive signal generation unit 131 is a positive disconnect control signal, and the negative control signal generated by the negative signal generation unit 132 is a negative conduction control signal. The control unit 133 can disconnect the connection between the power port VCC and the positive power supply terminal AVDD of the internal circuit to prevent positive ground bounce noise from entering the internal circuit.

[0078] When the external power signal received by the power port VCC contains negative ground bounce noise, the negative control signal generated by the negative signal generation unit 132 is a negative disconnect control signal. At this time, the positive control signal generated by the positive signal generation unit 131 is a positive conduction control signal. The control unit 133 can disconnect the connection between the power port VCC and the positive power supply terminal AVDD of the internal circuit to prevent reverse ground bounce noise from entering the internal circuit.

[0079] When the external power signal received by the power port VCC does not contain ground bounce noise, that is, it does not contain negative ground bounce noise or positive ground bounce noise, the positive control signal generated by the positive signal generation unit 131 is a positive conduction control signal, and the negative control signal generated by the negative signal generation unit 132 is a negative conduction control signal. The control unit 133 can connect the power port VCC to the positive power terminal AVDD of the internal circuit.

[0080] Thus, when the positive control signal is a positive conduction control signal and the negative control signal is a negative conduction control signal, the control unit 133 conducts the connection between the power supply port VCC and the positive power supply terminal AVDD of the internal circuit. When the positive control signal is a positive disconnection control signal or the negative control signal is a negative disconnection control signal, the control unit 133 disconnects the connection between the power supply port VCC and the positive power supply terminal AVDD of the internal circuit to prevent ground bounce noise from entering the internal circuit.

[0081] In summary, the power control circuit provided in this disclosure determines whether the external power signal received by the power port contains ground bounce noise based on the voltage difference between the internal node voltage and the power port voltage. When the external power signal received by the power port contains ground bounce noise, the connection between the power port and the power supply terminal of the internal circuit is disconnected to prevent ground bounce noise from entering the internal circuit, thereby improving chip stability. Furthermore, the power control circuit can adaptively determine whether the external power signal contains ground bounce noise based on the amplitude and duration of the ground bounce noise, without needing to acquire the power stage output signal. Therefore, it eliminates the need for additional circuitry to monitor the chip's power stage operating state, and to monitor, acquire, and transmit the power stage output signal, reducing circuit complexity and thus chip area.

[0082] In some embodiments, Figure 5 A circuit diagram of a power control circuit provided in an embodiment of this disclosure is shown below. Figure 5As shown, the positive comparison unit 121 includes a first transistor M1 and a first resistor R1. Among them, the control terminal of the first transistor M1 is connected to the first output terminal of the node voltage generation module 110, the first terminal of the first transistor M1 is connected to the power supply port VCC, the second terminal of the first transistor M1 is connected to the first input terminal of the control module 130 and the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the chip ground GND_CHIP.

[0083] Exemplarily, the first transistor M1 can be a P-type metal oxide semiconductor field effect transistor (P-Metal Oxide Semiconductor Field Effect Transistor, PMOS). The gate of the first transistor M1 is connected to the output terminal of the first node voltage generation unit 111, so the gate voltage of the first transistor M1 is the first internal node voltage Vnode1. The source of the first transistor M1 is connected to the power supply port VCC, so the source voltage of the first transistor M1 is the power supply port voltage Vcc. The drain of the first transistor M1 is connected to the input terminal of the positive signal generation unit 131 and the first terminal of the first resistor R1, so the drain voltage of the first transistor M1 is the first comparison signal.

[0084] The first preset voltage Vth1 is the threshold voltage of the first transistor M1. When the external power signal received by the power supply port VCC contains positive ground bounce noise, Vcc - Vnode1 ≥ Vth1, that is, Vcc ≥ Vnode1 + Vth1. The first transistor M1 is in the conducting state, and the drain voltage of the first transistor M1 is pulled up to the power supply port voltage Vcc. Then, the first comparison signal provided by the positive comparison unit 121 to the positive signal generation unit 131 is the first level signal to disconnect the connection between the power supply port VCC and the positive power supply terminal AVDD of the internal circuit.

[0085] When the external power signal received by the power supply port VCC does not contain positive ground bounce noise, Vcc - Vnode1 < Vth1, that is, Vcc < Vnode1 + Vth1. The first transistor M1 is in the off state, and the drain voltage of the first transistor M1 is pulled down to the chip ground GND_CHIP. Then, the first comparison signal provided by the positive comparison unit 121 to the positive signal generation unit 131 is the second level signal to support the conduction of the connection between the power supply port VCC and the positive power supply terminal AVDD of the internal circuit.

[0086] In some embodiments, continue to refer to Figure 5The negative comparison unit 122 includes a second transistor M2, a second resistor R2, a third resistor R3, and a first capacitor C1. The control terminal of the second transistor M2 is connected to the first plate of the first capacitor C1 and the first terminal of the third resistor R3. The second plate of the first capacitor C1 is connected to the power supply port VCC. The second terminal of the third resistor R3 is connected to the positive power supply terminal AVDD of the internal circuit. The first terminal of the second transistor M2 is connected to the second output terminal of the node voltage generation module 110. The second terminal of the second transistor M2 is connected to the second input terminal of the control module 130 and the first terminal of the second resistor R2. The second terminal of the second resistor R2 is connected to the chip ground GND_CHIP.

[0087] For example, the second transistor M2 can be a PMOS. The gate of the second transistor M2 is connected to the first plate of the first capacitor C1 and the first end of the third resistor R3. When the power supply port voltage Vcc changes, the presence of the first capacitor C1 causes the gate voltage of the second transistor M2 to follow the power supply port voltage Vcc. Therefore, it can be considered that the gate voltage of the second transistor M2 is equal to the power supply port voltage Vcc in the transient state. When the power supply port voltage Vcc does not change, the gate voltage of the second transistor M2 is the internal circuit voltage Vdd, and Vdd = Vcc. Therefore, the gate voltage of the second transistor M2 is equal to the internal circuit voltage Vdd or the power supply port voltage Vcc in the static state.

[0088] The source of the second transistor M2 is connected to the output of the second node voltage generation unit 112, so the source voltage of the second transistor M2 is the second internal node voltage Vnode2. The drain of the second transistor M2 is connected to the input of the negative signal generation unit 132 and the first end of the second resistor R2, so the drain voltage of the second transistor M2 is the second comparison signal.

[0089] The second preset voltage Vth2 is the threshold voltage of the second transistor M2. When the external power signal received by the power port VCC contains negative ground bounce noise, the power port voltage Vcc changes. At this time, the gate voltage of the second transistor M2 is the power port voltage Vcc, Vnode2-Vcc≥Vth2, that is, Vcc+Vth2≤Vnode2. The second transistor M2 is in the on state, and the drain voltage of the second transistor M2 is pulled up to the power port voltage Vcc. Then, the second comparison signal provided by the negative comparison unit 122 to the negative signal generation unit 132 is the first level signal, so as to disconnect the connection between the power port VCC and the positive power supply terminal AVDD of the internal circuit.

[0090] When the external power supply signal received by the power supply port VCC does not contain negative ground bounce noise, if the power supply port VCC is used as an input and the positive power supply terminal AVDD of the internal circuit is used as an output, the gate voltage of the second transistor M2 is the power supply port voltage Vcc, Vnode2 - Vcc < Vth2, that is, Vcc + Vth2 > Vnode2, the second transistor M2 is in an off state, the drain voltage of the second transistor M2 is pulled down to the chip ground GND_CHIP, and the second comparison signal provided by the negative comparison unit 122 to the negative signal generation unit 132 is the second level signal to support the conduction between the power supply port VCC and the positive power supply terminal AVDD of the internal circuit.

[0091] When the external power supply signal received by the power supply port VCC does not contain negative ground bounce noise, if the power supply port VCC is used as an output and the positive power supply terminal AVDD of the internal circuit is used as an input, the gate voltage of the second transistor M2 is the internal circuit voltage Vdd, Vnode2 - Vdd < Vth2, that is, Vdd + Vth2 > Vnode2, the second transistor M2 is in an off state, the drain voltage of the second transistor M2 is pulled down to the chip ground GND_CHIP, and the second comparison signal provided by the negative comparison unit 122 to the negative signal generation unit 132 is the second level signal to support the conduction between the power supply port VCC and the positive power supply terminal AVDD of the internal circuit.

[0092] In some embodiments, continue to refer to Figure 5 , the positive signal generation unit 131 includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a fourth resistor R4.

[0093] Among them, the control end of the third transistor M3 and the control end of the fourth transistor M4 are connected to the first output end of the comparison module 120, the first end of the third transistor M3 and the first end of the fifth transistor M5 are connected to the power supply port VCC, the second end of the third transistor M3 is connected to the second end of the fourth transistor M4 and the control end of the fifth transistor M5, the second end of the fifth transistor M5 is connected to the first end of the fourth resistor R4 and the first control end of the control unit 133, and the second end of the fourth resistor R4 and the first end of the fourth transistor M4 are connected to the chip ground GND_CHIP.

[0094] Exemplarily, the third transistor M3 and the fifth transistor M5 are PMOS, and the fourth transistor M4 is NMOS. The source of the third transistor M3 and the source of the fifth transistor M5 are connected to the power supply port VCC, and the gate of the third transistor M3 and the gate of the fourth transistor M4 are connected to the output end of the positive comparison unit 121, so the gate voltage of the third transistor M3 and the gate voltage of the fourth transistor M4 are the first comparison signal.

[0095] The drain of the third transistor M3 is connected to the drain of the fourth transistor M4 and the gate of the fifth transistor M5. The source of the fourth transistor M4 is connected to the chip ground GND_CHIP. The drain of the fifth transistor M5 is connected to the first terminal of the fourth resistor R4 and the first control terminal of the control unit 133. Therefore, the drain voltage of the fifth transistor M5 is a positive control signal.

[0096] When the external power signal received at the power port VCC contains positive ground bounce noise, the gate voltages of the third transistor M3 and the fourth transistor M4 are equal to the power port voltage Vcc. The third transistor M3 is off and the fourth transistor M4 is on, with its drain voltage pulled low to chip ground GND_CHIP. At this time, the gate voltage of the fifth transistor M5 is pulled low to chip ground GND_CHIP, and the fifth transistor M5 is on. Its drain voltage is pulled high to the power port voltage Vcc. Therefore, the positive control signal provided by the positive signal generation unit 131 to the control unit 133 is a positive disconnect control signal.

[0097] When the external power signal received by the power supply port VCC does not contain forward ground bounce noise, the gate voltages of the third transistor M3 and the fourth transistor M4 are at chip ground GND_CHIP. The third transistor M3 is in the ON state and the fourth transistor M4 is in the OFF state. The drain voltage of the third transistor M3 is pulled high to the power supply port voltage Vcc. At this time, the gate voltage of the fifth transistor M5 is pulled high to the power supply port voltage Vcc. The fifth transistor M5 is in the OFF state, and the drain voltage of the fifth transistor M5 is pulled low to chip ground GND_CHIP. Therefore, the forward control signal provided by the forward signal generation unit 131 to the control unit 133 is a forward conduction control signal.

[0098] In some embodiments, see continue to see Figure 5 The negative signal generation unit 132 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a fifth resistor R5.

[0099] Among them, the control terminals of the sixth transistor M6 and the seventh transistor M7 are connected to the second output terminal of the comparator module 120, the first terminal of the sixth transistor M6 and the first terminal of the eighth transistor M8 are connected to the positive power supply terminal AVDD of the internal circuit, the second terminal of the sixth transistor M6 is connected to the second terminal of the seventh transistor M7 and the control terminal of the eighth transistor M8, the second terminal of the eighth transistor M8 is connected to the first terminal of the fifth resistor R5 and the second control terminal of the control unit 133, and the second terminal of the fifth resistor R5 and the second terminal of the seventh transistor M7 are connected to the chip ground GND_CHIP.

[0100] For example, the sixth transistor M6 and the eighth transistor M8 are PMOS, and the seventh transistor M7 is NMOS. The source of the sixth transistor M6 and the source of the eighth transistor M8 are connected to the positive power supply terminal AVDD of the internal circuit, and the gate of the sixth transistor M6 and the gate of the seventh transistor M7 are connected to the output terminal of the negative comparator unit 122. Then, the gate voltage of the sixth transistor M6 and the gate voltage of the seventh transistor M7 are the second comparison signal.

[0101] The drain of the sixth transistor M6 is connected to the drain of the seventh transistor M7 and the gate of the eighth transistor M8. The source of the seventh transistor M7 is connected to the chip ground GND_CHIP. The drain of the eighth transistor M8 is connected to the first terminal of the fifth resistor R5 and the second control terminal of the control unit 133. Therefore, the drain voltage of the eighth transistor M8 is a negative control signal.

[0102] When the external power signal received by the power supply port VCC contains negative ground bounce noise, the gate voltages of the sixth transistor M6 and the seventh transistor M7 are equal to the internal circuit voltage Vdd. The sixth transistor M6 is in the off state, and the seventh transistor M7 is in the on state. The drain voltage of the seventh transistor M7 is pulled low to the chip ground GND_CHIP. At this time, the gate voltage of the eighth transistor M8 is pulled low to the chip ground GND_CHIP, and the eighth transistor M8 is in the on state. The drain voltage of the eighth transistor M8 is pulled high to the internal circuit voltage Vdd. Therefore, the negative control signal provided by the negative signal generation unit 132 to the control unit 133 is a negative disconnect control signal.

[0103] When the external power signal received by the power supply port VCC does not contain negative ground bounce noise, the gate voltage of the sixth transistor M6 and the gate voltage of the seventh transistor M7 are chip ground GND_CHIP. The sixth transistor M6 is in the on state and the seventh transistor M7 is in the off state. The drain voltage of the sixth transistor M6 is pulled high to the internal circuit voltage Vdd. At this time, the gate voltage of the eighth transistor M8 is pulled high to the internal circuit voltage Vdd. The eighth transistor M8 is in the off state, and the drain voltage of the eighth transistor M8 is pulled low to chip ground GND_CHIP. Therefore, the negative control signal provided by the negative signal generation unit 132 to the control unit 133 is a negative conduction control signal.

[0104] In some embodiments, see continue to see Figure 5The control unit 133 includes a ninth transistor M9 and a tenth transistor M10. The control terminal of the ninth transistor M9 is connected to the output terminal of the positive signal generation unit 131, and the control terminal of the tenth transistor M10 is connected to the output terminal of the negative signal generation unit 132. The first terminal of the ninth transistor M9 is connected to the power supply port VCC, the first terminal of the tenth transistor M10 is connected to the positive power supply terminal AVDD of the internal circuit, and the second terminal of the ninth transistor M9 is connected to the second terminal of the tenth transistor M10.

[0105] For example, the ninth transistor M9 and the tenth transistor M10 are PMOS. The gate of the ninth transistor M9 is connected to the output terminal of the positive signal generation unit 131, so the gate voltage of the ninth transistor M9 is a positive control signal. The gate of the tenth transistor M10 is connected to the output terminal of the negative signal generation unit 132, so the gate voltage of the tenth transistor M10 is a negative control signal.

[0106] The source of the ninth transistor M9 is connected to the power supply port VCC, the source of the tenth transistor M10 is connected to the positive power supply terminal AVDD of the internal circuit, and the drain of the ninth transistor M9 is connected to the drain of the tenth transistor M10.

[0107] Figure 6 This is a schematic diagram of the voltage at each node in a power supply control circuit provided in this disclosure, as shown below. Figure 6 As shown, during the time period T0 to T1, the external power signal received by the power supply port VCC does not contain ground bounce noise. The gate voltage of the ninth transistor M9 and the gate voltage of the tenth transistor M10 are pulled down to the chip ground GND_CHIP, while the source-gate voltage VSG_M9 of the ninth transistor M9 and the source-gate voltage VSG_M10 of the tenth transistor M10 are maintained at 5V.

[0108] At this time, the source-gate voltage VSG_M9 of the ninth transistor M9 is greater than the threshold voltage of the ninth transistor M9, and the source-gate voltage VSG_M10 of the tenth transistor M10 is greater than the threshold voltage of the tenth transistor M10. The ninth transistor M9 and the tenth transistor M10 are in the on state, so that the power supply port VCC is connected to the positive power supply terminal AVDD of the internal circuit. Then the internal circuit voltage Vdd is equal to the power supply port voltage Vcc.

[0109] like Figure 6 As shown, during the time period T1 to T2, the external power signal received by the power supply port VCC contains negative ground bounce noise. The gate voltage of the tenth transistor M10 is pulled up to the internal circuit voltage Vdd, and the source-gate voltage VSG_M10 of the tenth transistor M10 drops to 0. Therefore, the source-gate voltage VSG_M10 of the tenth transistor M10 is less than the threshold voltage of the tenth transistor M10, and the tenth transistor M10 is in the off state.

[0110] At this time, the gate voltage of the ninth transistor M9 gradually increases from the chip ground GND_CHIP, and the source-gate voltage VSG_M10 of the ninth transistor M9 gradually decreases. However, the ninth transistor M9 remains in the on state. Since the ninth transistor M9 and the tenth transistor M10 are connected in series, the disconnection of the tenth transistor M10 can disconnect the connection between the power supply port VCC and the positive power supply terminal AVDD of the internal circuit, preventing reverse ground bounce noise from entering the internal circuit. The internal circuit voltage Vdd remains the voltage of the previous state.

[0111] like Figure 6 As shown, during the time period T2 to T3, the external power signal received by the power supply port VCC contains positive ground bounce noise. The gate voltage of the ninth transistor M9 is pulled up to the power supply port voltage Vcc, and the source-gate voltage VSG_M9 of the ninth transistor M9 drops to 0. Therefore, the source-gate voltage VSG_M9 of the ninth transistor M9 is less than the threshold voltage of the ninth transistor M9, and the ninth transistor M9 is in the off state.

[0112] At this time, the source-gate voltage VSG_M10 of the tenth transistor M10 remains at 0, and the tenth transistor M10 is in the off state, which disconnects the connection between the power supply port VCC and the positive power supply terminal AVDD of the internal circuit, preventing positive ground bounce noise from entering the internal circuit. The internal circuit voltage Vdd remains at the voltage of the previous state.

[0113] like Figure 6 As shown, during the T3 to T4 time period, the external power supply signal does not contain negative ground bounce noise. The gate voltage of the ninth transistor M9 and the gate voltage of the tenth transistor M10 are pulled down to the chip ground GND_CHIP, and the source-gate voltage VSG_M9 of the ninth transistor M9 and the source-gate voltage VSG_M10 of the tenth transistor M10 gradually rise to 5V.

[0114] In some embodiments, see continue to see Figure 5 The first node voltage generation unit 111 includes a sixth resistor R6 and a second capacitor C2. The first end of the sixth resistor R6 is connected to the power supply port VCC, and the second end of the sixth resistor R6 is connected to the first plate of the second capacitor C2 and the first input terminal of the comparator module 120. The second plate of the second capacitor C2 is connected to the chip ground GND_CHIP.

[0115] For example, the second end of the sixth resistor R6 is connected to the input terminal of the positive comparator unit 121, and the second end of the sixth resistor R6 is connected to the chip ground GND_CHIP through the second capacitor C2. Then the second capacitor C2 can stabilize the voltage at the second end of the sixth resistor R6, that is, it can stabilize the power supply port voltage Vcc, thereby obtaining the first internal node voltage Vnode1, so as to provide a stable first internal node voltage Vnode1 to the positive comparator unit 121.

[0116] In some embodiments, see continue to see Figure 5 The second node voltage generation unit 112 includes a seventh resistor R7 and a third capacitor C3. The first end of the seventh resistor R7 is connected to the positive power supply terminal AVDD of the internal circuit. The second end of the seventh resistor R7 is connected to the first plate of the third capacitor C3 and the second input terminal of the comparator module 120. The second plate of the third capacitor C3 is connected to the chip ground GND_CHIP.

[0117] For example, the second end of the seventh resistor R7 is connected to the input terminal of the negative comparator unit 122, and the second end of the seventh resistor R7 is connected to the chip ground GND_CHIP through the third capacitor C3. Then the third capacitor C3 can stabilize the voltage at the second end of the seventh resistor R7, that is, it can stabilize the internal circuit voltage Vdd, thereby obtaining the second internal node voltage Vnode2, so as to provide a stable second internal node voltage Vnode2 to the negative comparator unit 122.

[0118] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” are to be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” should be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, the “example” is merely exemplary and illustrative, and should not be considered exclusive or extensive.

[0119] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A power control circuit for a chip, characterized by, The chip comprises a power port and an internal circuit, and the power control circuit comprises a node voltage generation module, a comparison module and a control module; The node voltage generation module is configured to establish a stable first internal node voltage according to a power port voltage and a stable second internal node voltage according to an internal circuit voltage, wherein the power port voltage is the voltage of an external power signal received by the power port, and the internal circuit voltage is the power supply voltage of the internal circuit; The comparison module is configured to compare the first internal node voltage and the power port voltage to obtain a first comparison signal, and compare the second internal node voltage and the power port voltage to obtain a second comparison signal; The control module is configured to control the on-off of the power port and the power supply end of the internal circuit according to the first comparison signal and the second comparison signal, so as to avoid the ground bounce noise in the external power signal from entering the internal circuit; The comparison module comprises a positive comparison unit and a negative comparison unit; The positive comparison unit is configured to determine the first comparison signal as a first level signal when the power port voltage is greater than or equal to the sum of the first internal node voltage and a first preset voltage, so as to determine that the external power signal contains positive ground bounce noise; and determine the first comparison signal as a second level signal when the power port voltage is less than the sum of the first internal node voltage and the preset voltage, so as to determine that the external power signal does not contain the positive ground bounce noise. The negative comparison unit is configured to determine the second comparison signal as the first level signal when the sum of the power port voltage and a second preset voltage is less than or equal to the second internal node voltage, so as to determine that the external power signal contains reverse ground bounce noise; and determine the second comparison signal as the second level signal when the sum of the power port voltage and the second preset voltage is greater than the second internal node voltage, so as to determine that the external power signal does not contain the reverse ground bounce noise.

2. The power control circuit of claim 1, wherein The positive comparison unit comprises a first transistor and a first resistor; The control end of the first transistor is connected to the first output end of the node voltage generation module, the first end of the first transistor is connected to the power port, the second end of the first transistor is connected to the first input end of the control module and the first end of the first resistor, and the second end of the first resistor is connected to the chip ground.

3. The power control circuit of claim 1, wherein The negative comparison unit comprises a second transistor, a second resistor, a third resistor and a first capacitor; The control end of the second transistor is connected to the first plate of the first capacitor and the first end of the third resistor, the second plate of the first capacitor is connected to the power port, the second end of the third resistor is connected to the power supply end of the internal circuit, the first end of the second transistor is connected to the second output end of the node voltage generation module, the second end of the second transistor is connected to the second input end of the control module and the first end of the second resistor, and the second end of the second resistor is connected to the chip ground.

4. The power control circuit of claim 1, wherein The control module comprises a positive signal generation unit, a negative signal generation unit and a control unit; The input end of the positive signal generation unit is connected with the first output end of the comparison module, the output end of the positive signal generation unit is connected with the first control end of the control unit, the input end of the negative signal generation unit is connected with the second output end of the comparison module, the output end of the negative signal generation unit is connected with the second control end of the control unit, the input end of the control unit is connected with the power port, and the output end of the control unit is connected with the power end of the internal circuit; The positive signal generation unit is configured to generate a positive control signal according to the first comparison signal, and the positive control signal comprises a positive on control signal and a positive off control signal; The negative signal generation unit is configured to generate a negative control signal according to the second comparison signal, and the negative control signal comprises a negative on control signal and a negative off control signal; The control unit is configured to turn on the connection between the power port and the power end of the internal circuit when the positive control signal is the positive on control signal and the negative control signal is the negative on control signal, and turn off the connection between the power port and the power end of the internal circuit when the positive control signal is the positive off control signal or the negative control signal is the negative off control signal, so as to avoid the ground bounce noise from entering the internal circuit.

5. The power control circuit of claim 4, wherein, The positive signal generation unit comprises a third transistor, a fourth transistor, a fifth transistor and a fourth resistor; The control end of the third transistor and the control end of the fourth transistor are connected with the first output end of the comparison module, the first end of the third transistor and the first end of the fifth transistor are connected with the power port, the second end of the third transistor is connected with the second end of the fourth transistor and the control end of the fifth transistor, the second end of the fifth transistor is connected with the first end of the fourth resistor and the first control end of the control unit, and the second end of the fourth resistor and the first end of the fourth transistor are connected with the chip ground.

6. The power control circuit of claim 4, wherein, The negative signal generation unit comprises a sixth transistor, a seventh transistor, an eighth transistor and a fifth resistor; The control end of the sixth transistor and the control end of the seventh transistor are connected with the second output end of the comparison module, the first end of the sixth transistor and the first end of the eighth transistor are connected with the power end of the internal circuit, the second end of the sixth transistor is connected with the second end of the seventh transistor and the control end of the eighth transistor, the second end of the eighth transistor is connected with the first end of the fifth resistor and the second control end of the control unit, and the second end of the fifth resistor and the second end of the seventh transistor are connected with the chip ground.

7. The power control circuit of claim 4, wherein, The control unit comprises a ninth transistor and a tenth transistor; A control end of the ninth transistor is connected to an output end of the positive signal generation unit, a control end of the tenth transistor is connected to an output end of the negative signal generation unit, a first end of the ninth transistor is connected to the power port, a first end of the tenth transistor is connected to a power end of the internal circuit, and a second end of the ninth transistor is connected to a second end of the tenth transistor.

8. The power control circuit of any one of claims 1-7, wherein, The node voltage generation module comprises a sixth resistor, a seventh resistor, a second capacitor and a third capacitor. A first end of the sixth resistor is connected to the power port, a second end of the sixth resistor is connected to a first plate of the second capacitor and a first input end of the comparison module, a first end of the seventh resistor is connected to a power end of the internal circuit, a second end of the seventh resistor is connected to a first plate of the third capacitor and a second input end of the comparison module, and a second plate of the second capacitor and a second plate of the third capacitor are connected to a chip ground.

9. A chip, characterized by The power supply control circuit comprises a power port, an internal circuit and the power supply control circuit according to any one of claims 1-8.

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