A chip verification method, system and medium based on UVM

Abstract

The present invention relates to the field of chip verification, and specifically to a chip verification method, system and medium based on UVM. The present invention comprises: building a verification platform based on UVM, dividing the verification level according to the verification function points, dividing the function points belonging to the same verification level, and developing the function points that can be cross-verified into a test case. In addition to the basic configuration, the test case of each verification level controls the specific implementation of the corresponding function points through simulation parameters. The verification method is controlled by a script, and random or specified simulation parameters can be selected to cross-verify the function points belonging to the same level, without the need to develop directional use cases separately for the verification of different function points; at the same time, when verifying different function points through simulation parameter control, there is no need to recompile the design to be tested and the verification environment, which effectively improves the verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip verification, and in particular to a UVM-based chip verification method, system and medium. Background Art

[0002] UVM verification methodology is currently the most commonly used standard verification methodology in chip verification. The UVM-based verification platform effectively improves the development efficiency of complex verification environments through object-oriented verification methods, high reusability and strong scalability.

[0003] In the chip verification front-end verification process of large-scale digital integrated circuits, when verifying test cases, usually, test cases for verifying different functional points or different paths need to be written separately. When mixed verification of multiple functional points is performed, test cases also need to be developed separately, which increases the workload of the verifiers and reduces the verification efficiency. Summary of the invention

[0004] In view of the defects of the prior art, the present invention provides a chip verification method, system and medium based on UVM, which sets a function point verification execution switch and randomly selects function points for single or cross verification in combination with script control. At the same time, the function point verification is controlled by simulation parameters, and once compiled, cross verification of multiple different function points can be realized, which reduces compilation time and improves verification efficiency.

[0005] In order to solve the technical problem, the technical solution adopted by the present invention is: a chip verification method based on UVM, the method includes two parts: test case division and random function point generation; Test case division First, the verification level of each function point is divided according to the function points listed in the verification plan and the configuration required for verification of each function point. Then, the test cases are preliminarily divided according to the characteristics of the verification function points of the level to which they belong. For function points of the same level, the paths or function points that support cross-verification are developed into one test case. In the test case, a switch is set for the verification of each function point to control whether the verification of the function point is turned on or off. The generation of random function points is controlled by a script. The script connects the configuration file and the command line input. The script obtains the information of random function points and the level information of the test case by reading the configuration file. The configuration file contains the test case level, the number of function points included in each level, and the switch parameter information of all function points developed at each level. After the environment compilation is completed, the script first obtains and parses the command line input, which includes the test case name, the number of random function points executed, the simulation parameters and corresponding values ​​of one or more function points in the test case hierarchy, and then judges the parsed information. First, it judges whether the number of random function points for verification is entered. If so, it continues to judge whether the number of random function points is less than or equal to the number of verification function points supported by the test case. If it is not less than, an error log is output. If it is less than, the function points supported by the test case are searched, the corresponding number of function points are randomly selected, the verification switch of the selected function points is turned on, and random parameter values ​​are generated according to the set parameter value range. The random parameter values ​​corresponding to the function points and other configuration information are transmitted to the verification platform to complete the verification; If the number of random function points to be verified is not entered, it will continue to determine whether the simulation parameters corresponding to the function points are entered. If yes, the verification switch of the function point is turned on and the simulation parameters corresponding to the function point and other configuration information are transmitted to the verification platform. Otherwise, the test case name and other configuration information are transmitted to the verification platform. In the above description, other configuration information is general configuration and has nothing to do with function point verification, such as the selection of random seeds, the redundancy of printed information, etc.

[0006] Furthermore, the function point verification switch is controlled by a simulation parameter, and the function point verification switch is set to a number or a character string.

[0007] Furthermore, for special function configuration, the function point verification switch is controlled by compiling parameters. Special function configuration is an additional configuration for specific functions, mainly referring to some configurations such as switching models and matrix loading. Because it is a compilation parameter, it can also be classified into the hierarchical division.

[0008] Furthermore, the verification function points are bound to the divided verification levels, and the test cases only support random verification of the function points of their level.

[0009] Furthermore, when the number of random function points to be verified is not input but the corresponding simulation parameters of the function points are input, the number of function points of the input simulation parameters is one or more, the switch parameters of the function points to be verified and their corresponding values ​​are passed into the script, and the script generates simulation commands to control the execution of the function point verification.

[0010] Furthermore, when the number of random function points to be verified is not input and the simulation parameters corresponding to the function points are not input, that is, when the test case is input and the number of random function points is not input, the script randomly turns on the verification switch of the function point and executes the test case randomly.

[0011] Furthermore, function coverage points are set for all function points, and the completeness of function point verification is perceived through function coverage.

[0012] The present invention also discloses a UVM-based chip verification system, comprising a processor and a memory storing program instructions, wherein the processor is configured to execute the UVM-based chip verification method as described above when running the program instructions.

[0013] The present invention also discloses a storage medium storing program instructions, wherein the program instructions execute the UVM-based chip verification method as described above when running.

[0014] The beneficial effects of the present invention are as follows: the present invention divides verification levels and develops use cases according to verification function points, which facilitates verification use case management and use case regression; the verification function points are controlled by simulation parameters to achieve random verification of different function points, without the need to separately develop targeted use cases for verification of different function points, thereby reducing use case development time; at the same time, through script control, simulation parameters corresponding to function points can be randomly selected for cross-verification, and there is no need to recompile the design to be tested and the verification environment when verifying different function points, thereby shortening the verification time and effectively improving the verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the UVM verification platform; Figure 2 Flowchart divided into test cases; Figure 3 Flowchart generated for random function points. DETAILED DESCRIPTION

[0016] The present invention will be further described below in conjunction with the accompanying drawings and specific implementations.

[0017] Example 1 The present embodiment discloses a chip verification method based on UVM, which includes: building a verification platform based on UVM, dividing the verification levels according to the verification function points, dividing the function points belonging to the same verification level, and developing the cross-verifiable function points into a test case. In addition to the basic configuration, the test case of each verification level controls the specific implementation of the corresponding function points through simulation parameters. The verification method is controlled by a script, and can select random or specified simulation parameters to cross-verify the function points belonging to the same level, without the need to develop directional use cases separately for the verification of different function points; at the same time, when verifying different function points through simulation parameter control, there is no need to recompile the design to be tested and the verification environment, which effectively improves the verification efficiency.

[0018] like Figure 1As shown, a UVM verification platform is built according to the function of the module to be tested, including a stimulus generator, a monitoring module, a reference model, a scoreboard and a design to be tested. The verification platform obtains configuration information through a script, and inputs the corresponding information into the stimulus generator to drive the design to be tested. The monitoring module monitors the input and output information of the design to be tested and transmits it to the reference model; the use case execution result is verified in the scoreboard.

[0019] According to the function points listed in the verification plan and the configuration required for verification of each function point, the verification level of each function point is divided. Then, according to the characteristics of the verification function points at the level to which they belong, the verification use cases are preliminarily divided, such as Figure 2 As shown. For example, if base_test is regarded as the A level, then based on this level, the function points that need to configure the B operation of the design under test to verify are classified as the B level; based on the configuration of the B level, the function points that need to configure the C operation additionally are classified as the C level, and so on. Based on the above hierarchical division, the function points belonging to the same level will develop the paths or function points that support cross-validation into a test case. Different function points in the same test case are realized through simulation parameter control. In the test case, a switch is set for the verification of each function point to control the opening or closing of the verification of the function point. The function point verification switch is controlled by the simulation parameter, and the function point verification switch can be set to a number or a string. In addition, for special function configuration, it can be controlled by compilation parameters. Special function configuration is an additional configuration for specific functions, mainly referring to some configurations such as switching models and matrix loading. Because it is a compilation parameter, it can also be classified as a hierarchical division. The verification function point is bound to the divided verification level, that is, the test case only supports random verification of the function points of the level where the case is located.

[0020] Based on the above configuration, the function points of the test case are randomly controlled by the script during verification. The script connects the configuration file and the command line input. The script obtains the information of the random function points and the level information of the test case by reading the configuration file. The configuration file contains the test case level, the number of function points included in each level, and the switch parameter information of all function points developed at each level (such as the switch parameter name, the range of possible values, etc.).

[0021] After the environment is compiled, the script first obtains and parses the command line input, which includes the test case name, the number of random function points executed, the simulation parameters and corresponding values ​​of one or more function points in the test case hierarchy, and then makes a judgment on the parsed information.

[0022] like Figure 3As shown, first determine whether the number of random function points to be verified is entered. If yes, continue to determine whether the number of random function points is less than or equal to the number of verification function points supported by the test case. If not, output the error log. If less, find the function points supported by the test case, randomly select the corresponding number of function points, turn on the verification switch of the selected function points, generate random parameter values ​​according to the set parameter value range, transmit the corresponding parameter random values ​​and other configuration information of the function points to the verification platform, and complete the verification. This process corresponds to the random cross-validation of function points. The script obtains the name of the test case to be executed and the number of random function points, randomly selects to turn on the function point verification switch, and controls the execution of simulation commands through simulation parameters, thereby realizing the random cross-validation of the function points of the test case.

[0023] If the number of random function points to be verified is not entered, it will continue to determine whether the corresponding simulation parameters of the function points are entered. If yes, the verification switch of the function point is turned on and the corresponding simulation parameters and other configuration information of the function point are transmitted to the verification platform. This process corresponds to the verification of one or more specified function points, and the switch parameters of the function points to be verified and their corresponding values ​​are passed into the script, so that the script generates simulation commands, and the simulation parameters control the execution of the function point verification. In the above description, other configuration information is general configuration and has nothing to do with function point verification, such as the selection of random seeds, the redundancy of printed information, etc.

[0024] When the number of random function points to be verified is not entered and the corresponding simulation parameters of the function points are not entered, that is, only the test case is entered without entering the number of random function points, the script randomly turns on the verification switch of the function point and executes the test case randomly.

[0025] If the number of verification function points or test case information passed in does not match the configuration file, an error log is output and the program exits.

[0026] Functional coverage points are set for each development function point, and the completeness of the function point verification is ultimately perceived through the functional coverage rate.

[0027] Example 2 The embodiment of the present disclosure provides a chip verification system based on UVM, including a processor and a memory. Optionally, the device may also include a communication interface and a bus. The processor, the communication interface, and the memory may communicate with each other through the bus. The communication interface may be used for information transmission. The processor may call the logic instructions in the memory to execute the chip verification method based on UVM of the above embodiment.

[0028] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0029] The memory, as a computer-readable storage medium, can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor executes functional applications and data processing by running the program instructions / modules stored in the memory, that is, implementing the chip verification method based on UVM in the above embodiment.

[0030] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory may include a high-speed random access memory and may also include a non-volatile memory.

[0031] Example 3 An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the UVM-based chip verification method.

[0032] The computer-readable storage medium mentioned above may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0033] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, including: a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes, or a transient storage medium.

[0034] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the scope of protection. As used in the description in the text, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method or device including the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0035] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians may clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

Claims

1. A chip verification method based on UVM, characterized in that: This method includes two parts: test case division and random function point generation; Test case division First, the verification level of each function point is divided according to the function points listed in the verification plan and the configuration required for verification of each function point. Then, the test cases are preliminarily divided according to the characteristics of the verification function points of the level to which they belong. For function points of the same level, the paths or function points that support cross-verification are developed into one test case. In the test case, a switch is set for the verification of each function point to control whether the verification of the function point is turned on or off. The generation of random function points is controlled by a script. The script connects the configuration file and the command line input. The script obtains the information of random function points and the level information of the test case by reading the configuration file. The configuration file contains the test case level, the number of function points included in each level, and the switch parameter information of all function points developed at each level. After the environment compilation is completed, the script first obtains and parses the command line input, which includes the test case name, the number of random function points executed, the simulation parameters and corresponding values ​​of one or more function points in the test case hierarchy, and then judges the parsed information. First, it judges whether the number of random function points for verification is entered. If so, it continues to judge whether the number of random function points is less than or equal to the number of verification function points supported by the test case. If it is not less than, an error log is output. If it is less than, the function points supported by the test case are searched, the corresponding number of function points are randomly selected, the verification switch of the selected function points is turned on, and random parameter values ​​are generated according to the set parameter value range. The random parameter values ​​corresponding to the function points and other configuration information are transmitted to the verification platform to complete the verification; If the number of random function points to be verified is not entered, continue to determine whether the simulation parameters corresponding to the function points are entered. If so, turn on the function point verification switch and transmit the simulation parameters and other configuration information corresponding to the function points to the verification platform. Otherwise, transmit the test case name and other configuration information to the verification platform.

2. The chip verification method based on UVM according to claim 1, characterized in that: The function point verification switch is controlled by simulation parameters, and the function point verification switch is set to a number or a string.

3. The chip verification method based on UVM according to claim 2, characterized in that: For special function configuration, the function point verification switch is controlled by compiling parameters.

4. The chip verification method based on UVM according to claim 1, characterized in that: Verification function points are bound to the divided verification levels, and test cases only support random verification of function points at their level.

5. The chip verification method based on UVM according to claim 1, characterized in that: When there is no input for the number of random function points to be verified but there are corresponding simulation parameters for the input function points, the number of function points for the input simulation parameters is one or more, the switch parameters of the function points to be verified and their corresponding values ​​are passed into the script, and the script generates simulation commands to control the execution of the function point verification.

6. The chip verification method based on UVM according to claim 1, characterized in that: When the number of random function points to be verified is not entered and the corresponding simulation parameters of the function points are not entered, that is, when the test case is entered and the number of random function points is not entered, the script randomly turns on the verification switch of the function point and executes the test case randomly.

7. The chip verification method based on UVM according to claim 1, characterized in that: Functional coverage points are set for all function points, and the completeness of function point verification is perceived through functional coverage.

8. A chip verification system based on UVM, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the UVM-based chip verification method according to any one of claims 1 to 7 when running the program instructions.

9. A storage medium storing program instructions, characterized in that: When the program instructions are run, the UVM-based chip verification method according to any one of claims 1 to 7 is executed.

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