A chip layout structure and design method
By distinguishing the digital layout area from the simulated layout in the chip layout structure, and introducing simulated layout partitioning and simplifying line layout in the simulated layout area, problems such as irregular module shapes and complex power lines and ground lines in the existing technology have been solved, and more efficient area utilization and performance improvement have been achieved.
Patent Information
- Application Number
- CN202411793799.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-04-01
AI Technical Summary
The existing analog circuit layout structure has problems such as irregular module shape, complex power lines and ground lines, and complex interface signal lines, resulting in increased chip area and cost, and the power lines, ground lines and interface signal lines interfere with each other, affecting chip performance.
A chip layout structure is proposed. By distinguishing the digital layout area from the analog layout area and introducing M simulation layout partitions into the simulation layout area, the simulation modules are highly consistent in each partition, the power line and ground wire are arranged at the center of the simulation module, and the interface signal lines are arranged outside the analog layout partition, which simplifies the line layout and connection.
The overall floorplan shape of the analog layout area is realized, the area utilization rate of the digital layout area is improved, the power line and ground connection between the analog modules is simplified, the chip area and cost are reduced, and the mutual interference between the power line, ground line and interface signal line is reduced, and the chip performance is improved.
Smart Images
Figure CN119740540A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip layout structure and a design method. Background Art
[0002] Chip layout design is an important step in chip design. Controlling the size of the chip in the layout design and then reducing the size of the chip by optimizing the layout structure can effectively control the cost of the chip.
[0003] Mixed signal chips usually contain analog circuits and digital circuits. The analog circuits usually contain multiple analog modules. The existing analog circuit layout structure is as follows: Figure 1 As shown. The existing analog circuit layout has the following characteristics: the sizes of multiple analog module layouts are unrelated, the widths and heights of different modules are relatively random, and the overall layout of the chip (floorplan) mainly depends on the layout engineer to arrange them as neatly as possible; the power lines and ground lines between multiple analog module layouts are unrelated, the access positions of the power lines and ground lines may be at various positions of the analog modules, and the widths of the power lines and ground lines are usually relatively random. During chip integration, the layout engineer needs to connect them through a complex power line network and ground line network; the interface signal lines between multiple analog module layouts are unrelated, and the access positions of the interface signal lines are usually relatively random. During chip integration, the layout engineer needs to connect them through a complex interface signal line network.
[0004] Figure 1 The existing analog circuit layout method shown is a common method in the industry, and its disadvantages are obvious:
[0005] 1. The shapes and sizes of various analog modules are different, and there are often some spaces left blank, which cannot be fully utilized and wastes area; the overall floorplan of the analog module is irregular in shape. In order to save area as much as possible, the overall floorplan of the digital module will also be made into an irregular shape according to the overall floorplan of the analog module, thereby reducing the area utilization of the digital module.
[0006] 2. The routing network of power lines and ground lines between analog modules is complex. Usually, the routing width of power lines and ground lines is relatively large, and the routing spacing between different analog modules needs to be increased, which not only increases the connection length and parasitic resistance, but also increases the chip area and cost.
[0007] 3. The routing network of the input and output interface signal lines of the analog module is complex. The number of interface signal lines is usually large, and there is no consistent planning of interface signal line channels, which leads to the need to increase the routing spacing and connection complexity between modules, thereby increasing the chip area and cost.
[0008] 4. The power line, ground line and interface signal line are all together, and the spacing between different lines is very small, which increases the mutual interference between the power line, ground line and interface signal line, thereby affecting the function of the chip or reducing the performance of the chip. Summary of the invention
[0009] In view of some or all of the problems in the prior art, the present invention provides a chip layout structure, which includes a digital layout area and an analog layout area, wherein the digital layout area is separated from the analog layout area, the digital layout area is arranged with digital modules, and the analog layout area is arranged with analog modules;
[0010] The analog layout area includes M analog layout partitions, namely the first analog layout partition, the second analog layout partition, ..., the Mth analog layout partition, the first analog layout partition, the second analog layout partition, ..., the Mth analog layout partition are respectively arranged in the first row, the second row ..., the Mth row of the analog layout area, the M analog layout partitions are aligned in the column direction, and M is an integer not less than 1; the digital layout area is arranged on the left or right side of the analog layout area;
[0011] The interface signal line is arranged outside the M analog layout partitions, and the interface signal line is connected to the analog modules in the M analog layout partitions and the digital layout area;
[0012] Each analog layout partition contains no more than N analog modules, and the analog modules arranged in each analog layout partition are aligned in a row direction, where N is an integer not less than 1;
[0013] If an analog layout partition arranges K first analog modules with the same size in the column direction in a column, the power lines and ground lines of the analog layout partition are arranged at the center of the K first analog modules in the column direction, and K is an integer not less than 1.
[0014] Further, the first simulation layout partition, the second simulation layout partition, ..., the Mth simulation layout partition are respectively arranged in the first column, the second column ..., the Mth column of the simulation layout area, and the M simulation layout partitions are aligned in the row direction, and M is an integer not less than 1;
[0015] The digital layout area is arranged on the upper side or the lower side of the analog layout area.
[0016] Furthermore, each analog layout partition includes analog modules with the same size in the column direction on different columns.
[0017] Furthermore, the analog module is an analog-to-digital converter or a digital-to-analog converter or a reset power supply or a low-dropout voltage regulator or an oscillator or an amplifier or a phase-locked loop or a DC-DC converter or a reference voltage circuit.
[0018] Furthermore, the widths of the power line and the ground line are the same or different.
[0019] Furthermore, an analog layout partition arranges two first analog modules with the same size in the column direction in one column, and arranges one second analog module with a size twice that of the first analog module in the column direction in another column, and the power line and ground line of the analog layout partition are arranged at the center of the size of the first analog module in the column direction and at 3 / 4 and 1 / 4 of the size of the second analog module in the column direction.
[0020] The present invention also provides a chip layout design method, which comprises the following steps:
[0021] Establishing a layout size relationship between multiple analog modules, arranging the multiple analog modules in an analog layout area, wherein the analog layout area includes a first analog layout partition, a second analog layout partition, ..., and an Mth analog layout partition, wherein the first analog layout partition, the second analog layout partition, ..., and the Mth analog layout partition are respectively arranged in the first row, the second row ..., and the Mth row of the analog layout area, wherein the M analog layout partitions are aligned in a column direction, and M is an integer not less than 1; arranging the digital layout area on the left or right side of the analog layout area;
[0022] Arrange the positions of power lines and ground lines between multiple analog modules. If a simulation layout partition arranges K first analog modules with the same size in the column direction in a column, the power lines and ground lines of the simulation layout partition are arranged at the center of the size of the K first analog modules in the column direction, and K is an integer not less than 1;
[0023] Arrange the interface signal line position, the interface signal line is arranged outside the M analog layout partitions, and the interface signal line is connected to the analog modules in the M analog layout partitions and the digital layout area.
[0024] Further, the first simulation layout partition, the second simulation layout partition, ..., the Mth simulation layout partition are respectively arranged in the first column, the second column ..., the Mth column of the simulation layout area, and the M simulation layout partitions are aligned in the row direction, and M is an integer not less than 1;
[0025] The digital layout area is arranged on the upper side or the lower side of the analog layout area.
[0026] Furthermore, each analog layout partition includes analog modules with the same size in the column direction on different columns.
[0027] The present invention also provides a computer-readable storage medium on which machine-readable instructions are stored. When the machine-readable instructions are executed by a processor, the steps of the chip layout design method are executed.
[0028] The technical solution provided by the present invention has the following beneficial effects:
[0029] 1. In the chip layout structure provided by the present invention, each analog module in the analog layout area is highly consistent, the overall floorplan shape of the analog layout area is relatively regular, with less empty space, and the overall floorplan shape of the digital layout area is also correspondingly regular, thereby improving the area utilization rate of the digital layout area.
[0030] 2. In the chip layout structure provided by the present invention, the power lines and ground lines between analog modules can be automatically aligned and connected, which saves the wiring spacing between analog modules and the parasitic capacitance and parasitic resistance of the connecting wiring, saving chip area and cost.
[0031] 3. In the chip layout structure provided by the present invention, the input and output interface signal lines of the analog module are all outside the analog module, which makes the connection simple, shortens the wiring distance, saves the wiring spacing between the analog modules, and saves chip area and cost.
[0032] 4. In the chip layout structure provided by the present invention, the power lines, ground lines and interface signal lines are not arranged together and do not interfere with each other, thereby improving the performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] To further illustrate the above and other advantages and features of various embodiments of the present invention, a more specific description of various embodiments of the present invention will be presented with reference to the accompanying drawings. It will be understood that these drawings only depict typical embodiments of the present invention and are therefore not to be considered as limiting the scope thereof. In the accompanying drawings, for clarity, identical or corresponding parts will be represented by identical or similar reference numerals.
[0034] Figure 1 It is a schematic diagram of the existing chip layout structure;
[0035] Figure 2 A schematic diagram of a chip layout structure according to an embodiment of the present invention;
[0036] Figure 3 A schematic diagram of a chip layout structure according to another embodiment of the present invention; and
[0037] Figure 4 The figure is a flow chart of a chip layout design method according to an embodiment of the present invention. DETAILED DESCRIPTION
[0038] In the following description, the present invention is described with reference to various embodiments. However, those skilled in the art will recognize that various embodiments may be implemented without one or more specific details or with other replacement and / or additional methods or components. In other cases, well-known structures or operations are not shown or described in detail to avoid obscuring the inventive point of the present invention. Similarly, for the purpose of explanation, specific numbers and configurations are set forth to provide a comprehensive understanding of embodiments of the present invention. However, the present invention is not limited to these specific details.
[0039] In this specification, reference to "one embodiment" or "the embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present invention. The phrase "in one embodiment" appearing in various places in this specification does not necessarily all refer to the same embodiment.
[0040] In this specification, unless otherwise specified, the quantifiers "plurality" and "multiple" refer to one or more than one element.
[0041] It should be noted that the embodiments of the present invention describe the method steps in a specific order, but this is only for the purpose of illustrating the specific embodiment, rather than limiting the order of the steps. On the contrary, in different embodiments of the present invention, the order of the steps can be adjusted according to actual needs.
[0042] In view of the shortcomings of the prior art, the present invention proposes a new chip layout structure. This layout structure makes the overall layout more regular, the power line and the signal line straighter, reduces the winding length, and saves the routing spacing, which can save the chip area and cost and improve the chip performance.
[0043] The technical solutions in the embodiments of the present invention are described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.
[0044] The chip layout structure provided by the present invention comprises a digital layout area and an analog layout area, wherein the digital layout area is separated from the analog layout area, the digital layout area is arranged with digital modules, and the analog layout area is arranged with analog modules.
[0045] In one embodiment of the present invention, the simulation layout area includes M simulation layout partitions, namely the 1st simulation layout partition, the 2nd simulation layout partition, ..., the Mth simulation layout partition, the 1st simulation layout partition, the 2nd simulation layout partition, ..., the Mth simulation layout partition are respectively arranged in the 1st row, the 2nd row..., the Mth row of the simulation layout area, the M simulation layout partitions are aligned in the column direction, and M is an integer not less than 1.
[0046] Figure 2A schematic diagram of a chip layout structure according to an embodiment of the present invention.
[0047] like Figure 2 As shown in FIG. 1 , the chip layout structure includes a first analog layout partition 201, a second analog layout partition 202, and a digital layout area 203. The first analog layout partition 201 constitutes the second analog layout partition 202. Figure 2 As shown, the digital layout area 203 is arranged on the right side of the analog layout area. In one embodiment of the present invention, the digital layout area 203 can also be arranged on the left side of the analog layout area.
[0048] like Figure 2 As shown, the interface signal lines are arranged outside the two analog layout partitions, that is, the upper and lower interface signal lines are connected to the analog modules and the digital layout area in the two analog layout partitions.
[0049] like Figure 2 As shown, the first simulation layout partition 201 includes 4 simulation modules, the second simulation layout partition 202 includes 1 simulation module, and the simulation modules arranged in each simulation layout partition are aligned in the row direction. Figure 2 As shown, the analog modules with larger areas, including the second analog module and the third analog module, all have substantially the same height, and the analog modules with smaller areas, including the first analog module 1 and the first analog module 2, all have half the height of the second analog module and the third analog module. After appropriate layout, the overall layout can be uniform. Figure 2 As shown, the power lines and ground lines are uniformly arranged at 1 / 4 height and 3 / 4 height of the second analog module and the third analog module with larger areas, and the power lines and ground lines of substantially the same width are arranged at 1 / 2 height of the first analog module 1 and the first analog module 2 with smaller areas, so that the power lines and ground lines of all modules can be automatically aligned, and the wiring becomes very simple and efficient, thereby saving area. In one embodiment of the present invention, the widths of the power lines and ground lines can be the same, substantially the same, or different, and are arranged on the same layer.
[0050] In one embodiment of the present invention, the analog module may be an analog-to-digital converter or a digital-to-analog converter or a reset power supply or a low dropout regulator or an oscillator or an amplifier or a phase-locked loop or a DC-DC converter or a reference voltage circuit, etc.
[0051] In one embodiment of the present invention, the first simulation layout partition, the second simulation layout partition, ..., the Mth simulation layout partition are respectively arranged in the first column, the second column..., the Mth column of the simulation layout area, and the M simulation layout partitions are aligned in the row direction, and M is an integer not less than 1.
[0052] Figure 3FIG. 1 is a schematic diagram of a chip layout structure according to another embodiment of the present invention. Figure 3 As shown in FIG. 1 , the chip layout structure includes a first analog layout partition 301, a second analog layout partition 302, and a digital layout area 303. Figure 3 As shown, the digital layout area 303 is arranged at the lower side of the analog layout area. In one embodiment of the present invention, the digital layout area 303 can also be arranged at the upper side of the analog layout area.
[0053] like Figure 3 As shown, the interface signal lines are arranged outside the two analog layout partitions, that is, the left and right interface signal lines are connected to the analog modules and the digital layout area in the two analog layout partitions.
[0054] like Figure 3 As shown, the first simulation layout partition 301 includes 4 simulation modules, the second simulation layout partition 302 includes 1 simulation module, and the simulation modules arranged in each simulation layout partition are aligned in the row direction. Figure 3 As shown, the analog modules with larger areas, including the second analog module and the third analog module, all have substantially the same width, and the analog modules with smaller areas, including the first analog module 1 and the first analog module 2, all have half the width of the second analog module and the third analog module. After appropriate layout, the overall layout can be uniform. Figure 3 As shown, the power lines and ground lines are uniformly arranged at 1 / 4 width and 3 / 4 width of the second analog module and the third analog module with larger areas, and the power lines and ground lines of substantially the same width are arranged at 1 / 2 width of the first analog module 1 and the first analog module 2 with smaller areas, so that the power lines and ground lines of all modules can be automatically aligned, and the wiring becomes very simple and efficient, thereby saving area. In one embodiment of the present invention, the widths of the power lines and ground lines can be the same, substantially the same, or different, and are arranged on the same layer.
[0055] Figure 4 FIG. 1 is a flow chart of a chip layout design method according to an embodiment of the present invention. Figure 4 As shown, the design method includes the following steps:
[0056] First, establish a layout size relationship between multiple simulation modules. Arrange the multiple simulation modules in a simulation layout area, the simulation layout area includes the first simulation layout partition, the second simulation layout partition, ..., the Mth simulation layout partition, the first simulation layout partition, the second simulation layout partition, ..., the Mth simulation layout partition are arranged in the first row, the second row ..., the Mth row of the simulation layout area respectively, and the M simulation layout partitions are aligned in the column direction, and M is an integer not less than 1. For example Figure 2In the example, analog modules with larger areas have substantially the same height, and analog modules with smaller areas have half the same height, and the overall layout can be made uniform through appropriate layout. Each analog layout partition can include analog modules with the same size in the column direction on different columns. The digital layout area is arranged on the left or right side of the analog layout area.
[0057] Next, the power lines and ground lines between multiple analog modules are arranged. If a simulation layout partition arranges K first analog modules with the same size in the column direction in a column, the power lines and ground lines of the simulation layout partition are arranged at the center of the K first analog modules in the column direction, and K is an integer not less than 1. For example Figure 2 In the process, the power lines and ground lines are uniformly arranged at 1 / 4 height and 3 / 4 height of the second analog module and the third analog module with larger areas, and the power lines and ground lines of basically the same width are arranged at 1 / 2 height of the first analog module 1 and the first analog module 2 with smaller areas. The power lines and ground lines of all modules can be automatically aligned, and the wiring becomes very simple and efficient.
[0058] Finally, the interface signal line is arranged outside the M analog layout partitions, and the interface signal line is connected to the analog modules in the M analog layout partitions and the digital layout area. Figure 2 In the process, the interfaces of the interface signal lines are uniformly placed above or below the modules, which can make the routing of the interface signal lines not only neat and short, but also prevent the interface signal lines from interfering with the power lines and ground lines, and the spacing between modules can be greatly reduced.
[0059] The chip layout structure designed by the chip layout design method provided by the present invention can also be as follows Figure 3 As shown, the first analog layout partition, the second analog layout partition, ..., the Mth analog layout partition are respectively arranged in the first column, the second column, ..., the Mth column of the analog layout area, and the M analog layout partitions are aligned in the row direction, and M is an integer not less than 1. The digital layout area is arranged on the upper side or the lower side of the analog layout area.
[0060] The chip layout structure provided by the present invention has the advantages that each analog module in the analog layout area is highly consistent, the overall floorplan shape of the analog layout area is relatively regular, with less empty space, and the overall floorplan shape of the digital layout area is also correspondingly regular, thereby improving the area utilization rate of the digital layout area; the power lines and ground lines between the analog modules can be automatically aligned and connected, saving the wiring spacing between the analog modules and the parasitic capacitance and parasitic resistance of the connecting wiring; the input and output interface signal lines of the analog modules are all on the outside of the analog modules, making the connection simple, shortening the wiring distance, and saving the chip area and cost; the power lines, ground lines and interface signal lines are not arranged together and do not interfere with each other, thereby improving the performance of the chip.
[0061] In one embodiment of the present invention, the present invention further provides a computer-readable storage medium having machine-readable instructions stored thereon, wherein the machine-readable instructions implement the following processing steps when executed by a processor: establishing a layout size relationship between multiple simulation modules, arranging the multiple simulation modules in a simulation layout area, wherein the simulation layout area includes a first simulation layout partition, a second simulation layout partition, ..., an Mth simulation layout partition, wherein the first simulation layout partition, the second simulation layout partition, ..., and the Mth simulation layout partition are respectively arranged in the first row, the second row ..., and the Mth row of the simulation layout area, wherein the M simulation layout partitions are aligned in the column direction, and M is not less than 1. an integer of 1; arranging a plurality of digital modules in a digital layout area, wherein the digital layout area is arranged on the left or right side of the analog layout area; arranging the positions of power lines and ground lines between the plurality of analog modules, if an analog layout partition arranges K first analog modules with the same size in a column direction in a column, then the power lines and ground lines of the analog layout partition are arranged at the center of the size of the K first analog modules in the column direction, and K is an integer not less than 1; arranging the positions of interface signal lines, wherein the interface signal lines are arranged outside the M analog layout partitions, and the interface signal lines are connected to the analog modules in the M analog layout partitions and the digital layout area.
[0062] The readable storage medium includes: a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and other media that can store machine-readable instructions.
[0063] Although various embodiments of the present invention are described above, it should be understood that they are presented as examples only and not as limitations. It is obvious to those skilled in the relevant art that various combinations, modifications and changes can be made thereto without departing from the spirit and scope of the present invention. Therefore, the breadth and scope of the present invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should only be defined according to the attached claims and their equivalents.
Claims
1. A chip layout structure, characterized in that: It includes a digital layout area and an analog layout area, wherein the digital layout area is separated from the analog layout area, the digital layout area is arranged with digital modules, and the analog layout area is arranged with analog modules; The analog layout area includes M analog layout partitions, namely the first analog layout partition, the second analog layout partition, ..., the Mth analog layout partition, the first analog layout partition, the second analog layout partition, ..., the Mth analog layout partition are respectively arranged in the first row, the second row ..., the Mth row of the analog layout area, the M analog layout partitions are aligned in the column direction, and M is an integer not less than 1; the digital layout area is arranged on the left or right side of the analog layout area; The interface signal line is arranged outside the M analog layout partitions, and the interface signal line is connected to the analog modules in the M analog layout partitions and the digital layout area; Each analog layout partition contains no more than N analog modules, and the analog modules arranged in each analog layout partition are aligned in a row direction, where N is an integer not less than 1; An analog layout partition arranges K first analog modules of the same size in a column direction in a column, and the power lines and ground lines of the analog layout partition are arranged at the center of the K first analog modules in the column direction, and K is an integer not less than 1.
2. The chip layout structure according to claim 1, characterized in that: The first simulation layout partition, the second simulation layout partition, ..., the Mth simulation layout partition are respectively arranged in the first column, the second column ..., the Mth column of the simulation layout area, and the M simulation layout partitions are aligned in the row direction, and M is an integer not less than 1; The digital layout area is arranged on the upper side or the lower side of the analog layout area.
3. The chip layout structure according to claim 1, characterized in that: Each analog layout partition includes analog modules with the same size in the column direction on different columns.
4. The chip layout structure according to claim 1, characterized in that: The analog module is an analog-to-digital converter or a digital-to-analog converter or a reset power supply or a low-dropout voltage regulator or an oscillator or an amplifier or a phase-locked loop or a DC-DC converter or a reference voltage circuit.
5. The chip layout structure according to claim 1, characterized in that: The widths of the power line and the ground line are the same or different.
6. The chip layout structure according to claim 1, characterized in that: An analog layout partition arranges two first analog modules with the same size in the column direction in one column, and arranges one second analog module with a size twice that of the first analog module in the column direction in another column. The power line and ground line of the analog layout partition are arranged at the center of the size of the first analog module in the column direction and at 3 / 4 and 1 / 4 of the size of the second analog module in the column direction.
7. A chip layout design method, characterized in that: include: Establishing a layout size relationship between multiple analog modules, arranging the multiple analog modules in an analog layout area, wherein the analog layout area includes a first analog layout partition, a second analog layout partition, ..., and an Mth analog layout partition, wherein the first analog layout partition, the second analog layout partition, ..., and the Mth analog layout partition are respectively arranged in the first row, the second row ..., and the Mth row of the analog layout area, wherein the M analog layout partitions are aligned in a column direction, and M is an integer not less than 1; arranging the digital layout area on the left or right side of the analog layout area; Arrange the positions of power lines and ground lines between multiple analog modules. If a simulation layout partition arranges K first analog modules with the same size in the column direction in a column, the power lines and ground lines of the simulation layout partition are arranged at the center of the size of the K first analog modules in the column direction, and K is an integer not less than 1; Arrange the interface signal line position, the interface signal line is arranged outside the M analog layout partitions, and the interface signal line is connected to the analog modules in the M analog layout partitions and the digital layout area.
8. The chip layout design method according to claim 7, characterized in that: The first simulation layout partition, the second simulation layout partition, ..., the Mth simulation layout partition are respectively arranged in the first column, the second column ..., the Mth column of the simulation layout area, and the M simulation layout partitions are aligned in the row direction, and M is an integer not less than 1; The digital layout area is arranged on the upper side or the lower side of the analog layout area.
9. The chip layout design method according to claim 7, characterized in that: Each analog layout partition includes analog modules with the same size in the column direction on different columns.
10. A computer-readable storage medium, characterized in that: Machine readable instructions are stored thereon, and when the machine readable instructions are executed by a processor, the steps of the method according to any one of claims 7 to 9 are performed.