Method and system for selecting wafer stacking scheme

Abstract

The invention relates to the technical field of semiconductor stacking, in particular to a selection method and system of a wafer stacking scheme, a wafer is provided with a plurality of valid crystal grains and invalid crystal grains, the method comprises the steps that at least one first wafer is selected from candidate wafers according to a first selection rule, and a plurality of second wafers can be stacked on the first wafer; continuously selecting at least one second wafer group corresponding to the first wafer from the candidate wafers, wherein the second wafer group comprises m second wafers; calculating a stacking index of the at least one simulation stacking scheme by using a stacking evaluation model; wherein the simulation stacking scheme is a scheme formed by stacking a first wafer and a second wafer group; and judging whether the stacking index is greater than a set first stacking threshold value or not, and if yes, outputting a corresponding simulation stacking scheme. According to the selection method provided by the invention, the yield of semiconductor stacking can be improved, namely, the utilization rate of the candidate wafers is improved, and the stacking cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer stacking, and in particular to a method and system for selecting a wafer stacking solution. Background Art

[0002] At present, the yield of semiconductor devices stacked at the wafer level is greatly affected by the process yield during wafer manufacturing or bonding. If one layer of the stacked chips has a malfunction, the entire stacked chip will be damaged, resulting in a decrease in the process yield. In order to solve the yield problem, improve production efficiency, and improve the performance of stacked chips, related technologies may adopt a method of reconstructing wafers. However, the introduction of organic materials during wafer reconstruction increases the complexity of the wafer reconstruction process, the wafer is greatly deformed after reconstruction, and the increased process line width cannot meet the requirements of the high-density hybrid bonding process, making it difficult to achieve multi-layer stacking of wafers.

[0003] In addition, patent application CN108701675A also discloses a correction die for wafer / die stacking. The method can provide correction for defective die in wafer-to-wafer stacking or die stacking. The correction die is coupled to a die in a stack including a defective die. The correction die electrically replaces the defective die. The method attempts to reduce the stacking cost increased by defects by setting the correction die.

[0004] However, with the application of wafer-level stacked semiconductor devices in accelerating AI, big data, supercomputing and other fields, the current requirements for the computing power, performance and yield of wafer-level stacked semiconductor devices are becoming higher and higher. In particular, when the functional integration of semiconductor devices increases, the number of stacking layers required and the number of effective functional areas in one layer also increase significantly. However, traditional yield optimization methods still have great limitations when facing these challenges.

[0005] Therefore, there is an urgent need for a method that can control the yield of semiconductor devices during the stacking process. Summary of the invention

[0006] The object of the present invention is to provide a method and system for selecting a wafer stacking solution, which can partially solve or alleviate the above-mentioned deficiencies in the prior art, improve the effective utilization rate of wafers, and reduce stacking costs.

[0007] In order to solve the above-mentioned technical problems, the present invention specifically adopts the following technical solutions: A first aspect of the present invention is to provide a method for selecting a wafer stacking scheme, wherein a plurality of grains are arranged at intervals on the wafer, and the grains include: valid grains and invalid grains. Correspondingly, the method includes the steps of: S101, selecting at least one first wafer from candidate wafers using a first selection rule, wherein a plurality of second wafers can be stacked on the first wafer, and wherein the first selection rule requires that the number of valid die in the first wafer is greater than or equal to a preset first valid number T1; S102, continue to select at least one second wafer group corresponding to the first wafer from the candidate wafers, the second wafer group including: m the second wafer; S103, using a stacking evaluation model to calculate a stacking index of at least one simulated stacking scheme; wherein the simulated stacking scheme is a scheme consisting of stacking the first wafer and the second wafer group, and the stacking evaluation model is: L = aX + Yj ; Y = m + 1 ; L For the stacking index, a is the first weight, b is the second weight, X is the effective number of valid channels, Y is the number of effective stacking layers; wherein, when the grains of the first wafer and the plurality of the candidate wafers in the second wafer group at the same coordinates are all effective grains, it is considered that the corresponding effective grains form an effective channel; S104, determining whether the stacking index is greater than a set first stacking threshold, if so, outputting the corresponding simulated stacking solution; if not, returning to S102.

[0008] In some embodiments, the valid die are divided into a first type of valid die and a second type of valid die; wherein the first type of valid die is in a workable state, and the second type of valid die can be repaired to a workable state through at least one repair process.

[0009] In some embodiments, the stack assessment model is: L = aX + Yj ; Y = m + 1 ; ; in, n is the number of the two types of effective grains in the effective channel, For the The repair cost of the two types of effective grains is: is the maximum repair cost set.

[0010] In some embodiments, the steps include: Divide among the candidate wafers α candidate partitions; Calculating effective grain indices in the candidate partitions respectively, wherein the effective grain indices are the number of effective grains, or the effective grain indices are the proportion of the effective grains in the grains; According to the effective grain index, the multiple candidate wafers are divided into multiple candidate combinations, wherein a candidate combination includes: multiple candidate wafers; in the same candidate combination, the number of the candidate partitions having a first correlation between one candidate wafer and another candidate wafer is greater than a first correlation threshold; wherein, when the difference between the effective grain indexes of the two candidate partitions at the same position of the two candidate wafers is less than or equal to the set first effective threshold, it is considered that the two candidate partitions have the first correlation with each other.

[0011] In some embodiments, S102 includes the steps of: For the current first wafer selected in the current S101 , multiple first candidate wafers are selected from the first candidate combination as the second wafer group, and the first candidate combination is the candidate combination to which the first wafer belongs.

[0012] In some embodiments, the steps include: When the stacking index of the simulated stacking scheme is less than or equal to the first stacking threshold, it is considered that the second wafer group currently belongs to the secondary stacking scheme; Correspondingly, S102 also includes: Selecting at least one second candidate wafer from the second candidate combination; wherein the number of the candidate partitions having the first correlation between the candidate wafer in the second candidate combination and the current first wafer is greater than the second correlation threshold and less than or equal to the first correlation threshold; The at least one second candidate wafer and a plurality of the first candidate wafers form a new second wafer group; Then the process enters S103 again according to the new second wafer group.

[0013] In some embodiments, the steps include: Setting a first invalid candidate number for the first candidate combination; wherein, when the second wafer group selected from the first candidate combination belongs to a sub-selected stacking solution, recording that the first candidate set generates an invalid candidate once; Monitoring the number of first invalid candidates in a first time period; When the first invalid candidate number is greater than a set invalid threshold, it is recommended to update the grouping of the candidate combination.

[0014] The present invention also provides a system for selecting a wafer stacking solution, wherein a plurality of grains are arranged at intervals on the wafer, and the grains include: valid grains and invalid grains. Correspondingly, the system: A first selection module, configured to select at least one first wafer from candidate wafers by using a first selection rule, wherein a plurality of second wafers can be stacked on the first wafer, and wherein the first selection rule requires that the number of valid die in the first wafer is greater than or equal to a preset first valid number T1; A second selection module is used to continue selecting at least one second wafer group corresponding to the first wafer from the candidate wafers, wherein the second wafer group includes: m second wafers; An evaluation module is used to calculate a stacking index of at least one simulated stacking scheme using a stacking evaluation model; wherein the simulated stacking scheme is a scheme composed of stacking the first wafer and the second wafer group, and the stacking evaluation model is: L = aX + Yj ; Y = m + 1 ; L For the stacking index, a is the first weight, b is the second weight, X is the effective channel indicator, Y is an effective stacking index; wherein, when the grains of the first wafer and the plurality of the candidate wafers in the second wafer group at the same coordinates are all effective grains, it is considered that the corresponding effective grains form an effective channel; The recommendation module is used to determine whether the stacking index is greater than a set first stacking threshold. If so, output the corresponding simulated stacking solution; if not, return to the second selection module.

[0015] In some embodiments, the valid die are divided into a first type of valid die and a second type of valid die; wherein the first type of valid die is in a workable state, and the second type of valid die can be repaired to a workable state through at least one repair process.

[0016] In some embodiments, the stack assessment model is: L = aX + Yj ; Y = m + 1 ; ; in, n is the number of the two types of effective grains in the effective channel, For the The repair cost of the two types of effective grains is: is the maximum repair cost set.

[0017] Beneficial technical effects: The present invention provides a method for selecting a wafer stacking scheme, that is, a wafer selection method. The wafer selection method can quickly screen multiple candidate wafers through the two dimensions of stacking yield and stacking performance, so as to comprehensively screen out a group of better second wafer groups. Moreover, from the perspective of candidate wafers, the effective utilization rate of candidate wafers can be improved through the overall evaluation of stacking yield and performance, and the best stacking scheme can be simulated in the current candidate wafer library. As a result, the present invention can reduce the stacking cost increased due to invalid stacking (such as too few available stacking layers, or too few effective channels after stacking).

[0018] Furthermore, the present invention also provides a hierarchical selection mode based on correlation candidate partition evaluation. Specifically, a large number of candidate wafers are grouped by using regional correlation evaluation, and then when screening the second wafer group, the candidate priorities corresponding to the groups are screened step by step, so as to improve the efficiency of the selection process when facing a large number of available candidate wafers and reduce the amount of invalid calculations to a certain extent.

[0019] Furthermore, the present invention also provides an update mechanism for updating the grouping mode based on the application time and the screening accuracy. For example, the present invention monitors the candidate results (such as the success rate of the candidate stacking solution) to flexibly adjust the division and grouping rules of the candidate partitions in combination with the candidate results, so as to improve the accuracy and reliability of the candidate priority classification, thereby further improving the efficiency of the selection process. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale. Obviously, the drawings described below are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without paying creative labor.

[0021] Figure 1 is a schematic structural diagram of an exemplary candidate wafer in the present invention; Figure 2 is a schematic structural diagram of another exemplary candidate wafer in the present invention; Figure 3 A schematic diagram of setting candidate partitions for candidate wafers in an exemplary embodiment of the present invention; Figure 4 A schematic diagram of setting candidate partitions for candidate wafers in another exemplary embodiment of the present invention; Figure 5 is a schematic diagram of the stacking relationship of wafers in an exemplary embodiment of the present invention; Figure 6 A schematic diagram of a flow chart of a stacking scheme selection method in an exemplary embodiment of the present invention; Figure 7 The figure is a schematic diagram of the module structure of a stacking solution selection system in an exemplary embodiment of the present invention.

[0022] Summary of reference numerals: wafer 01 , die 010 , first wafer 011 , second wafer 012 , wafer A 012 a , wafer E 012 e , first candidate partition 10 , second candidate partition 20 , third candidate partition 30 . DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0024] Herein, suffixes such as "module", "component" or "unit" used to represent elements are only used to facilitate the description of the present invention, and have no specific meanings by themselves. Therefore, "module", "component" or "unit" can be used mixedly.

[0025] In this document, the terms "upper", "lower", "inner", "outer", "front", "back", "one end", "the other end" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0026] In this document, unless otherwise clearly specified and limited, the terms "installed", "provided with", "connected", etc. should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] Herein "and / or" includes any and all combinations of one or more of the associated listed items.

[0028] Herein, "plurality" means two or more than two, ie, it includes two, three, four, five, etc.

[0029] As used in this specification, the term "about" typically means + / - 5% of the stated value, more typically + / - 4% of the stated value, more typically + / - 3% of the stated value, more typically + / - 2% of the stated value, even more typically + / - 1% of the stated value, and even more typically + / - 0.5% of the stated value.

[0030] In this specification, some embodiments may be disclosed in a format of being in a range. It should be understood that this description of "being in a range" is only for convenience and brevity, and should not be interpreted as a rigid limitation on the disclosed range. Therefore, the description of the range should be considered to have specifically disclosed all possible sub-ranges and independent numerical values ​​within this range. For example, the description of the range 1-6 should be considered to have specifically disclosed sub-ranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as individual numbers within this range, such as 1, 2, 3, 4, 5 and 6. Regardless of the breadth of the range, the above rules apply.

[0031] In this article, wafer refers to the silicon wafer used to make silicon semiconductor circuits. "Dies" can be small pieces cut from the wafer, also called "dies". "Dies" with circuit structures processed on them can also be called "chips". For example, see Figure 1 As shown, a plurality of dies 010 are formed at intervals on a wafer 01 , wherein a die marked as “G” indicates that the die is a valid die, that is, the die can have normal signal communication (such as electrical signal communication) with other dies after stacking.

[0032] Generally, multiple dies need to be stacked to package into a complete semiconductor device. For example, in a mother wafer (for example, it can be a packaging substrate, that is, Substrate (abbreviated as SUB)), or it can be a packaging substrate that stacks multiple wafer layers in sequence. Among them, a wafer layer includes multiple dies, and in particular, a wafer layer refers to a wafer with multiple dies.

[0033] See also Figure 5 As shown, multiple wafers are stacked from bottom to top to form a semiconductor device. In the exemplary stacking process of the present invention, a first wafer 011 can be selected from multiple candidate wafers first, and the first wafer 011 is packaged as the bottom wafer. Subsequently, multiple second wafers 012 (such as wafer A 012a ... wafer E 012e, etc.) are selected from the remaining multiple candidate wafers and stacked on top of the first wafer in sequence to form a semiconductor device.

[0034] like Figure 1 , Figure 2 As shown, a wafer is provided with multiple grains. When the grains located at the same coordinates in multiple wafers are all valid grains, an effective path can be formed between the multiple grains, that is, normal signal connection can be achieved. When there are a large number of effective paths in a semiconductor device, it can be regarded as a valid product.

[0035] Embodiment 1 See also Figure 6 As shown, the present invention provides a method for selecting a wafer stacking scheme, wherein a plurality of grains are arranged at intervals on the wafer, and the grains include: valid grains and invalid grains. Correspondingly, the method includes the steps of: S101, selecting at least one first wafer from candidate wafers, where a plurality of second wafers can be stacked on the first wafer.

[0036] For example, in some embodiments, a first selection rule is used to select a first wafer from candidate wafers. Specifically, the first selection rule requires that the number of valid dies in the first wafer is greater than or equal to a preset first valid number T1.

[0037] For another example, in some embodiments, a first wafer is arbitrarily selected directly from wafers marked as good products.

[0038] S102, continue to select at least one second wafer group corresponding to the first wafer from the candidate wafers, the second wafer group including: m candidate wafers (equivalent to selecting a plurality of second wafers); S103, using a stacking evaluation model to calculate a stacking index of at least one simulated stacking scheme; wherein the simulated stacking scheme is a scheme consisting of stacking the first wafer and the second wafer group, and the stacking evaluation model is: L = aX + Yj ; Y = m + 1 ; L For the stacking index, a is the first weight, b is the second weight, X is the effective number of effective channels, Y is the number of effective stacking layers; wherein, when the grains of the first wafer and the plurality of the candidate wafers in the second wafer group at the same coordinates are all effective grains, it is considered that the corresponding effective grains form an effective channel; In this embodiment, the effective number of effective channels is used to characterize the yield of the semiconductor product of the reaction stack.

[0039] For example, in some embodiments, the effective number of effective channels X is the actual number of valid channels.

[0040] For example, in some embodiments, the effective number of effective channels X It can also be the relative number of valid channels.

[0041] Furthermore, the method further includes the step: S104, determining whether the stacking index is greater than a set first stacking threshold, and if so, outputting the corresponding simulated stacking solution (equivalent to outputting a recommended solution); if not, returning to S102.

[0042] In some embodiments, a plurality of second wafer groups may be selected at the same time, and a plurality of stacking indicators of a plurality of simulated stacking schemes formed may be calculated at the same time.

[0043] For example, in some embodiments, one or more simulated stacking solutions with the largest stacking index may be selected as recommended solutions.

[0044] In some embodiments, there may be a same second wafer between any two selected second wafer groups.

[0045] In some embodiments, the number of second wafers in the second wafer group may be about 1-10. Of course, as the requirements for the integration of semiconductor devices (also referred to as stacked devices) become higher and higher, the number of second wafers may also increase accordingly. In this embodiment, the number of stacked layers is used to characterize the functional integration of the stacked semiconductor device, that is, the performance.

[0046] The present invention provides a method for selecting a wafer stacking scheme, that is, a wafer selection method. The wafer selection method can quickly screen multiple candidate wafers through the two dimensions of stacking yield and stacking performance, so as to comprehensively screen out a group of better second wafer groups. Moreover, from the perspective of candidate wafers, the effective utilization rate of candidate wafers can be improved through the overall evaluation of stacking yield and performance, and the best stacking scheme can be simulated in the current candidate wafer library. As a result, the present invention can reduce the stacking cost increased due to invalid stacking (such as too few available stacking layers, or too few effective channels after stacking).

[0047] In some embodiments, the effective grains are divided into one type of effective grains and two type of effective grains; wherein, the one type of effective grains are in a workable state, that is, they can be normally electrically connected to adjacent grains, and the two type of effective grains can be repaired to a workable state through at least one repair process.

[0048] Generally, when there are certain defects on a grain, it may cause certain faults in its electrical connection performance, so this type of grain can be classified as a Class II valid grain. In addition, due to the different types and quantities of defects generated, the repair processes that different Class II valid grains need to undergo will also vary. Correspondingly, the repair difficulty or repair cost required for different Class II valid grains is also different. Among them, when the defects of a grain are too many to be repaired, or the repair cost is too high and does not meet the cost requirements, it can be classified as an invalid grain.

[0049] In some embodiments, the effective Class II grains may be further divided into more subcategories according to the difficulty or cost of repairing them, such as first Class II grains, second Class II grains, third Class II grains, and so on.

[0050] For example, in some embodiments, the grains that can be repaired by only one repair process can be classified as first-class grains, and the grains that can be repaired by only two repair processes can be classified as second-class grains.... For another example, in some embodiments, the grains whose repair cost is less than the first repair cost can be classified as first-class grains, and the grains whose repair cost is greater than or equal to the first repair cost and less than the second repair cost can be classified as second-class grains....

[0051] Furthermore, in some embodiments, the effectiveness level of the effective channels may also be scored.

[0052] For example, in some embodiments, the effective level .

[0053] Among them, λ is the set coefficient, is the number of effective grains of a type in an effective channel, is the total amount of grains in an effective channel; For example, in some embodiments, is the average value of a type of effective grains in multiple effective channels. Correspondingly, the effective number , is the total number of valid channels.

[0054] For example, the effective number ; is the total number of valid channels, For the j The effective level of each valid channel. For example, , correspondingly, the effective number .in, f 1 , f 2 … f x are the number of effective grains of a type in each effective channel.

[0055] Furthermore, in some embodiments, ;in, is the first coefficient, is the number of effective grains of a type, is the second coefficient, is the number of effective grains of type II.

[0056] In particular, in some embodiments, It refers to the number of effective grains of the first and second categories, that is, effective grains of the second category with lower repair costs.

[0057] The present invention comprehensively considers the stacking performance, stacking yield and repair cost of the simulated stacking device to further control the overall product performance of the actual stacking device, that is, to further improve the effective utilization rate of the candidate wafers. Among them, the improvement of the effective utilization rate reduces the stacking cost of the stacking device (that is, reduces the probability of invalid stacking) on ​​the one hand, and can improve the yield and service life of the stacking device on the other hand.

[0058] In some embodiments, the stack assessment model is: L = aX + Yj ; Y = m + 1 ; ; in, n is the number of the two types of effective grains in the effective channel, For the The repair cost of the two types of effective grains is: is the maximum repair cost set.

[0059] Preferably, in this embodiment, only when the repair cost does not exceed the maximum repair cost, the corresponding stacking indicator or simulated stacking solution is allowed to be output.

[0060] In this embodiment, by comprehensively evaluating the number of stacked layers, the number of effective channels, and the repair cost, a coordinated evaluation of the simulated stacking solution in terms of the overall performance and cost of the simulated stacking solution is achieved. Preferably, only when the simulated stacking solution is relatively reasonable in terms of application effect and stacking cost, it is output as a recommended solution to quickly assist users in selecting a stacking solution with a higher yield.

[0061] From another perspective, the stacking scheme selection method (also referred to as the wafer selection method) in the present invention can improve the effective utilization rate of candidate wafers, thereby greatly reducing the stacking cost caused by invalid stacking (such as too many defects in the stacking scheme and the yield is too low to be used) during the stacking process.

[0062] In some embodiments, the step further includes: grouping the candidate wafers according to a set grouping condition; the grouping condition includes: the number α of the candidate partitions, and a set value of the first effective threshold; The step of grouping the candidate wafers includes: Dividing the candidate wafer into α candidate partitions; Calculating effective grain indices in the candidate partitions respectively, wherein the effective grain indices are the number of effective grains, or the effective grain indices are the proportion of the effective grains in the grains; Dividing the plurality of candidate wafers into a plurality of candidate combinations according to the effective die index, wherein a candidate combination includes: a plurality of candidate wafers; In the same candidate combination, the number of candidate partitions having a first correlation between one candidate wafer and another candidate wafer is greater than a first correlation threshold; wherein, when the difference between the effective grain indicators of the two candidate partitions at the same position of the two candidate wafers is less than or equal to the set first effective threshold, the two candidate partitions are considered to have a first correlation with each other.

[0063] That is, when the number of effective dies and the distribution trend of wafers are similar, they can be grouped into the same candidate combination. In this embodiment, candidate wafers are pre-evaluated regionally by candidate partitioning, so as to set candidate priorities for subsequent selection of the second wafer.

[0064] Correspondingly, when multiple second wafers need to be selected for the first wafer, they are preferably selected from the same candidate combination.

[0065] For example, see Figure 3 As shown, the wafer can be gradually divided into three candidate partitions along the direction from the center to the edge of the wafer, namely, a first candidate partition 10 , a second candidate partition 20 , and a third candidate partition 30 .

[0066] For example, in other embodiments, other partitioning methods may be used to partition, such as Figure 4 As shown, it can be divided into a first candidate partition 10, a second candidate partition 20, ... according to the horizontal and vertical coordinates.

[0067] This embodiment proposes a method of grouping candidate wafers according to the correlation of multiple candidate partitions, so as to preliminarily classify the matching between the candidate wafers and the first wafer in combination with the regional correlation, thereby improving the efficiency of selecting suitable recommended solutions and further reducing the screening cost.

[0068] In other words, this embodiment actually provides a hierarchical selection mode based on correlation candidate partition evaluation. Specifically, a large number of candidate wafers are grouped by using regional correlation evaluation, and then when screening the second wafer group, the candidate priorities corresponding to the groups are screened step by step, so as to improve the efficiency of the selection process when facing a large number of available candidate wafers and reduce the amount of invalid calculations to a certain extent.

[0069] In some embodiments, the candidate combinations are divided into different candidate sets, which are equivalent to being divided into different candidate priorities; correspondingly, in step S102: For the current first wafer selected in S101, multiple first candidate wafers are selected from a first candidate combination (equivalent to the candidate combination being marked as the first candidate priority) as the second wafer group, and the first candidate combination is the candidate combination to which the first wafer belongs.

[0070] Furthermore, in some embodiments, the method further comprises: When the stacking index of the simulated stacking scheme is less than or equal to the first stacking threshold, it is considered that the second wafer group currently belongs to the secondary stacking scheme; Correspondingly, S102 also includes: Select at least one second candidate wafer from the second candidate combination (equivalent to being marked as the second candidate priority); wherein the number of the candidate partitions having the first correlation between the candidate wafer in the second candidate combination and the current first wafer is greater than the second correlation threshold and less than or equal to the first correlation threshold; The at least one second candidate wafer and a plurality of the first candidate wafers form a new second wafer group; Then the process enters S103 again according to the new second wafer group.

[0071] In some embodiments, the steps include: Setting a first invalid candidate number for the first candidate set; wherein, when the second wafer group selected from the first candidate set belongs to a sub-selected stacking solution, recording that the first candidate set generates an invalid candidate once; Monitoring the number of first invalid candidates in a first time period; When the first invalid candidate number is greater than a set first invalid threshold, it is suggested to update the grouping of the candidate combination. For example, a first prompt signal may be issued to remind the user to determine whether the grouping needs to be updated. Alternatively, a second prompt signal may be issued to start the step of updating the grouping of the candidate combination.

[0072] For example, in some embodiments, the step of updating the grouping of the candidate combinations includes: Updating the grouping condition, wherein the grouping condition includes: the number α of the candidate partitions, and the set value of the first effective threshold; The currently remaining candidate wafers are grouped again according to the grouping condition.

[0073] Alternatively, in some other embodiments, a plurality of new candidate wafers may be acquired to comprehensively classify the currently remaining candidate wafers and the newly acquired candidate wafers.

[0074] For example, in some embodiments, the step of updating the grouping condition includes: increasing the number α.

[0075] That is to say, the present invention also provides an update mechanism for updating the grouping mode based on the application time and the screening accuracy. For example, the present invention monitors the candidate results (such as the success rate of the candidate stacking solution) to flexibly adjust the division and grouping rules of the candidate partitions in combination with the candidate results, so as to improve the accuracy and reliability of the candidate priority classification, thereby further improving the efficiency of the selection process.

[0076] In some embodiments, the steps include: Recording the second invalid candidate number of the candidate wafer; wherein, when the simulated stacking scheme composed of the candidate wafers is identified as a secondary stacking scheme, it is recorded that the candidate wafer has generated an invalid candidate number, such as the record of the second invalid candidate number is increased by one; When the second invalid candidate number is greater than a set second invalid threshold, it is recommended to delete the candidate wafer from the corresponding candidate combination to update the candidate combination.

[0077] In this embodiment, when the matching degree between the candidate wafer and the first wafer is too low, the candidate wafer is deleted from the candidate combination in a timely manner to reduce the amount of invalid calculation.

[0078] That is to say, the present invention also proposes a filtering mechanism for updating candidate wafers, and the selection efficiency in the candidate process can be further improved by filtering and updating the candidate wafers.

[0079] Embodiment 2 Another aspect of the present invention further provides a system for selecting a wafer stacking solution, wherein a plurality of crystal grains are arranged at intervals on the wafer, and the crystal grains include: valid crystal grains and invalid crystal grains, correspondingly, see Figure 7 As shown, the system: A first selection module 11 is used to select at least one first wafer from candidate wafers using a first selection rule, wherein a plurality of second wafers can be stacked on the first wafer, and wherein the first selection rule requires that the number of valid die in the first wafer is greater than or equal to a preset first valid number T1; A second selection module 12 is used to continue selecting at least one second wafer group corresponding to the first wafer from the candidate wafers, wherein the second wafer group includes: m second wafers; The evaluation module 13 is used to calculate the stacking index of at least one simulated stacking scheme by using a stacking evaluation model; wherein the simulated stacking scheme is a scheme composed of stacking the first wafer and the second wafer group, and the stacking evaluation model is: L = aX + Yj ; Y = m + 1 ; L For the stacking index, a is the first weight, b is the second weight, X is the effective channel indicator, Yis an effective stacking index; wherein, when the grains of the first wafer and the plurality of the candidate wafers in the second wafer group at the same coordinates are all effective grains, it is considered that the corresponding effective grains form an effective channel; The recommendation module 14 is used to determine whether the stacking index is greater than a set first stacking threshold, and if so, output the corresponding simulated stacking solution; if not, return to the second selection module.

[0080] In some embodiments, the valid die are divided into a first type of valid die and a second type of valid die; wherein the first type of valid die is in a workable state, and the second type of valid die can be repaired to a workable state through at least one repair process.

[0081] In some embodiments, the stack assessment model is: L = aX + Yj ; Y = m + 1 ; ; in, n is the number of the two types of effective grains in the effective channel, For the The repair cost of the two types of effective grains is: is the maximum repair cost set.

[0082] In some embodiments, it also includes: a grouping module, used to group the candidate wafers according to set grouping conditions.

[0083] In some embodiments, the grouping module includes: A partitioning unit, used for dividing the candidate wafer into α candidate partitions; A calculation unit, used to calculate the effective grain index in the candidate partitions respectively, where the effective grain index is the number of the effective grains, or the effective grain index is the proportion of the effective grains in the grains; A grouping unit is used to group the plurality of candidate wafers into a plurality of candidate combinations according to the effective grain index, wherein a candidate combination includes: a plurality of candidate wafers; in the same candidate combination, the number of candidate partitions having a first correlation between one candidate wafer and another candidate wafer is greater than a first correlation threshold; wherein, when the difference between the effective grain indexes of the two candidate partitions at the same position of the two candidate wafers is less than or equal to the set first effective threshold, the two candidate partitions are considered to have a first correlation with each other. Correspondingly, when it is necessary to select a plurality of second wafers for the first wafer, they are first selected from the same candidate combination.

[0084] Further, in some embodiments, for the current first wafer selected in the first selection module 11, multiple first candidate wafers are selected from the first candidate combination as the second wafer group, and the first candidate combination is the candidate combination to which the first wafer belongs.

[0085] In some embodiments, when the stacking index of the simulated stacking scheme is less than or equal to the first stacking threshold, it is considered that the current second wafer group belongs to the secondary stacking scheme; correspondingly, the second selection module 12 further includes: A selection unit, configured to select at least one second candidate wafer from the second candidate combination; wherein the number of the candidate partitions having a first correlation between the candidate wafers in the second candidate combination and the current first wafer is greater than a second correlation threshold and less than or equal to the first correlation threshold; a combining unit, configured to combine the at least one second candidate wafer and a plurality of the first candidate wafers to form a new second wafer group; The re-evaluation unit is used to re-enter the evaluation module 13 according to the new second wafer group.

[0086] In some embodiments, it also includes: a candidate grouping update module, used to set a first invalid candidate number for the first candidate combination; wherein, when the second wafer group selected from the first candidate combination belongs to the sub-selected stacking scheme, it is recorded that the first candidate set has generated an invalid candidate; the first invalid candidate number within the first time period is monitored; when the first invalid candidate number is greater than the set invalid threshold, it is recommended to update the grouping of the candidate combination.

[0087] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0088] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for a computer terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0089] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation modes, which are merely illustrative rather than restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A method for selecting a wafer stacking scheme, characterized in that: A plurality of crystal grains are arranged at intervals on the wafer, and the crystal grains include: effective crystal grains and invalid crystal grains. Correspondingly, the method includes the steps of: S101, selecting at least one first wafer from candidate wafers using a first selection rule, wherein a plurality of second wafers can be stacked on the first wafer, and wherein the first selection rule requires that the number of valid die in the first wafer is greater than or equal to a preset first valid number; S102, continue to select at least one second wafer group corresponding to the first wafer from the candidate wafers, the second wafer group including: m the second wafer; S103, using a stacking evaluation model to calculate a stacking index of at least one simulated stacking scheme; wherein the simulated stacking scheme is a scheme composed of stacking the first wafer and the second wafer group, and the stacking evaluation model includes: L = aX + Yj ； Y = m + 1 ； L For the stacking index, a is the first weight, b is the second weight, X is the effective number of valid channels, Y is the number of effective stacking layers; wherein, when the grains of the first wafer and the plurality of the candidate wafers in the second wafer group at the same coordinates are all effective grains, it is considered that the corresponding effective grains form an effective channel; S104, determining whether the stacking index is greater than a set first stacking threshold, if so, outputting the corresponding simulated stacking solution; if not, returning to S102.

2. The method for selecting a wafer stacking scheme according to claim 1, characterized in that: The effective grains are divided into a first-class effective grain and a second-class effective grain; wherein the first-class effective grain is in a workable state, and the second-class effective grain can be repaired to a workable state through at least one repair process.

3. The method for selecting a wafer stacking scheme according to claim 2, characterized in that: The stacking assessment model includes: L = aX + Yj ； Y = m + 1 ； ； in, n is the number of the two types of effective grains in the effective channel, For the The repair cost of the two types of effective grains is: is the maximum repair cost set.

4. The method for selecting a wafer stacking scheme according to claim 1, characterized in that: Also includes the steps: Divide among the candidate wafers α candidate partitions; Calculating effective grain indices in the candidate partitions respectively, wherein the effective grain indices are the number of effective grains, or the effective grain indices are the proportion of the effective grains in the grains; According to the effective grain index, the multiple candidate wafers are divided into multiple candidate combinations, wherein a candidate combination includes: multiple candidate wafers; in the same candidate combination, the number of the candidate partitions having a first correlation between one candidate wafer and another candidate wafer is greater than a first correlation threshold; wherein, when the difference between the effective grain indexes of the two candidate partitions at the same position of the two candidate wafers is less than or equal to the set first effective threshold, the two candidate partitions are considered to have the first correlation with each other.

5. The wafer selection method for wafer stacking according to claim 4, characterized in that: S102 includes the following steps: For the current first wafer selected in the current S101 , multiple first candidate wafers are selected from the first candidate combination as the second wafer group, and the first candidate combination is the candidate combination to which the first wafer belongs.

6. The wafer selection method for wafer stacking according to claim 5, characterized in that: Also includes the steps: When the stacking index of the simulated stacking scheme is less than or equal to the first stacking threshold, it is considered that the second wafer group currently belongs to the secondary stacking scheme; Correspondingly, S102 also includes: Selecting at least one second candidate wafer from the second candidate combination; wherein the number of the candidate partitions having a first correlation between the candidate wafer in the second candidate combination and the current first wafer is greater than a second correlation threshold and less than or equal to the first correlation threshold; The at least one second candidate wafer and a plurality of the first candidate wafers form a new second wafer group; Then the process enters S103 again according to the new second wafer group.

7. The method for selecting a wafer stacking scheme according to claim 6, characterized in that: Also includes the steps: Setting a first invalid candidate number for the first candidate combination; wherein, when the second wafer group selected from the first candidate combination belongs to a sub-selected stacking solution, recording that the first candidate set generates an invalid candidate once; Monitoring the number of first invalid candidates in a first time period; When the first invalid candidate number is greater than a set invalid threshold, it is recommended to update the grouping of the candidate combination.

8. A wafer stacking scheme selection system, characterized in that: A plurality of crystal grains are arranged at intervals on the wafer, and the crystal grains include: effective crystal grains and invalid crystal grains. Correspondingly, the system includes: A first selection module, configured to select at least one first wafer from candidate wafers by using a first selection rule, wherein a plurality of second wafers can be stacked on the first wafer, and wherein the first selection rule requires that the number of valid die in the first wafer is greater than or equal to a preset first valid number; The second selection module is used to continue selecting at least one second wafer group corresponding to the first wafer from the candidate wafers, wherein the second wafer group includes: m the second wafer; An evaluation module, configured to calculate a stacking index of at least one simulated stacking scheme using a stacking evaluation model; wherein the simulated stacking scheme is a scheme composed of stacking the first wafer and the second wafer group, and the stacking evaluation model includes: L = aX + Yj ； Y = m + 1 ； L For the stacking index, a is the first weight, b is the second weight, X is the effective channel indicator, Y is an effective stacking index; wherein, when the grains of the first wafer and the plurality of the candidate wafers in the second wafer group at the same coordinates are all effective grains, it is considered that the corresponding effective grains form an effective channel; The recommendation module is used to determine whether the stacking index is greater than a set first stacking threshold. If so, output the corresponding simulated stacking solution; if not, return to the second selection module.

9. The wafer stacking scheme selection system according to claim 8, characterized in that: The effective grains are divided into a first-class effective grain and a second-class effective grain; wherein the first-class effective grain is in a workable state, and the second-class effective grain can be repaired to a workable state through at least one repair process.

10. The wafer stacking scheme selection system according to claim 9, characterized in that: The stacking assessment model includes: L = aX + Yj ； Y = m + 1 ； ； in, n is the number of the two types of effective grains in the effective channel, For the The repair cost of the two types of effective grains is: is the maximum repair cost set.

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