Package structure and manufacturing method thereof

Abstract

A package structure includes a circuit substrate, a semiconductor package, a thermal interface material structure, a plating layer, a first intermetallic compound, a second intermetallic compound, and a cap structure. The semiconductor package is disposed on the circuit substrate and includes a central region and a peripheral region. A thermal interface material structure is disposed on the central region and the peripheral region of the semiconductor package. The plating layer is disposed on the thermal interface material structure. A first intermetallic compound is formed between the thermal interface material structure and the plating layer over the central region. A second intermetallic compound is formed between the thermal interface material structure and the plating layer over the peripheral region of the semiconductor package, wherein the second intermetallic compound is different from the first intermetallic compound. The cover structure is disposed on the circuit substrate and covers the semiconductor package.

Description

Technical Field

[0001] The invention relates to a packaging structure and a manufacturing method of the packaging structure. Background Art

[0002] Semiconductor devices and integrated circuits used in various electronic applications (such as cell phones and other mobile electronic devices) are typically manufactured on a single semiconductor wafer. The die of the wafer is processed and packaged with other semiconductor devices or dies at the wafer level, and various technologies have been developed for wafer-level packaging. Summary of the invention

[0003] The embodiment of the present disclosure provides a packaging structure including a circuit substrate, a semiconductor package, a thermal interface material structure, a plating layer, a first intermetallic compound, a second intermetallic compound and a cover structure. The semiconductor package is arranged on the circuit substrate and electrically connected to the circuit substrate, wherein the semiconductor package includes a central area and a peripheral area. The thermal interface material structure is arranged on the central area and the peripheral area of ​​the semiconductor package. The plating layer is arranged on the thermal interface material structure. The first intermetallic compound is formed between the thermal interface material structure and the plating layer above the central area of ​​the semiconductor package. The second intermetallic compound is formed between the thermal interface material structure and the plating layer above the peripheral area of ​​the semiconductor package, wherein the second intermetallic compound is different from the first intermetallic compound. The cover structure is arranged on the circuit substrate and covers the semiconductor package.

[0004] The embodiment of the present disclosure provides a packaging structure including an interconnection structure, a plurality of first semiconductor dies, a plurality of second semiconductor dies, a first heat dissipation component, a second heat dissipation component, and a cover structure. The first semiconductor die is arranged on the central area of ​​the interconnection structure and is electrically connected to the interconnection structure. The second semiconductor die is arranged on the peripheral area of ​​the interconnection structure and is electrically connected to the interconnection structure. The first heat dissipation component is arranged on the back side of the plurality of first semiconductor dies and covers the back side of the plurality of first semiconductor dies. The second heat dissipation component is arranged on the back side of the plurality of second semiconductor chips and covers the back side of the plurality of second semiconductor chips, wherein the first heat dissipation component and the second heat dissipation component include different materials. The cover structure is arranged on the first heat dissipation component and the second heat dissipation component and contacts the first heat dissipation component and laterally surrounds the first heat dissipation component, the second heat dissipation component, the plurality of first semiconductor dies, the plurality of second semiconductor dies, and the interconnection structure.

[0005] The present disclosure provides a method for manufacturing a packaging structure. The method includes the following steps. A semiconductor package is arranged on a circuit substrate, wherein the semiconductor package includes a central area and a peripheral area. A thermal interface material structure is formed on the central area and the peripheral area of ​​the semiconductor package. A plating layer is arranged on the thermal interface material structure, and a cover structure is arranged on the circuit substrate, wherein the cover structure contacts the plating layer and covers the semiconductor package. A heating process is performed to form a first intermetallic compound between the thermal interface material structure and the plating layer above the central area of ​​the semiconductor package, and a second intermetallic compound is formed between the thermal interface material structure and the plating layer above the peripheral area of ​​the semiconductor package, wherein the second intermetallic compound is different from the first intermetallic compound. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the critical dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figures 1A to 8 are schematic top views and cross-sectional views of various stages in a method for manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure.

[0008] Fig. 9 is a schematic cross-sectional view of a semiconductor package according to some other exemplary embodiments of the present disclosure.

[0009] Figures 10 to 15 are schematic top views and cross-sectional views of various stages in a method for manufacturing a package structure according to some exemplary embodiments of the present disclosure.

[0010] Fig.16 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0011] Figures 17 to 20 are schematic top views and cross-sectional views of various stages in a method for manufacturing a package structure according to some other exemplary embodiments of the present disclosure.

[0012] Fig.21 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0013] Fig. 22 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure.

[0014] Description of Reference Numerals

[0015] 21, 22: Semiconductor die

[0016] 21S, 22S, 114b: dorsal surface

[0017] 100, 100': Intermediary layer structure

[0018] 100A, R1: Central area

[0019] 100B, R2: Surrounding area

[0020] 101A, 116a: Dielectric layer

[0021] 101B: Conductive layer

[0022] 101C, 106: Conductive pads

[0023] 102: Core part

[0024] 102a: First surface

[0025] 102b: Second surface

[0026] 104: Through hole

[0027] 110: Electrical connector

[0028] 112, 350: Bottom filling structure

[0029] 114: Insulation enclosure

[0030] 114a, 116s: Top surface

[0031] 116: Redistribution Structure

[0032] 116b: Metallized pattern

[0033] 118: Conductive terminal

[0034] 120: Back metal layer

[0035] 210, 220: Main body

[0036] 211, 221: Active surface

[0037] 212, 222: Connecting pads

[0038] 300: Circuit substrate

[0039] 310, 320: Contact pads

[0040] 330: Metallization layer

[0041] 410: Thermal interface material structure

[0042] 410A: The first thermal interface material

[0043] 410B: Second thermal interface material

[0044] 420: Plating layer

[0045] 420A: First plating layer

[0046] 420B: Second plating layer

[0047] 430: Adhesive

[0048] 440: Cover structure

[0049] AX: Air gap

[0050] Cx: carrier

[0051] DL: Cutting Lane

[0052] FR: Frame

[0053] HX1: The first heat sink

[0054] HX2: Second heat sink

[0055] IMC1: The first intermetallic compound

[0056] IMC2: Second Intermetallic Compound

[0057] PDX: Passive Devices

[0058] PK1, PK2, PK3, PK4, PK5: Package structure

[0059] PKR: Packaging Region

[0060] RDL: Redistribution Layer

[0061] SM1, SM2: Semiconductor packaging

[0062] TP: Tape

[0063] Tx, Ty: thickness DETAILED DESCRIPTION

[0064] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a second feature on or on a first feature may include an embodiment in which the second feature is formed to be in direct contact with the first feature, and may also include an embodiment in which an additional feature may be formed between the second feature and the first feature, thereby making it possible for the second feature to not be in direct contact with the first feature. In addition, the present disclosure may reuse component symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0065] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "on", "over", "overlying", "above", "upper", etc. may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0066] Other features and processes may also be included. For example, test structures may be included to assist in verification testing of 3D packages or 3DIC devices. Test structures may include, for example, test pads formed on a redistribution layer or substrate that allow for testing of the 3D package or 3DIC, the use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with test methods that incorporate intermediate verification of known good dies to increase yield and reduce costs.

[0067] In current applications, some packages are designed with a thermal interface material structure on the back side to achieve high heat dissipation. However, during the reflow process of bonding the conductive terminals to the substrate of the package, material loss of different thermal interface materials may occur at different areas of the package. For example, during the reflow soldering process of the package, when indium (In) is used as the thermal interface material, material loss is found in the peripheral area of ​​the package, while when indium silver (In10Ag) is used as the thermal interface material, material loss is found in the central area. During the reflow soldering process, the material loss of the thermal interface material may be caused by different factors, such as material properties, warpage performance of the package, cover design, and reflow profiles. In some embodiments of the present disclosure, a heat dissipation component with a hybrid thermal interface material is used to avoid the material loss problem.

[0068] Figures 1A to 8 Schematic top view and cross-sectional view of various stages in a method for manufacturing a semiconductor package according to some exemplary embodiments of the present disclosure. Figure 1A , providing an interposer structure 100 (or interconnect structure). In some embodiments, the interposer structure 100 includes a core portion 102, a plurality of through holes 104, and a conductive pad 106 formed therein. In some embodiments, the core portion 102 is a substrate such as a bulk semiconductor substrate, a silicon on insulator (SOI) substrate, or a multilayer semiconductor material substrate. In some embodiments, the semiconductor material of the substrate (core portion 102) includes silicon, germanium, silicon rhodium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or a combination thereof. In some embodiments, the core portion 102 is doped or undoped.

[0069] like Figure 1AAs shown, the conductive pad 106 is formed on the first surface 102a of the core portion 102. In some embodiments, the through hole 104 is formed in the core portion 102 and connected to the conductive pad 106. In some embodiments, the through hole 104 extends into the core portion 102 at a specific depth. In some embodiments, the through hole 104 is a through-substratevias. In some embodiments, when the core portion 102 is a silicon substrate, the through hole 104 is a silicon through-hole. In some embodiments, the through hole 104 is formed by forming a hole or groove in the core portion 102 and then filling the groove with a conductive material. In some embodiments, the groove is formed by, for example, etching, milling, laser drilling or the like. In some embodiments, the conductive material is formed via an electrochemical plating process, chemical vapor deposition (CVD), atomic layer deposition (ALD) or physical vapor deposition (PVD), and the conductive material may include copper, tungsten, aluminum, silver, gold or a combination thereof. In some embodiments, a conductive pad 106 formed on the interposer structure 100 and connected to the via 104 is formed as a conductive portion of a redistribution layer. In some embodiments, the conductive pad 106 includes an under bump metallurgy (UBM). In some embodiments, the interposer structure 100 may also include active or passive devices formed in the core portion 102, such as transistor, capacitor, resistor, or diode passive devices.

[0070] Further Figure 1A As shown, the core part 102 has a plurality of package regions PKR and a dicing lane DL separating each of the plurality of package regions PKR. A through hole 104 and a conductive pad 106 are formed in the core part 102 within the package region PKR. In some embodiments, a plurality of semiconductor dies 21 (first semiconductor dies) and a plurality of semiconductor dies 22 (second semiconductor dies) are disposed on the interposer structure 100 or on the core part 102 within the package region PKR. The semiconductor dies 21 and the semiconductor dies 22 are separate dies cut from a wafer. In some embodiments, the semiconductor dies 21 include the same circuit, such as the same device and metallization pattern, or the semiconductor dies 21 are dies of the same type. In some embodiments, the semiconductor dies 22 include the same circuit, or the semiconductor dies 22 are dies of the same type. In some embodiments, the semiconductor dies 21 and the semiconductor dies 22 have different circuits or are dies of different types. In some embodiments, the semiconductor dies 21 and the semiconductor dies 22 may have the same circuit.

[0071] In some embodiments, semiconductor die 21 is a major die, and semiconductor die 22 is a tributary die. Figure 1B As shown, the main die (semiconductor die 21) is arranged on the core portion 102 in the central area 100A of the interposer structure 100 (interconnection structure) of each package region PKR. The branch die (semiconductor die 22) is arranged on the peripheral area 100B of the interposer structure 100 (interconnection structure) and is arranged side by side and spaced apart from the main die. In some embodiments, the branch die is arranged next to the main die and surrounds or encircles the main die. In one embodiment, each package region PKR arranges four, six, or eight branch dies around each main die. For example, as Figure 1B As shown, in one exemplary embodiment, four semiconductor dies 22 (branch dies) surround each semiconductor die 21 (main die) in each package region PKR.

[0072] Continue to refer back Figure 1A In some embodiments, semiconductor die 21 has a larger surface area than semiconductor die 22. Also, in some embodiments, semiconductor die 21 and semiconductor die 22 have different sizes, including different surface areas and / or different thicknesses. In some embodiments, semiconductor die 21 is a logic die, including a central processing unit (CPU) die, a graphics processing unit (GPU) die, a system-on-a-chip (SoC), a microcontroller, etc. In some embodiments, semiconductor die 21 is a power management die, such as a power management integrated circuit (PMIC) die. In some embodiments, semiconductor die 22 is a memory die, including a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, or a high bandwidth memory (HBM) die. In some other embodiments, semiconductor die 22 is a dummy die that does not perform any electrical function. However, the present disclosure is not limited thereto, and the number, size, and type of semiconductor dies disposed on the core portion 102 may be appropriately adjusted according to product requirements.

[0073] like Figure 1AAs shown, semiconductor die 21 includes a body 210 and connection pads 212 formed on an active surface 211 of body 210. In some embodiments, connection pads 212 may also include a columnar structure for bonding semiconductor die 21 to other semiconductor die 21. In some embodiments, semiconductor die 22 includes a body 220 and connection pads 222 formed on an active surface 221 of body 220. In other embodiments, connection pads 222 may also include a columnar structure for bonding die 22 to other structures.

[0074] In some embodiments, the semiconductor die 21 and the semiconductor die 22 are attached to the first surface 102a of the core portion 102 by flip-chip bonding, for example, with the aid of an electrical connector 110. The electrical connector 110 is formed between the connection pads 212, 222 and the conductive pads 106 through a reflow process, and physically connects the semiconductor die 21, 22 to the core portion 102 of the interposer structure 100. In some embodiments, the electrical connector 110 is located between the semiconductor die 21, 22 and the conductive pads 106. In some embodiments, the semiconductor die 21, 22 is electrically connected to the through-hole 104 and the conductive pads 106 through the electrical connector 110. In some embodiments, when the semiconductor die 22 is a dummy die, the semiconductor die 22 can be attached to the electrical connector 110 by physical connection without establishing an electrical connection therewith. In other words, the connection pads 222 of the semiconductor chip 22 can be, for example, dummy pads.

[0075] In some embodiments, the electrical connector 110 is a microbump, such as a microbump with a copper metal column. In another embodiment, the electrical connector 110 is a solder bump, a lead-free solder bump, or a microbump, such as a controlled collapse chip connection (C4) bump or a microbump containing a copper column. In some embodiments, the bonding between the semiconductor die 21, 22 and the core portion 102 is a solder bond. In some embodiments, the bonding between the semiconductor die 21, 22 and the core portion 102 is a direct metal-to-metal bonding such as copper-to-copper bonding.

[0076] refer to Figure 2In a subsequent step, an underfill structure 112 may be formed to cover the plurality of electrical connectors 110 and fill the space between the semiconductor dies 21, 22 and the interposer structure 100. In some embodiments, the underfill structure 112 also covers the sidewalls of the semiconductor dies 21, 22 and is located within the package region PKR. Thereafter, an insulating encapsulant 114 (or a molding compound) may be formed over the interposer structure 100 (or over the core portion 102) to cover the underfill structure 112 and surround the semiconductor dies 21 and 22.

[0077] In some embodiments, the insulating encapsulation 114 is formed on the first surface 102a of the core part 102 in the packaging region PKR and above the scribe line DL. In some embodiments, the insulating encapsulation 114 is formed by, for example, a compression molding process or transfer molding. In one embodiment, a curing process is performed to cure the insulating encapsulation 114. In some embodiments, the semiconductor die 21, 22 and the electrical connector 110 are encapsulated by the insulating encapsulation 114. In some embodiments, a planarization process (including grinding or polishing) is performed to partially remove the insulating encapsulation 114, thereby exposing the back side surfaces 21S, 22S of the semiconductor die 21, 22. Therefore, the back side surfaces 21S, 22S of the semiconductor die 21, 22 are flush with the top surface 114a of the insulating encapsulation 114. The top surface 114a is opposite to the back side surface 114b of the insulating encapsulation 114, wherein the back side surface 114b is in contact with the core part 102. In some alternative embodiments, the backside surfaces 21S, 22S of the semiconductor dies 21 , 22 are not exposed from the insulating encapsulation 114 and are well protected by the insulating encapsulation 114 .

[0078] In some embodiments, the material of the insulating encapsulation 114 includes a polymer (e.g., epoxy resin, phenolic resin, silicone resin or other suitable resin), a dielectric material with low dielectric constant (Dk) and low loss tangent (Df) characteristics, or other suitable materials. In another embodiment, the insulating encapsulation 114 may include an acceptable insulating encapsulation material. In some embodiments, the insulating encapsulation 114 may also include an inorganic filler or an inorganic compound (e.g., silica, clay, etc.), which may be added thereto to optimize the coefficient of thermal expansion (CTE) of the insulating encapsulation 114. The present disclosure is not limited thereto.

[0079] See also Figure 3 After forming the insulating encapsulation body 114, Figure 2The structure of is turned upside down or flipped over and placed on a carrier Cx so that the carrier Cx directly contacts the backside surfaces 21S, 22S of the semiconductor dies 21, 22 and the top surface 114a of the insulating encapsulation body 114. Figure 3 At this processing stage, the interposer structure 100 has not been thinned and has a thickness Tx. In other words, the vias 104 are not exposed and are embedded in the core portion 102 of the interposer structure 100.

[0080] Please refer to Figure 4 , a thinning process is performed on the interposer structure 100 to partially remove or thin the core portion 102 of the interposer structure 100 until the through hole 104 is exposed and the second surface 102b of the core portion 102 is formed. In some embodiments, the thinning process may include a back grinding process, a polishing process, or an etching process. In some embodiments, after the thinning process, the interposer structure 100 is thinned to a thickness Ty. In some embodiments, the ratio of the thickness Ty to the thickness Tx is in the range of about 0.1 to about 0.5.

[0081] refer to Figure 5 , the redistribution structure 116 is formed on the second surface 102b of the core portion 102 in the package area PKR and above the cutting line DL. The second surface 102b is opposite to the first surface 102a of the core portion 102. In some embodiments, the redistribution structure 116, the core portion 102, the through-hole 104 and the conductive pad 106 constitute an interposer structure 100'. In some embodiments, the redistribution structure 116 is electrically connected to the through-hole 104 and / or electrically connects the through-hole 104 to an external device. In certain embodiments, the redistribution structure 116 includes at least one dielectric layer 116a and a metallization pattern 116b in the dielectric layer 116a. In some embodiments, the metallization pattern 116b may include pads, through-holes and / or traces to internally connect the through-hole 104, and further connect the through-hole 104 to one or more external devices. Although Figure 5 , a dielectric layer 116 a and a metallization pattern 116 b are shown, but it should be noted that the number of layers of the dielectric layer 116 a and the metallization pattern 116 b is not limited thereto and can be adjusted according to requirements.

[0082] In some embodiments, the material of the dielectric layer 116a includes silicon oxide, silicon nitride, silicon carbide, silicon oxynitride or a low dielectric constant (low-K) dielectric material (e.g., phosphosilicate glass material, fluorosilicate glass material, borophosphosilicate glass material, SiOC, spin-on glass material, spin-on polymer or silicon carbon material). In some embodiments, the dielectric layer 116a is formed by spin-coating or deposition, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD) or the like. In some embodiments, the metallization pattern 116b includes an under-bump metal (UBM). In some embodiments, the formation of the metallization pattern 116b may include patterning the dielectric layer using photolithography and one or more etching processes, and filling the metal material into the opening of the patterned dielectric layer. Any excess conductive material on the dielectric layer may be removed, for example, using a chemical mechanical polishing process. In some embodiments, the material of the metallization pattern 116 b includes copper, aluminum, tungsten, silver, and combinations thereof.

[0083] like Figure 5As further shown, a plurality of conductive terminals 118 are disposed on the metallization pattern 116b and electrically coupled to the through hole 104. In some embodiments, the conductive terminal 118 is disposed on the top surface 116s of the redistribution structure and is electrically connected to the through hole 104 through the metallization pattern 116b in the package region PKR. In certain embodiments, the conductive terminal 118 is disposed on the metallization pattern 116b and physically attached to the metallization pattern 116b. In some embodiments, the conductive terminal 118 includes a lead-free solder ball, a solder ball, a ball grid array (BGA) ball, a bump, a controlled collapse chip connection (C4) bump, or a microbump. In some embodiments, the conductive terminal 118 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or a combination thereof. In some embodiments, solder paste is formed on the redistribution structure 116 by, for example, evaporation, electroplating, printing, or solder transfer, and then reflowed into a desired bump shape to form the conductive terminal 118. In some embodiments, the conductive terminal 118 is disposed on the redistribution structure 116 by means of ball placement or the like. In other embodiments, a solder-free metal column (e.g., a copper column) is formed by sputtering, printing, chemical plating, electroplating, or CVD, and then the conductive terminal 118 is formed by plating on the metal column to form a lead-free cap layer. The conductive terminal 118 can be used to connect to an external device or an additional electrical component. In some embodiments, the conductive terminal 118 is used to connect to a circuit substrate, a semiconductor substrate, or a packaging substrate.

[0084] refer to Figure 6 After forming the conductive terminals 118, the carrier Cx is stripped. For example, the stripping process includes projecting light such as laser or ultra-voilet (UV) light onto a stripping layer (e.g., a light-to-heat-conversion release layer) attached to the carrier (not shown), so that the carrier Cx can be easily removed together with the stripping layer. In some embodiments, the backside surfaces 21S, 22S of the semiconductor dies 21, 22 are exposed after the stripping process.

[0085] refer to Figure 7 In the subsequent steps, Figure 6 The structure shown is attached to a tape TP (eg, dicing tape) supported by a frame FR. Figure 6The structure shown is cut or singulated to form a plurality of semiconductor packages SM1. For example, a cutting process is performed to cut through the redistribution structure 116, the core portion 102, and the insulating encapsulation body 114 to remove portions of the redistribution structure 116, the core portion 102, and the insulating encapsulation body 114 along the dicing lines DL. In some embodiments, the cutting process or singulation process generally involves cutting using a rotating blade or a laser beam. In other words, the cutting or singulation process is, for example, a laser cutting process, a mechanical sawing process, or other suitable processes.

[0086] refer to Figure 8 , after separating the carrier Cx, a singulated semiconductor package SM1 can be obtained. In some embodiments, a back metal layer 120 is optionally formed on the back side surfaces 21S, 22S of the semiconductor die 21, 22. The back metal layer 120 can also be considered as a part of the semiconductor package SM1. In some embodiments, the back metal layer 120 may include a metal material such as aluminum (Al), titanium (Ti), nickel (Ni), vanadium (V), gold (Au), silver (Ag) or copper (Cu). In some embodiments, the back metal layer 120 is formed by sputtering, electroplating, deposition or dispensing processes. In certain embodiments, the thickness of the back metal layer 120 is in the range of about 0.1 μm to about 10 μm. After forming the back metal layer 120, the semiconductor package SM1 according to some embodiments of the present disclosure is completed.

[0087] Fig. 9 is a schematic cross-sectional view of a semiconductor package according to some other exemplary embodiments of the present disclosure. Fig. 9 The semiconductor package SM2 shown in Figure 8 Therefore, the same component symbols will be used to represent the same or similar parts, and their detailed description will be omitted here. The difference between the embodiments is that Figure 8 The interposer structure 100' is shown Fig. 9 The redistribution layer RDL (or interconnect structure) shown in FIG. Fig. 9 As shown, the redistribution layer RDL is disposed on the insulating encapsulation 114 and is electrically connected to the semiconductor dies 21 , 22 through the electrical connector 110 .

[0088] In some embodiments, the redistribution layer RDL is formed by sequentially forming one or more dielectric layers 101A and one or more conductive layers 101B that are alternately stacked. In some embodiments, the conductive layer 101B is sandwiched between the dielectric layers 101A and is electrically and physically connected to the electrical connector 110. In an exemplary embodiment, the number of dielectric layers 101A and conductive layers 101B included in the redistribution layer RDL is not limited thereto, but may be specified and selected according to design requirements. For example, the number of dielectric layers 101A and conductive layers 101B may be one or more than one layer.

[0089] In some embodiments, the material of the dielectric layer 101A is polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like, and it can be patterned using photolithography and / or etching processes. In some embodiments, the material of the dielectric layer 101A is formed by a suitable manufacturing technique such as spin coating, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or the like. The present disclosure is not limited thereto.

[0090] In some embodiments, the material of the conductive layer 101B is made of a conductive material formed by electroplating or deposition, such as aluminum, titanium, copper, nickel, tungsten, and / or alloys thereof, which can be patterned using photolithography and etching processes. In some embodiments, the conductive layer 101B may be a patterned copper layer or other suitable patterned metal layer. Throughout the specification, the term "copper" is intended to include substantially pure elemental copper, copper containing inevitable impurities, and copper alloys containing small amounts of elements (such as tantalum, indium, tin, zinc, manganese, chromium, titanium, germanium, strontium, platinum, magnesium, aluminum, or zirconium, etc.).

[0091] In some embodiments, the redistribution layer RDL also includes a plurality of conductive pads 101C disposed on the conductive layer 101B for electrically connecting to the conductive terminals 118. In some embodiments, the material of the conductive pads 101C may include copper, nickel, titanium, tungsten. Or its alloys, etc., and may be formed by, for example, an electroplating process. The present disclosure does not limit the number of conductive pads 101C, and it may be selected based on the design layout. In some embodiments, the conductive pads 101C may be omitted. In other words, the conductive terminals 118 formed in subsequent steps may be directly disposed on the conductive layer 101B of the redistribution layer RDL.

[0092] Figures 10 to 15 Schematic top view and cross-sectional view of various stages in a method for manufacturing a package structure according to some exemplary embodiments of the present disclosure. Fig.10 , in some embodiments, Figure 8 The semiconductor package SM1 obtained is mounted or attached to the circuit substrate 300 through the conductive terminal 118. In some embodiments, the circuit substrate 300 includes a contact pad 310, a contact pad 320, a metallization layer 330 and a through hole (not shown). In some embodiments, the contact pad 310 and the contact pad 320 are respectively distributed on opposite sides of the circuit substrate 300, and are exposed to be electrically connected to the components / features formed subsequently. In some embodiments, the metallization layer 330 and the through hole are embedded in the circuit substrate 300, and together provide the circuit substrate 300 with a wiring function, wherein the metallization layer 330 and the through hole are electrically connected to the contact pad 310 and the contact pad 320. In other words, at least some of the contact pads 310 are electrically connected to some of the contact pads 320 through the metallization layer 330 and the through hole. In some embodiments, the contact pad 310 and the contact pad 320 may include a metal pad or a metal alloy pad. In some embodiments, the material of the metallization layer 330 and the vias may be substantially the same as or similar to the material of the contact pads 310 and the contact pads 320 .

[0093] Furthermore, in some embodiments, the semiconductor package SM1 is bonded to the circuit substrate 300 by physically connecting the conductive terminals 118 with the contact pads 310 to form a stacked structure. In some embodiments, the semiconductor package SM1 includes a central region R1 and a peripheral region R2, whereby some semiconductor dies 21 are located in the central region R1 and some semiconductor dies 22 are located in the peripheral region R2. In certain embodiments, the semiconductor package SM1 is electrically connected to the circuit substrate 300. In some embodiments, the circuit substrate 300 is, for example, an organic flexible substrate or a printed circuit board. In some embodiments, the semiconductor package SM1 is bonded to the circuit substrate 300 by physically connecting the conductive terminals 118 and the contact pads 310 of the circuit substrate 300 through a chip on wafer on substrate (CoWoS) packaging process. Additionally, as Fig.10 As shown, the passive device PDX (integrated passive device or surface mount component) can be mounted on the circuit substrate 300. For example, the passive device PDX can be mounted on the contact pad 310 of the circuit substrate 300 by a welding process. The present disclosure is not limited to this. In some embodiments, the passive device PDX can be mounted on the circuit substrate around the semiconductor package SM1. In some embodiments, the passive device PDX is omitted.

[0094] like Fig.10 As further shown, in some embodiments, an underfill structure 350 is formed to fill the space between the circuit substrate 300 and the semiconductor package SM. In some embodiments, the underfill structure 350 fills the space between adjacent conductive terminals 118 and covers the conductive terminals 118. For example, the underfill structure 350 surrounds a plurality of conductive terminals 118. In some embodiments, the passive device PDX is exposed by the underfill structure 350 and is kept at a certain distance from the underfill structure 350. In other words, the underfill structure 350 does not cover the passive device PDX.

[0095] refer to Fig.11 In a subsequent step, the first thermal interface material 410A is disposed on the central region R1 above the back metal layer 120, wherein the first thermal interface material 410A is located outside the peripheral region R2. For example, the first thermal interface material 410A is disposed on the semiconductor die 21 and overlaps with the semiconductor die 21. In some embodiments, the first thermal interface material 410A is applied to the upper surface of the back metal layer 120 by a pick-and-place process. In some embodiments, a flux material (not shown) may be used to promote attachment between the first thermal interface material 410A and the back metal layer 120 below. For example, the flux material is applied to the back metal layer 120 by a flux jetting process to promote soldering, brazing and / or welding between the semiconductor package SM1 and the layers formed above it. In some embodiments, the first thermal interface material 410A is a suitable candidate material for helping the semiconductor package SM1 dissipate heat. In an exemplary embodiment, the first thermal interface material 410A is indium (In). In some embodiments, the first thermal interface material 410A may have a thermal conductivity greater than about 1 W / (m·K), greater than about 5 W / (m·K), greater than about 10 W / (m·K), or higher.

[0096] refer to Fig.12, in a subsequent step, the second thermal interface material 410B is disposed on the peripheral region R2 above the back metal layer 120. For example, the second thermal interface material 410B is disposed next to the first thermal interface material 410A and is in physical contact with the first thermal interface material 410A. In some embodiments, the second thermal interface material 410B is applied to the upper surface of the back metal layer 120 by a pick-and-place process. In some embodiments, the same flux material (not shown) as described above can be used to promote the attachment between the second thermal interface material 410B and the back metal layer 120 below. In the present embodiment, the first thermal interface material 410A and the second thermal interface material 410B together constitute a thermal interface material structure 410, wherein the first thermal interface material 410A and the second thermal interface material 410B include different materials. In an exemplary embodiment, the second thermal interface material 410B is indium silver (In10Ag). In some embodiments, the second thermal interface material 410B may have a thermal conductivity greater than about 1 W / (m·K), greater than about 5 W / (m·K), greater than about 10 W / (m·K), or higher.

[0097] FIG. 13A to FIG. 13E Shows Fig.12 A top view of different possible arrangements of the first thermal interface material 410A and the second thermal interface material 410B on the semiconductor package SM1 is shown. Fig.13A As shown, in one embodiment, the first thermal interface material 410A is disposed on the central region R1 of the semiconductor package SM1, wherein the first thermal interface material 410A covers and overlaps with two semiconductor dies 21. In some embodiments, the second thermal interface material 410B is disposed on the peripheral region R2 of the semiconductor package SM1 and is disposed on two opposite side surfaces of the first thermal interface material 410A. For example, the second thermal interface material 410B covers each semiconductor die 22 and overlaps each semiconductor die 22.

[0098] refer to Fig. 13B In another embodiment, the first thermal interface material 410A is disposed on the central region R1 of the semiconductor package SM1, wherein the first thermal interface material 410A covers and overlaps with the two semiconductor dies 21. In some embodiments, the area occupied by the first thermal interface material 410A is substantially equal to the area occupied by the two semiconductor dies 21. For example, one or more side surfaces of the first thermal interface material 410A may be aligned with the side surfaces of the two semiconductor dies 21. In addition, the second thermal interface material 410B is disposed on the peripheral region R2 of the semiconductor package SM1 and laterally surrounds the first thermal interface material 410A. In certain embodiments, the second thermal interface material 410B covers each semiconductor die 22 and overlaps with each semiconductor die 22.

[0099] refer to Fig. 13C In another embodiment, the first thermal interface material 410A is disposed on the central region R1 of the semiconductor package SM1, wherein the first thermal interface material 410A covers and overlaps two semiconductor dies 21, and covers and overlaps a portion of the semiconductor die 22. In some embodiments, the second thermal interface material 410B is disposed on the peripheral region R2 of the semiconductor package SM1, and is disposed at the four corners of the first thermal interface material 410A. For example, the second thermal interface material 410B located at the four corners of the first thermal interface material 410A, or the second thermal interface material 410B located at the four corners of the semiconductor package SM1 are separated from each other by the first thermal interface material 410A. The second thermal interface material 410B disposed at each of the four corners may include a square / rectangular pattern that covers or overlaps one semiconductor die 22, respectively.

[0100] refer to Fig.13D In another embodiment, the first thermal interface material 410A is disposed on the central region R1 of the semiconductor package SM1, wherein the first thermal interface material 410A covers and partially overlaps with two semiconductor dies 21, and covers and overlaps with a portion of the semiconductor die 21. In some embodiments, the second thermal interface material 410B is disposed on the peripheral region R2 of the semiconductor package SM1, and is disposed on two opposite side surfaces of the first thermal interface material 410A. For example, the second thermal interface material 410B covers and partially overlaps with two semiconductor dies 21, and covers and overlaps with another portion of the semiconductor die 21.

[0101] Please refer to Fig.13E In another embodiment, the first thermal interface material 410A is disposed on the central region R1 of the semiconductor package SM1, wherein the first thermal interface material 410A covers and overlaps with two semiconductor dies 21. In addition, the second thermal interface material 410B is disposed on the peripheral region R2 of the semiconductor package SM1, wherein the second thermal interface material 410B includes a plurality of square / rectangular patterns, and each square / rectangular pattern covers or overlaps with a semiconductor die 22. In some embodiments, each square / rectangular pattern of the second thermal interface material 410B is separated from each other by an air gap Ax. In addition, the side surface of each square / rectangular pattern of the second thermal interface material 410B is attached to the side surface of the first thermal interface material 410A.

[0102] By the above FIG. 13A to FIG. 13EIt can be seen from the illustrated embodiment that the relative positions of the first thermal interface material 410A and the second thermal interface material 410B can be appropriately adjusted, as long as the first thermal interface material 410A is disposed in the central region R1 on the semiconductor package SM1, and the second thermal interface material 410B is disposed in the peripheral region R2 on the semiconductor package SM1. In some embodiments, the first thermal interface material 410A is disposed in the central region R1, corresponding to the low warpage exchange region (low warpage exchange region) of the semiconductor package SM1. In certain embodiments, the second thermal interface material 410B is disposed in the peripheral region R2, corresponding to the high warpage exchange region (high warpage exchange region) of the semiconductor package SM1. In addition, Fig.12 The first thermal interface material 410A and the second thermal interface material 410B shown may also be based on FIG. 13A to FIG. 13E The method shown in any of the embodiments is set on the semiconductor package SM1.

[0103] See also Fig.14 After forming the thermal interface material structure 410 including the first thermal interface material 410A and the second thermal interface material 410B, a plating layer 420 is formed on the thermal interface material structure 410, and a cover structure 440 is attached to the circuit substrate 300 by an adhesive 430. In some embodiments, before attaching the plating layer 420 to the thermal interface material structure 410, a flux material is applied to the thermal interface material structure 410 by a flux spraying process to facilitate soldering, brazing and / or welding between the thermal interface material structure 410 and the layer formed thereon. In some embodiments, the cover structure 440 is attached to the thermal interface material structure 410 together with the plating layer 420 by the flux material.

[0104] In an exemplary embodiment, the plating layer 420 includes a first plating layer 420A and a second plating layer 420B. For example, the first plating layer 420A is disposed on the first thermal interface material 410A and has a pattern corresponding to the pattern of the first thermal interface material 410A below. Similarly, the second plating layer 420B is disposed on the second thermal interface material 410B and has a pattern corresponding to the pattern of the second thermal interface material 410B below. In other words, the first plating layer 420A is disposed on the thermal interface material structure 410 above the central region R1, and the second plating layer 420B is disposed on the thermal interface material structure 410 above the peripheral region R2. In an exemplary embodiment, the first plating layer 420A and the second plating layer 420B are made of the same material. For example, the first plating layer 420A and the second plating layer 420B include nickel-gold (Ni-Au) plating.

[0105] refer to Fig.15 After the cover structure 440 is attached together with the plating layer 420 to the thermal interface material structure 410, a heating process (hot clamping process) is performed to fix the plating layer 420 to the thermal interface material structure 410. For example, after the heating process, a first intermetallic compound IMC1 is formed between the first thermal interface material 410A and the first plating layer 420A in the central region R1, and a second intermetallic compound IMC2 is formed between the second thermal interface material 410B and the second plating layer 420B. For example, the first intermetallic compound IMC1 is formed over the central region R1 of the semiconductor package SM1, and the second intermetallic compound IMC2 is formed over the peripheral region R2 of the semiconductor package SM1. In some embodiments, the heating process is performed at a temperature range of 100°C to 200°C.

[0106] In some embodiments, the position of the first intermetallic compound IMC1 corresponds to the position of the first thermal interface material 410A, and the position of the formed second intermetallic compound IMC2 corresponds to the position of the second thermal interface material 410B. For example, if the first thermal interface material 410A and the second thermal interface material 410B are formed according to Fig.13A or Fig.13D If the first thermal interface material 410A and the second thermal interface material 410B are arranged in the manner shown, the second intermetallic compound IMC2 can also be formed on two opposite side surfaces of the first intermetallic compound IMC1. Fig. 13C In the manner shown, the second intermetallic compound IMC2 may be formed on the four corners of the first intermetallic compound IMC1.

[0107] In an exemplary embodiment, the first thermal interface material 410A is indium (In), the second thermal interface material 410B is (In10Ag), and the first plating layer 420A and the second plating layer 420B include plated nickel gold (Ni-Au). In this case, the first intermetallic compound IMC1 formed between the first thermal interface material 410A and the first plating layer 420A will include at least one selected from the group consisting of AuIn2 and Ni-Au-In, and the second intermetallic compound IMC2 formed between the second thermal interface material 410B and the second plating layer 420B will include at least one selected from the group consisting of AgIn, AuIn 2, Ni-Ag-In, and Ni-Au-In. In one embodiment, the first intermetallic compound IMC1 includes at least AuIn2, and the second intermetallic compound includes at least Ni-Ag-In. In some embodiments, the first intermetallic compound IMC1 and the second intermetallic compound IMC2 include different materials.

[0108] like Fig.15 As further shown, after forming the first intermetallic compound IMC1 and the second intermetallic compound IMC2, a plurality of conductive terminals 340 are respectively formed on the circuit substrate 300. For example, the conductive terminals 340 are connected and bonded to the contact pads 320 of the circuit substrate 300 through a reflow process. In other words, the conductive terminals 340 are electrically connected to the circuit substrate 300 through the contact pads 320. Through the contact pads 310 and the contact pads 320, some of the conductive terminals 340 are electrically connected to the semiconductor package SM1 (for example, to the semiconductor dies 21 and 22 included therein). In some embodiments, the conductive terminals 340 are, for example, solder balls or ball grid array (BGA) balls.

[0109] After the conductive terminal 340 is formed on the circuit substrate 300, the package structure PK1 according to some embodiments of the present disclosure is completed. In the package structure PK1, the first heat dissipation component HX1 and the second heat dissipation component HX2 are formed on the semiconductor package SM1 to provide an improved heat dissipation effect. In the present embodiment, the first heat dissipation component HX1 includes a first thermal interface material 410A, a first intermetallic compound IMC1 and a first plating layer 420A, and the second heat dissipation component HX2 includes a second thermal interface material 410B, a second intermetallic compound IMC2 and a second plating layer 420B. In the present exemplary embodiment, since the first heat dissipation component HX1 is disposed in the central region R1 above the semiconductor package SM1, and the second heat dissipation component HX2 is disposed in the peripheral region R2 above the semiconductor package SM1, and the first heat dissipation component HX1 and the second heat dissipation component HX2 include mixed thermal interface materials (410A, 410B), the material loss of the thermal interface material structure 410 is minimized during the reflow process of bonding the conductive terminal 340 to the circuit substrate 300. As such, by using different heat dissipation material components in different regions of the semiconductor package SM1 , the resulting package structure PK1 may have improved reliability and heat dissipation performance.

[0110] Fig.16 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Fig.16 The package structure PK2 shown is Fig.15 The package structure PK1 shown is similar. Therefore, the same component symbols will be used to represent the same or similar parts, and their detailed description will be omitted here. The difference between the embodiments is that Fig.16 The semiconductor package SM2 shown is used to replace Fig.15 The semiconductor package SM1 is shown. The details of the semiconductor package SM2 can be referred to Fig. 9 The description of will not be repeated here. Fig.16As shown, in an exemplary embodiment, since the first heat dissipation component HX1 is disposed in the central region R1 above the semiconductor package SM1, and the second heat dissipation component HX2 is disposed in the peripheral region R2 above the semiconductor package SM1, and the first heat dissipation component HX1 and the second heat dissipation component HX2 include mixed thermal interface materials (410A, 410B), the material loss of the thermal interface material structure 410 is minimized during the reflow process of bonding the conductive terminal 340 to the circuit substrate 300. In this way, by using different heat dissipation material components in different regions of the semiconductor package SM2, the resulting package structure PK2 can have improved reliability and heat dissipation performance.

[0111] Figures 17 to 20 are schematic top views and cross-sectional views of various stages in a method for manufacturing a package structure according to some other exemplary embodiments of the present disclosure. Figures 17 to 20 The method shown is similar to Figures 1A to 15 Therefore, the same component symbols will be used to represent the same or similar parts, and their detailed description will be omitted here. Fig.17 , is executed with Figures 1A to 10 The same steps as shown in the figure are performed to form a semiconductor package SM1 on the circuit substrate 300. Subsequently, the thermal interface material structure 410 is disposed on the central region R1 and the peripheral region R2 of the semiconductor package SM1 by a pick-and-place process, and is located above the back metal layer 120. For example, the first thermal interface material 410A is disposed on the central region R1 and overlaps with the semiconductor die 21, while the second thermal interface material 410B is disposed on the peripheral region R2 and overlaps with the semiconductor die 22. In some embodiments, a flux material (not shown) can be used to promote the attachment between the first thermal interface material 410A, the second thermal interface material 410B and the back metal layer 120 located below.

[0112] In some embodiments, the first thermal interface material 410A and the second thermal interface material 410B are made of the same material. For example, the material of the first thermal interface material 410A and the second thermal interface material 410B is indium (In). In some embodiments, the first thermal interface material 410A and the second thermal interface material 410B may have a thermal conductivity greater than about 1 W / (m·K), greater than about 5 W / (m·K), greater than about 10 W / (m·K), or higher.

[0113] refer to Fig.18After forming the thermal interface material structure 410 including the first thermal interface material 410A and the second thermal interface material 410B, a plating layer 420 is formed over the thermal interface material structure 410, and a cover structure 440 is attached to the circuit substrate 300 by an adhesive 430. In some embodiments, before attaching the plating layer 420 to the thermal interface material structure 410, a flux material is applied to the thermal interface material structure 410 by a flux spraying process to facilitate soldering, brazing and / or welding between the thermal interface material structure 410 and the layer formed thereon. In some embodiments, the cover structure 440 is attached to the thermal interface material structure 410 together with the plating layer 420 by the flux material.

[0114] In an exemplary embodiment, the plating layer 420 includes a first plating layer 420A and a second plating layer 420B. For example, the first plating layer 420A is disposed on the thermal interface material structure 410 above the central region R1, and the second plating layer 420B is disposed on the thermal interface material structure 410 above the peripheral region R2. In an exemplary embodiment, the first plating layer 420A and the second plating layer 420B are made of different materials. For example, the first plating layer 420A includes plated nickel gold (Ni-Au), and the second plating layer 420B includes plated nickel silver (Ni-Ag).

[0115] FIG. 19A to FIG. 19E Shows Fig.18 FIG. 4 is a top view of possible different arrangements of the first plating layer 420A and the second plating layer 420B on the thermal interface material structure 410. Fig.19A As shown, in one embodiment, the first plating layer 420A is disposed on the first thermal interface material 410A above the central region R1 of the semiconductor package SM1. For example, the first plating layer 420A covers and overlaps with two semiconductor dies 21. In some embodiments, the second plating layer 420B is disposed on the second thermal interface material 410B above the peripheral region R2 of the semiconductor package SM1, and is disposed on two opposite side surfaces of the first plating layer 420A. For example, the second plating layer 420B covers each semiconductor die 22 and overlaps with each semiconductor die 22.

[0116] refer to Fig.19BIn another embodiment, the first plating layer 420A is disposed on the first thermal interface material 410A and is located above the central region R1 of the semiconductor package SM1, wherein the first plating layer 420A covers and overlaps with the two semiconductor dies 21. In some embodiments, the area occupied by the first plating layer 420A is substantially equivalent to the area occupied by the two semiconductor dies 21. For example, one or more side surfaces of the first plating layer 420A may be aligned with the side surfaces of the two semiconductor dies 21. In addition, the second plating layer 420B is disposed on the second thermal interface material 410B above the peripheral region R2 of the semiconductor package SM1 and laterally surrounds the first plating layer 420A. In some embodiments, the second plating layer 420B covers each semiconductor die 22 and overlaps with each semiconductor die 22.

[0117] refer to Fig.19C In another embodiment, the first plating layer 420A is disposed on the first thermal interface material 410A and is located above the central region R1 of the semiconductor package SM1, wherein the first plating layer 420A covers and overlaps two semiconductor dies 21, and covers and overlaps a portion of the semiconductor die 22. In some embodiments, the second plating layer 420B is disposed on the second thermal interface material 410B above the peripheral region R2 of the semiconductor package SM1, and is disposed on the four corners of the first plating layer 420A. For example, the second plating layers 420B located on the four corners of the first plating layer 420A, or the second plating layers 420B located on the four corners of the semiconductor package SM1 are separated from each other by the first plating layer 420A. The second plating layer 420B disposed at each of the four corners may include a square / rectangular pattern that covers or overlaps one semiconductor die 22, respectively.

[0118] refer to Fig.19D In another embodiment, the first plating layer 420A is disposed on the first thermal interface material 410A and is located above the central region R1 of the semiconductor package SM1, wherein the first plating layer 420A covers and partially overlaps the two semiconductor dies 21, and covers and overlaps a portion of the semiconductor die 22. In some embodiments, the second plating layer 420B is disposed on the second thermal interface material 410B above the peripheral region R2 of the semiconductor package SM1, and is disposed on two opposite side surfaces of the first plating layer 420A. For example, the second plating layer 420B covers and partially overlaps the two semiconductor dies 21, and covers and overlaps another portion of the semiconductor die 22.

[0119] refer to Fig.19EIn another embodiment, the first plating layer 420A is disposed on the first thermal interface material 410A and above the central region R1 of the semiconductor package SM1, wherein the first plating layer 420A covers and overlaps two semiconductor dies 21. In some embodiments, the second plating layer 420B is disposed on the second thermal interface material 410B above the peripheral region R2 of the semiconductor package SM1, wherein the second plating layer 420B includes a plurality of square / rectangular patterns, and each square / rectangular pattern covers or overlaps a semiconductor die 22. In some embodiments, each square / rectangular pattern of the second plating layer 420B is separated from each other by the first plating layer 420A. In other words, the first plating layer 420A laterally surrounds each square / rectangular pattern of the second plating layer 420B.

[0120] From the above FIG. 19A to FIG. 19E It can be seen from the illustrated embodiment that the relative positions of the first plating layer 420A and the second plating layer 420B can be appropriately adjusted, as long as the first plating layer 420A is disposed in the central region R1 on the semiconductor package SM1, and the second plating layer 420B is disposed in the peripheral region R2 on the semiconductor package SM1. In some embodiments, the first plating layer 420A is disposed in the central region R1, corresponding to the low warpage exchange region of the semiconductor package SM1. In some embodiments, the second plating layer 420B is disposed in the peripheral region R2, corresponding to the high warpage exchange region of the semiconductor package SM1. In addition, Fig.18 The first plating layer 420A and the second plating layer 420B shown can be FIG. 19A to FIG. 19E Any of the embodiments shown is disposed on a thermal interface material structure 410 above the semiconductor package SM1.

[0121] refer to Fig. 20 After the cover structure 440 is attached together with the plating layer 420 to the thermal interface material structure 410, a heating process (hot clamping process) is performed to fix the plating layer 420 to the thermal interface material structure 410. For example, after the heating process, a first intermetallic compound IMC1 is formed between the first thermal interface material 410A and the first plating layer 420A in the central region R1, and a second intermetallic compound IMC2 is formed between the second thermal interface material 410B and the second plating layer 420B. For example, the first intermetallic compound IMC1 is formed over the central region R1 of the semiconductor package SM1, and the second intermetallic compound IMC2 is formed over the peripheral region R2 of the semiconductor package SM1. In some embodiments, the heating process is performed at a temperature range of 100°C to 200°C.

[0122] In an exemplary embodiment, the first thermal interface material 410A and the second thermal interface material 410B are indium (In), while the first plating layer 420A includes plated nickel gold (Ni-Au), and the second plating layer 420B includes plated nickel silver (Ni-Ag). In this case, the first intermetallic compound IMC1 formed between the first thermal interface material 410A and the first plating layer 420A will include at least one selected from the group consisting of AuIn2 and Ni-Au-In, and the second intermetallic compound IMC2 formed between the second thermal interface material 410B and the second plating layer 420B will include at least one selected from the group consisting of AgIn and Ni-Ag-In. In other words, the first intermetallic compound IMC1 and the second intermetallic compound IMC2 include different materials.

[0123] like Fig. 20 As further shown, after forming the first intermetallic compound IMC1 and the second intermetallic compound IMC2, a plurality of conductive terminals 340 are respectively formed on the circuit substrate 300. In some embodiments, the conductive terminals 340 are, for example, solder balls or ball grid array (BGA) balls. After forming the conductive terminals 340 on the circuit substrate 300, the package structure PK3 according to some embodiments of the present disclosure is completed.

[0124] In the package structure PK3, the first heat dissipation component HX1 and the second heat dissipation component HX2 are formed on the semiconductor package SM1 to provide improved heat dissipation. In the present embodiment, the first heat dissipation component HX1 includes a first thermal interface material 410A, a first intermetallic compound IMC1, and a first plating layer 420A, and the second heat dissipation component HX2 includes a second thermal interface material 410B, a second intermetallic compound IMC2, and a second plating layer 420B. In the present exemplary embodiment, since the first heat dissipation component HX1 is disposed in the central region R1 above the semiconductor package SM1, and the second heat dissipation component HX2 is disposed in the peripheral region R2 above the semiconductor package SM1, and the first heat dissipation component HX1 and the second heat dissipation component HX2 include mixed plating layer materials (420A, 420B), the mixed plating layer materials (420A, 420B) can react with different regions of the thermal interface material structure 410 to form intermetallic compounds (IMC1, IMC2) with different thermal properties. Thus, material loss of the thermal interface material structure 410 is minimized during the soldering process of bonding the conductive terminal 340 to the circuit substrate 300. Overall, by using different heat dissipation material components on different regions of the semiconductor package SM1, the resulting package structure PK3 can have improved reliability and heat dissipation performance.

[0125] Fig.21is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Fig.21 The package structure PK4 shown is Fig. 20 The package structure PK3 shown is similar. Therefore, the same component symbols will be used to represent the same or similar parts, and their detailed description will be omitted here. The difference between the embodiments lies in the design of the thermal interface material structure 410 and the plating layer 420. Fig. 20 In the embodiment of FIG. 4 , the first plating layer 420A and the second plating layer 420B are shown to have the same thickness. However, the present disclosure is not limited thereto. Fig.21 As shown, the first plating layer 420A and the second plating layer 420B have different thicknesses. For example, the second plating layer 420B is formed to have a thickness greater than the first plating layer 420B. In such an embodiment, the first intermetallic compound IMC1 is formed to be misaligned with the second intermetallic compound IMC2. In addition, the thickness of the first thermal interface material 410A can be greater than the thickness of the second thermal interface material 410B.

[0126] exist Fig.21 In the package structure PK4 shown, since the first heat dissipation component HX1 is arranged in the central region R1 above the semiconductor package SM1, and the second heat dissipation component HX2 is arranged in the peripheral region R2 above the semiconductor package SM1, the first heat dissipation component HX1 is set in the central region R1 above the semiconductor package SM1, and the first heat dissipation component HX1 and the second heat dissipation component HX2 include mixed plating layer materials (420A, 420B), so the mixed plating layer materials (420A, 420B) can react with different regions of the thermal interface material structure 410 to form intermetallic compounds (IMC1, IMC2) with different thermal properties. In this way, during the welding process of bonding the conductive terminal 340 to the circuit substrate 300, the material loss of the thermal interface material structure 410 will be minimized. Overall, by using different heat dissipation material components on different regions of the semiconductor package SM1, the resulting package structure PK4 can have improved reliability and heat dissipation performance.

[0127] Fig. 22 is a schematic cross-sectional view of a packaging structure according to some other exemplary embodiments of the present disclosure. Fig. 22 The package structure PK5 shown is Fig. 20 Therefore, the same component symbols will be used to represent the same or similar parts, and their detailed description will be omitted here. Fig. 22 The semiconductor package SM2 shown in the figure is used as an alternative Fig. 20 The semiconductor package SM1 shown in FIG. The details of the semiconductor package SM2 can be referred to Fig. 9 The description of will not be repeated here. Fig. 22 As shown, in an exemplary embodiment, since the first heat dissipation component HX1 is disposed in the central region R1 above the semiconductor package SM1, and the second heat dissipation component HX2 is disposed in the peripheral region R2 above the semiconductor package SM1, and the first heat dissipation component HX1 and the second heat dissipation component HX2 include mixed thermal interface materials (410A, 410B), the material loss of the thermal interface material structure 410 is minimized during the reflow process of bonding the conductive terminal 340 to the circuit substrate 300. Overall, by using different heat dissipation material components on different regions of the semiconductor package SM2, the resulting package structure PK5 can have improved reliability and heat dissipation performance.

[0128] In the above embodiment, the first heat dissipation component and the second heat dissipation component are arranged on the back surface of the semiconductor package. Since the first heat dissipation component and the second heat dissipation component include different thermal interface materials or different plating layer materials, during the reflow process of forming the package structure, the material loss of the thermal interface material structure in different areas above the semiconductor package will be minimized. In this way, by utilizing the flexible thermal characteristics of different heat dissipation material components in different areas of the semiconductor package, the obtained package structure can have improved reliability and heat dissipation performance.

[0129] According to some embodiments of the present disclosure, a packaging structure includes a circuit substrate, a semiconductor package, a thermal interface material structure, a plating layer, a first intermetallic compound, a second intermetallic compound, and a cover structure. The semiconductor package is disposed on the circuit substrate and electrically connected to the circuit substrate, wherein the semiconductor package includes a central area and a peripheral area. The thermal interface material structure is disposed on the central area and the peripheral area of ​​the semiconductor package. The plating layer is disposed on the thermal interface material structure. The first intermetallic compound is formed between the thermal interface material structure and the plating layer above the central area of ​​the semiconductor package. The second intermetallic compound is formed between the thermal interface material structure and the plating layer above the peripheral area of ​​the semiconductor package, wherein the second intermetallic compound is different from the first intermetallic compound. The cover structure is disposed on the circuit substrate and covers the semiconductor package.

[0130] In some embodiments, the thickness of the first plating layer is different from the thickness of the second plating layer. In some embodiments, the second intermetallic compound is formed on two opposite side surfaces of the first intermetallic compound. In some embodiments, the second intermetallic compound is formed at four corners of the first intermetallic compound.

[0131] According to some other embodiments of the present disclosure, a packaging structure includes an interconnect structure, a plurality of first semiconductor dies, a plurality of second semiconductor dies, a first heat dissipation component, a second heat dissipation component, and a cover structure. The first semiconductor die is disposed on a central area of ​​the interconnect structure and is electrically connected to the interconnect structure. The second semiconductor die is disposed on a peripheral area of ​​the interconnect structure and is electrically connected to the interconnect structure. The first heat dissipation component is disposed on the back side of the plurality of first semiconductor dies and covers the back side of the plurality of first semiconductor dies. The second heat dissipation component is disposed on the back side of the plurality of second semiconductor chips and covers the back side of the plurality of second semiconductor chips, wherein the first heat dissipation component and the second heat dissipation component include different materials. The cover structure is disposed on the first heat dissipation component and the second heat dissipation component and contacts the first heat dissipation component and laterally surrounds the first heat dissipation component, the second heat dissipation component, the plurality of first semiconductor dies, the plurality of second semiconductor dies, and the interconnect structure.

[0132] In some embodiments, the first thermal interface material is indium (In), the second thermal interface material is indium silver (In10Ag), and the first plating layer and the second plating layer include plated nickel gold (Ni-Au). In some embodiments, the first thermal interface material and the second thermal interface material are indium (In), the first plating layer includes plated nickel gold (Ni-Au), and the second plating layer includes plated nickel silver (Ni-Ag). In some embodiments, the package structure further includes a first intermetallic compound formed between the first thermal interface material and the first plating layer, and a second intermetallic compound formed between the second thermal interface material and the second plating layer. In some embodiments, the first intermetallic compound includes at least one selected from the group consisting of AuIn2 and Ni-Au-In, and the second intermetallic compound includes at least one selected from the group consisting of AgIn, AuIn2, Ni-Ag-In, and Ni-In.

[0133] According to another embodiment of the present disclosure, a method for manufacturing a package structure is described. The method includes the following steps. A semiconductor package is disposed on a circuit substrate, wherein the semiconductor package includes a central area and a peripheral area. A thermal interface material structure is formed on the central area and the peripheral area of ​​the semiconductor package. A plating layer is disposed on the thermal interface material structure, and a cover structure is disposed on the circuit substrate, wherein the cover structure contacts the plating layer and covers the semiconductor package. A heating process is performed to form a first intermetallic compound between the thermal interface material structure and the plating layer above the central area of ​​the semiconductor package, and a second intermetallic compound is formed between the thermal interface material structure and the plating layer above the peripheral area of ​​the semiconductor package, wherein the second intermetallic compound is different from the first intermetallic compound.

[0134] In some embodiments, forming the thermal interface material structure includes forming a first thermal interface material on the central area, and forming a second thermal interface material different from the first thermal interface material on the peripheral area. In some embodiments, the first thermal interface material is indium (In), and the second thermal interface material is indium silver (In10Ag). In some embodiments, the heating process is performed at a temperature range of 100°C to 200°C.

[0135] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A packaging structure, comprising: Circuit substrate; a semiconductor package disposed on the circuit substrate and electrically connected to the circuit substrate, wherein the semiconductor package includes a central area and a peripheral area; a thermal interface material structure disposed on the central region and the peripheral region of the semiconductor package; A coating layer is disposed on the thermal interface material structure; a first intermetallic compound formed between the thermal interface material structure and the plating layer over the central region of the semiconductor package; a second intermetallic compound formed between the thermal interface material structure and the plating layer over the peripheral region of the semiconductor package, wherein the second intermetallic compound is different from the first intermetallic compound; as well as The cover structure is disposed on the circuit substrate and covers the semiconductor package. 2 . The package structure according to claim 1 , wherein the thermal interface material structure comprises a first thermal interface material disposed in the central area and a second thermal interface material different from the first thermal interface material disposed in the peripheral area. 3 . The packaging structure according to claim 2 , wherein the first thermal interface material is In, and the second thermal interface material is In10Ag.

4. The packaging structure according to claim 1, wherein: The plating layer includes a first plating layer disposed on the thermal interface material structure over the central area, and a second plating layer different from the first plating layer disposed on the thermal interface material structure over the peripheral area.

5. The packaging structure according to claim 4, wherein: The first plating layer includes Ni-Au plating, and the second plating layer includes Ni-Ag plating.

6. A packaging structure, comprising: Interconnection line structure; a plurality of first semiconductor dies disposed on a central region of the interconnect structure and electrically connected to the interconnect structure; a plurality of second semiconductor dies disposed on a peripheral region of the interconnect structure and electrically connected to the interconnect structure; a first heat dissipation component disposed on and covering the backsides of the plurality of first semiconductor dies; a second heat dissipation component disposed on and covering the backsides of the plurality of second semiconductor dies, wherein the first heat dissipation component and the second heat dissipation component comprise different materials; as well as A cover structure is disposed above and in contact with the first heat dissipation component and the second heat dissipation component, and laterally surrounds the first heat dissipation component, the second heat dissipation component, the plurality of first semiconductor dies, the plurality of second semiconductor dies, and the interconnection line structure.

7. The packaging structure according to claim 6, wherein: The first heat dissipation component includes a first thermal interface material and a first plating layer disposed on the first thermal interface material; and The second heat dissipation component includes a second thermal interface material and a second plating layer disposed on the second thermal interface material, wherein the second thermal interface material and the first thermal interface material include different materials, or the second plating layer and the first plating layer include different materials. 8 . The package structure according to claim 7 , wherein the first plating layer and the second plating layer have different thicknesses.

9. A method for manufacturing a packaging structure, comprising: Disposing a semiconductor package on a circuit substrate, wherein the semiconductor package includes a central area and a peripheral area; forming a thermal interface material structure on the central region and the peripheral region of the semiconductor package; Disposing a plating layer on the thermal interface material structure, and disposing a cover structure on the circuit substrate, wherein the cover structure contacts the plating layer and covers the semiconductor package; as well as A heating process is performed to form a first intermetallic compound between the thermal interface material structure and the plating layer over the central region of the semiconductor package, and a second intermetallic compound between the thermal interface material structure and the plating layer over the peripheral region of the semiconductor package, wherein the second intermetallic compound is different from the first intermetallic compound. 10 . The method of claim 9 , wherein forming the plating layer comprises forming a first plating layer on the thermal interface material structure over the central area, and forming a second plating layer different from the first plating layer on the thermal interface material structure over the peripheral area.

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