On-orbit high-speed data transmission and processing system based on optical module interface

Abstract

An on-orbit high-speed data transmission and processing system based on an optical module interface is characterized in that an FPGA (Field Programmable Gate Array) processing control unit receives a remote control signal through an RS422 communication bus, further analyzes the remote control signal and configures a register of a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) detector, and the FPGA processing control unit can extract a system state in real time and then sends the system state to an electric control box through the RS422 communication bus; the FPGA processing control unit provides a time sequence driving signal required by the CMOS detector and controls the imaging of the CMOS detector; after the CMOS detector generates image data, the CMOS detector receives the data; the DDR3 module comprises two DDR3 chips and is used for realizing ping-pong caching of data; the FPGA processing control unit processes and encodes the image data extracted from the DDR3 module, packages the image data and prepares for data downloading; the FPGA processing control unit downloads the packaged data through an optical module interface; and on-orbit real-time refreshing of the FPGA processing control unit is realized through the refreshing module.

Description

Technical Field

[0001] The invention relates to an on-orbit high-speed data transmission and processing system based on an optical module interface, belonging to the technical field of space visible camera imaging. Background Art

[0002] At present, with the increasing demand for target detection, the detection tasks have higher and higher requirements on the camera's temporal resolution, spatial resolution, width and other performance. Therefore, in order to improve performance, remote sensing cameras are increasingly using high-frame-rate, multi-pixel CMOS detectors, and such high-frame-rate, high-data-rate detectors also require the remote sensing camera's electronics system to have high-speed, stable data real-time transmission and processing capabilities. Traditional high-speed electronics systems mostly use electrical interfaces such as 2711 and CXP, with a maximum interface speed of 6.25Gbps, which is difficult to meet the data transmission speed required by current detectors.

[0003] Therefore, how to establish new methods suitable for on-orbit high-speed data transmission and processing has become a new challenge. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an on-orbit high-speed data transmission and processing system based on an optical module interface, which can effectively overcome the problem of low data transmission speed and difficulty in transmitting large amounts of data in traditional methods.

[0005] The purpose of the present invention is achieved through the following technical solutions:

[0006] An on-orbit high-speed data transmission and processing system based on an optical module interface, comprising a CMOS detector, an FPGA processing control unit, an RS422 communication bus, a power supply module, a DDR3 module, a refresh module, and an optical module interface;

[0007] The power supply module provides power to all modules in the system;

[0008] The FPGA processing control unit receives the remote control signal through the RS422 communication bus, analyzes the remote control signal, and configures the register of the CMOS detector. The FPGA processing control unit can extract the system status in real time and send it to the electric control box through the RS422 communication bus to realize the telemetry function;

[0009] The FPGA processing control unit provides the timing driving signal required by the CMOS detector to control its imaging; and after the CMOS detector generates image data, it receives the multi-channel raw image data output by the CMOS detector;

[0010] The DDR3 module contains two DDR3 chips to implement data ping-pong caching; the FPGA processing control unit processes and encodes the image data taken out from the DDR3 module according to the image data frame format requirements, and packages the image data for data download; the FPGA processing control unit transmits the packaged data through the optical module interface to achieve data download;

[0011] The refresh module is used to realize the on-orbit real-time refresh of the FPGA processing control unit.

[0012] In one embodiment of the present invention, the CMOS detector uses a high frame rate large area array detector to meet the requirements of high temporal resolution and high spatial resolution.

[0013] In one embodiment of the present invention, the FPGA configures the registers of the CMOS detector to change its detection mode, exposure time, and gain to realize the remote control function;

[0014] In one embodiment of the present invention, the on-track high-speed data is automatically aligned in the following manner:

[0015] After the CMOS detector is adjusted to the test mode and the synchronization code is output, the FPGA processing control unit starts data detection and finds the first data conversion edge. After the first data conversion, it starts detection again and finds the second data conversion edge. Taking one channel as the benchmark, the delay beats of the remaining channels are recorded, and the data of each channel is delayed or pushed forward according to the delay beats to complete the bit alignment. At the same time, after the bit alignment is completed, the clock sampling edge is placed in the data center; then the FPGA phase of each channel data is adjusted, and the training words at different phases are read to determine whether they are consistent with the synchronization code output by the CMOS detector. When they are consistent, the FPGA phase at this time is recorded, and the data of each channel is delayed or pushed forward to complete the word alignment; finally, based on the bit alignment and word alignment, the slowest transmission channel is used as the benchmark to record the advance time of each channel. In the next frame of the image, the advanced data of each channel is delayed, and after the last channel is transmitted, the multi-channel data is read out simultaneously.

[0016] In one embodiment of the present invention, high-speed and massive data on track is compressed by the following method:

[0017] First, the event range and threshold are set, and the center and range of the area of ​​interest are screened out according to the width and threshold. The remote sensing image data is sliced, the area of ​​interest is retained, and spatial redundant information is removed. Then the weighted average of the first ten frames of image data is taken as the background estimation. The background is removed from the current frame image, and the information data of the current frame image is taken as the background estimation value. Finally, the processed image is retrieved for events according to the threshold, and the information frame is stored.

[0018] In one embodiment of the present invention, the optical module interface includes a primary optical module interface and a backup optical module interface, which can realize the switching between the primary and backup.

[0019] In one embodiment of the present invention, the signal transmission speed between the FPGA processing control unit and the optical module interface can reach 10 Gbps.

[0020] In one embodiment of the present invention, the FPGA processing control unit caches the received original image of the current frame into the DDR3 module, and simultaneously takes out the image data of the previous frame from another DDR3 for processing.

[0021] In one embodiment of the present invention, the FPGA processing control unit realizes the on-track injection of the FPGA processing control unit through the RS422 communication bus.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] (1) The present invention provides an on-orbit high-speed data transmission and processing system based on an optical module interface, which can effectively overcome the problem of low data transmission speed and difficulty in transmitting large amounts of data in traditional methods, and can effectively ensure high-reliability, high-efficiency, and error-free transmission of high-speed remote sensing image data. The data transmission speed reaches 10 Gbps and can be applied to a variety of scenarios with high time resolution, such as lightning detection, moving target detection, space attack and defense, etc.

[0024] (2) The present invention proposes a high-speed circuit crosstalk prevention design method for the optical module interface in the system, which has strong guidance for the high-speed PCB design of optical modules and other devices, making the high-speed PCB design simpler and clearer.

[0025] (3) The present invention proposes an FPGA-based on-orbit high-speed data automatic alignment method based on the core processor FPGA in the system, which can effectively support the alignment problem of data above 10G.

[0026] (4) The present invention proposes an on-orbit high-speed data compression processing method based on FPGA, a core processor in the system, which can effectively support on-orbit compression of massive remote sensing data, extract effective information, and alleviate the on-orbit data transmission pressure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the on-orbit high-speed data transmission and processing system based on the optical module interface.

[0028] Figure 2 The flowchart of the on-orbit high-speed data automatic alignment method based on FPGA processing control unit.

[0029] Figure 3This is a flow chart of the on-orbit high-speed massive data compression processing method based on FPGA processing control unit.

[0030] Figure 4 The result diagram of the back-end signal attenuation simulation for the PCB. DETAILED DESCRIPTION

[0031] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0032] In order to solve the problem that the traditional remote sensing camera electronics system transmits a large amount of data but a low transmission rate, the present invention is proposed, which is an on-orbit high-speed data transmission and processing system based on an optical module interface.

[0033] An on-orbit high-speed data transmission and processing system based on an optical module interface, such as Figure 1 , including CMOS detector, FPGA processing control unit, RS422 communication bus, power supply module, DDR3 module, refresh module, and optical module interface.

[0034] The power supply module mainly supplies power to all modules in the system. The CMOS detector is connected to the FPGA processing control unit. The RS422 communication bus is connected to the FPGA processing control unit. The DDR3 module is connected to the FPGA processing control unit. The refresh module is connected to the FPGA processing control unit and the RS422 communication bus. The optical module interface is connected to the FPGA processing control unit.

[0035] The CMOS detector uses a high frame rate large array detector to meet the requirements of high temporal resolution and high spatial resolution.

[0036] The FPGA processing control unit receives the remote control signal through the RS422 communication bus, analyzes the remote control signal, and configures the registers of the CMOS detector to change its detection mode, exposure time, gain, etc. to realize the remote control function; the FPGA processing control unit can extract the system status in real time and send it to the electric control box through the RS422 communication bus to realize the telemetry function.

[0037] The FPGA processing control unit provides the timing driving signal required by the CMOS detector to control its imaging; and after the CMOS detector generates image data, it receives the multi-channel original image data output by the CMOS detector.

[0038] The multi-channel raw image data output by the CMOS detector has the problem that the channels cannot be aligned. To solve this problem, an on-orbit high-speed data automatic alignment method based on FPGA processing control unit is proposed. Figure 2. Adjust the CMOS detector to the test mode, and after the synchronization code is output, the FPGA processing control unit starts data detection, finds the first data conversion edge, and after the first data conversion, starts detection again, finds the second data conversion edge, takes one channel as the benchmark, records the delay beats of the remaining channels, and delays or pushes forward the data of each channel according to the delay beats to complete the bit alignment. At the same time, after the bit alignment is completed, the clock sampling edge is placed in the data center. Then adjust the FPGA phase of each channel data, read the training words at different phases, and judge whether it is consistent with the synchronization code output by the CMOS detector. When they are consistent, record the FPGA phase at this time, delay or push forward the data of each channel, and complete the word alignment. Finally, based on the bit alignment and word alignment, take the slowest transmission channel as the benchmark, record the advance time of each channel, and in the next frame of the image, delay the advance data of each channel, and wait until the last channel completes the transmission, and then read out the multi-channel data at the same time.

[0039] The DDR3 module contains two DDR3 chips to implement data ping-pong caching to solve the problem of fast image data transmission and inability to achieve real-time processing. The FPGA processing control unit caches the received current frame original image into the DDR3 module and simultaneously takes out the previous frame image data from another DDR3 for processing.

[0040] The FPGA processing control unit processes and encodes the image data taken out from the DDR3 module according to the image data frame format requirements, and packages the image data in preparation for data download.

[0041] The system has the problem of large data volume and heavy transmission pressure. To solve this problem, an on-orbit high-speed massive data compression processing method based on FPGA processing control unit is proposed in the software processing flow. Figure 3 , remove spatial redundant information, estimate background, remove background, retrieve events, and store information frames for remote sensing information. First, set the event range and threshold, filter out the center and range of the area of ​​interest according to the width and threshold, and slice the remote sensing image data to retain the area of ​​interest and remove spatial redundant information. Then take the weighted average of the first ten frames of image data as background estimation. And remove the background of the current frame image, and use the current frame image data minus the background estimation value as the information data of the current frame image. Finally, perform event retrieval on the processed image according to the threshold and store the information frame.

[0042] The FPGA processing control unit transmits the packaged data through the optical module interface to achieve data download. The system is designed with primary and backup optical module interfaces to realize primary and backup switching. If the primary optical module interface fails, the backup optical module interface can switch to the primary at any time to ensure uninterrupted operation. Since the signal transmission speed between the FPGA processing control unit and the optical module interface reaches 10Gbps, a high-speed circuit design method based on simulation is adopted when designing the PCB. The designed circuit schematic is imported into the PCB development tool CADENCE for front-end simulation, and the impedance control rules and wiring parameter rules in the corresponding PCB are formulated, and the layout and wiring of components are performed according to the simulation results. The back-end signal attenuation simulation is then performed on the laid-out PCB. The simulation results are as follows: Figure 4 , verify the integrity of high-speed PCB signals based on simulation results, and then make detailed adjustments based on the simulation results.

[0043] In addition, the FPGA processing control unit realizes the on-track injection of the FPGA processing control unit through the RS422 communication bus. The on-track real-time refresh of the FPGA processing control unit is realized through the refresh module, which greatly improves the reliability of the system.

[0044] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

[0045] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. An on-orbit high-speed data transmission and processing system based on an optical module interface, characterized in that: Including CMOS detector, FPGA processing control unit, RS422 communication bus, power supply module, DDR3 module, refresh module, optical module interface; The power supply module provides power to all modules in the system; The FPGA processing control unit receives the remote control signal through the RS422 communication bus, analyzes the remote control signal, and configures the register of the CMOS detector. The FPGA processing control unit can extract the system status in real time and send it to the electric control box through the RS422 communication bus to realize the telemetry function; The FPGA processing control unit provides the timing driving signal required by the CMOS detector to control its imaging; and after the CMOS detector generates image data, it receives the multi-channel raw image data output by the CMOS detector; The DDR3 module contains two DDR3 chips to implement data ping-pong caching; the FPGA processing control unit processes and encodes the image data taken out from the DDR3 module according to the image data frame format requirements, and packages the image data for data download; the FPGA processing control unit transmits the packaged data through the optical module interface to achieve data download; The refresh module is used to realize the on-orbit real-time refresh of the FPGA processing control unit.

2. The on-orbit high-speed data transmission and processing system according to claim 1, characterized in that: The CMOS detector uses a high frame rate large array detector to meet the requirements of high temporal resolution and high spatial resolution.

3. The on-orbit high-speed data transmission and processing system according to claim 1, characterized in that: FPGA configures the registers of the CMOS detector to change its detection mode, exposure time, gain, and realize remote control function.

4. The on-orbit high-speed data transmission and processing system according to claim 1, characterized in that: In-orbit high-speed data is automatically aligned in the following ways: The CMOS detector is adjusted to the test mode. After the synchronization code is output, the FPGA processing control unit starts data detection and finds the first data conversion edge. After the first data conversion, detection starts again to find the second data conversion edge. With one channel as the benchmark, the delay beats of the remaining channels are recorded, and the data of each channel is delayed or pushed forward according to the delay beats to complete the bit alignment. After the bit alignment is completed, the clock sampling edge is placed in the center of the data; then the FPGA phase of each channel data is adjusted, and the training words at different phases are read to determine whether they are consistent with the synchronization code output by the CMOS detector. When they are consistent, the FPGA phase at this time is recorded, and the data of each channel is delayed or pushed forward to complete the word alignment; Finally, based on bit alignment and word alignment, the advance time of each channel is recorded with the slowest transmission channel as the benchmark. In the next frame of the image, the advanced data of each channel is delayed. After the last channel completes the transmission, the multi-channel data is read out simultaneously.

5. The on-orbit high-speed data transmission and processing system according to claim 1, characterized in that: The high-speed and massive data on-orbit is compressed and processed in the following ways: First, the event range and threshold are set, and the center and range of the area of ​​interest are screened out according to the width and threshold. The remote sensing image data is sliced, the area of ​​interest is retained, and spatial redundant information is removed. Then the weighted average of the first ten frames of image data is taken as the background estimation. The background is removed from the current frame image, and the information data of the current frame image is taken as the background estimation value. Finally, the processed image is retrieved for events according to the threshold, and the information frame is stored.

6. The on-orbit high-speed data transmission and processing system according to claim 1, characterized in that: The optical module interface includes a primary optical module interface and a backup optical module interface, which can realize the switching between primary and backup.

7. The on-orbit high-speed data transmission and processing system according to claim 1, characterized in that: The signal transmission speed between the FPGA processing control unit and the optical module interface can reach 10Gbps.

8. The on-orbit high-speed data transmission and processing system according to claim 1, characterized in that: The FPGA processing control unit caches the received current frame original image into the DDR3 module, and at the same time takes out the previous frame image data from another DDR3 for processing.

9. The on-orbit high-speed data transmission and processing system according to claim 1, characterized in that: The FPGA processing control unit realizes the on-orbit injection of the FPGA processing control unit through the RS422 communication bus.

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