A MEMS device with ultra-thick structure and ultra-small structure gap and a processing method thereof

Abstract

The present application belongs to the technical field of micro-electro-mechanical system, and particularly relates to a MEMS device with an ultra-thick structure and an ultra-small structure gap and a processing method. The MEMS device comprises a cover plate (333), a silicon structure layer (201) and a through silicon via sheet (111), which are combined by bonding, a second cavity (28) is formed by backside lithography and etching in the thin movable structure (24) and small structure gap (23) area of the silicon structure layer (201) to change the thickness of the movable structure, and the large structure gap (27) and the small structure gap (23) are simultaneously realized by lithography and etching on the non-patterned surface of the silicon structure layer (201), so that the lag effect is effectively eliminated. By changing the thickness of the local structure layer, the problems of difficulty in improving the etching aspect ratio in the processing of the ultra-thick structure and limitation of the structure gap on the etching aspect ratio are solved at the same time, the size of the minimum structure gap in the ultra-thick structure is further reduced, and the driving and detection capability of the capacitive MEMS device is significantly improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of micro-electro-mechanical systems, and particularly relates to a MEMS device with an ultra-thick structure and an ultra-small structure gap and a processing method. BACKGROUND

[0002] Micro Electro-Mechanical Systems (MEMS) can realize the advantages of mass production and low cost, and at the same time, the small size and low power consumption of the device are applied more and more in the fields of biology, gas, and inertial sensing.

[0003] MEMS device structure processing can generally be divided into surface micro-processing technology and bulk silicon processing technology. The bulk silicon processing technology realizes the combination of wafers or the sealing of devices through wafer bonding, and the structure layer can adopt a single crystal silicon wafer. Compared with deposited polycrystalline silicon, the single crystal silicon material has better mechanical and electrical properties, and is widely applied in high-precision inertial sensing MEMS gyroscopes, accelerometers and other devices. MEMS gyroscopes and accelerometers can effectively increase the sensing mass and improve the device performance by increasing the thickness of the movable structure. For capacitive MEMS devices, the capacitor gap is also a key parameter affecting the signal-to-noise ratio of the device. Reducing the capacitor gap can significantly increase the driving capacity of the capacitor or significantly improve the detection sensitivity of the capacitor.

[0004] Compared with the surface micro-processing technology, the bulk silicon technology can realize the processing of thicker MEMS device core structures through photolithography combined with anisotropic dry etching and isotropic wet etching. However, the ratio of structure thickness to minimum structure gap is limited due to the MEMS processing capability, especially the DRIE etching aspect ratio. Generally, the movable structure thickness of MEMS is 50um-70um, and the minimum capacitor gap is generally 2um-5um. For the processing of ultra-thick structures, on the one hand, as the etching depth increases, the etching efficiency significantly decreases, the etching time significantly prolongs, the photoresist mask loss is more, and the DRIE etching aspect ratio is more difficult to improve. On the other hand, the etching rate in the region with small structure gap is significantly lower than that in the region with large structure gap, i.e. the lag effect leads to a significant decrease in the uniformity of the MEMS device processing. In order to improve the etching uniformity, a Dummy filling structure is generally added in the structure to ensure the consistency of the etching structure gap. However, the structure gap is limited by the dry etching aspect ratio, and as the structure thickness increases, the structure gap is larger. SUMMARY

[0005] Invention purposes: to provide a MEMS device with ultra-thick structure and ultra-small structure gap and a processing method, to solve the problem of difficulty in improving etching aspect ratio during processing of ultra-thick silicon structure, and the problem of limited structure gap due to etching aspect ratio, effectively eliminate the influence of lag effect, and realize etching of large structure gap and small structure gap. The method breaks the limitation of DRIE etching aspect ratio of ultra-thick structure, and further reduces the size of the minimum structure gap in the ultra-thick structure.

[0006] Technical solutions:

[0007] A MEMS device with ultra-thick structure and ultra-small structure gap comprises a cover plate 333, a silicon structure layer 201, and a through silicon via sheet 111, which are bonded together,

[0008] The through silicon via sheet 111 comprises a first cavity 6, a first support structure 7, a through silicon via 5, an oxide layer 4, and a conductive metal 9, wherein the first cavity 6 is a square shallow cavity in the sheet, the side wall of the first cavity 6 is the first support structure 7, the through silicon via 5 comprises a dry etching hole 8 and a trapezoidal hole formed by wet etching corresponding to the position of the dry etching hole 8, the dry etching hole 8 is circular, square or polygonal, and the conductive metal 9 is located on the inner wall surface of the through silicon via 5;

[0009] The silicon structure layer 201 comprises a thin movable structure 24 of the MEMS device, a thick movable structure 26, a first anchor point 25, a filling structure anchor point 29, an electrode 22, and a first sealing ring 21, the small structure gap 23 is the gap between the thin movable structure 24 and the electrode 22; the gap between the thick movable structure 26 and the first anchor point 25, the gap between the thick movable structure 26 and the filling structure anchor point 29, and the gap between the thick movable structures 26 are all large structure gaps 27; the thin movable structure 24 in the sheet and the small structure gap 23 have a second cavity 28 in the back area, the second cavity 28 is a square shallow cavity made by dry etching or a trapezoidal shallow cavity made by wet etching, the silicon structure layer 201 and the through silicon via sheet 111 are connected by silicon-silicon bonding, the first anchor point 25 is located corresponding to the support structure 7 of the through silicon via sheet 111, the first sealing ring 21 is located on the periphery of the sheet and also corresponds to the support structure 7 of the through silicon via sheet 111, the electrode 22 of the silicon structure layer corresponds to the dry etching hole 8 of the through silicon via 5 on the through silicon via sheet 111, and the signal is directly led out through the conductive metal 9 of the through silicon via 5 on the through silicon via sheet 111;

[0010] The SOI sheet used for the cover plate 333 comprises a top silicon layer 31 bonded with the silicon structure layer 201, an intermediate buffer layer 32, and a support layer 33, the top silicon layer 31 structure of the cover plate 333 comprises a second sealing ring 36 corresponding to the position of the first sealing ring 21 of the silicon structure layer 201, and a second anchor point 37 corresponding to the anchor point of the silicon structure layer 201, and the cover plate 333 and the silicon structure layer 201 are sealed by intermediate metal layer 35 bonding.

[0011] Further, the SOI top layer silicon 31 structure of the cover plate 333 further comprises: a silicon conducting band 38 connecting the second anchor point 37 and the electrode 22, the silicon conducting band 38 is formed by twice etching on the SOI top layer silicon 31, the silicon conducting band 38 is used to reduce the number and arrangement of the through silicon vias 5, the top layer silicon 31 is low resistance silicon with a resistivity of 0.001 Ω·cm to 0.1 Ω·cm.

[0012] Further, the cover plate 333 is a silicon wafer 666, the structure of the cover plate 333 comprises a third anchor point 63, an oxide layer 61 and a third sealing ring 62, the silicon wafer 666 is etched to form the third anchor point 63 and the third sealing ring 62, then the oxide layer 61 is formed on the surface by thermal oxidation, and finally the intermediate metal layer 35 for bonding is made to bond and seal with the silicon structure layer 201.

[0013] Further, the through silicon via wafer 111 comprises: a first cavity 6, a through silicon via 5, an oxide layer 4 and a conductive metal 9, the through silicon via 5 comprises a dry etching hole 8 and a trapezoidal hole formed by wet etching corresponding to the dry etching hole 8, the silicon structure layer 444 comprises a fourth sealing ring 41, a fourth anchor point 46, a fourth filling structure anchor point 50, a fourth cavity 47, a fifth cavity 45, a fourth thin movable structure 44 and a fourth thick movable structure 48, wherein,

[0014] The fourth cavity 47 is a shallow cavity etched around the fourth anchor point 46 in the wafer, which is a square shallow cavity formed by dry etching or a trapezoidal shallow cavity formed by wet etching, and the fifth cavity 45 is located in the corresponding area on the back surface between the fourth thin movable structure 44 and the fourth small structure gap 43, wherein the depth of the fourth cavity 47 is less than the depth of the fifth cavity 45.

[0015] The fourth small structure gap 43 is the gap between the fourth electrode 42 and the fourth thin movable structure 44, and the fourth large structure gap 43 is the gap between the fourth thick movable structure 44, between the fourth thick movable structure 44 and the fourth filling structure anchor point 50, and between the fourth thick movable structure 44 and the fourth anchor point 46.

[0016] Further, the SOI top layer silicon used for the silicon structure layer 444 is etched to form the fourth cavity 47, the fourth anchor point 46 and the fifth cavity 45 by twice photolithography and etching, then the silicon structure layer 444 is bonded with the through silicon via wafer 111 by silicon-silicon bonding, then the fourth small structure gap 43 and the fourth large structure gap 49 are made by photolithography and etching on the pattern-free surface of the top layer silicon 401, the fourth sealing ring 41, the fourth anchor point 46, the fourth thin movable structure 44, the fourth filling structure anchor point 50 and the fourth thick movable structure 48 are formed, and finally the cover plate 333 is bonded and sealed.

[0017] A method of the above-mentioned MEMS device, comprising the following steps:

[0018] a Fabricate the through silicon via sheet 111, fabricate the support structure 7 and dry etching hole 8 by dry etching, fabricate the through silicon via 5 by wet etching, and then oxidize the through silicon via sheet 111;

[0019] b Fabricate the silicon structure layer 201, deposit the silicon oxide 13 on the SOI sheet with a certain thickness of the top layer silicon 201, spin the photoresist 14 on the back surface area of the thin movable structure 24 and the small structure gap 23, photoetch and RIE etch the silicon oxide, fabricate the second cavity 28 by dry etching or wet etching, remove the surface silicon oxide of the top layer silicon 201, clean, and perform silicon-silicon bonding between the top layer silicon 201 of the SOI sheet and the through silicon via sheet 111, and remove the support layer 203 and the buffer layer 202 of the SOI sheet; fabricate the small structure gap 23 and the large structure gap 27 on the top layer silicon 201 bonded with the through silicon via sheet 111 by photoetching, form the thin movable structure 24, the thick movable structure 26, the bonding anchor point 29, the filling structure anchor point 29 and the electrode 22;

[0020] c Fabricate the second sealing ring 36 and the second anchor point 37 structure on the top layer silicon 31 of the cover plate 333 SOI, deposit the bonding intermediate metal layer 35, photoetch and etch the intermediate metal layer 35, and realize the connection and sealing between the cover plate 333 and the silicon structure layer 201 by using the intermediate metal layer bonding mode of gold-silicon bonding or gold-gold bonding, and realize the electrode lead-out by plating the conductive metal 9 in the through silicon via 5 of the through silicon via sheet 111 through a hard mask.

[0021] Further, the silicon structure layer 201 is selected as the double-polished silicon sheet 666, the operation is performed by temporarily bonding the double-polished silicon sheet 666 with the support sheet, the second cavity 28 is fabricated by photoetching and etching, the silicon structure layer 201 is bonded with the through silicon via sheet 111 after the silicon-silicon bonding, and the temporary support sheet and the temporary bonding glue are removed.

[0022] Further, the silicon structure layer 201 is the double-polished silicon sheet, the through silicon via sheet 111 is bonded after the fabrication of the second cavity 28 on the first surface of the silicon sheet, and the second surface is fabricated again by using the silicon sheet with a proper thickness obtained by thinning the silicon sheet after the bonding.

[0023] Advantageous effects:

[0024] The full-silicon MEMS structure device has good temperature characteristics, directly leads out the electrode by using the through silicon via, realizes the interconnection between the electrodes in the cavity, the rearrangement and sealing of the through silicon via electrode by using the SOI cover plate, is convenient for the electrical signal lead-out, and has high design flexibility. The thickness of the high aspect ratio region is reduced by the back alignment etching in the small structure gap region of the structure layer, the influence of the lag effect is effectively eliminated, and the etching of the large structure gap and the small structure gap is realized. The method breaks the limitation of the aspect ratio of the super-thick structure DRIE etching, further reduces the size of the minimum structure gap in the super-thick structure, and significantly improves the driving and detection capability of the capacitive MEMS device. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A MEMS device with ultra-thick structure and ultra-small gap between structures is shown in one embodiment of the present application;

[0026] Figures 2(a) to 2(i) A method for processing a MEMS device with ultra-thick structure and ultra-small gap between structures is shown in one embodiment of the present application, wherein,

[0027] Figure 2(a) shows the first cavity 6, support structure 7 and dry etching hole 8 made by dry etching;

[0028] Figure 2(b) shows the through silicon via 5 made by wet etching;

[0029] Figure 2(c) shows the silicon via wafer 111 oxidized;

[0030] Figure 2(d) shows the second cavity 10 made on the silicon structure layer 201 of the SOI wafer 222;

[0031] Figure 2(e) shows the SOI wafer 222 with silicon structure layer 201 and the silicon-silicon bonding of the silicon via 111;

[0032] Figure 2(f) shows the deposition of Si3N4 thin film 12, and the removal of the support layer 203 and the intermediate buffer layer 202 of the SOI wafer 222 with silicon structure layer 201;

[0033] Figure 2(g) shows the back-alignment lithography etching of the silicon structure layer 201 to make the device structure;

[0034] Figure 2(h) shows the lithography etching to make the cover plate 333 structure including the second sealing ring 36 and the second anchor point 37 structure, and the bonding of the intermediate metal layer 35;

[0035] Figure 2(i) shows the bonding of the cover plate 333 with the silicon structure layer 201, and the plating of the conductive metal of the through silicon via 5 to make the electrode;

[0036] Figure 3 A MEMS device with ultra-thick structure and ultra-small gap between structures is shown in another embodiment of the present application, wherein the cover plate SOI top layer silicon is made of a silicon conduction band;

[0037] Figure 4 A MEMS device with ultra-thick structure and ultra-small gap between structures is shown in yet another embodiment of the present application, wherein the silicon structure layer is self-supported by the anchor point of the MEMS device structure;

[0038] Figure 5 A MEMS device with ultra-thick structure and ultra-small gap between structures is shown in still another embodiment of the present application, wherein the cover plate is a silicon wafer with support anchor points and sealing rings and surface oxidation. DETAILED DESCRIPTION

[0039] A kind of MEMS device of ultra-thick structure and ultra-small structure gap for processing, by bonding from three by cover plate 333, silicon structure layer 201 and silicon through hole sheet 111.

[0040] The silicon through hole sheet 111 includes: first cavity 6, first support structure 7, silicon through hole 5, oxide layer 4 and conductive metal 9, wherein the first cavity 6 is a square shallow cavity located in the sheet, the first cavity 6 side wall is the first support structure 7, the silicon through hole 5 includes dry etching hole 8 and trapezoidal hole formed by wet etching corresponding to the position of the dry etching hole 8, the dry etching hole 8 is circular, square or polygonal, and the conductive metal 9 is located on the inner wall surface of the silicon through hole 5.

[0041] The silicon structure layer 201 includes thin movable structure 24, thick movable structure 26, first anchor point 25, filling structure anchor point 29, electrode 22 and first sealing ring 21 of MEMS device. The silicon structure layer 201 structure includes large structure gap 27 and small structure gap 23. The small structure gap 23 is the gap between the thin movable structure 24 and the electrode 22, and the large structure gap 27 includes the gap between the thick movable structure 26 and the first anchor point 25, the gap between the thick movable structure 26 and the filling structure anchor point 29 and the gap between the thick movable structures 26. The back area of the thin movable structure 24 and the small structure gap 23 in the sheet has a second cavity 28. The second cavity 28 can be a square shallow cavity made by dry etching or a trapezoidal shallow cavity made by wet etching. The silicon structure layer 201 and the silicon through hole sheet 111 are connected by silicon-silicon bonding mode, the first anchor point 25 is located in the sheet and corresponds to the support structure 7 of the silicon through hole sheet, and the first sealing ring 21 is located on the periphery of the sheet and also corresponds to the support structure 7 of the silicon through hole sheet. The electrode 22 of the silicon structure layer corresponds to the dry etching hole 8 of the silicon through hole 5 on the silicon through hole sheet 111, and the signal is directly led out through the conductive metal 9 of the silicon through hole 5 on the silicon through hole sheet 111.

[0042] The cover plate 333 uses SOI sheet, which includes top layer silicon 31 bonded with the silicon structure layer 201, intermediate buffer layer 32 and support layer 33. The top layer silicon 31 structure of the cover plate 333 includes second sealing ring 36 corresponding to the position of the first sealing ring 21 of the silicon structure layer 201, and second anchor point 37 corresponding to the anchor point of the silicon structure layer 201, which is sealed by intermediate metal layer 35 such as gold-silicon or gold-gold bonding mode

[0043] In an embodiment of the present application, the SOI top layer silicon 31 structure of the cover plate 333 can optionally include silicon conduction band 38, second anchor point 37 and second sealing ring 36. The redistribution of the silicon through hole 5 is realized by twice etching to make the silicon conduction band 38 on the SOI top layer silicon 31. The top layer silicon 31 is low resistance silicon, and the general resistivity is 0.001Ω·cm-0.1Ω·cm.

[0044] In one embodiment of the present application, the cover plate 333 can be a silicon wafer 666, the structure includes a third anchor point 63, an oxide layer 61 and a third sealing ring 62. The silicon wafer 666 is etched to form the third anchor point 63 and the third sealing ring 62, then the surface is heated to form the oxide layer 61, and finally the intermediate metal layer 35 is bonded to the silicon structure layer 201.

[0045] The back etching of the capacitor reduces the thickness of the capacitor, the area of the capacitor is reduced, but the reduced gap of the capacitor can bring greater driving force or capacitor detection ability.

[0046] In one embodiment of the present application, the through-silicon wafer 111 includes a first cavity 6, a dry etching hole 8, a through-silicon hole 5, an oxide layer 4, and a conductive metal 9, but no support structure 7. The silicon structure layer 444 includes a fourth small structure gap 43, a fourth large structure gap 49, a fourth sealing ring 41, a fourth anchor point 46, a fourth filling structure anchor point 50, a fourth cavity 47, a fifth cavity 45, a fourth thin movable structure 44, and a fourth thick movable structure 48.

[0047] The fourth cavity 47 is a shallow cavity etched around the fourth anchor point 46 on the wafer, which can be a square-shaped shallow cavity etched by dry etching or a trapezoidal-shaped shallow cavity etched by wet etching. The fifth cavity 45 is located in the corresponding area on the back of the fourth thin movable structure 44 and the fourth small structure gap 43, and the depth of the fourth cavity 47 is less than the depth of the fifth cavity 45.

[0048] The fourth small structure gap 43 is the gap between the fourth electrode 42 and the fourth thin movable structure 44. The fourth large structure gap 43 is the gap between the fourth thick movable structure 44, between the fourth thick movable structure 44 and the fourth filling structure anchor point 50, and between the fourth thick movable structure 44 and the fourth anchor point 46.

[0049] The SOI top layer silicon used in the silicon structure layer 444 is etched by twice photolithography and etching to form the fourth cavity 47, the fourth anchor point 46 and the fifth cavity 45. Then the silicon structure layer 444 is bonded to the through-silicon wafer 111 by silicon-silicon bonding. Then the top layer silicon 401 is patterned and etched by photolithography to form the fourth small structure gap 43 and the fourth large structure gap 49, and to form the fourth sealing ring 41, the fourth anchor point 46, the fourth thin movable structure 44, the fourth filling structure anchor point 50 and the fourth thick movable structure 48. Finally, the bonding and sealing are performed with the cover plate 333.

[0050] A method for manufacturing the above-mentioned MEMS device structure, the method comprising the following steps:

[0051] a: manufacturing the through-silicon wafer 111. The support structure 7 and the dry etching hole 8 are manufactured by dry etching, the through-silicon hole 5 is manufactured by wet etching, and the through-silicon wafer 111 is oxidized.

[0052] b: Fabricating the silicon structure layer 201. Deposition of silicon oxide 13 on the SOI wafer of a certain thickness of top layer silicon 201, spin coating photoresist 14 on the back surface area of thin movable structure 24 and small structure gap 23, photoetching, RIE etching of silicon oxide, dry etching or wet etching of silicon to fabricate the second cavity 28, removing the surface silicon oxide of the top layer silicon 201, cleaning, silicon-silicon bonding of the top layer silicon 201 of the SOI wafer with the through-silicon wafer 111, removing the support layer 203 and the buffer layer 202 of the SOI wafer. Photoetching and etching of the top layer silicon 201 bonded with the through-silicon wafer 111 to fabricate the small structure gap 23 and the large structure gap 27, forming the thin movable structure 24, the thick movable structure 26, the bonding anchor point 29, the filling structure anchor point 29 and the electrode 22;

[0053] c: Fabricating the second sealing ring 36, the second anchor point 37 and other structures on the top layer silicon 31 of the cover plate 333 SOI, depositing the bonding intermediate metal layer 35, photoetching and etching the intermediate metal layer 35, using gold-silicon bonding, gold-gold bonding and other intermediate metal layer bonding methods to realize the connection and sealing of the cover plate 333 and the silicon structure layer 201, plating conductive metal 9 in the through-silicon hole 5 of the through-silicon wafer 111 through a hard mask to realize the electrode lead-out.

[0054] The silicon structure layer 201 can be selected as a double-polished silicon wafer 666, which is operated by temporary bonding with a support wafer. After photoetching and etching to fabricate the second cavity 28, the silicon structure layer 201 is bonded with the through-silicon wafer 111 by silicon-silicon bonding, and then the temporary support wafer and the temporary bonding glue are removed.

[0055] The silicon structure layer 201 can also be selected as a double-polished silicon wafer, which is bonded with the through-silicon wafer 111 after the fabrication of the second cavity 28 on the first surface of the silicon wafer. After bonding, the silicon wafer can be thinned to a certain thickness. In this case, the surface of the silicon wafer needs to be polished to achieve a surface roughness that can be used for subsequent bonding.

[0056] The structure and method of the present application are suitable for super-thick structures with a thickness ranging from 150 microns to 500 microns, and super-small structures with a gap ranging from 3 microns to 15 microns.

[0057] The manufacturing method of the MEMS device structure is described in detail below with reference to FIG. 2, and in combination with Figure 1 , for example.

[0058] Embodiment 1:

[0059] Fabrication of the through-silicon wafer 111, as shown in FIGS. 2(a)-(c).

[0060] First, a layer of oxide 11 is oxidized on a double-side polished silicon wafer. According to the design of the MEMS device, a first cavity 6, a support structure 7 and a dry etching hole 8 are formed on one side of the silicon wafer by dry etching (see Fig. 2(a)). Then, a silicon through hole 5 is formed on the other side of the silicon wafer by wet etching at the position corresponding to the electrode hole 8, thereby forming the silicon through hole 5 (see Fig. 2(b)). The formation of the silicon through hole 5 from the other side has the advantages of simple process and convenience. Finally, after removing the oxide layer, the entire silicon wafer is re-oxidized to form a new oxide layer 4, thereby obtaining a silicon through hole wafer 111 (see Fig. 2(c)).

[0061] The silicon structure layer 201 is formed as shown in Figs. 2(d) to (g).

[0062] First, a specific thickness of top layer silicon of the SOI wafer is PECVD (plasma enhanced chemical vapor deposition) deposited with silicon oxide 13, and then photoresist 14 is spin-coated on the silicon oxide 13 for photoetching. The surface silicon oxide 13 is RIE (reactive ion etching) etched, and a certain thickness of silicon is dry etched on the back of the thin movable structure 24 and the small structure gap 23 to form a second cavity 28 (see Fig. 2(d)). The surface photoresist 14 is cleaned and removed. The silicon through hole wafer 111 and the SOI wafer 222 are bonded by silicon-silicon bonding (see Fig. 2(e)), the SOI support layer is dry etched, and Si3N4 thin film 12 is deposited by LPCVD (low pressure chemical vapor deposition). The surface Si3N4 thin film 12 of the buffer layer 202 is RIE etched, and the SOI wafer buffer layer 202 is wet etched (see Fig. 2(f)). A layer of silicon oxide 13 is PECVD deposited, photoresist 14 is spin-coated for back alignment photoetching, and the small structure gap 23 and the large structure gap 27 are dry etched to form the thin movable structure 24, the thick movable structure 26, the first anchor point 25, the filling structure anchor point 29, the first sealing ring 21 and the electrode 22 (see Fig. 2(g)).

[0063] The silicon structure layer 201 can also be selected as a double-polished silicon wafer, which is bonded with the silicon through hole wafer 111 after the second cavity 28 is formed on the first side. After the bonding, the appropriate thickness of the silicon structure layer 201 can be obtained by thinning the double-polished silicon wafer. In this case, the surface of the silicon wafer needs to be polished to achieve the surface roughness that can be bonded subsequently.

[0064] The cover plate 333 is formed as shown in Fig. 2(h).

[0065] First, a layer of silicon oxide 13 is grown on the surface of the SOI wafer, and the second sealing ring 36 and the second anchor point 37 structure are formed by dry etching the top layer silicon 31 of the SOI wafer to the buffer layer 32 of the SOI wafer. The surface silicon oxide 13 is wet etched to form the SOI cover plate 333. Of course, the electrode bonding anchor point and the sealing ring can also be formed on the top layer silicon 31 of the SOI wafer by wet etching. The bonding metal is deposited, and the bonding intermediate metal layer 35 is formed by photoetching and wet etching.

[0066] Bonding and in-hole metallization, as shown in Figure 2(i);

[0067] The cover plate 333 is bonded to the silicon structure layer 201, and the first sealing ring 21 of the silicon structure layer 201 is bonded to the second sealing ring 36 of the cover plate 333. Then, the Si3N4 thin film 12 inside the through-silicon via 5 is etched using a hard mask. Finally, a conductive metal 9, preferably aluminum, is deposited inside the through-silicon via 5 using a hard mask and then annealed, thereby bringing out the electrodes of the silicon structure layer 201 through the through-silicon via 5.

[0068] As described above, the fabrication of the aforementioned MEMS device structure is now complete.

[0069] Example 2:

[0070] The difference between Example 2 and Example 1 above is that: Figure 3 As shown, the cover plate 333SOI top silicon 31 structure includes silicon conductive strips 38, a second anchor point 37, and a second sealing ring 36. The silicon vias 5 are rearranged by etching the silicon conductive strips 38 twice on the SOI top silicon 31. The top silicon 31 is low-resistivity silicon, typically with a resistivity of 0.001 Ω·cm to 0.1 Ω·cm.

[0071] Example 3:

[0072] The difference between Example 3 and Example 1 above is that: Figure 4 As shown, the through-silicon via (TSV) plate 111 includes a first cavity 6, a dry-etched via 8, a TSV 5, an oxide layer 4, and a conductive metal 9, but no supporting structure 7. The silicon structure layer 444 includes a fourth small structure gap 43, a fourth large structure gap 49, a fourth sealing ring 41, a fourth anchor point 46, a fourth filling structure anchor point 50, a fourth cavity 47, a fifth cavity 45, a fourth thin movable structure 44, and a fourth thick movable structure 48.

[0073] The fourth cavity 47 is a shallow cavity etched around the fourth anchor point 46 within the wafer. It can be a square shallow cavity etched by dry etching or a trapezoidal shallow cavity etched by wet etching. The fifth cavity 45 is located in the area corresponding to the back side of the gap 43 between the fourth thin movable structure 44 and the fourth small structure, wherein the depth of the fourth cavity 47 is less than the depth of the fifth cavity 45.

[0074] The fourth small structural gap 43 is the gap between the fourth electrode 42 and the fourth thin movable structure 44. The fourth large structural gap 43 is the gap between the fourth thick movable structures 44, between the fourth thick movable structure 44 and the fourth filling structure anchor point 50, and between the fourth thick movable structure 44 and the fourth anchor point 46.

[0075] The SOI top layer silicon used in the silicon structure layer 444 is etched to form the fourth cavity 47, the fourth anchor point 46 and the fifth cavity 45 through twice photolithography and etching. Then the silicon structure layer 444 is bonded with the silicon through hole sheet 111 through silicon-silicon bonding. Then the top layer silicon 401 is etched through photolithography and etching to form the fourth small structure gap 43 and the fourth large structure gap 49, and to form the fourth sealing ring 41, the fourth anchor point 46, the fourth thin movable structure 44, the fourth filling structure anchor point 50 and the fourth thick movable structure 48. Finally, the cover plate 333 is bonded and sealed.

[0076] Example 4:

[0077] Example 4 is different from Example 1 described above in that, as shown in Figure 5 the cover plate 333 can be selected as a silicon sheet 666, and the structure includes the third anchor point 63, the oxide layer 61 and the third sealing ring 62. The silicon sheet 666 is etched to form the third anchor point 63 and the third sealing ring 62, and then the thermal oxidation is performed on the surface to form the oxide layer 61. Finally, the intermediate metal layer 35 for bonding is bonded and sealed with the silicon structure layer 201.

[0078] The full-silicon MEMS structure device has good temperature characteristics, adopts the silicon through hole to directly lead out the electrode, adopts the SOI cover plate to simultaneously realize the interconnection between the electrodes in the cavity, the rearrangement of the silicon through hole electrode and the sealing, the electrical signal leading out is convenient, and the design flexibility is high. The lag effect is effectively eliminated by etching the small structure gap region in the structure layer in a back-to-back manner to reduce the thickness of the high aspect ratio region, and the etching of the large structure gap and the small structure gap is simultaneously realized. The full-silicon MEMS structure device has good temperature characteristics, the difficulty in improving the etching aspect ratio in the processing process of the super-thick structure is solved by changing the thickness of the local structure layer, the problem that the structure gap is limited by the etching aspect ratio is solved, the size of the minimum structure gap in the super-thick structure is further reduced, and the driving and detection capability of the capacitive MEMS device is significantly improved.

[0079] The above-described embodiments only express several implementation manners of the present application, the description is relatively specific and detailed, but it cannot be understood as the limitation on the patent scope of the present application. It should be noted that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims. The part not described in detail in the present application belongs to the common knowledge of the skilled person in the art.

Claims

1. A MEMS device of ultra-thick structures and ultra-small inter-structure gaps, characterized in that, The thickness of the super-thick structure ranges from 150 microns to 500 microns; The gap of the super-small structure ranges from 3 microns to 15 microns, and includes: a cover plate, a silicon structure layer, and a through-silicon via sheet, which are bonded together, and the through-silicon via sheet includes: a first cavity, a first support structure, a through-silicon via, an oxide layer, and a conductive metal, wherein the first cavity is a square shallow cavity in the sheet, the side wall of the first cavity is the first support structure, the through-silicon via includes a dry etching hole and a trapezoidal hole formed by wet etching corresponding to the position of the dry etching hole, the dry etching hole is circular, square or polygonal, and the conductive metal is located on the inner wall of the through-silicon via; the silicon structure layer includes: a thin movable structure of a MEMS device, a thick movable structure, a first anchor point, a filling structure anchor point, an electrode, and a first sealing ring, the gap between the thin movable structure and the electrode is the small structure gap; the gap between the thick movable structure and the first anchor point, the gap between the thick movable structure and the filling structure anchor point, and the gap between the thick movable structures are large structure gaps; the thin movable structure in the sheet and the back area of the small structure gap have a second cavity, which is a square shallow cavity etched by dry etching or a trapezoidal shallow cavity etched by wet etching, and the silicon structure layer and the through-silicon via sheet are connected by a silicon-silicon bonding method, The first anchor point is located in the sheet and corresponds to the support structure of the through-silicon via sheet, the first sealing ring is located on the periphery of the sheet and also corresponds to the support structure of the through-silicon via sheet, the electrode of the silicon structure layer corresponds to the dry etching hole of the through-silicon via on the through-silicon via sheet, and the signal is directly led out through the conductive metal of the through-silicon via on the through-silicon via sheet; the SOI sheet used for the cover plate includes a top silicon layer bonded with the silicon structure layer, an intermediate buffer layer, and a support layer, the top silicon structure of the cover plate includes a second sealing ring corresponding to the position of the first sealing ring of the silicon structure layer, a second anchor point corresponding to the first anchor point of the silicon structure layer, and the cover plate and the silicon structure layer are sealed by a bonding method through an intermediate metal layer.

2. The MEMS device of claim 1, wherein, The SOI top silicon structure of the cover plate further includes: a silicon conduction band, which connects the second anchor point and the electrode, the silicon conduction band is formed by etching twice on the SOI top silicon, and the silicon conduction band is used to reduce the number and arrangement of through-silicon vias, the top silicon is low-resistance silicon with a resistivity of 0.001 Ω·cm to 0.1 Ω·cm.

3. The MEMS device of claim 1, wherein, The cover plate is a silicon sheet, and the cover plate structure includes a third anchor point, an oxide layer, and a third sealing ring, the silicon sheet is etched to form the third anchor point and the third sealing ring, then the surface is thermally oxidized to form the oxide layer, and finally the intermediate metal layer for bonding is bonded with the silicon structure layer to seal.

4. The MEMS device of claim 2, wherein, The through-silicon via sheet includes: a first cavity, a through-silicon via, an oxide layer, and a conductive metal, the through-silicon via includes a dry etching hole and a trapezoidal hole formed by wet etching corresponding to the position of the dry etching hole, the silicon structure layer includes a fourth sealing ring, a fourth anchor point, a fourth filling structure anchor point, a fourth cavity, a fifth cavity, a fourth thin movable structure, and a fourth thick movable structure, wherein the fourth cavity is a shallow cavity etched around the fourth anchor point in the sheet, which is a square shallow cavity etched by dry etching or a trapezoidal shallow cavity etched by wet etching, and the fifth cavity is located in the corresponding area of the back of the fourth thin movable structure and the fourth small structure gap, wherein the depth of the fourth cavity is less than the depth of the fifth cavity; The fourth small structure gap is a gap between the fourth electrode and the fourth thin movable structure, and the fourth large structure gap is a gap between the fourth thick movable structures, between the fourth thick movable structure and the fourth filling structure anchor point, and between the fourth thick movable structure and the fourth anchor point.

5. The MEMS device of claim 4, wherein, The SOI top layer silicon used in the silicon structure layer is etched into the fourth cavity, the fourth anchor point and the fifth cavity through two times of photolithography and etching; Then the silicon structure layer is bonded with the through silicon via wafer through silicon-silicon bonding; Then the top layer silicon is patterned and etched through photolithography to form the fourth small structure gap and the fourth large structure gap, and the fourth sealing ring, the fourth anchor point, the fourth thin movable structure, the fourth filling structure anchor point and the fourth thick movable structure are formed, and finally the cover plate is bonded and sealed.

6. A method of manufacturing the MEMS device of claim 1, wherein, The method comprises the following steps: (a) manufacturing a through silicon via wafer, supporting structures and dry etching holes are manufactured through dry etching, and a through silicon via is manufactured through wet etching, and then the through silicon via wafer is oxidized; (b) manufacturing a silicon structure layer, depositing silicon oxide on a SOI wafer with a certain thickness of top layer silicon, spin coating photoresist on the back surface area of the thin movable structure and the small structure gap, etching the silicon oxide through photolithography and RIE etching, dry etching or wet etching the silicon to form the second cavity, removing the surface silicon oxide of the top layer silicon, cleaning, and then bonding the top layer silicon of the SOI wafer with the through silicon via wafer through silicon-silicon bonding, and removing the support layer and buffer layer of the SOI wafer; the small structure gap and the large structure gap are manufactured on the top layer silicon of the through silicon via wafer bonded with the SOI wafer through photolithography and etching, and the thin movable structure, the thick movable structure, the first anchor point, the filling structure anchor point and the electrode are formed; (c) manufacturing a second sealing ring and a second anchor point structure on the top layer silicon of the cover plate SOI, depositing an intermediate metal layer, and then etching the intermediate metal layer through photolithography and etching, and then connecting and sealing the cover plate and the silicon structure layer through gold-silicon bonding or gold-gold bonding of the intermediate metal layer, and then plating a conductive metal in the through silicon via of the through silicon via wafer through a hard mask to realize the electrode lead-out.

7. The method of claim 6, wherein, The silicon structure layer is a double-polished silicon wafer, and the temporary support wafer and the temporary bonding glue are removed after the silicon structure layer is bonded with the through silicon via wafer through silicon-silicon bonding after the second cavity is manufactured on the first surface of the double-polished silicon wafer.

8. The method of claim 6, wherein, The silicon structure layer is a double-polished silicon wafer, and the temporary support wafer and the temporary bonding glue are removed after the silicon structure layer is bonded with the through silicon via wafer through silicon-silicon bonding after the second cavity is manufactured on the first surface of the double-polished silicon wafer.

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