A device and method for characterizing the dynamic threshold voltage of a power field-effect transistor.

Abstract

This invention belongs to the field of electronic circuit technology and provides a characterization device and method for the dynamic threshold voltage of a power MOSFET. The characterization device includes: a voltage stress application circuit, a device under test (DUT) module, a control signal output circuit, a conduction current application circuit, and a data acquisition module. The voltage stress application circuit is connected to the DUT module; the DUT module is connected to the conduction current application circuit; the control signal output circuit is connected to both the voltage stress application circuit and the conduction current application circuit; and the data acquisition module is connected to the conduction current application circuit. Before applying drain current to the DUT, this invention applies a conduction current to the DUT through the conduction current application circuit, subjecting the DUT to current stress, which more closely approximates the operating conditions of the DUT in an actual circuit, thereby improving the accuracy of the dynamic threshold voltage measurement of the DUT.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a device and method for characterizing the dynamic threshold voltage of a power field-effect transistor. Background Technology

[0002] Power semiconductor electronic devices are the core components of power electronics technology. Their main function is to realize the conversion of electrical energy and control of circuits in power equipment by switching on and off states. They are widely used in energy systems, computer systems, aerospace and other fields. Wide bandgap power semiconductor devices have the characteristics of high voltage rating, low on-resistance, and fast switching speed, which can improve the power density and efficiency of power supply systems.

[0003] However, GaN and SiC field-effect transistors exhibit poor dynamic stability, specifically, their threshold voltage varies during operation. This instability leads to system instability and, in severe cases, system malfunction. Therefore, to quantitatively evaluate the dynamic characteristics of wide-bandgap power semiconductor devices, it is necessary to characterize and measure their dynamic threshold voltage.

[0004] However, traditional measurement methods are static measurements, which obtain the electrical characteristics of a device by measuring its static characteristic curve using a power device analyzer. Since there is a significant time delay between when the device is subjected to external stress and when the electrical parameters are measured, and wide-bandgap power devices are usually in dynamic operating conditions with high-speed switching, conventional static measurement methods cannot reflect the actual performance of the device in a timely and accurate manner. Therefore, dynamic measurement methods are needed to be more accurate and appropriate.

[0005] In addition, the existing dynamic threshold voltage test method has the following drawback: it is generally impossible to provide a conduction current before applying voltage to the device under test, so it is impossible to apply current stress.

[0006] Therefore, it is necessary to provide a device and method for characterizing the dynamic threshold voltage of a power field-effect transistor. Summary of the Invention

[0007] This invention provides a device and method for characterizing the dynamic threshold voltage of a power field-effect transistor. Before applying drain current to the device under test (DUT), a conduction current is applied to the DUT through a conduction current application circuit, so that the DUT is subjected to current stress, which is closer to the operating conditions of the DUT in the actual circuit, thereby improving the accuracy of the dynamic threshold voltage measurement of the DUT.

[0008] This invention provides a device for characterizing the dynamic threshold voltage of a power field-effect transistor, comprising:

[0009] The system comprises a voltage stress application circuit, a device under test (DUT) module, a control signal output circuit, a current application circuit, and a data acquisition module. The voltage stress application circuit is connected to the DUT module. The DUT module is connected to the current application circuit. The control signal output circuit is connected to both the voltage stress application circuit and the current application circuit. The data acquisition module is connected to the current application circuit.

[0010] The control signal output circuit is a field-programmable gate array (FPGA) circuit used to generate drive signals; the drive signals are used to drive the power MOSFETs in the control voltage stress application circuit and the conduction current application circuit.

[0011] The voltage stress application circuit is used to apply drain voltage stress to the device under test (DUT) in the DUT module; the on-current application circuit is used to provide on-current before the DUT receives drain voltage stress, so as to ensure that the DUT has on-current before the test begins.

[0012] The data acquisition module is used to acquire the dynamic threshold voltage of the device under test.

[0013] Furthermore, the control signal output circuit includes output pin 1, output pin 2, and output pin 3.

[0014] Furthermore, the voltage stress application circuit includes a power supply Vin, a power MOSFET S1, a power MOSFET S2, an inductor L1, and a resistor R. L The circuit consists of a diode D1, a capacitor C1, and a resistor R3; one end of capacitor C1 is connected to the positive terminal of the power supply Vin, and the other end of capacitor C1 is connected to the negative terminal of the power supply Vin; one end of inductor L1 is connected to one end of capacitor C1, and the other end of inductor L1 is connected to resistor R3. L One end; resistor R L The other end is connected to the drain of power MOSFET S1; the cathode of diode D1 is connected to one end of capacitor C1, and the anode of diode D1 is connected to the drain of power MOSFET S1; the source of power MOSFET S1 is connected to one end of resistor R3, and the gate of power MOSFET S1 is connected to output pin 1; the drain of power MOSFET S2 is connected to the other end of resistor R3, the source of power MOSFET S2 is connected to the negative terminal of power supply Vin, and the gate of power MOSFET S2 is connected to output pin 2; the negative terminal of power supply Vin is grounded.

[0015] Furthermore, the device under test (DUT) module also includes a low-voltage DC power supply, denoted as Vcc; the drain of the DUT is connected to the source of the power MOSFET S1; the gate of the DUT is connected to the positive terminal of the low-voltage DC power supply; the negative terminal of the low-voltage DC power supply is connected to the negative terminal of the power supply Vin; the voltage value of the low-voltage DC power supply is configured to be significantly greater than the threshold voltage of the DUT and lower than the maximum allowable voltage of the gate of the DUT.

[0016] Furthermore, the current application circuit includes a sampling capacitor Cm, a resistor R2, and a power MOSFET S3; one end of the sampling capacitor Cm is connected to the source of the device under test, and the other end of the sampling capacitor Cm is connected to the negative terminal of the power supply Vin; one end of the resistor R2 is connected to the source of the device under test, and the other end of the resistor R2 is connected to the drain of the power MOSFET S3; the source of the power MOSFET S3 is connected to the negative terminal of the power supply Vin, and the gate of the power MOSFET S3 is connected to the output pin 3.

[0017] Furthermore, the drive signal controls the power MOSFET S1 to turn on and off via output pin 1; or controls the power MOSFET S2 to turn on and off via output pin 2; or controls the power MOSFET S3 to turn on and off via output pin 3.

[0018] Furthermore, the data acquisition module includes an oscilloscope, which is used to acquire the voltage waveform changes on the sampling capacitor Cm, extract the channel current waveform of the device under test, and then obtain the dynamic threshold voltage of the device under test.

[0019] Furthermore, resistors R2 and R3 are variable resistors; when power MOSFETs S1, S2, and S3 are all turned on, resistors R2 and R3 are connected in parallel, and the conduction current of the device under test can be controlled by changing the resistance ratio of resistors R2 and R3.

[0020] A method for characterizing the dynamic threshold voltage of a power MOSFET, applied to a characterization device for the dynamic threshold voltage of a power MOSFET, includes: measuring the dynamic threshold voltage of the device under test by means of the following steps, with power MOSFETs S1, S2, and S3 all in a turned-off state:

[0021] S11: Drive the power MOSFET S2 to turn on by the drive signal, and connect the source of the power MOSFET S1 to ground.

[0022] S12: Drive the power MOSFET S1 to turn on by the drive signal, so that the power MOSFET S2 can receive the first on-current.

[0023] S13: Drive the power MOSFET S3 to turn on via the drive signal, and provide a second on-current to the device under test;

[0024] S14: When the second conduction current reaches the preset value, the power MOSFET S3 is turned off;

[0025] S15: Turn off the power MOSFET S2 and apply the first conduction current to the device under test. At this time, the sampling capacitor Cm is in the charging state.

[0026] S16: According to the formula: The channel current of the device under test is calculated. ;in, The capacitance value of the sampling capacitor Cm;

[0027] S17: According to the formula: Calculate the voltage between the gate and source of the device under test. ,Will Channel current is used as the horizontal axis. Plot the channel current as the vertical axis. With voltage The waveform changes accordingly, and the dynamic threshold voltage of the device under test can be obtained from the waveform.

[0028] S18: After the device under test is turned off, repeat steps S11, S13, S14, S15, S16, and S17 to obtain the threshold voltage change under continuous switching pulses. Do not execute step S12 to keep the power MOSFET S1 in the on state and provide the drain voltage.

[0029] Furthermore, it also includes using a set on-current control circuit to regulate resistors R2 and R3, specifically including:

[0030] A conduction current control circuit is constructed, which is connected to both the voltage stress application circuit and the conduction current application circuit. The conduction current control circuit includes a monitoring component and a control sub-circuit. The monitoring component is connected to the control sub-circuit.

[0031] By using monitoring components, the process of applying stress to the drain voltage of the device under test, providing conduction current to the device under test, and the charging state of the sampling capacitor Cm are monitored to obtain monitoring data;

[0032] The monitoring data is compared with the set normal operating status data, and the comparison signal is obtained by the comparator in the monitoring component and sent to the control sub-circuit.

[0033] The control sub-circuit generates a first control command, a second control command, or a third control command based on the received comparison signal;

[0034] According to the first control command, control the alarm device to issue an alarm for process abnormality or abnormal charging status of sampling capacitor Cm;

[0035] According to the second control command, the control resistor R2 is adjusted to several set resistance values ​​to obtain multiple second conduction currents;

[0036] According to the third control command, the control resistor R3 is adjusted to several set resistance values ​​to obtain multiple first conduction currents.

[0037] Compared with the prior art, the present invention has the following advantages and beneficial effects: before applying drain current to the device under test, a conduction current is applied to the device under test through a conduction current application circuit, so that the device under test is subjected to current stress, which is closer to the working conditions of the device under test in the actual circuit, and can improve the accuracy of dynamic threshold voltage measurement of the device under test.

[0038] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the written description and the accompanying drawings.

[0039] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0040] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0041] Figure 1 This is a schematic diagram of a device for characterizing the dynamic threshold voltage of a power field-effect transistor.

[0042] Figure 2 This is a schematic diagram of the internal connections of the device used to characterize the dynamic threshold voltage of a power MOSFET.

[0043] Figure 3 A switching waveform timing diagram for measuring the change in threshold voltage of the device under test under different drain voltage application times;

[0044] Figure 4 The waveforms of the current and voltage across the sampling capacitor Cm are shown.

[0045] Figure 5 A schematic diagram illustrating a method for extracting the dynamic threshold voltage of a device under test;

[0046] Figure 6 This is a schematic diagram illustrating the steps of a method for characterizing the dynamic threshold voltage of a power MOSFET. Detailed Implementation

[0047] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0048] This invention provides a characterization device for the dynamic threshold voltage of a power field-effect transistor, such as... Figure 1 As shown, it includes:

[0049] The system comprises a voltage stress application circuit, a device under test (DUT) module, a control signal output circuit, a current application circuit, and a data acquisition module. The voltage stress application circuit is connected to the DUT module. The DUT module is connected to the current application circuit. The control signal output circuit is connected to both the voltage stress application circuit and the current application circuit. The data acquisition module is connected to the current application circuit.

[0050] The control signal output circuit is a field-programmable gate array (FPGA) circuit used to generate drive signals; the drive signals are used to drive the power MOSFETs in the control voltage stress application circuit and the conduction current application circuit.

[0051] The voltage stress application circuit is used to apply drain voltage stress to the device under test (DUT) in the DUT module; the on-current application circuit is used to provide on-current before the DUT receives drain voltage stress, so as to ensure that the DUT has on-current before the test begins.

[0052] The data acquisition module is used to acquire the dynamic threshold voltage of the device under test.

[0053] The working principle of the above technical solution is as follows: To characterize the dynamic threshold voltage of power MOSFETs, this invention proposes a voltage stress application circuit, a device under test (DUT) module, a control signal output circuit, a conduction current application circuit, and a data acquisition module. The voltage stress application circuit is connected to the DUT module; the DUT module is connected to the conduction current application circuit; the control signal output circuit is connected to both the voltage stress application circuit and the conduction current application circuit; the data acquisition module is connected to the conduction current application circuit. The control signal output circuit is a field-programmable gate array (FPGA) used to generate a drive signal. The drive signal is used to drive the power MOSFETs in the voltage stress application circuit and the conduction current application circuit. The voltage stress application circuit applies drain voltage stress to the DUT module. The conduction current application circuit provides conduction current before the DUT receives drain voltage stress, ensuring that the DUT has conduction current before the test begins. The data acquisition module acquires the dynamic threshold voltage of the DUT.

[0054] The beneficial effects of the above technical solution are as follows: By adopting the solution provided in this embodiment, before applying drain current to the device under test, conduction current is applied to the device under test through the conduction current application circuit, so that the device under test is subjected to current stress, which is closer to the working conditions of the device under test in the actual circuit, and the accuracy of dynamic threshold voltage measurement of the device under test can be improved.

[0055] In one embodiment, such as Figure 2 , Figure 3 As shown, the control signal output circuit includes output pin 1, output pin 2, and output pin 3. The output waveforms of output pin 1, output pin 2, and output pin 3 respectively correspond to... Figure 3 V in GS_S1 V GS_S2 V GS_S3 .

[0056] The working principle of the above technical solution is as follows: In order to ensure that the control signal output circuit outputs the control signal, the control signal output circuit includes output pin 1, output pin 2 and output pin 3.

[0057] The beneficial effects of the above technical solution are as follows: by using the solution provided in this embodiment, the output control signal can be guaranteed through the three output pins of the control signal output circuit.

[0058] In one embodiment, such as Figure 2 As shown, the voltage stress application circuit includes a power supply Vin, a power MOSFET S1, a power MOSFET S2, an inductor L1, and a resistor R. L The circuit consists of a diode D1, a capacitor C1, and a resistor R3; one end of capacitor C1 is connected to the positive terminal of the power supply Vin, and the other end of capacitor C1 is connected to the negative terminal of the power supply Vin; one end of inductor L1 is connected to one end of capacitor C1, and the other end of inductor L1 is connected to resistor R3. L One end; resistor R L The other end is connected to the drain of power MOSFET S1; the cathode of diode D1 is connected to one end of capacitor C1, and the anode of diode D1 is connected to the drain of power MOSFET S1; the source of power MOSFET S1 is connected to one end of resistor R3, and the gate of power MOSFET S1 is connected to output pin 1; the drain of power MOSFET S2 is connected to the other end of resistor R3, the source of power MOSFET S2 is connected to the negative terminal of power supply Vin, and the gate of power MOSFET S2 is connected to output pin 2; the negative terminal of power supply Vin is grounded.

[0059] The working principle of the above technical solution is as follows: In order to realize the function of the voltage stress application circuit, the voltage stress application circuit includes a power supply Vin, a power field-effect transistor S1, a power field-effect transistor S2, an inductor L1, and a resistor R. L The circuit consists of a diode D1, a capacitor C1, and a resistor R3; one end of capacitor C1 is connected to the positive terminal of the power supply Vin, and the other end of capacitor C1 is connected to the negative terminal of the power supply Vin; one end of inductor L1 is connected to one end of capacitor C1, and the other end of inductor L1 is connected to resistor R3. L One end; resistor R LThe other end is connected to the drain of power MOSFET S1; the cathode of diode D1 is connected to one end of capacitor C1, and the anode of diode D1 is connected to the drain of power MOSFET S1; the source of power MOSFET S1 is connected to one end of resistor R3, and the gate of power MOSFET S1 is connected to output pin 1; the drain of power MOSFET S2 is connected to the other end of resistor R3, the source of power MOSFET S2 is connected to the negative terminal of power supply Vin, and the gate of power MOSFET S2 is connected to output pin 2; the negative terminal of power supply Vin is grounded.

[0060] The beneficial effects of the above technical solution are as follows: by adopting the solution provided in this embodiment, the function of the voltage stress application circuit can be realized through the configuration and connection of the voltage stress application circuit.

[0061] In one embodiment, the device under test (DUT) module further includes a low-voltage DC power supply, the voltage of which is denoted as Vcc; the drain of the DUT is connected to the source of the power MOSFET S1; the gate of the DUT is connected to the positive terminal of the low-voltage DC power supply; the negative terminal of the low-voltage DC power supply is connected to the negative terminal of the power supply Vin; the voltage value of the low-voltage DC power supply is configured to be significantly greater than the threshold voltage of the DUT and lower than the maximum allowable voltage across the gate of the DUT.

[0062] The working principle of the above technical solution is as follows: In order to realize the function of the device under test module, a low-voltage DC power supply is configured in the device under test module; the drain of the device under test is connected to the source of the power field-effect transistor S1; the gate of the device under test is connected to the positive terminal of the low-voltage DC power supply; the negative terminal of the low-voltage DC power supply is connected to the negative terminal of the power supply Vin; the voltage value of the low-voltage DC power supply is configured to be significantly greater than the threshold voltage of the device under test and lower than the maximum allowable voltage of the gate of the device under test.

[0063] The beneficial effects of the above technical solution are as follows: by adopting the solution provided in this embodiment, the safe testing of the device under test can be guaranteed through the configuration in the device under test module.

[0064] In one embodiment, the current application circuit includes a sampling capacitor Cm, a resistor R2, and a power MOSFET S3; one end of the sampling capacitor Cm is connected to the source of the device under test, and the other end of the sampling capacitor Cm is connected to the negative terminal of the power supply Vin; one end of the resistor R2 is connected to the source of the device under test, and the other end of the resistor R2 is connected to the drain of the power MOSFET S3; the source of the power MOSFET S3 is connected to the negative terminal of the power supply Vin, and the gate of the power MOSFET S3 is connected to the output pin 3.

[0065] The working principle of the above technical solution is as follows: In order to realize the function of the current application circuit, the current application circuit is equipped with a sampling capacitor Cm, a resistor R2, and a power MOSFET S3; one end of the sampling capacitor Cm is connected to the source of the device under test, and the other end of the sampling capacitor Cm is connected to the negative terminal of the power supply Vin; one end of the resistor R2 is connected to the source of the device under test, and the other end of the resistor R2 is connected to the drain of the power MOSFET S3; the source of the power MOSFET S3 is connected to the negative terminal of the power supply Vin, and the gate of the power MOSFET S3 is connected to the output pin 3.

[0066] The beneficial effects of the above technical solution are as follows: by using the solution provided in this embodiment, the function of the conducting current application circuit can be realized by configuring the components of the conducting current application circuit.

[0067] In one embodiment, the drive signal controls the power MOSFET S1 to turn on and off via output pin 1; or controls the power MOSFET S2 to turn on and off via output pin 2; or controls the power MOSFET S3 to turn on and off via output pin 3.

[0068] The working principle of the above technical solution is as follows: the power MOSFET S1 is turned on and off, or the power MOSFET S2 is turned on and off, or the power MOSFET S3 is turned on and off, through three output pins.

[0069] The beneficial effects of the above technical solution are as follows: by adopting the solution provided in this embodiment, different power field-effect transistors can be controlled by different driving signals through the pins.

[0070] In one embodiment, the data acquisition module includes an oscilloscope, which is used to acquire the voltage waveform change on the sampling capacitor Cm, extract the channel current waveform of the device under test, and then obtain the dynamic threshold voltage of the device under test.

[0071] The working principle of the above technical solution is as follows: In order to achieve data acquisition, the present invention is equipped with an oscilloscope to acquire the voltage waveform change on the sampling capacitor Cm, extract the channel current waveform of the device under test, and then obtain the dynamic threshold voltage of the device under test.

[0072] The beneficial effects of the above technical solution are as follows: by using the solution provided in this embodiment, data acquisition can be achieved through the configuration of an oscilloscope.

[0073] In one embodiment, resistors R2 and R3 are variable resistors; when power MOSFETs S1, S2, and S3 are all turned on, resistors R2 and R3 are connected in parallel, and the conduction current of the device under test can be controlled by changing the resistance ratio of resistors R2 and R3.

[0074] The working principle of the above technical solution is as follows: In order to ensure the control of resistors R2 and R3, resistors R2 and R3 in this invention are configured as variable resistors. When power MOSFET S1, power MOSFET S2, and power MOSFET S3 are all turned on, resistors R2 and R3 are connected in parallel. The conduction current of the device under test can be controlled by changing the resistance ratio of resistors R2 and R3.

[0075] The beneficial effects of the above technical solution are as follows: by using the solution provided in this embodiment, different resistance values ​​can be adjusted through the configuration of variable resistors.

[0076] A method for characterizing the dynamic threshold voltage of a power MOSFET, such as... Figure 3 , Figure 4 As shown, a characterization device for the dynamic threshold voltage of a power MOSFET includes: measuring the dynamic threshold voltage of the device under test by means of the following steps, with power MOSFETs S1, S2, and S3 all in a turned-off state:

[0077] S11: By driving the signal, the power MOSFET S2 is turned on, connecting the source of the power MOSFET S1 to ground. Figure 3 At time t0;

[0078] S12: By driving the signal, the power MOSFET S1 is turned on, causing the power MOSFET S2 to receive the first on-state current, corresponding to... Figure 3 The t1 to t2 time period;

[0079] S13: Driven by the driving signal, the power MOSFET S3 is turned on, providing a second on-current to the device under test. Figure 3 The t2 to t3 time period;

[0080] S14: When the second conduction current reaches a preset value, the power MOSFET S3 is turned off, corresponding to... Figure 3 The t3 to t4 time period;

[0081] S15: Turn off power MOSFET S2, applying the entire first conduction current to the device under test. At this time, sampling capacitor Cm is in a charging state, corresponding to... Figure 3 The t4 to t5 time period;

[0082] S16: According to the formula: Calculation obtained Figure 3 Channel current of the device under test during the time period t4 to t5 ;in, The capacitance value of the sampling capacitor Cm corresponds to Figure 3 , Figure 4 In Waveform;

[0083] S17: According to the formula: Calculate the voltage between the gate and source of the device under test. ,Will Channel current is used as the horizontal axis. Plot the channel current as the vertical axis. With voltage The waveform changes accordingly. Based on the waveform, the dynamic threshold voltage of the device under test can be obtained, such as... Figure 5 As shown, The Vgs corresponding to a voltage of 0.1A is the threshold voltage.

[0084] S18: After the device under test (DUT) is turned off, repeat steps S11, S13, S14, S15, S16, and S17 to obtain the threshold voltage change under continuous switching pulses. Do not execute step S12 to keep the power MOSFET S1 on and provide drain voltage. Figure 3 The period following T5.

[0085] For measuring a device under test (DUT) after it has been subjected to drain voltage stress, the measurement content is to measure the dynamic threshold voltage of the DUT after it has been subjected to drain voltage stress, specifically including the stress application stage and the dynamic characteristic measurement stage. Figure 3 Set the driving waveform corresponding to this measurement method;

[0086] The voltage across the sampling capacitor Cm The waveform is used to obtain the channel current of the sampling capacitor Cm. Waveform, such as Figure 4 As shown, when the power MOSFET S2 is turned off, the sampling capacitor Cm charges, and the voltage across the sampling capacitor Cm rises; Figure 5 As shown, Channel current is used as the horizontal axis. Using the vertical axis as the coordinate, the dynamic threshold voltage of the device under test can be read.

[0087] The working principle of the above technical solution is as follows: To achieve a method for characterizing the dynamic threshold voltage of a power MOSFET, this invention measures the dynamic threshold voltage of the device under test (DUT) when power MOSFETs S1, S2, and S3 are all in a turned-off state. The specific steps are as follows: First, a driving signal is used to drive power MOSFET S2 to conduct, connecting the source of power MOSFET S1 to ground; then, a driving signal is used to drive power MOSFET S1 to conduct, allowing power MOSFET S2 to receive a first conduction current; next, a driving signal is used to drive power MOSFET S3 to conduct, providing a second conduction current to the DUT; when the second conduction current reaches a preset value, power MOSFET S3 is turned off; then, power MOSFET S2 is turned off again, applying the entire first conduction current to the DUT, at which point the sampling capacitor Cm is in a charging state; according to the formula... The channel current of the device under test is calculated. ;in, Let Cm be the capacitance value of the sampling capacitor; according to the formula Calculate the voltage between the gate and source of the device under test. ,Will Channel current is used as the horizontal axis. Plot the channel current as the vertical axis. With voltage The waveform changes accordingly. Based on the waveform, the dynamic threshold voltage of the device under test is obtained. Preferably, after the device under test is turned off, steps S11, S13, S14, S15, S16, and S17 are repeated to obtain the threshold voltage change under continuous switching pulses. Step S12 is not executed to keep the power MOSFET S1 in the on state and provide the drain voltage.

[0088] The beneficial effects of the above technical solution are as follows: By using the solution provided in this embodiment, before applying drain current to the device under test, a conduction current is applied to the device under test through a conduction current application circuit, so that the device under test is subjected to current stress, which is closer to the working conditions of the device under test in the actual circuit, thereby improving the accuracy of dynamic threshold voltage measurement of the device under test.

[0089] In one embodiment, the method further includes adjusting resistors R2 and R3 using a configured on-current control circuit, specifically including:

[0090] A conduction current control circuit is constructed, which is connected to both the voltage stress application circuit and the conduction current application circuit. The conduction current control circuit includes a monitoring component and a control sub-circuit. The monitoring component is connected to the control sub-circuit.

[0091] By using monitoring components, the process of applying stress to the drain voltage of the device under test, providing conduction current to the device under test, and the charging state of the sampling capacitor Cm are monitored to obtain monitoring data;

[0092] The monitoring data is compared with the set normal operating status data, and the comparison signal is obtained by the comparator in the monitoring component and sent to the control sub-circuit.

[0093] The control sub-circuit generates a first control command, a second control command, or a third control command based on the received comparison signal;

[0094] According to the first control command, control the alarm device to issue an alarm for process abnormality or abnormal charging status of sampling capacitor Cm;

[0095] According to the second control command, the control resistor R2 is adjusted to several set resistance values ​​to obtain multiple second conduction currents;

[0096] According to the third control command, the control resistor R3 is adjusted to several set resistance values ​​to obtain multiple first conduction currents.

[0097] The working principle of the above technical solution is as follows: In order to achieve the regulation of resistors R2 and R3, the present invention sets up a conduction current control circuit, specifically, a conduction current control circuit is built that is connected to the voltage stress application circuit and the conduction current application circuit respectively; the conduction current control circuit includes a monitoring component and a control sub-circuit; the monitoring component is connected to the control sub-circuit;

[0098] By using monitoring components, the process of applying stress to the drain voltage of the device under test, providing conduction current to the device under test, and the charging state of the sampling capacitor Cm are monitored to obtain monitoring data;

[0099] The monitoring data is compared with the set normal operating status data, and the comparison signal is obtained by the comparator in the monitoring component and sent to the control sub-circuit.

[0100] The control sub-circuit generates a first control command, a second control command, or a third control command based on the received comparison signal;

[0101] According to the first control command, control the alarm device to issue an alarm for process abnormality or abnormal charging status of sampling capacitor Cm;

[0102] According to the second control command, the control resistor R2 is adjusted to several set resistance values ​​to obtain multiple second conduction currents;

[0103] According to the third control command, the control resistor R3 is adjusted to several set resistance values ​​to obtain multiple first conduction currents.

[0104] The beneficial effects of the above technical solution are as follows: by using the solution provided in this embodiment to regulate resistors R2 and R3 using the conduction current control circuit, the regulation effect and quality can be improved.

[0105] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A device for characterizing the dynamic threshold voltage of a power field-effect transistor, characterized in that, include: Voltage stress application circuit, device under test module, control signal output circuit, conduction current application circuit, and data acquisition module; The voltage stress application circuit is connected to the device under test module; The device under test module is connected to the on-current application circuit; the control signal output circuit is connected to both the voltage stress application circuit and the on-current application circuit; the data acquisition module is connected to the on-current application circuit. The control signal output circuit is a field-programmable gate array (FPGA) circuit used to generate drive signals, including output pin 1, output pin 2 and output pin 3; the drive signal controls the power MOSFET S1 to turn on and off via output pin 1; or controls the power MOSFET S2 to turn on and off via output pin 2; or controls the power MOSFET S3 to turn on and off via output pin 3. The voltage stress application circuit includes a power supply Vin, a power MOSFET S1, a power MOSFET S2, an inductor L1, and a resistor R. L The circuit consists of a diode D1, a capacitor C1, and a resistor R3; one end of capacitor C1 is connected to the positive terminal of the power supply Vin, and the other end of capacitor C1 is connected to the negative terminal of the power supply Vin; one end of inductor L1 is connected to one end of capacitor C1, and the other end of inductor L1 is connected to resistor R3. L One end; resistor R L The other end is connected to the drain of power MOSFET S1; the cathode of diode D1 is connected to one end of capacitor C1, and the anode of diode D1 is connected to the drain of power MOSFET S1; the source of power MOSFET S1 is connected to one end of resistor R3, and the gate of power MOSFET S1 is connected to output pin 1; the drain of power MOSFET S2 is connected to the other end of resistor R3, the source of power MOSFET S2 is connected to the negative terminal of power supply Vin, and the gate of power MOSFET S2 is connected to output pin 2. The negative terminal of the power supply Vin is grounded; the voltage stress application circuit is used to apply drain voltage stress to the device under test in the device under test module; The device under test module also includes a low-voltage DC power supply, the voltage of which is denoted as Vcc; The drain of the device under test is connected to the source of the power MOSFET S1; The gate of the device under test (DUT) is connected to the positive terminal of a low-voltage DC power supply; the negative terminal of the low-voltage DC power supply is connected to the negative terminal of the power supply Vin; the voltage value of the low-voltage DC power supply is configured to be significantly greater than the threshold voltage of the DUT and lower than the maximum allowable voltage that the gate of the DUT can pass through. The current application circuit includes a sampling capacitor Cm, a resistor R2, and a power MOSFET S3. One end of the sampling capacitor Cm is connected to the source of the device under test (DUT), and the other end is connected to the negative terminal of the power supply Vin. One end of the resistor R2 is connected to the source of the DUT, and the other end is connected to the drain of the power MOSFET S3. The source of the power MOSFET S3 is connected to the negative terminal of the power supply Vin, and the gate of the power MOSFET S3 is connected to output pin 3. Resistors R2 and R3 are variable resistors. When all three power MOSFETs S1, S2, and S3 are turned on, resistors R2 and R3 are connected in parallel. The current applied to the DUT can be adjusted by changing the ratio of the resistance values ​​of resistors R2 and R3. The on-current application circuit is used to provide on-current before the device under test (DUT) is subjected to drain voltage stress, so as to ensure that the DUT has on-current before the test begins; The data acquisition module includes an oscilloscope, which is used to acquire the voltage waveform changes on the sampling capacitor Cm, extract the channel current waveform of the device under test, and then obtain the dynamic threshold voltage of the device under test.

2. A method for characterizing the dynamic threshold voltage of a power MOSFET, applied to the characterization device for the dynamic threshold voltage of a power MOSFET as described in claim 1, characterized in that, include: With power MOSFETs S1, S2, and S3 all in the off state, the dynamic threshold voltage of the device under test is measured using the following steps: S11: Drive the power MOSFET S2 to turn on by the drive signal, and connect the source of the power MOSFET S1 to ground. S12: Drive the power MOSFET S1 to turn on by the drive signal, so that the power MOSFET S2 can receive the first on-current. S13: Drive the power MOSFET S3 to turn on via the drive signal, and provide a second on-current to the device under test; S14: When the second conduction current reaches the preset value, the power MOSFET S3 is turned off; S15: Turn off the power MOSFET S2 and apply the first conduction current to the device under test. At this time, the sampling capacitor Cm is in the charging state. S16: According to the formula: The channel current of the device under test is calculated. ;in, The voltage across the sampling capacitor Cm is... The capacitance value of the sampling capacitor Cm; S17: According to the formula: Calculate the voltage between the gate and source of the device under test. ,Will Channel current is used as the horizontal axis. Plot the channel current as the vertical axis. With voltage The waveform changes accordingly, and the dynamic threshold voltage of the device under test can be obtained from the waveform. The voltage of the low-voltage DC power supply in the device under test module. The source voltage of the device under test; S18: After the device under test is turned off, repeat steps S11, S13, S14, S15, S16, and S17 to obtain the threshold voltage change under continuous switching pulses. Do not execute step S12 to keep the power MOSFET S1 in the on state and provide the drain voltage.

3. The method for characterizing the dynamic threshold voltage of a power field-effect transistor according to claim 2, characterized in that, It also includes using a set on-current control circuit to adjust resistors R2 and R3, specifically including: A conduction current control circuit is constructed, which is connected to both the voltage stress application circuit and the conduction current application circuit. The conduction current control circuit includes a monitoring component and a control sub-circuit. The monitoring component is connected to the control sub-circuit. By using monitoring components, the process of applying stress to the drain voltage of the device under test, providing conduction current to the device under test, and the charging state of the sampling capacitor Cm are monitored to obtain monitoring data; The monitoring data is compared with the set normal operating status data, and the comparison signal is obtained by the comparator in the monitoring component and sent to the control sub-circuit. The control sub-circuit generates a first control command, a second control command, or a third control command based on the received comparison signal; According to the first control command, control the alarm device to issue an alarm for process abnormality or abnormal charging status of sampling capacitor Cm; According to the second control command, the control resistor R2 is adjusted to several set resistance values ​​to obtain multiple second conduction currents; According to the third control command, the control resistor R3 is adjusted to several set resistance values ​​to obtain multiple first conduction currents.

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