Time-to-digital converter circuit and working method thereof

Abstract

The invention provides a time-to-digital converter circuit and a working method thereof. The time-to-digital converter circuit comprises a logic control module, a quantizer and a reading circuit which are connected in sequence, the time-to-digital converter circuit is used for outputting a data readable signal RDY and a quantization code D0-DN according to an input reset signal RST, a system clock CKS and a signal TIN to be quantized. According to the invention, the time can be quantized through the time-to-digital converter based on the time register, and the provided circuit and the implementation mode have the advantages of low power consumption, high reliability and the like, and can be widely applied to related applications such as laser range finders, fluorescence lifetime imaging microscopes and the like.

Description

Technical Field

[0001] The invention relates to the technical field of time measurement and digitization, and in particular to a time-to-digital converter circuit and a working method thereof. Background Art

[0002] A time-to-digital converter (TDC) is a device that can quantify time intervals. The current structure of a time-to-digital converter requires complex calibration techniques and large encoding circuits to ensure its accuracy, which has limitations. This patent proposes a calibration-free time-to-digital converter, which is expected to expand the use scenarios of time-to-digital converters. Summary of the invention

[0003] The purpose of the present invention is to propose a time-to-digital converter circuit and a working method thereof. The present invention can quantify time through a time-to-digital converter based on a time register. The proposed circuit and implementation method have the advantages of low power consumption and high reliability, and can be widely used in related applications such as laser rangefinders and fluorescence lifetime imaging microscopes.

[0004] To achieve the above object, the technical solution of the present invention is as follows:

[0005] A time-to-digital converter circuit comprises a logic control module, a quantizer and a readout circuit connected in sequence; the time-to-digital converter circuit is used to output a data readable signal RDY and a quantization code D0-DN according to an input reset signal RST, a system clock CKS and a signal to be quantized TIN; specifically,

[0006] The input end of the logic control module includes RST_C, CK_C, TIN_C, TRG1 and TRG2, and the output end includes STR, TIND, CKR1, CKR2, CKP1, CKP2 and RDY; wherein RST_C, CK_C and TIN_C respectively receive the input reset signal RST, system clock CKS and signal to be quantized TIN, TRG1 and TRG2 respectively receive the residual signal TRES1 and residual signal TRES2 of the quantizer TRES1 and TRES2, and the RDY end outputs the data readable signal RDY, and the other output ends output corresponding signals;

[0007] The input end of the quantizer includes a STR_TR end, a TIN_TR end, a CKR1 end, a CKR2 end, a CKP1 end, a CKP2 end and a RST_TR end; the output end includes a TRES1 end, a TRES2 end, a TDC1 end and a TDC2 end; wherein the STR_TR end, the TIN_TR end, the CKR1 end, the CKR2 end, the CKP1 end, the CKP2 end and the RST_TR end receive signals from the STR end, the TIND end, the CKR1 end, the CKR2 end, the CKP1 end, the CKP2 end and the RDY end of the logic control module respectively, and the output end outputs corresponding signals;

[0008] The input end of the readout circuit includes DIN1, DIN2, RST_RO, CK1_RO and CK2_RO; the output end includes D0-D N wherein the DIN1 terminal and the DIN2 terminal receive the signals of the quantizer TDC1 terminal and the TDC2 terminal respectively, the RST_RO terminal receives the input reset signal RST, the CK1_RO terminal and the CK2_RO terminal receive the CKP1 signal and the CKP2 signal of the logic control module CKP1 terminal and the CKP2 terminal respectively, and the output terminals D0-D N The ends output quantization codes D0-DN respectively.

[0009] Preferably, the quantizer includes a data selector, a first residual operation unit, a second residual operation unit, a first time-to-digital converter, a second time-to-digital converter, a first OR gate and a second OR gate.

[0010] Preferably, for any residual operation unit of the first residual operation unit and the second residual operation unit: the input end includes a CKA end, a CKB end, a CKP end and a RST_R end, and the output end includes a CKOA end, a CKOB end and a TRES end;

[0011] For any one of the first time-to-digital converter and the second time-to-digital converter: the input terminal includes the DI terminal, the CK terminal, the RST_T terminal and the CG terminal, and the output terminal is the DO terminal;

[0012] The input terminals of the data selector include the A terminal, the B terminal and the S terminal, and the output terminal is the Y terminal;

[0013] For any one of the first OR gate and the second OR gate: the input end includes the a end and the b end, and the output end is the y end;

[0014] Among them, the STR_TR end of the quantizer corresponds to the data selector S end, the first time digital converter RST_T end and the second time digital converter RST_T end, the TIN_TR end of the quantizer corresponds to the data selector B end, the CKR1 end of the quantizer corresponds to the first residual operation unit CKB end and the a end of the second OR gate, the CKR2 end of the quantizer corresponds to the second residual operation unit CKB end and the a end of the first OR gate, the CKP1 end and the CKP2 end of the quantizer correspond to the first residual operation unit CKP end and the second residual operation unit CKP end respectively, and the RST_TR end of the quantizer corresponds to the first OR gate b end and the second OR gate b end; the TRES1 end, TRES2 end, TDC1 end and TDC2 end of the quantizer correspond to the first residual operation unit TRES end, the second residual operation unit TRES end, the first time digital converter DO end and the second time digital converter DO end respectively;

[0015] The data selector A terminal receives the output signal of the second residual operation unit TRES terminal;

[0016] The first residual operation unit CKA terminal receives the output signal of the data selector Y terminal, and the first residual operation unit RST_R terminal receives the output signal of the first OR gate y terminal;

[0017] The second residual operation unit CKA terminal receives the output signal of the first residual operation unit TRES terminal, and the second residual operation unit RST_R terminal receives the output signal of the second OR gate y terminal;

[0018] The first time-to-digital converter DI receives the output signal of the first residual operation unit CKOA, the first time-to-digital converter CK receives the output signal of the first residual operation unit CKOB, and the first time-to-digital converter CG receives the output signal of the second time-to-digital converter DO;

[0019] The second time-to-digital converter DI receives the output signal of the second residual operation unit CKOA, the second time-to-digital converter CK receives the output signal of the second residual operation unit CKOB, and the second time-to-digital converter CG receives the output signal of the first time-to-digital converter DO.

[0020] Preferably, the working method of the logic control module is as follows:

[0021] After the system is reset, the logic control module is in a waiting state; if it is in the waiting state, when event 1 occurs, the working state jumps from the waiting state to state 1; if it is in state 1 or state 7, when event 2 occurs, it jumps to state 2; if it is in state 2, when event 3 occurs, it jumps from state 2 to state 3; if it is in state 3, it makes a decision on judgment 1, if it is true, it returns to the waiting state, if it is false, it jumps to state 4; if it is in state 4, when event 4 occurs, it jumps from state 4 to state 5; if it is in state 5, when event 5 occurs, it jumps from state 5 to state 6; if it is in state 6, it makes a decision on judgment 2, if it is true, it returns to the waiting state, if it is false, it jumps to state 7;

[0022] Waiting state: when the reset signal RST input to the RST_C terminal of the logic control module is at a logic high level, the logic control module is in a reset state, the data readable signal RDY output from the RDY terminal is at a logic high level, and the output signals of the other output terminals are at a logic low level; when the reset signal RST input to the RST_C terminal is at a logic low level, the logic control module is in a working state. When the logic control module is in a working state, a value tdcfsh is set to record the number of edge transition events of the CKP1 signal and the CKP2 signal at the CKP1 and CKP2 terminals, the tdcfsh value is set to 0, and the data readable signal RDY at the RDY terminal is set to a logic high level;

[0023] Event 1: The rising edge of the signal to be quantized TIN input to the logic control module TIN_C terminal jumps to the edge;

[0024] State 1: After the rising edge of the signal to be quantified TIN jumps, the STR signal at the STR end of the logic control module is immediately set to a logic high level, and the RDY signal at the RDY end of the logic control module is set to a logic low level. After that, when the sixth edge jump of the system clock CKS input at the CK_C end of the logic control module arrives, the STR signal is set to a logic low level; the input signal to be quantified TIN is delayed by t ST1 After that, it is output to the TIND terminal; when the first edge transition of the system clock CKS arrives after the STR signal is at a logic high level, the CKR1 signal at the CKR1 terminal of the logic control module is set to a logic high level; when the third edge transition of the system clock CKS arrives, the CKR1 signal at the CKR1 terminal of the logic control module is set to a logic low level; when the sixth edge transition of the system clock CKS arrives, the CKP1 signal at the CKP1 terminal of the logic control module is set to a logic high level, and a value ckptms is set at the same time to record the number of edge transitions of the system clock CKS thereafter;

[0025] Event 2: The residual signal TRES1 input to the logic control module TRG1 has a falling edge transition;

[0026] Event 3: The falling edge of the CKP1 signal occurs;

[0027] State 3: add 1 to tdcfsh;

[0028] Judgment 1: Whether the value of tdcfsh is equal to the preset value N;

[0029] State 4: When the first edge of the system clock CKS jumps after the falling edge of the CKP1 signal, the CKR2 signal at the CKR2 end is set to a logic high level; when the third edge of the system clock CKS jumps, the CKR2 signal is set to a logic low level; when the fourth edge of the system clock CKS jumps, the CKP2 signal is set to a logic high level, and the counting of the edge jumps of the system clock CKS is restarted, and the count value is kept at ckptms;

[0030] Event 4: The residual signal TRES2 input to the logic control module TRG2 has a falling edge transition;

[0031] Event 5: The falling edge of the CKP2 signal occurs;

[0032] State 6: add 1 to tdcfsh;

[0033] Judgment 2: Whether the value of tdcfsh is equal to the preset value N;

[0034] State 7: When the first edge of the system clock CKS jumps after the falling edge of the CKP2 signal jumps, the CKR1 signal at the CKR1 end is set to a logic high level; when the third edge of the system clock CKS jumps, the CKR1 signal is set to a logic low level; when the fourth edge of the system clock CKS jumps, the CKP1 signal is set to a logic high level, and the counting of the edge jumps of the system clock CKS is restarted, and the count value is kept at ckptms;

[0035] State 2 and state 5 adopt control mode 1 or control mode 2;

[0036] When in control mode 1:

[0037] State 2: Determine whether the edge transition count value ckptms reaches the preset value M. If so, set the CKP1 signal to a logic low level, stop ckptms from counting the edge transitions of the system clock CKS, and clear the ckptms value;

[0038] State 5: Determine whether the edge transition count value ckptms reaches the preset value M. If so, set the CKP2 signal to a logic low level, stop ckptms from counting the edge transitions of the system clock CKS, and clear the ckptms value;

[0039] When in control mode 2:

[0040] State 2: Set the CKP1 signal to a logic low level;

[0041] State 5: Set the CKP2 signal to a logic low level.

[0042] Preferably, the input signal to be quantized TIN is delayed by t ST1 Then output to TIND terminal, delay time t ST1 No more than the system clock CKS period T S half.

[0043] Preferably, for any residual operation unit of the first residual operation unit and the second residual operation unit, the working method is specifically as follows:

[0044] When the RST_R signal at the RST_R terminal is at a logic high level, the residual operation unit is in a reset state, and the output signals at the output terminals are all at a logic low level; when the RST_R signal is at a logic low level, the residual operation unit is in a working state;

[0045] When the residual operation unit is in working state, it first waits for the arrival of a single pulse on the CKA input signal and the CKB input signal, and after the arrival of the single pulse, records the single pulse width tA on the CKA input signal and the single pulse width tB on the CKB input signal; after the pulse of the CKP input signal arrives, the CKOA output signal and the CKOB output signal are set to a logic high level, the time difference between the arrival moment of the CKP input signal pulse and the moment when the CKOA output signal becomes a logic high level is tOA, and the time difference between the arrival moment of the CKP input signal pulse and the moment when the CKOB output signal becomes a logic high level is tOB, then the residual operation unit will ensure that (tOB-tOA) is equal to 2 times (tA-tB); after the CKOA output signal and the CKOB output signal both become a logic high level, the residual operation unit will generate a pulse with a width equal to 2(tA-tB) at the TRES end.

[0046] Preferably, for any one of the first time-to-digital converter and the second time-to-digital converter, the working method is specifically as follows:

[0047] When the input signal at the RST_T terminal is at a logic high level, the time digital converter is in a reset state, and the output signal at the DO terminal is at a logic high level; when the input signal at the RST_T terminal is at a logic low level, the time digital converter is in a working state;

[0048] When the time-to-digital converter is in working state, it will detect whether the states of the DI input signal and the CK input signal are transformed into a logic high level, and compare the moments when the DI input signal and the CK input signal are transformed into a logic high level; the CG input signal is used to control the logic value of the final DO output signal:

[0049] If the CK input signal has not yet changed to a logic high level when the DI input signal changes to a logic high level, if the CG input signal is a logic high level at this time, the DO output signal is set to a logic high level; if the CG input signal is a logic low level, the DO output signal is set to a logic low level;

[0050] If it is found that the DI input signal has not changed to a logic high level when the CK input signal changes to a logic high level, if the CG input signal is a logic high level at this time, the DO output signal is set to a logic low level; if the CG input signal is a logic low level, the DO output signal is set to a logic high level.

[0051] Preferably, the working method of the data selector is as follows:

[0052] When the S-terminal input signal is at a logic high level, the B-terminal input signal is mapped to the Y-terminal output signal; when the S-terminal input signal is at a logic low level, the A-terminal input signal is mapped to the Y-terminal output signal.

[0053] Preferably, for any one of the first OR gate and the second OR gate, the working method is as follows:

[0054] As long as any one of the input signals at the a-end and the b-end is at a logic high level, the output signal at the y-end is at a logic high level; otherwise, the output signal at the y-end is at a logic low level.

[0055] Preferably, the working method of the readout circuit is as follows:

[0056] When the reset signal RST input at the RST_RO terminal is at a logic high level, the readout circuit is in a reset state, and D0-D N When the quantization code D0-DN outputted by the terminal is at a logic low level; when the reset signal RST inputted at the RST_RO terminal is at a logic low level, the readout circuit is in working state;

[0057] When the readout circuit is in working state; if N is an odd number; when the nth falling edge of the CKP1 signal input at the CK1_RO terminal jumps, the DIN1 terminal input signal is transmitted to D 2n-2 terminal, where n = 1, 2, ..., (N + 1) / 2; when the mth falling edge of the CKP2 signal input at the CK2_RO terminal arrives, the input signal at the DIN2 terminal is transmitted to the D2m-1 terminal, where m = 1, 2, ..., (N + 1) / 2; if N is an even number; when the nth falling edge of the CKP1 signal input at the CK1_RO terminal arrives, the input signal at the DIN1 terminal is transmitted to the D 2n-2 terminal, where n = 1, 2, ..., (N + 2) / 2; when the mth falling edge of the CKP2 signal input at the CK2_RO terminal arrives, the DIN2 terminal input signal is transmitted to D 2m-1 end, where m = 1, 2, ..., N / 2; and finally N+1 output quantization codes D0-DN are obtained.

[0058] Compared with the prior art, the present invention has the following beneficial effects:

[0059] The present invention can quantify time through a time-to-digital converter based on a time register. The proposed circuit and implementation method have the advantages of low power consumption and high reliability, and can be widely used in related applications such as laser rangefinders and fluorescence lifetime imaging microscopes. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 is a circuit diagram of a time-to-digital converter of the present invention;

[0061] Figure 2 It is a working flow chart of the logic control module of the present invention;

[0062] Figure 3 This is a specific structural diagram of the quantizer of the present invention. DETAILED DESCRIPTION

[0063] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings.

[0064] The present invention provides a time-to-digital converter circuit, such as Figure 1 As shown, it includes: a logic control module, a quantizer and a readout circuit. The input of the circuit is a reset signal RST, a system clock CKS, and a signal to be quantized TIN. Its output end includes a data readable signal RDY and quantization codes D0~DN.

[0065] The specific structure of the quantizer is as follows Figure 3 As shown, it is composed of a data selector, a residual operation unit 1, a residual operation unit 2, a time digital converter 1, a time digital converter 2, an OR gate 1 and an OR gate 2. The input end of the quantizer includes a start signal STR_TR, a quantizer reset signal RST_TR, a signal to be quantized TIN_TR, a reference signal CKR1, a reference signal CKR2, an output control signal CKP1 and an output control signal CKP2, and the output end includes a residual signal TRES1, a residual signal TRES2, a quantization result TDC1 and a quantization result TDC2.

[0066] The input end of the residual operation unit includes CKA, CKB, CKP and RST_R, and the output end includes CKOA, CKOB and TRES.

[0067] The input terminals of the time-to-digital converter include DI, CK, RST_T and CG, and the output terminal is DO.

[0068] The data selector input terminals include A, B and S, and the output terminal is Y.

[0069] The input terminals of the OR gate include A and B, and the output terminal is Y.

[0070] The input end of the readout circuit includes DIN1, DIN2, RST_RO, CK1_RO and CK2_RO, and the output end includes quantization codes D0~DN.

[0071] The present invention provides a working method of a time-to-digital converter circuit, wherein the working flow diagram of the logic control module is as follows: Figure 2 As shown in the figure, the state refers to the possible working state of the logic control module, and the event refers to the reason that triggers the logic control module to change from one working state to another. The workflow of the entire logic control module is described as follows:

[0072] After the system is reset, the logic control module is in a waiting state; if it is in the waiting state, when event 1 occurs, the working state jumps from the waiting state to state 1; if it is in state 1 or state 7, when event 2 occurs, it jumps to state 2; if it is in state 2, when event 3 occurs, it jumps from state 2 to state 3; if it is in state 3, it makes a decision on judgment 1, if it is true, it returns to the waiting state, if it is false, it jumps to state 4; if it is in state 4, when event 4 occurs, it jumps from state 4 to state 5; if it is in state 5, when event 5 occurs, it jumps from state 5 to state 6; if it is in state 6, it makes a decision on judgment 2, if it is true, it returns to the waiting state, if it is false, it jumps to state 7.

[0073] The logic control module has two control modes. The state flip logic of the two control modes complies with the workflow described above. Except for the slight difference between state 2 and state 5, the contents of other states and events are the same. For the sake of convenience, the details of the states and events common to the two control modes are first described, including:

[0074] Waiting state: When the logic control module input signal RST_C is at a logic high level, the logic control module is in a reset state, the RDY signal is at a logic high level, and the other output signals are at a logic low level; when the RST_C signal is at a logic low level, the logic control module is in a working state. When the logic control module is in a working state, a value tdcfsh is set to record the number of edge transition events of the logic control module output signals CKP1 and CKP2; the tdcfsh value is set to 0; and the RDY signal is set to a logic high level.

[0075] Event 1: The logic control module input signal TIN_C has a rising edge transition.

[0076] State 1: After the rising edge of the logic control module input signal TIN_C jumps, the logic control module output signal STR is immediately set to a logic high level and the logic control module output signal RDY is set to a logic low level; thereafter, when the sixth edge of the logic control module input signal CK_C jumps, STR is set to a logic low level. Delay TIN_C by t ST1 Then it is output to the logic control module output signal TIND, the delay time t ST1 Not exceeding the system clock CK_C period T S Half of . When the first edge transition of CK_C arrives after STR is at a logic high level, the logic control module output signal CKR1 is set to a logic high level; when the third edge transition of CK_C arrives, the logic control module output signal CKR1 is set to a logic low level; when the sixth edge transition of CK_C arrives, the logic control module output signal CKP1 is set to a logic high level; at the same time, a value ckptms is set for the number of edge transitions of CK_C thereafter.

[0077] Event 2: The logic control module input signal TRG1 has a falling edge transition.

[0078] Event 3: CKP1 falling edge transition occurs.

[0079] State 3: Increase tdcfsh by 1.

[0080] Judgment 1: Whether the value of tdcfsh is equal to the preset value N.

[0081] State 4: When the first edge transition of CK_C arrives after the falling edge transition of CKP1 arrives, CKR2 is set to a logic high level; when the third edge transition of CK_C arrives, CKR2 is set to a logic low level; when the fourth edge transition of CK_C arrives, the logic control module output signal CKP2 is set to a logic high level, and the counting of the edge transitions of the CK_C signal is restarted, and the count value is kept at ckptms.

[0082] Event 4: The logic control module input signal TRG2 has a falling edge transition.

[0083] Event 5: CKP2 falling edge transition occurs.

[0084] State 6: Increase tdcfsh by 1.

[0085] Decision 2: Whether the value of tdcfsh is equal to the preset value N.

[0086] State 7: When the first edge transition of CK_C arrives after the falling edge transition of CKP2 arrives, CKR1 is set to a logic high level; when the third edge transition of CK_C arrives, CKR1 is set to a logic low level; when the fourth edge transition of CK_C arrives, the logic control module output signal CKP1 is set to a logic high level, and the counting of the edge transitions of the CK_C signal is restarted, and the count value is kept at ckptms.

[0087] The different states in the two control modes are described as follows:

[0088] State 2: When in control mode 1, determine whether the edge transition count value ckptms reaches the preset value M. If it reaches, set CKP1 to a logic low level, stop ckptms from counting the edge transitions of CK_C, and clear the ckptms value. When in control mode 2, set CKP1 to a logic low level.

[0089] State 5: When in control mode 1, determine whether the edge transition count value ckptms reaches the preset value M. If it reaches, set CKP2 to a logic low level, stop ckptms from counting the edge transitions of CK_C, and clear the ckptms value. When in control mode 2, set CKP2 to a logic low level.

[0090] The working principle of the residual operation unit of the quantizer is as follows: when its RST_R signal is at a logic high level, the residual operation unit is in a reset state, and its output signals are all at a logic low level; when the RST_R signal is at a logic low level, the residual operation unit is in a working state. When the residual operation unit is in a working state, it first waits for the arrival of a single pulse on the input signals CKA and CKB. Assuming that the width of the single pulse on CKA is tA and that on CKB is tB; the residual operation unit records the width of these two pulses; after the pulse on CKP arrives, CKOA and CKOB are set to a logic high level. Assuming that the time difference between the arrival of the CKP pulse and the moment when CKOA becomes a logic high level is tOA, and the time difference between the moment when CKOB becomes a logic high level is tOB; then the residual operation unit will ensure that (tOB-tOA) is equal to 2 times (tA-tB). After both CKOA and CKOB become logic high levels, the residual operation unit will generate a pulse on its output TRES, and the pulse width is equal to 2 times (tA-tB).

[0091] The working principle of the time-to-digital converter of the quantizer is as follows: when its RST_T signal is at a logic high level, the time-to-digital converter is in a reset state, and its output signal DO is at a logic high level; when the RST_T signal is at a logic low level, the time-to-digital converter is in a working state. When the time-to-digital converter is in a working state, it will detect whether the states of the DI signal and the CK signal have changed to a logic high level, and compare the moments when the DI signal and the CK signal change to a logic high level. The CG signal is used to control the logic value of the final DO signal. If it is found that the CK signal has not changed to a logic high level when the state of the DI signal changes to a logic high level, if the CG signal is at a logic high level at this time, the DO signal is set to a logic high level, and if the CG signal is at a logic low level, the DO signal is set to a logic low level; if it is found that the DI signal has not changed to a logic high level when the state of the CK signal changes to a logic high level, if the CG signal is at a logic high level at this time, the DO signal is set to a logic low level, and if the CG signal is at a logic low level, the DO signal is set to a logic high level.

[0092] The working principle of the data selector of the quantizer is: when the S signal is at a logic high level, the B signal is mapped to the Y signal; when the S signal is at a logic low level, the A signal is mapped to the Y signal.

[0093] The working principle of the OR gate of the quantizer is: as long as any one of the A and B signals is at a logic high level, the Y signal is at a logic high level; otherwise, the Y signal is at a logic low level.

[0094] The working principle of the readout circuit is: when its RST_RO signal is at a logic high level, the readout circuit is in a reset state, and its output signals D0~DN are at a logic low level; when the RST_RO signal is at a logic low level, the readout circuit is in a working state. When the readout circuit is in a working state, DIN1 is transferred to D0 when the first CK1_RO falling edge jump arrives; DIN2 is transferred to D1 when the first CK2_RO falling edge jump arrives; DIN1 is transferred to D2 when the second CK1_RO falling edge jump arrives; DIN2 is transferred to D3 when the second CK2_RO falling edge jump arrives. And so on, N+1 output quantization codes are finally obtained.

[0095] The above are preferred embodiments of the present invention. Any changes made according to the technical solution of the present invention, as long as the resulting functions do not exceed the scope of the technical solution of the present invention, belong to the protection scope of the present invention.

Claims

1. A time-to-digital converter circuit, characterized in that: It includes a logic control module, a quantizer and a readout circuit connected in sequence; the time-to-digital converter circuit is used to output a data readable signal RDY and a quantization code D0-DN according to the input reset signal RST, the system clock CKS and the signal to be quantized TIN; specifically, The input end of the logic control module includes RST_C, CK_C, TIN_C, TRG1 and TRG2, and the output end includes STR, TIND, CKR1, CKR2, CKP1, CKP2 and RDY; wherein RST_C, CK_C and TIN_C respectively receive the input reset signal RST, system clock CKS and signal to be quantized TIN, TRG1 and TRG2 respectively receive the residual signal TRES1 and residual signal TRES2 of the quantizer TRES1 and TRES2, and the RDY end outputs the data readable signal RDY, and the other output ends output corresponding signals; The input end of the quantizer includes a STR_TR end, a TIN_TR end, a CKR1 end, a CKR2 end, a CKP1 end, a CKP2 end and a RST_TR end; the output end includes a TRES1 end, a TRES2 end, a TDC1 end and a TDC2 end; wherein the STR_TR end, the TIN_TR end, the CKR1 end, the CKR2 end, the CKP1 end, the CKP2 end and the RST_TR end receive signals from the STR end, the TIND end, the CKR1 end, the CKR2 end, the CKP1 end, the CKP2 end and the RDY end of the logic control module respectively, and the output end outputs corresponding signals; The input end of the readout circuit includes DIN1, DIN2, RST_RO, CK1_RO and CK2_RO; the output end includes D0-D N wherein the DIN1 terminal and the DIN2 terminal receive the signals of the quantizer TDC1 terminal and the TDC2 terminal respectively, the RST_RO terminal receives the input reset signal RST, the CK1_RO terminal and the CK2_RO terminal receive the CKP1 signal and the CKP2 signal of the logic control module CKP1 terminal and the CKP2 terminal respectively, and the output terminals D0-D N The ends output quantization codes D0-DN respectively.

2. A time-to-digital converter circuit according to claim 1, characterized in that: The quantizer includes a data selector, a first residual operation unit, a second residual operation unit, a first time-to-digital converter, a second time-to-digital converter, a first OR gate, and a second OR gate.

3. A time-to-digital converter circuit according to claim 2, characterized in that: For any residual operation unit of the first residual operation unit and the second residual operation unit: the input end includes a CKA end, a CKB end, a CKP end and a RST_R end, and the output end includes a CKOA end, a CKOB end and a TRES end; For any one of the first time-to-digital converter and the second time-to-digital converter: the input terminal includes the DI terminal, the CK terminal, the RST_T terminal and the CG terminal, and the output terminal is the DO terminal; The input terminals of the data selector include the A terminal, the B terminal and the S terminal, and the output terminal is the Y terminal; For any one of the first OR gate and the second OR gate: the input end includes the a end and the b end, and the output end is the y end; Among them, the STR_TR end of the quantizer corresponds to the data selector S end, the first time digital converter RST_T end and the second time digital converter RST_T end, the TIN_TR end of the quantizer corresponds to the data selector B end, the CKR1 end of the quantizer corresponds to the first residual operation unit CKB end and the a end of the second OR gate, the CKR2 end of the quantizer corresponds to the second residual operation unit CKB end and the a end of the first OR gate, the CKP1 end and the CKP2 end of the quantizer correspond to the first residual operation unit CKP end and the second residual operation unit CKP end respectively, and the RST_TR end of the quantizer corresponds to the first OR gate b end and the second OR gate b end; the TRES1 end, TRES2 end, TDC1 end and TDC2 end of the quantizer correspond to the first residual operation unit TRES end, the second residual operation unit TRES end, the first time digital converter DO end and the second time digital converter DO end respectively; The data selector A terminal receives the output signal of the second residual operation unit TRES terminal; The first residual operation unit CKA terminal receives the output signal of the data selector Y terminal, and the first residual operation unit RST_R terminal receives the output signal of the first OR gate y terminal; The second residual operation unit CKA terminal receives the output signal of the first residual operation unit TRES terminal, and the second residual operation unit RST_R terminal receives the output signal of the second OR gate y terminal; The first time-to-digital converter DI receives the output signal of the first residual operation unit CKOA, the first time-to-digital converter CK receives the output signal of the first residual operation unit CKOB, and the first time-to-digital converter CG receives the output signal of the second time-to-digital converter DO; The second time-to-digital converter DI receives the output signal of the second residual operation unit CKOA, the second time-to-digital converter CK receives the output signal of the second residual operation unit CKOB, and the second time-to-digital converter CG receives the output signal of the first time-to-digital converter DO.

4. The operating method of a time-to-digital converter circuit according to claim 3, characterized in that: The working method of the logic control module is as follows: After the system is reset, the logic control module is in a waiting state; if it is in the waiting state, when event 1 occurs, the working state jumps from the waiting state to state 1; if it is in state 1 or state 7, when event 2 occurs, it jumps to state 2; if it is in state 2, when event 3 occurs, it jumps from state 2 to state 3; if it is in state 3, it makes a decision on judgment 1, if it is true, it returns to the waiting state, if it is false, it jumps to state 4; if it is in state 4, when event 4 occurs, it jumps from state 4 to state 5; if it is in state 5, when event 5 occurs, it jumps from state 5 to state 6; if it is in state 6, it makes a decision on judgment 2, if it is true, it returns to the waiting state, if it is false, it jumps to state 7; Waiting state: when the reset signal RST input to the RST_C terminal of the logic control module is at a logic high level, the logic control module is in a reset state, the data readable signal RDY output from the RDY terminal is at a logic high level, and the output signals of the other output terminals are at a logic low level; when the reset signal RST input to the RST_C terminal is at a logic low level, the logic control module is in a working state. When the logic control module is in a working state, a value tdcfsh is set to record the number of edge transition events of the CKP1 signal and the CKP2 signal at the CKP1 and CKP2 terminals, the tdcfsh value is set to 0, and the data readable signal RDY at the RDY terminal is set to a logic high level; Event 1: The rising edge of the signal to be quantized TIN input to the logic control module TIN_C terminal jumps to the edge; State 1: After the rising edge of the signal to be quantified TIN jumps, the STR signal at the STR end of the logic control module is immediately set to a logic high level, and the RDY signal at the RDY end of the logic control module is set to a logic low level. After that, when the sixth edge jump of the system clock CKS input at the CK_C end of the logic control module arrives, the STR signal is set to a logic low level; the input signal to be quantified TIN is delayed by t ST1 After that, it is output to the TIND terminal; when the first edge transition of the system clock CKS arrives after the STR signal is at a logic high level, the CKR1 signal at the CKR1 terminal of the logic control module is set to a logic high level; when the third edge transition of the system clock CKS arrives, the CKR1 signal at the CKR1 terminal of the logic control module is set to a logic low level; when the sixth edge transition of the system clock CKS arrives, the CKP1 signal at the CKP1 terminal of the logic control module is set to a logic high level, and a value ckptms is set at the same time to record the number of edge transitions of the system clock CKS thereafter; Event 2: The residual signal TRES1 input to the logic control module TRG1 has a falling edge transition; Event 3: The falling edge of the CKP1 signal occurs; State 3: add 1 to tdcfsh; Judgment 1: Whether the value of tdcfsh is equal to the preset value N; State 4: When the first edge of the system clock CKS jumps after the falling edge of the CKP1 signal, the CKR2 signal at the CKR2 end is set to a logic high level; when the third edge of the system clock CKS jumps, the CKR2 signal is set to a logic low level; when the fourth edge of the system clock CKS jumps, the CKP2 signal is set to a logic high level, and the counting of the edge jumps of the system clock CKS is restarted, and the count value is kept at ckptms; Event 4: The residual signal TRES2 input to the logic control module TRG2 has a falling edge transition; Event 5: The falling edge of the CKP2 signal occurs; State 6: add 1 to tdcfsh; Judgment 2: Whether the value of tdcfsh is equal to the preset value N; State 7: When the first edge of the system clock CKS jumps after the falling edge of the CKP2 signal jumps, the CKR1 signal at the CKR1 end is set to a logic high level; when the third edge of the system clock CKS jumps, the CKR1 signal is set to a logic low level; when the fourth edge of the system clock CKS jumps, the CKP1 signal is set to a logic high level, and the counting of the edge jumps of the system clock CKS is restarted, and the count value is kept at ckptms; State 2 and state 5 adopt control mode 1 or control mode 2; When in control mode 1: State 2: Determine whether the edge transition count value ckptms reaches the preset value M. If so, set the CKP1 signal to a logic low level, stop ckptms from counting the edge transitions of the system clock CKS, and clear the ckptms value to zero. State 5: Determine whether the edge transition count value ckptms reaches the preset value M. If so, set the CKP2 signal to a logic low level, stop ckptms from counting the edge transitions of the system clock CKS, and clear the ckptms value; When in control mode 2: State 2: Set the CKP1 signal to a logic low level; State 5: Set the CKP2 signal to a logic low level.

5. The working method of a time-to-digital converter circuit according to claim 4, characterized in that: The input signal to be quantized TIN is delayed by t ST1 Then output to TIND terminal, delay time t ST1 No more than the system clock CKS period T S half.

6. The operating method of a time-to-digital converter circuit according to claim 3, characterized in that: For any residual operation unit in the first residual operation unit and the second residual operation unit, the working method is specifically as follows: When the RST_R signal at the RST_R terminal is at a logic high level, the residual operation unit is in a reset state, and the output signals at the output terminals are all at a logic low level; when the RST_R signal is at a logic low level, the residual operation unit is in a working state; When the residual operation unit is in working state, it first waits for the arrival of a single pulse on the CKA input signal and the CKB input signal, and after the arrival of the single pulse, records the single pulse width tA on the CKA input signal and the single pulse width tB on the CKB input signal; after the pulse of the CKP input signal arrives, the CKOA output signal and the CKOB output signal are set to a logic high level, the time difference between the arrival moment of the CKP input signal pulse and the moment when the CKOA output signal becomes a logic high level is tOA, and the time difference between the arrival moment of the CKP input signal pulse and the moment when the CKOB output signal becomes a logic high level is tOB, then the residual operation unit will ensure that (tOB-tOA) is equal to 2 times (tA-tB); after the CKOA output signal and the CKOB output signal both become a logic high level, the residual operation unit will generate a pulse with a width equal to 2(tA-tB) at the TRES end.

7. The operating method of a time-to-digital converter circuit according to claim 3, characterized in that: For any one of the first time-to-digital converter and the second time-to-digital converter, the working method is specifically as follows: When the input signal at the RST_T terminal is at a logic high level, the time digital converter is in a reset state, and the output signal at the DO terminal is at a logic high level; when the input signal at the RST_T terminal is at a logic low level, the time digital converter is in a working state; When the time-to-digital converter is in working state, it will detect whether the states of the DI input signal and the CK input signal are transformed into a logic high level, and compare the moments when the DI input signal and the CK input signal are transformed into a logic high level; the CG input signal is used to control the logic value of the final DO output signal: If the CK input signal has not yet changed to a logic high level when the DI input signal changes to a logic high level, if the CG input signal is a logic high level at this time, the DO output signal is set to a logic high level; if the CG input signal is a logic low level, the DO output signal is set to a logic low level; If it is found that the DI input signal has not changed to a logic high level when the CK input signal changes to a logic high level, if the CG input signal is a logic high level at this time, the DO output signal is set to a logic low level; if the CG input signal is a logic low level, the DO output signal is set to a logic high level.

8. The operating method of a time-to-digital converter circuit according to claim 3, characterized in that: The working method of the data selector is as follows: When the S-terminal input signal is at a logic high level, the B-terminal input signal is mapped to the Y-terminal output signal; when the S-terminal input signal is at a logic low level, the A-terminal input signal is mapped to the Y-terminal output signal.

9. The operating method of a time-to-digital converter circuit according to claim 3, characterized in that: For any one of the first OR gate and the second OR gate, the working method is as follows: As long as any one of the input signals at the a-end and the b-end is at a logic high level, the output signal at the y-end is at a logic high level; otherwise, the output signal at the y-end is at a logic low level.

10. The working method of a time-to-digital converter circuit according to claim 3, characterized in that: The working method of the readout circuit is specifically as follows: When the reset signal RST input at the RST_RO terminal is at a logic high level, the readout circuit is in a reset state, and D0-D N When the quantization code D0-DN outputted by the terminal is at a logic low level; when the reset signal RST inputted at the RST_RO terminal is at a logic low level, the readout circuit is in working state; When the readout circuit is in working state; if N is an odd number; when the nth falling edge of the CKP1 signal input at the CK1_RO terminal jumps, the DIN1 terminal input signal is transmitted to D 2n-2 terminal, where n = 1, 2, ..., (N + 1) / 2; when the mth falling edge of the CKP2 signal input at the CK2_RO terminal arrives, the input signal at the DIN2 terminal is transmitted to the D 2m-1 terminal, where m = 1, 2, ..., (N + 1) / 2; if N is an even number; when the nth falling edge of the CKP1 signal input at the CK1_RO terminal arrives, the DIN1 terminal input signal is transmitted to D 2n-2 terminal, where n = 1, 2, ..., (N + 2) / 2; when the mth falling edge of the CKP2 signal input at the CK2_RO terminal arrives, the DIN2 terminal input signal is transmitted to D 2m-1 end, where m = 1, 2, ..., N / 2; and finally N+1 output quantization codes D0-DN are obtained.

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