Chip verification method, device, electronic device and storage medium

Abstract

The present invention discloses a chip verification method, device and storage medium. The method comprises: pre-configuring a base class function of the SV language in the verification framework, the base class function is used to describe the verification process; pre-configuring a C language program in the verification framework, the C language program is used to perform hardware calculations of the processor; obtaining the number of test cycles and verification parameters through the virtual function of the base class function of the SV language; within each test cycle, writing the verification parameters to a shared storage area through a virtual function, and sharing the verification parameters to the C language program through the shared storage area; the C language program controls the processor hardware to complete the verification calculation according to the verification parameters, and writes the calculation results to the shared storage area. Verification engineers can write test cases according to the same set of standards, which improves the efficiency of chip verification.

Description

Technical Field

[0001] The present invention belongs to the field of chip technology, and in particular to the field of system-level verification of a system-on-chip (Soc) of a digital semiconductor IC, and specifically to a chip verification method, device, electronic equipment and storage medium. Background Art

[0002] With the development of chip technology, system-on-chip (SoC) in the field of digital integrated circuit (IC) has been widely used. The functions of SoC are becoming more and more abundant, and the verification of SoC is becoming more and more complicated.

[0003] At present, when verifying the system-level chip, engineers of different projects edit the verification code required for their own projects to verify the system-level chip. How to improve the verification efficiency of the project in the system-level chip has become an urgent problem to be solved. Summary of the invention

[0004] The purpose of the present invention is to provide a chip verification method, device, electronic device and storage medium, which can improve the verification efficiency of system-level chip projects.

[0005] According to a first aspect of the present invention, there is provided a chip verification method, comprising:

[0006] Pre-configuring a base class function of the SV language in the verification framework, the base class function is used to describe the verification process; pre-configuring a C language program in the verification framework, the C language program is used to execute hardware calculations of the processor;

[0007] Obtain the number of test cycles and verification parameters through the virtual function of the base class function of the SV language;

[0008] In each test cycle, the verification parameters are written into a shared storage area through a virtual function, and the verification parameters are shared with a C language program through the shared storage area; the C language program controls the processor hardware to complete the verification calculation according to the verification parameters, and writes the calculation results into the shared storage area.

[0009] According to a second aspect of the present invention, there is provided a chip verification device, comprising:

[0010] An architecture configuration module, used to pre-configure a base class function of the SV language in the verification framework, the base class function is used to describe the verification process; pre-configure a C language program in the verification framework, the C language program is used to execute hardware calculations of the processor;

[0011] A verification parameter acquisition module, used to obtain the number of test cycles and verification parameters through the virtual function of the base class function of the SV language;

[0012] The verification module is used to write the verification parameters into a shared storage area through a virtual function within each test cycle, and share the verification parameters with a C language program through the shared storage area; the C language program controls the processor hardware to complete the verification calculation according to the verification parameters, and writes the calculation results into the shared storage area.

[0013] According to a third aspect of the present invention, there is provided an electronic device, the electronic device comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor so that the at least one processor can perform the chip verification method described in any embodiment.

[0017] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the chip verification method described in any embodiment of the present invention when executed.

[0018] The technical solution provided by the present invention is to pre-configure the base class function of the SV language in the verification framework, and the base class function is used to describe the verification process; pre-configure the C language program in the verification framework, and the C language program is used to execute the hardware calculation of the processor; obtain the test cycle number and verification parameters through the virtual function of the base class function of the SV language; in each test cycle number, write the verification parameter into the shared storage area through the virtual function, and share the verification parameter with the C language program through the shared storage area; the C language program controls the processor hardware to complete the verification calculation according to the verification parameter, and writes the calculation result into the shared storage area. Compared with the current verification required by different projects, which is independent of each other and verification engineers write the verification code of their own projects, the present invention proposes a new verification framework, in which the base class function of the SV language is pre-configured, and when verification of different projects is required, the test cycle number and verification parameters are obtained through the virtual function of the base function; in each test cycle number, write the verification parameter into the shared storage area through the virtual function, and share the verification parameter with the C language program through the shared storage area. When verifying different projects, the present invention only requires verification engineers to make corresponding modifications in virtual functions according to their own needs to complete the verification of the project. Verification engineers can write test cases following the same set of standards, which reduces the difficulty of understanding and modifying other people's codes and improves chip verification efficiency.

[0019] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a schematic diagram of a chip verification method provided by an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of the interaction between the C language and the SV language provided in an embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of the structure of a chip verification device provided by an embodiment of the present invention;

[0024] Figure 4 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] With the development of chip technology, system-on-chip (SoC) in the field of digital integrated circuit (IC) has been widely used. The functions of SoC are becoming more and more abundant, and the verification of SoC is becoming more and more complicated.

[0028] At present, when verifying the system-level chip, engineers of different projects edit the verification code required for their own projects to verify in the system-level chip. Due to the lack of a unified verification architecture, different engineers will edit the verification code according to their own programming. As a result, other engineers cannot reuse the verification code, resulting in each engineer needing to edit the verification code by themselves, which leads to low verification efficiency. How to improve the verification efficiency of projects in the system-level chip has become an urgent problem to be solved.

[0029] Figure 1 : is a flow chart of a chip verification method provided by an embodiment of the present invention. This embodiment is applicable to the case of verifying a program project applied to a system-level chip. The method can be executed by a chip verification device, which can be implemented in the form of hardware and / or software. The method includes:

[0030] Step S101 : pre-configure a base class function of the SV language in a verification framework, wherein the base class function is used to describe a verification process; and pre-configure a C language program in the verification framework.

[0031] The verification framework provided by the embodiment of the present invention includes a base class function of the SV language (SystemVer.log) and a C language program. The C language program is used to perform hardware calculations of the processor. The C language program controls the operation of the processor by calling C language instructions. The processor can be a central processing unit (CPU) adapted to the C language.

[0032] SV language (SystemVer.log, SV) is a hardware description language (Hardware Description Language, HDL) based on Ver.log language. Each base class function of SV language is used to define different processes in the verification process. The combination of multiple base class functions realizes the standardized verification process. When verifying different projects, they can be divided into verification processes corresponding to base class functions. Step S101 implements the definition of base class functions and the editing of C language programs by pre-configuring the verification framework. When verifying the project later, all the functions of the base class function can be inherited by constructing a virtual function of the base class function. On this basis, the verification engineer edits the parameters in the virtual function according to the actual needs of the project, and the verification of the project can be realized by calling the edited virtual function. There is no need for the verification engineer to edit the entire set of verification code.

[0033] Optionally, the base class function of the SV language in the pre-configured verification framework can be implemented in the following way:

[0034] A first base class function of the SV language is configured, wherein the first base class function is used to obtain the number of test cycles. A first process of the SV language is created, wherein the first process is used to control the cycle verification.

[0035] The first process includes a second base class function, a third base class function and a fourth base class function; the second base class function is used to obtain verification parameters and write the verification parameters to a second address interval of a shared storage area; the third base class function is used to write a first identifier to a first address interval of a shared storage area after the second base class function is executed; the fourth base class function is used to simulate process control and read data returned to the first address area by a C language program within a configured time; if the data in the first address area is a second identifier, it is determined that the execution of the C language program is terminated.

[0036] The shared storage area is a storage area shared by the SV language and the C language. The storage area is divided into multiple address areas. Different address areas store different identifiers to facilitate orderly project verification.

[0037] Through the definition of the above base class function, the functions of different processes in project verification can be defined in the base class function. When performing verification later, the functions of the base class function can be used by creating a virtual function of the base class function, avoiding repeated editing by verification engineers and improving project verification efficiency.

[0038] Furthermore, in the above implementation, writing the verification parameter into the second address interval of the shared storage area may be implemented as follows:

[0039] Acquire second address information of the second address interval; and write the verification parameter into the second address interval of the shared storage area according to the second address information.

[0040] Correspondingly, writing the first identifier into the first address interval of the shared storage area can be implemented as follows: obtaining first address information of the first address interval; and writing the verification parameter into the second address interval of the shared storage area according to the first address information.

[0041] The above implementation method can directly write the first identifier or verification parameter into the second address interval through the backdoor without converting the physical address, thereby realizing fast writing of the first identifier or verification parameter and improving the verification efficiency of the project.

[0042] Optionally, the C language program in the pre-configured verification framework can be implemented in the following way:

[0043] Configure the C language program, and the C language program is used to control the processor to execute the following steps: continuously monitor whether the data in the first address interval is a first identifier; if it is the first identifier, read the verification parameters in the second address interval, and perform verification calculations based on the verification parameters; write the calculation results into the second address interval; write the second identifier into the first address interval.

[0044] The C language program determines whether to read the verification parameters in the second address interval based on the first identifier in the first address interval. If the data in the first address interval is the first identifier, it means that the SV program has written the verification parameters to the second address interval. The C language reads the data in the second address interval as the verification parameter, calls the C language function to control the CPU to perform calculations, and obtains the calculation results. The calculation results are written to the second address interval. The second identifier is written to the first address interval. The fourth base class function of the SV program reads the data returned to the second address area by the C language program within the configuration time; if the data in the second address area is the second identifier, it is determined that the execution of the C language program has ended.

[0045] The above implementation method can realize data interaction between SV language program and C language program based on the address area shared by SV language and C language, which not only saves storage space but also improves data interaction failure and accuracy.

[0046] Step S102: Obtain the number of test cycles and verification parameters through the virtual function of the base class function of the SV language.

[0047] Step S101 preconfigures the base class function of the SV language. When performing project verification, the verification engineer does not need to edit the base class function, but creates a virtual function of the base class function. By calling the virtual function and configuring the parameters in the virtual function, the editing of the project verification process can be achieved. The above process does not require the verification engineer to edit the logic in the base class function, so it can simplify the workload of the verification engineer and improve the verification efficiency.

[0048] Optionally, obtaining the number of test cycles and verification parameters through the virtual function of the base class function of the SV language can be implemented in the following way:

[0049] Create a virtual function of the first base class function, and configure the number of loops through the virtual function of the first base class function. Create a virtual function of the second base class function, and configure verification parameters through the virtual function of the second base class function. Create a virtual function of the fourth base class function, and read the calculation result of the verification from the second address interval through the virtual function of the fourth base class function, and configure the comparison rule corresponding to the calculation result.

[0050] The verification engineer configures the number of loops through the virtual function of the first base class function. The verification parameters are configured through the virtual function of the second base class function. The calculation result of the verification is read from the second address interval by calling the virtual function of the fourth base class function, and further comparison rules and verification processes are configured based on the calculation result. The configuration is performed in the virtual function according to the own needs to complete the configuration that meets the project verification requirements.

[0051] The above implementation method can complete the acquisition and interaction of the number of loops, verification parameters and calculation results through the virtual functions of the base class functions, so that verification engineers can quickly complete the configuration and improve the project verification efficiency.

[0052] Step S103: In each test cycle, the verification parameters are written into a shared storage area through a virtual function, and the verification parameters are shared with a C language program through the shared storage area. The C language program controls the processor hardware to complete the verification calculation according to the verification parameters, and writes the calculation results into the shared storage area.

[0053] Furthermore, based on the above implementation, the C language program is also used to store the printing information generated during the execution process into a third address interval of the shared storage area.

[0054] Correspondingly, after creating the first process of the SV language, it also includes: creating a second process of the SV language, the second process is used to read the printing information in the third address interval of the shared storage area, the printing information includes test progress information; configuring the fifth base class function of the SV language, the fifth base class function is used to print the read printing information.

[0055] In the above implementation, the fifth base class function can provide information printing for the third address range. By pre-configuring the fifth base class function, a quick result printing function can be provided for verification engineers.

[0056] Furthermore, after obtaining the number of test cycles and verification parameters through the virtual function of the base class function of the SV language, it also includes:

[0057] A virtual function of the fifth base class function is created, and the output of the simulation calculation result is configured through the virtual function of the fifth base class function.

[0058] Verification engineers can implement the output of calculation results by creating a virtual function of the fifth base class function.

[0059] Figure 2 Schematic diagram of the interaction between C language and SV language provided for an embodiment of the present invention. Exemplarily, SV first process: create a virtual function preloop of the first base class function, which is used to obtain the number of loops with C language and various verification parameters required for verification. SV second process: use SV statement (fork...join_any) to create two parallel processes, the first process cfg_op and the second process wa.t_msg.

[0060] The second process wait_msg is used to read the print information in the third address interval Buffer3 of the shared storage area. The print information may be the print information of the C language program, which is used to indicate the processing progress of the C language.

[0061] The first process cfg_op is used to execute the for loop, and the number of loops is defined by the verification engineer in the virtual function pre_loop of the first base class function. The for loop creates the virtual function preop of the second base class function, the virtual function op of the third base class function, and the virtual function post_op of the fourth base class function, a total of three virtual functions executed serially.

[0062] The virtual function pre_op of the second base class function is used to obtain the verification parameters prepared by the virtual function pre_loop of the first base class function through the SV language and write them into the second address interval Buffer2 of the shared storage area. The virtual function op of the third base class function is used to write the first identifier, such as "32′h5555", into the first address interval Buffer1 of the shared storage area through the SV language. The virtual function post_op of the fourth base class function is used to create the second identifier wait_label. The second identifier wait_label, such as "32′haaaa", is used for simulation process control. Specifically, the virtual function post_op of the fourth base class function reads the second identifier wait_label returned by the C language program to the first address interval Buffer1 within the configuration time, and determines whether the C program has been executed based on whether the data is "32′haaaa". The timing function c_exe_cnt is a while loop used to print the time waiting for 32′haaaa to be read. The timing function is included in the SV language in the verification framework and is used for timing. So that the virtual function post_op of the fourth type of function compares the timing result of the timing function with the configuration time, and realizes reading the second identifier wait_label of the first address interval Buffer1 returned to the C language program within the configuration time.

[0063] Correspondingly, the C language execution process based on the shared memory area includes three processes.

[0064] CPU first process: CPU first process is used to read the synchronization flag. The CPU reads the first mark in the first address interval Buffer1 in a loop until the first mark read is "32′h5555" and then stops. When the first mark is read, it means that the data SV has prepared the data required for C language execution, that is, the verification parameter data has been written to the second address interval Buffer2 of the shared storage area. Then, the CPU starts to execute data reading and instruction execution.

[0065] CPU second process: CPU second process is used to execute instructions. After the CPU reads the verification parameters from the second address interval Buffer2 address, it starts to execute the instruction operation according to the supervised data. Then, the result data generated by the operation is written to the second address interval Buffer2 address. In addition, the CPU can also write the printing information generated during the operation to the third address interval Buffer3 address.

[0066] CPU third process: CPU third process is used to rewrite the synchronization flag. The CPU writes the second identifier, such as "32′haaaa", into the first address interval Buffer1. This indicates that the verification parameters given by SV have been calculated and the data in the second address interval Buffer2 can be read. Correspondingly, the virtual function post_op of the fourth base class function continuously reads the first address interval Buffer1 of the shared storage area until the flag data read is the second identifier, such as "32′haaaa". Then, based on the calculation result in the second address interval Buffer2 of the shared storage area, the calculation result read is verified. Determine whether the calculation result in this cycle meets expectations. When the data verification is completed, the number of loops is reduced by 1, and the virtual function pre_op that executes the second base class function is returned. If the number of loops is greater than 0, the virtual function pre_op that executes the second base class function is returned. If the number of loops is equal to zero, the test ends.

[0067] In addition, there is a third SV process, which creates a virtual function post_loop of the fifth base class function, which is used to read the printing information in the third address interval of the shared storage area and print out the read printing information. The printing can be displayed on the screen.

[0068] In the above implementation, step S101 pre-configures the base class function in the verification framework. When performing project verification, the verification programmer only needs to perform the following steps to complete the project verification:

[0069] Step 1: Call the virtual function pre_loop of the first base class function through the inherited subclass method, and modify the number of loops and verification parameters according to the functional scenario.

[0070] Step 2: Call the virtual function pre_op of the second base class function by means of inherited subclasses, and write the verification parameters of the functional scenario into the second address interval buffer2 of the shared storage area according to the functional scenario.

[0071] Step 3: Call the virtual function post_op of the fourth base class function through the inherited subclass method, and read the execution result from the third address interval buffer3 of the shared storage area for comparison.

[0072] Step 4: By means of inherited subclasses, call the virtual function post_loop of the fifth base class function and print the simulation result information according to the functional scenario expansion.

[0073] The chip verification method provided by the present invention pre-configures the base class function of the SV language in the verification framework, and the base class function is used to describe the verification process; pre-configures the C language program in the verification framework, and the C language program is used to execute the hardware calculation of the processor; obtains the test cycle number and verification parameters through the virtual function of the base class function of the SV language; in each test cycle number, the verification parameter is written into the shared storage area through the virtual function, and the verification parameter is shared with the C language program through the shared storage area; the C language program controls the processor hardware to complete the verification calculation according to the verification parameter, and writes the calculation result into the shared storage area. Compared with the current verification required by different projects, which is independent of each other and verification engineers write the verification code of their own projects, the present invention proposes a new verification framework, in which the base class function of the SV language is pre-configured, and when verification of different projects is required, the test cycle number and verification parameters are obtained through the virtual function of the base function; in each test cycle number, the verification parameter is written into the shared storage area through the virtual function, and the verification parameter is shared with the C language program through the shared storage area. When verifying different projects, the present invention only requires verification engineers to make corresponding modifications in virtual functions according to their own needs to complete the verification of the project. Verification engineers can write test cases following the same set of standards, which reduces the difficulty of understanding and modifying other people's codes and improves chip verification efficiency.

[0074] The chip verification method provided by the present invention, in the SoC system verification environment, only needs to read and write the data of the second address interval Buffer2 according to the functional scenario based on the verification framework, and control the parameters of the number of interactions between the SV language program and the C language program according to the functional scenario. The functional scenario configuration parameters can be randomized by the SV language program and then passed to the C language program, and the C language program is configured according to the verification scenario. In addition, based on the verification architecture, the print information of the C program can be placed in the third address interval Buffer3, and the information of the third address interval Buffer3 can be read by the SV language program to determine the running progress of the C program, which is helpful to locate the bugs in the simulation. Through the architecture of the present invention, the verification engineer does not need to understand the identification content of the interaction between SV and C. The verification engineers of different projects all create corresponding virtual functions based on the base class functions provided by the pre-configured verification architecture, configure the verification process through the virtual functions according to the project verification requirements, expand the corresponding functions, and speed up the SoC verification progress. Using a set of configured verification frameworks can provide verification for different projects and improve verification efficiency.

[0075] As a further illustration of the above embodiment, the embodiment of the present invention also provides a chip verification method, including:

[0076] Step 201: configure a first base class function of the SV language, where the first base class function is used to obtain the number of test cycles;

[0077] Step 202: Create a first process in SV language, where the first process is used to control loop verification;

[0078] Step 203, the first process includes a second base class function, a third base class function and a fourth base class function; the second base class function is used to obtain verification parameters and write the verification parameters to the second address interval of the shared storage area; the third base class function is used to write a first identifier to the first address interval of the shared storage area after the second base class function is executed; the fourth base class function is used to simulate process control, and read the data returned to the second address area by the C language program within the configuration time; if the data in the second address area is the second identifier, it is determined that the execution of the C language program is completed.

[0079] The step of writing the verification parameter into the second address interval of the shared storage area may be implemented as follows: obtaining second address information of the second address interval; and writing the verification parameter into the second address interval of the shared storage area according to the second address information.

[0080] Writing the first identifier into the first address interval of the shared storage area may be implemented by: acquiring first address information of the first address interval; and writing the verification parameter into the second address interval of the shared storage area according to the first address information.

[0081] Step 204, configure the C language program, and the C language program is used to control the processor to execute the following steps: continuously monitor whether the data in the first address interval is a first identifier; if it is a first identifier, read the verification parameters in the second address interval, and perform verification calculations based on the verification parameters; write the calculation results into the second address interval; write the second identifier into the first address interval.

[0082] Step 205: Create a second process of the SV language, the second process is used to read the print information in the third address interval of the shared storage area, the print information includes the test progress information, and configure the fifth base class function of the SV language, the fifth base class function is used to print the read print information.

[0083] The C language program is also used to store the printing information generated during the execution process into the third address interval of the shared storage area.

[0084] Step 206, create a virtual function of the first base class function, and configure the number of loops through the virtual function of the first base class function; create a virtual function of the second base class function, and configure verification parameters through the virtual function of the second base class function; create a virtual function of the fourth base class function, and read the verified calculation result from the second address interval through the virtual function of the fourth base class function, and configure the comparison rules corresponding to the calculation result.

[0085] Step 207: In each test cycle, the verification parameters are written into a shared storage area through a virtual function, and the verification parameters are shared with a C language program through the shared storage area; the C language program controls the processor hardware to complete the verification calculation according to the verification parameters, and writes the calculation results into the shared storage area.

[0086] Step 208: Create a virtual function of the fifth base class function, and read the process information in the third address interval through the virtual function of the fifth base class function for output.

[0087] Figure 3 This is a schematic diagram of the structure of a chip verification device provided by an embodiment of the present invention. The chip verification device is used to implement the above chip verification method, including: an architecture configuration module 31, a verification parameter acquisition module 32 and a verification module 33.

[0088] The architecture configuration module 31 is used to pre-configure the base class function of the SV language in the verification framework, the base class function is used to describe the verification process; pre-configure the C language program in the verification framework, the C language program is used to execute the hardware calculation of the processor;

[0089] A verification parameter acquisition module 32, used to obtain the number of test cycles and verification parameters through the virtual function of the base class function of the SV language;

[0090] The verification module 33 is used to write the verification parameters into a shared storage area through a virtual function within each test cycle, and share the verification parameters with a C language program through the shared storage area; the C language program controls the processor hardware to complete the verification calculation according to the verification parameters, and writes the calculation results into the shared storage area.

[0091] Based on the above implementation, optionally, the architecture configuration module 31 is used to pre-configure the base class function of the SV language in the verification framework, including:

[0092] Configure a first base class function of the SV language, wherein the first base class function is used to obtain the number of test cycles;

[0093] Creating a first process of the SV language, the first process being used for controlling loop verification;

[0094] The first process includes a second base class function, a third base class function and a fourth base class function; the second base class function is used to obtain verification parameters and write the verification parameters to a second address interval of a shared storage area; the third base class function is used to write a first identifier to a first address interval of a shared storage area after the second base class function is executed; the fourth base class function is used to simulate process control and read data returned to the second address area by the C language program within a configured time; if the data in the second address area is a second identifier, it is determined that the execution of the C language program is terminated.

[0095] Based on the above implementation, optionally, the architecture configuration module 31 is used to pre-configure the C language program in the verification framework, including:

[0096] Configure the C language program, and the C language program is used to control the processor to execute the following steps: continuously monitor whether the data in the first address interval is a first identifier; if it is the first identifier, read the verification parameters in the second address interval, and perform verification calculations based on the verification parameters; write the calculation results into the second address interval; write the second identifier into the first address interval.

[0097] Based on the above implementation, optionally, the architecture configuration module 31 is used to write the verification parameter into the second address interval of the shared storage area, including:

[0098] Acquire second address information of a second address interval;

[0099] Writing the verification parameter into a second address interval of the shared storage area according to the second address information;

[0100] The architecture configuration module 31 is used to write a first identifier into a first address interval of a shared storage area, including:

[0101] Acquire first address information of a first address interval;

[0102] The verification parameter is written into a second address interval of the shared storage area according to the first address information.

[0103] Based on the above implementation, optionally, the C language program is further used to store the printing information generated during the execution process into a third address interval of the shared storage area;

[0104] The device further comprises a printing module, which is used to create a second process in the SV language after creating the first process in the SV language, wherein the second process is used to read printing information in a third address interval of the shared storage area, wherein the printing information comprises test progress information;

[0105] A fifth base class function of the SV language is configured, wherein the fifth base class function is used to print the read printing information.

[0106] On the basis of the above implementation, optionally, the verification parameter acquisition module 32 is used to obtain the number of test cycles and verification parameters through the virtual function of the base class function of the SV language, including:

[0107] Create a virtual function of the first base class function, and configure the number of loops through the virtual function of the first base class function;

[0108] Creating a virtual function of the second base class function, and configuring verification parameters through the virtual function of the second base class function;

[0109] A virtual function of the fourth base class function is created, a verified calculation result is read from the second address interval through the virtual function of the fourth base class function, and a comparison rule corresponding to the calculation result is configured.

[0110] Based on the above implementation, optionally, an output module is also included, which is used to create a virtual function of the fifth base class function after obtaining the number of test cycles and verification parameters through the virtual function of the base class function of the SV language, and configure the output of the simulation calculation results through the virtual function of the fifth base class function.

[0111] The chip verification device provided by the present invention includes an architecture configuration module 31, which is used to pre-configure the base class function of the SV language in the verification framework, and the base class function is used to describe the verification process; the C language program in the verification framework is pre-configured, and the C language program is used to execute the hardware calculation of the processor; the verification parameter acquisition module 32 is used to obtain the test cycle number and verification parameters through the virtual function of the base class function of the SV language; the verification module 33 is used to write the verification parameters into the shared storage area through the virtual function in each test cycle, and share the verification parameters with the C language program through the shared storage area; the C language program controls the processor hardware to complete the verification calculation according to the verification parameters, and writes the calculation results into the shared storage area. Compared with the current verification required by different projects being independent of each other, and verification engineers each writing the verification code of their own projects, the present invention proposes a new verification framework, in which the base class function of the SV language is pre-configured, and when verification of different projects is required, the test cycle number and verification parameters are obtained through the virtual function of the base function; in each test cycle number, the verification parameters are written into the shared storage area through the virtual function, and the verification parameters are shared with the C language program through the shared storage area. When verifying different projects, the present invention only requires verification engineers to make corresponding modifications in virtual functions according to their own needs to complete the verification of the project. Verification engineers can write test cases following the same set of standards, which reduces the difficulty of understanding and modifying other people's codes and improves chip verification efficiency.

[0112] The chip verification device provided in the embodiment of the present invention can execute the chip verification method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0113] Figure 4 1 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. The electronic device 10 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0114] like Figure 4 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0115] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0116] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a chip verification method.

[0117] In some embodiments, the chip verification method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the chip verification method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the chip verification method in any other appropriate manner (e.g., by means of firmware).

[0118] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0119] The computer program for implementing the chip verification method of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0120] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions can be used to enable a processor to execute a chip verification method, wherein the method includes:

[0121] Pre-configuring a base class function of the SV language in the verification framework, the base class function is used to describe the verification process; pre-configuring a C language program in the verification framework, the C language program is used to execute hardware calculations of the processor;

[0122] Obtain the number of test cycles and verification parameters through the virtual function of the base class function of the SV language;

[0123] In each test cycle, the verification parameters are written into a shared storage area through a virtual function, and the verification parameters are shared with a C language program through the shared storage area; the C language program controls the processor hardware to complete the verification calculation according to the verification parameters, and writes the calculation results into the shared storage area.

[0124] Based on the above implementation, optionally, the base class function of the SV language in the verification framework is pre-configured, including:

[0125] Configure a first base class function of the SV language, wherein the first base class function is used to obtain the number of test cycles;

[0126] Creating a first process of the SV language, the first process being used for controlling loop verification;

[0127] The first process includes a second base class function, a third base class function and a fourth base class function; the second base class function is used to obtain verification parameters and write the verification parameters to a second address interval of a shared storage area; the third base class function is used to write a first identifier to a first address interval of a shared storage area after the second base class function is executed; the fourth base class function is used to simulate process control and read data returned to the second address area by the C language program within a configured time; if the data in the second address area is a second identifier, it is determined that the execution of the C language program is terminated.

[0128] Based on the above implementation, optionally, a C language program in the pre-configuration verification framework includes:

[0129] Configure the C language program, and the C language program is used to control the processor to execute the following steps: continuously monitor whether the data in the first address interval is a first identifier; if it is the first identifier, read the verification parameters in the second address interval, and perform verification calculations based on the verification parameters; write the calculation results into the second address interval; write the second identifier into the first address interval.

[0130] Based on the above implementation, optionally, writing the verification parameter into the second address interval of the shared storage area includes:

[0131] Acquire second address information of a second address interval;

[0132] Writing the verification parameter into a second address interval of the shared storage area according to the second address information;

[0133] Writing a first identifier into a first address interval of a shared storage area includes:

[0134] Acquire first address information of a first address interval;

[0135] The verification parameter is written into a second address interval of the shared storage area according to the first address information.

[0136] Based on the above implementation, optionally, the C language program is further used to store the printing information generated during the execution process into a third address interval of the shared storage area;

[0137] Accordingly, after creating the first process of the SV language, it also includes:

[0138] Creating a second process in SV language, the second process is used to read the print information in the third address interval of the shared storage area, the print information including the test progress information;

[0139] A fifth base class function of the SV language is configured, wherein the fifth base class function is used to print the read printing information.

[0140] On the basis of the above implementation, optionally, obtaining the number of test cycles and verification parameters through a virtual function of the base class function of the SV language includes:

[0141] Create a virtual function of the first base class function, and configure the number of loops through the virtual function of the first base class function;

[0142] Creating a virtual function of the second base class function, and configuring verification parameters through the virtual function of the second base class function;

[0143] A virtual function of the fourth base class function is created, a verified calculation result is read from the second address interval through the virtual function of the fourth base class function, and a comparison rule corresponding to the calculation result is configured.

[0144] Based on the above implementation, optionally, after obtaining the number of test cycles and verification parameters through the virtual function of the base class function of the SV language, it also includes:

[0145] A virtual function of the fifth base class function is created, and the output of the simulation calculation result is configured through the virtual function of the fifth base class function.

[0146] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0147] To provide interaction with a verification engineer, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the verification engineer; and a keyboard and a pointing device (e.g., a mouse or trackball), through which the verification engineer can provide input to the electronic device. Other types of devices may also be used to provide interaction with the verification engineer; for example, the feedback provided to the verification engineer may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and the input from the verification engineer may be received in any form (including acoustic input, voice input, or tactile input).

[0148] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a verification engineer can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0149] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0150] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0151] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip verification method, characterized in that: include: Pre-configure a base class function of the SV language in the verification framework, wherein the base class function is used to describe the verification process; Pre-configure a C language program in the verification framework, wherein the C language program is used to perform hardware calculations of the processor; Obtain the number of test cycles and verification parameters through the virtual function of the base class function of the SV language; In each test cycle, the verification parameters are written into a shared storage area through a virtual function, and the verification parameters are shared with a C language program through the shared storage area; the C language program controls the processor hardware to complete the verification calculation according to the verification parameters, and writes the calculation results into the shared storage area.

2. The method according to claim 1, characterized in that The base class functions of the SV language in the pre-configured verification framework include: Configure a first base class function of the SV language, wherein the first base class function is used to obtain the number of test cycles; Creating a first process of the SV language, the first process being used for controlling loop verification; The first process includes a second base class function, a third base class function and a fourth base class function; the second base class function is used to obtain verification parameters and write the verification parameters to a second address interval of a shared storage area; the third base class function is used to write a first identifier to a first address interval of a shared storage area after the second base class function is executed; the fourth base class function is used to simulate process control and read data returned to the first address area by a C language program within a configured time; if the data in the first address area is a second identifier, it is determined that the execution of the C language program is terminated.

3. The method according to claim 2, characterized in that C language programs in the pre-configured verification framework include: Configure the C language program, and the C language program is used to control the processor to execute the following steps: continuously monitor whether the data in the first address interval is the first identifier; if it is the first identifier, read the verification parameters in the second address interval, and perform verification calculations based on the verification parameters; write the calculation results into the second address interval; write the second identifier into the first address interval.

4. The method according to claim 2, characterized in that: Writing the verification parameters to the second address interval of the shared storage area includes: Acquire second address information of a second address interval; Writing the verification parameter into the second address interval of the shared storage area according to the second address information; and writing the first identifier into the first address interval of the shared storage area include: Acquire first address information of a first address interval; The verification parameter is written into a second address interval of the shared storage area according to the first address information.

5. The method according to claim 3, characterized in that: The C language program is also used to store the printing information generated during the execution process into a third address interval of the shared storage area; Accordingly, after creating the first process of the SV language, it also includes: Creating a second process in SV language, the second process is used to read the print information in the third address interval of the shared storage area, the print information including the test progress information; A fifth base class function of the SV language is configured, wherein the fifth base class function is used to print the read printing information.

6. The method according to claim 3, characterized in that The number of test cycles and verification parameters are obtained through the virtual function of the base class function of the SV language, including: Create a virtual function of the first base class function, and configure the number of loops through the virtual function of the first base class function; Creating a virtual function of the second base class function, and configuring verification parameters through the virtual function of the second base class function; A virtual function of the fourth base class function is created, a verified calculation result is read from the second address interval through the virtual function of the fourth base class function, and a comparison rule corresponding to the calculation result is configured.

7. The method according to claim 5, characterized in that After obtaining the test cycle number and verification parameters through the virtual function of the base class function of the SV language, it also includes: A virtual function of the fifth base class function is created, and the output of the simulation calculation result is configured through the virtual function of the fifth base class function.

8. A chip verification device, characterized in that: include: An architecture configuration module, used for pre-configuring a base class function of the SV language in the verification framework, wherein the base class function is used for describing a verification process; Pre-configure a C language program in the verification framework, wherein the C language program is used to perform hardware calculations of the processor; A verification parameter acquisition module, used to obtain the number of test cycles and verification parameters through the virtual function of the base class function of the SV language; The verification module is used to write the verification parameters into a shared storage area through a virtual function within each test cycle, and share the verification parameters with a C language program through the shared storage area; the C language program controls the processor hardware to complete the verification calculation according to the verification parameters, and writes the calculation results into the shared storage area; until the verification rounds of the test cycle are completed.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the chip verification method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the chip verification method according to any one of claims 1 to 7 when executed.

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