Chip and chip pin control method

Abstract

The present application discloses a chip and a chip pin control method, belonging to the field of circuits. The chip provided by the present application includes: a target pin, a configuration module, a selection module and a target module; the selection module has a first input terminal, a second input terminal and an output terminal, the target pin is connected to the first input terminal of the selection module, the configuration module is connected to the second input terminal of the selection module, and the output terminal of the selection module is connected to the target module; wherein the selection module is used to select a target input value from the first input value of the target pin and the second input value configured by the configuration module, and use the target input value as the input value of the target module; the first input value is different from the second input value.

Description

Technical Field

[0001] The present application belongs to the field of circuits, and specifically relates to a chip and a chip pin control method. Background Art

[0002] Currently, it is very common to use the input value of the chip pin to initialize the chip during the use of the chip.

[0003] In the related art, the input value of the chip pin is fixed and cannot be modified by the user. For example, a chip pin is connected to the power ground during the chip packaging stage, and the input value of the chip pin is fixed to 0. For another example, a chip pin is connected to a pull-up resistor (or a pull-down resistor) on a PCB (Printed Circuit Board), and the input value of the chip pin is fixed to 1 (or 0). In this way, since the input value of the chip pin in the related art is fixed, it cannot be flexibly modified in many situations (such as facing new application scenarios), and it is difficult to meet actual usage needs. Summary of the invention

[0004] The embodiments of the present application provide a chip and a chip pin control method, which can solve the problem that the input value of the chip pin cannot be modified in the related art.

[0005] In a first aspect, an embodiment of the present application provides a chip, including: A target pin, a configuration module, a selection module and a target module; the selection module has a first input terminal, a second input terminal and an output terminal, the target pin is connected to the first input terminal of the selection module, the configuration module is connected to the second input terminal of the selection module, and the output terminal of the selection module is connected to the target module; The selection module is used to select a target input value from a first input value of the target pin and a second input value configured by the configuration module, and use the target input value as an input value of the target module; the first input value is different from the second input value.

[0006] In a second aspect, an embodiment of the present application provides a chip pin control method, which is applied to the chip described in the first aspect, and the control method includes: The selection module obtains a target selection signal; The selection module selects a target input value from the first input value of the target pin and the second input value configured by the configuration module based on the target selection signal, and uses the target input value as the input value of the target module; The first input value is different from the second input value.

[0007] In an embodiment of the present application, a chip includes a target pin, a configuration module, a selection module and a target module; the selection module has a first input terminal, a second input terminal and an output terminal, the target pin is connected to the first input terminal of the selection module, the configuration module is connected to the second input terminal of the selection module, and the output terminal of the selection module is connected to the target module; wherein the selection module is used to select a target input value from the first input value of the target pin and the second input value configured by the configuration module, and use the target input value as the input value of the target module; the first input value is different from the second input value. In this way, since the selection module can select a target input value from the first input value of the target pin and the second input value configured by the configuration module as the input value of the target module, for different application scenarios, the first input value or the second input value can be flexibly configured as the input value of the target pin input to the target module, thereby realizing a flexible modification configuration of the input value of the target pin, and solving the problem that the input value of the chip pin cannot be modified in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic structural diagram of a chip provided for related technology; Figure 2 A schematic structural diagram of a chip provided in an embodiment of the present application; Figure 3 A schematic structural diagram of another chip provided in an embodiment of the present application; Figure 4 A schematic structural diagram of another chip provided in an embodiment of the present application; Figure 5 A schematic structural diagram of another chip provided in an embodiment of the present application; Figure 6 A schematic structural diagram of another chip provided in an embodiment of the present application; Figure 7-1 A control timing diagram of a chip provided in an embodiment of the present application; Figure 7-2 A control timing diagram of another chip provided in an embodiment of the present application; Figure 7-3 A control timing diagram of another chip provided in an embodiment of the present application; Figure 7-4 A control timing diagram of another chip provided in an embodiment of the present application; Figure 7-5 A control timing diagram of another chip provided in an embodiment of the present application; Figure 8 A schematic structural diagram of another chip provided in an embodiment of the present application; Fig. 9A schematic flowchart of a chip pin control method provided in an embodiment of the present application.

[0009] Description of reference numerals: 10-chip; 100-target pin; 110-input pin; 120-input / output pin; 200-configuration module; 210-OTP data cache register; 220-OTP data parsing unit; 230-output unit; 240-OTP control circuit; 250-OTP unit; 300-selection module; A-first input end of the selection module; B-second input end of the selection module; C-output end of the selection module; D-control end of the selection module; 310-first selector; A1-first input end of the first selector; B1-second input end of the first selector; C1-output end of the first selector Output end; D1-control end of the first selector; 320-second selector; A2-first input end of the second selector; B2-second input end of the second selector; C2-output end of the second selector; D2-control end of the second selector; 400-target module; 410-first input unit; 420-latch unit; 421-third controller; 422-D trigger; 430-second input unit; 440-input / output control unit; 500-reset signal generating circuit; 600-reset signal delay circuit; 700-AND gate circuit; 800-OTP controller; 900-fourth selector. DETAILED DESCRIPTION

[0010] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0011] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0012] As described in the background art, the input value of the chip pin in the related art is fixed and cannot be modified by the user. For example, the metal contact (PAD) is grounded during the chip packaging stage, so that the chip pin (PIN) connected to the metal contact is always connected to the power ground, that is, the input value of the chip pin is fixed to 0.

[0013] For example, when the chip pin (PIN) is connected to the power supply (or power ground) through a pull-up resistor (or pull-down resistor) on the PCB, the input value of the chip is fixed to 1 (or 0). Since the chip pin may be connected to other chips, the chip pin can also be configured as an output. Figure 1 In actual applications, there are two situations for chip pins: One is that the chip pin is always configured as input mode, in which case the chip pin can be regarded as an input pin. When the input pin is connected to a pull-up resistor (or pull-down resistor) on the PCB, the pull-up (or pull-down) is always effective, that is, the input value of the input pin is always 1 (or 0); The other is that the chip pins can be configured as input mode or output mode. In this case, the chip pins can be regarded as input / output pins. During the chip power-on initialization phase, the chip pins are configured as input mode, and the chip pin input is 1 or 0. In this case, the chip can perform a power-on latch action through the selector and D flip-flop to latch the external input value during the power-on phase. Among them, the reset signal por_rstb of the D flip-flop generally comes from the reset signal generating circuit. The reset signal generated by the reset signal generating circuit can be obtained by ANDing the external pin reset signal and the power-on reset signal generated by the internal POR (Power on Reset) circuit. The reset signal (por_rstb) controls the action of triggering the power-on latch, and is also the source of resetting all circuits inside the chip.

[0014] It should be noted that the above methods of setting the input value of the chip pin to 1 or 0 are all implemented through hardware. The grounding in the chip package, or the pull-up resistor or pull-down resistor on the PCB, causes the input value of the chip pin to be a fixed value, which cannot be modified by the user. In many cases (such as facing new application scenarios), it cannot be flexibly modified, and it is difficult to meet actual usage needs.

[0015] For example, in actual applications, there are some scenarios where the input value of the chip pin needs to be modified. The following example describes: For example, a chip may be packaged into two versions, high-performance and low-performance. The two versions may have different maximum processor frequencies, internal functions, etc. For example, one version of the chip requires a memory (DDR) module, while the other version does not; another example is that one version of the chip requires 4 serial deserializer (Serdes) modules, while the other version only requires 2 serial deserializer modules. In this way, some chip pins can be used to enable memory modules and serial deserializer modules, and for scenarios that do not require them, the metal contacts (PAD) can be grounded to turn off this function. However, in specific application scenarios, new requirements may arise. For example, although it is a low-performance version of the chip, it may be necessary to reopen the DDR or Serdes function. At this time, the user needs to modify the input value of the chip pin. However, existing products cannot achieve this, and new models of chips need to be repackaged.

[0016] For another example, a chip includes different types of interfaces such as SPI, IIC, MDC / MDIO, etc. Different types of interfaces share 2 pins. The current mode needs to be defined by two pins. For example, "00" corresponds to the SPI interface and "01" corresponds to the IIC interface. The pins selected by these two modes need to add pull-up or pull-down resistors on the PCB. If a product's PCB only has reserved pull-ups, but it is found that pull-downs are also required in new application scenarios, the user needs to modify the input value of the chip pin. However, this cannot be achieved with existing products, and the pull-down resistors need to be re-soldered on the PCB.

[0017] For another example, the chip can use the SPI interface to access the flash memory chip. The flash memory chip can be accessed in two modes: 3-byte or 4-byte address mode. One chip pin can be used to select these two modes. Assume that the 3-byte address mode is currently used, but the flash memory particles are replaced in the application later and need to be switched to the 4-byte address mode. At this time, the user needs to modify the input value of the chip pin. However, the existing products cannot achieve this, and it may be necessary to modify the pull-up or pull-down resistors soldered on the PCB board, or even redesign the PCB board.

[0018] The above examples are all some of the defects of the existing solutions. Faced with new application scenarios, users cannot flexibly modify the input values ​​of chip pins. They may need to repackage the chip or redevelop the PCB board, which increases the product introduction cycle and even directly affects product introduction.

[0019] Based on this, in order to solve the problem that the input value of the chip pin cannot be modified in the related technology, the embodiment of the present application adds a setting selection module in the input direction of the chip pin. The selection module can select a value from the starting input value of the chip pin and an additional configured modification value (different from the starting input value) as the input value of the internal logic module of the chip, and then the starting input value of the chip pin can be modified through the selection module configuration, thereby solving the problem that the input value of the chip pin cannot be modified in the related technology.

[0020] It should be noted that in practical applications, chip pins can be input pins, input / output pins, etc., and the present application does not limit the specific type of chip pins. The chip can be various types of chips, and the present application does not limit the specific type of the chip.

[0021] The chip and chip pin control method provided in the embodiments of the present application are described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0022] Figure 2 A schematic structural diagram of a chip provided in an embodiment of the present application.

[0023] like Figure 2 As shown, the chip 10 provided in the embodiment of the present application may include: a target pin 100, a configuration module 200, a selection module 300 and a target module 400; the selection module 300 has a first input terminal A, a second input terminal B and an output terminal C, the target pin 100 is connected to the first input terminal A of the selection module 300, the configuration module 200 is connected to the second input terminal B of the selection module 300, and the output terminal C of the selection module 300 is connected to the target module 100; The selection module 300 is used to select a target input value from the first input value of the target pin 100 and the second input value configured by the configuration module 200, and use the target input value as the input value of the target module 400; the first input value is different from the second input value.

[0024] The target pin 100 may be always configured as an input mode, or the target pin 100 may be configured as an input mode or an output mode, which is not limited in the present application.

[0025] The target module 400 may be a logic module inside a chip, and the present application does not limit the specific type of the target module.

[0026] Among them, the first input value of the target pin 100 may be the initial input value of the target pin 100. The second input value configured by the configuration module 200 may be different from the first input value, and may be regarded as a modified value of the target pin 100. For example, when the target pin 100 is connected to a pull-up resistor on the PCB, the first input value of the target pin 100 is 1, and at this time, the second input value configured by the configuration module 200 may be 0. For another example, when the target pin 100 is connected to a pull-down resistor on the PCB, or when the target pin 100 is connected to the power ground through a metal contact, the first input value of the target pin 100 is 0, and at this time, the second input value configured by the configuration module 200 may be 1. In this way, the second input value configured by the configuration module 200 may be regarded as a modified value of the initial input value of the target pin 100.

[0027] In the embodiment of the present application, the selection module 300 can select the target input value from the first input value of the target pin 100 and the second input value configured by the configuration module 200, and use the target input value as the input value of the target module 400; the first input value is different from the second input value. In this way, for different application scenarios, the user can flexibly configure the first input value or the second input value as the input value of the target pin 100 to the target module 400, thereby realizing the flexible configuration of the input value of the target pin 100 and solving the problem that the input value of the chip pin cannot be modified in the related art.

[0028] According to the chip provided by the embodiment of the present application, the chip includes a target pin, a configuration module, a selection module and a target module; the selection module has a first input terminal, a second input terminal and an output terminal, the target pin is connected to the first input terminal of the selection module, the configuration module is connected to the second input terminal of the selection module, and the output terminal of the selection module is connected to the target module; wherein the selection module is used to select the target input value from the first input value of the target pin and the second input value configured by the configuration module, and use the target input value as the input value of the target module; the first input value is different from the second input value. In this way, since the selection module can select the target input value from the first input value of the target pin and the second input value configured by the configuration module as the input value of the target module, for different application scenarios, the first input value or the second input value can be flexibly configured as the input value of the target pin input to the target module, thereby realizing the flexible modification configuration of the input value of the target pin, and solving the problem that the input value of the chip pin cannot be modified in the related art.

[0029] In a specific embodiment, in order to further control the input value of the chip pin, such as Figure 2 As shown, in the chip provided in the embodiment of the present application, the selection module 300 further has a control terminal D, and the control terminal D of the selection module 300 is connected to the configuration module 200; The configuration module 200 may be used to output a target selection signal to the control terminal D of the selection module 300; the target selection signal is a first selection signal or a second selection signal; Wherein, when the target selection signal received by the control terminal D of the selection module 300 is the first selection signal, the selection module is used to select the first input value of the target pin as the target input value; In the case that the target selection signal received by the control terminal D of the selection module 300 is the second selection signal, the selection module is used to select the second input value configured by the configuration module as the target input value.

[0030] In the embodiment of the present application, the first selection signal is different from the second selection signal. For example, the first selection signal is 0 and the second selection signal is 1.

[0031] When the target selection signal received by the control terminal D of the selection module 300 is 0, the selection module may select the first input value (starting input value) of the target pin as the input value of the target module 400 .

[0032] When the target selection signal received by the control terminal D of the selection module 300 is 1, the selection module may select the second input value (modified value) configured by the configuration module as the input value of the target module 400 .

[0033] In this way, through the target selection signal provided by the configuration module 200, the first input value (starting input value) of the target pin or the second input value (modified value) configured by the configuration module is controlled to be selected as the input value of the target pin input to the target module, thereby realizing flexible configuration of the input value of the chip pin.

[0034] In practical applications, the chip pin can always be configured as an input mode, in which case the chip pin can be considered as an input pin. Alternatively, the target pin 100 can be configured as an input mode or an output mode, in which case the chip pin can be considered as an input / output pin. For different types of chip pins, the input value can be modified and configured, as illustrated below.

[0035] In a specific embodiment, when the chip pin is an input pin, in order to realize flexible modification configuration of the input value of the input pin, such as Figure 3 As shown, the target pin may include an input pin 110, the selection module may include a first selector 310, and the target module may include a first input unit 410; Among them, the first selector 310 has a first input terminal A1, a second input terminal B1 and an output terminal C1, the input pin 110 is connected to the first input terminal A1 of the first selector 310, the configuration module 200 is connected to the second input terminal B1 of the first selector 310, and the output terminal C1 of the first selector 310 is connected to the first input unit 410.

[0036] The first input unit 410 may be a logic unit inside the chip, and the present application does not limit the specific function of the first input unit 410 .

[0037] The first selector 310 can select a target input value from the first input value of the input pin 110 and the second input value configured by the configuration module 200, and use the target input value as the input value of the first input unit 410; the first input value is different from the second input value.

[0038] In this way, for different application scenarios, the user can flexibly configure the first input value or the second input value as the input value of the input pin 110, thereby achieving flexible configuration of the input value of the input pin 110 and solving the problem that the input value of the input pin cannot be modified.

[0039] In addition, if Figure 3 As shown, the first selector 310 also has a control end D1, and the control end D1 of the first selector 310 is connected to the configuration module 200; the configuration module 200 is used to output a target selection signal to the control end D1 of the first selector 310, and the target selection signal is a first selection signal or a second selection signal; wherein, when the target selection signal received by the control end D1 of the first selector 310 is the first selection signal, the first selector 310 selects the first input value of the input pin as the target input value; when the target selection signal received by the control end D1 of the first selector 310 is the second selection signal, the first selector 310 selects the second input value configured by the configuration module as the target input value.

[0040] In this way, through the target selection signal provided by the configuration module 200, the first input value (starting input value) of the input pin 110 or the second input value (modified value) configured by the configuration module is controlled to be selected as the input value of the input pin 110 input to the first input unit 410, thereby realizing flexible configuration of the input value of the input pin.

[0041] In another specific embodiment, when the chip pin is an input / output pin, in order to realize flexible modification configuration of the input value of the input / output pin, such as Figure 4 As shown, the target pin may include an input / output pin 120, the selection module may include a second selector 320, and the target module may include a latch unit 420 and a second input unit 430; Among them, the input / output pin 120 has an input end, the second selector 320 has a first input end A2, a second input end B2 and an output end C2, the input end of the input / output pin 120 is connected to the first input end A2 of the second selector 320, the configuration module 200 is connected to the second input end B2 of the second selector 320, and the output end C2 of the second selector 320 is connected to the second input unit 430 via the latch unit 420.

[0042] Among them, during the power-on initialization stage of the chip, the input / output pin is configured to the input mode, and the first input value of the input / output pin can be 1 or 0. In this case, the chip can perform a power-on latch action through the latch unit 420 to latch the output target input value during the power-on stage.

[0043] Among them, the second selector 320 can select the target input value from the first input value of the input / output pin 120 and the second input value configured by the configuration module 200, latch the output target input value during the chip power-on stage, and use the target input value as the input value of the second input unit 430.

[0044] In this way, for different application scenarios, the user can flexibly configure the first input value or the second input value as the input value of the input / output pin 120, thereby achieving flexible configuration of the input value of the input / output pin 120 and solving the problem that the input value of the input / output pin cannot be modified.

[0045] In addition, in practical applications, such as Figure 4 As shown, the target module may also include an input / output control unit 440, and the input / output pin 120 also has an output end. The input end of the input / output pin 120 is connected to the input / output control unit 440 via the second selector 320; the output end of the input / output pin 120 is connected to the input / output control unit 440.

[0046] The input / output control unit 440 can configure the working mode of the input / output pin 120, for example, configure the input / output pin 120 to the input mode, or configure the input / output pin 120 to the output mode. For example, in the embodiment of the present application, the input / output pin 120 can be configured to the input mode, and then the input value of the input / output pin 120 is modified by the second selector 320 during the chip power-on stage.

[0047] In addition, if Figure 4As shown, the second selector 320 also has a control terminal D2, and the control terminal D2 of the second selector 320 is connected to the configuration module 200; the configuration module 200 is used to output a target selection signal to the control terminal D2 of the second selector 320, and the target selection signal is a first selection signal or a second selection signal; wherein, when the target selection signal received by the control terminal D2 of the second selector 320 is the first selection signal, the second selector 320 can select the first input value of the input / output pin 120 as the target input value; when the target selection signal received by the control terminal D2 of the second selector 320 is the second selection signal, the second selector 320 can select the second input value configured by the configuration module as the target input value. Afterwards, in the chip power-on stage, the latch unit 420 latches the output target input value and uses the target input value as the input value of the second input unit 430.

[0048] In this way, through the target selection signal provided by the configuration module 200, the first input value (starting input value) of the input / output pin 120 or the second input value (modified value) configured by the configuration module is controlled to be selected as the input value of the input / output pin 120 input to the second input unit 430, thereby realizing flexible configuration of the input value of the input / output pin.

[0049] In a specific embodiment, in order to realize latching the target input value output by the second selector 320 during the chip power-on phase, as shown in FIG. Figure 5 As shown, the latch unit 420 may include a third selector 421 and a D flip-flop 422; Among them, the third selector 421 has a first input terminal, a second input terminal and an output terminal, the output terminal C2 of the second selector 320 is connected to the first input terminal of the third selector 421, the output terminal of the third selector 421 is connected to the input terminal of the D trigger 422, the output terminal of the D trigger 422 is connected to the second input terminal of the third selector 421, and the output terminal of the D trigger 422 is connected to the second input terminal of the third selector 421, and the output terminal of the D trigger 422 is connected to the second input unit 430.

[0050] In this way, the third selector 421 and the D flip-flop 422 are used to latch the target input value output by the second selector 320 during the chip power-on phase, and use the target input value as the input value of the second input unit 430 .

[0051] In order to avoid affecting other circuits inside the chip during the input value modification process, the power-on reset signal of the D flip-flop 422 can be executed later than other circuits. Figure 5 As shown, the chip 10 further includes a reset signal generating circuit 500, a reset signal delay circuit 600 and an AND gate circuit 700, and the D flip-flop 422 also has a reset terminal; Among them, the reset signal generating circuit 500 is connected to the input end of the reset signal delay circuit 600, the reset signal generating circuit 500 is connected to the first input end of the AND gate circuit 700, the output end of the reset signal delay circuit 600 is connected to the second input end of the AND gate circuit 700, and the output end of the AND gate circuit 700 is connected to the reset end of the D trigger 422.

[0052] The reset signal por_rstb generated by the reset signal generating circuit 500 may be obtained by ANDing an external pin reset signal and a power-on reset signal generated by an internal POR circuit.

[0053] The reset signal delay circuit 600 may delay the reset signal por_rstb to obtain a reset delay signal por_rstb_dly.

[0054] The AND gate circuit 700 can perform AND processing on the reset signal por_rstb generated by the reset signal generating circuit 500 and the reset delay signal por_rstb_dly output by the reset signal delay circuit 600 to obtain a delayed reset signal new_por_rstb. The delayed reset signal new_por_rstb can be subsequently output to the reset terminal of the D flip-flop 422 to trigger the latching action of the D flip-flop 422 during the power-on stage.

[0055] Furthermore, the new reset signal new_por_rstb may be a source for resetting the remaining circuits inside the chip except the reset signal delay circuit 600 and the configuration module 200 .

[0056] For example, in order to generate the "second input value" and "target selection signal" output by the configuration module 200, the configuration module 200 can work in advance. Specifically, the OTP control circuit, OTP data cache register, OTP data parsing unit, and output unit in the configuration circuit 200 are still reset using the reset signal por_rstb, and except for the reset signal delay circuit 600 and the configuration module 200, the remaining circuits inside the chip can be reset using the delayed reset signal new_por_rstb.

[0057] In this way, the reset signal por_rstb is delayed by the reset signal delay circuit 600 to obtain the delayed reset signal new_por_rstb, and the delayed reset signal new_por_rstb is used to reset the D flip-flop 422, so as to trigger the latching action of the D flip-flop 422 during the power-on stage. Furthermore, during the input value modification stage, the remaining internal circuits remain in a reset state, and only start to execute after the input value is modified, thereby achieving an effect that is almost completely equivalent to directly modifying the hardware circuit, and avoiding the influence of the remaining circuits.

[0058] In addition, in practical applications, the control signals of the selection module (such as the second modification value and the target selection signal) can be obtained by configuring the configuration module, and the control signals of the selection module can be configured in combination with OTP (One Time Programmable) technology. The specific structure of the configuration module is illustrated below.

[0059] In a specific embodiment, Figure 6 As shown, the configuration module may include an OTP data cache register 210, an OTP data parsing unit 220, and an output unit 230; The OTP data cache register 210 is connected to the OTP data parsing unit 220, the OTP data parsing unit 220 is connected to the output unit 230, and the output unit 230 is connected to the second input terminal B of the selection module 300; In the case where the selection module 300 further has a control terminal D, the output unit 230 is further connected to the control terminal D of the selection module 300 .

[0060] In the embodiment of the present application, the OTP data cache register 210 can cache the OTP data until it is reset by the por_rstb signal next time. The OTP data can be used to configure the control signal of the selection module, and the control signal of the selection module can include a target selection signal and a second input value.

[0061] In an embodiment of the present application, the OTP data parsing unit 220 can be used to parse the OTP data in the OTP data cache register to obtain a parsing result. The parsing result includes control information (Ctrl). For example, 3 bits of control information (Ctrl) are used to control whether to modify the input value of the target pin, that is, 3 bits are used to generate the "second input value" and "target selection signal" of the selection module mentioned above). The 3-bit control information (Ctrl) corresponding to the OTP data can refer to the following example: Ctrl=“0xx” means no modification; at this time, the target selection signal is 0; Ctrl="100" means changing the input value of the chip pin to 0 (that is, configuring the second input value to 0), and the modified value only maintains the chip power-on stage, corresponding to the application situation where the input / output pin is configured as input mode; at this time, the target selection signal is 1; Ctrl="101" means changing the input value of the chip pin to 1 (that is, configuring the second input value to 1), and the modified value only maintains the chip power-on stage, corresponding to the application situation where the input / output pin is configured as input mode; at this time, the target selection signal is 1; Ctrl="110" means changing the input value clock of the chip pin to 0 (that is, configuring the second input value to 0), corresponding to the application of the input pin; at this time, the target selection signal is 1; Ctrl="111" means changing the input value clock of the chip pin to 1 (that is, configuring the second input value to 1), corresponding to the application of the input pin; at this time, the target selection signal is 1.

[0062] In the embodiment of the present application, the output unit 230 is used to output the control signal (such as the second modification value and the target selection signal) of the selection module 300 to the selection module 300 according to the analysis result (ie, the control information Ctrl). Figure 7-1 to Figure 7-5 .

[0063] like Figure 7-1 As shown, when Ctrl="0xx", it means no modification; at this time, the target selection signal is 0; and the second input value is 0.

[0064] like Figure 7-2 As shown in the figure, when Ctrl = "100", it means that the input value of the input / output pin is modified to 0 during the chip power-on stage. At this time, the target selection signal is 1; the second input value is 0.

[0065] like Figure 7-3 As shown, when Ctrl="101", it means that the input value of the input / output pin is modified to 1 during the chip power-on stage. At this time, the target selection signal is 1; the second input value is 1.

[0066] like Figure 7-4 As shown, when Ctrl="110", it means that the input value of the input pin is modified to 0. At this time, the target selection signal is 1; the second input value is 0.

[0067] like Figure 7-5 As shown, when Ctrl="111", it means that the input value of the input pin is modified to 1. At this time, the target selection signal is 1; the second input value is 1.

[0068] It should be noted that in the two configurations of "100" and "101", the target selection signal of the selection module is 1 for only a period of time. The time point when it changes from 1 to 0 is after the delayed reset signal new_por_rstb is released and the power-on latch action is completed, usually only a few clock cycles after the release of new_por_rstb.

[0069] In addition, the reset signal delay circuit 600 is mainly used to generate a delayed reset signal por_rstb_dly, which is to output the reset signal por_rstb after delaying it for a period of time with the xtal clock. The signal output and por_rstb are ANDed to obtain the delayed reset signal new_por_rstb. Among them, the new reset signal new_por_rstb is the reset source of the remaining circuits except the main circuits of this scheme (such as the reset signal delay circuit and the configuration module). The purpose of the delay is to complete all the preparatory work for modifying the input value of the target pin first, and then release the subsequent circuits to make the new input value of the target pin take effect. Furthermore, all subsequent circuits do not need to be modified, and the modification of the input value of the target pin will not affect other circuits.

[0070] Among them, in order to obtain OTP data, such as Figure 6 As shown, the configuration module 200 further includes an OTP control circuit 240 and an OTP unit 250 . The OTP control circuit 240 is coupled to the OTP unit 250 , and the OTP unit 250 is connected to the OTP data cache register 210 .

[0071] In the embodiment of the present application, the OTP control circuit 240 may use an xtal clock, and the OTP control circuit 240 may specifically be an OTP partial read control circuit, which may send a clock / reset / read-write control signal to the OTP unit 250, so that the OTP unit 250 outputs the OTP data to the OTP data cache register 210. The read control of the OTP data is realized.

[0072] The OTP control circuit 240 can start working after the reset signal por_rstb is released, and the working clock is the xtal clock. The OTP control circuit 240 can generate a control signal (including clock and reset signals) for reading the OTP unit 250, and read out the relevant OTP data used to control the input value of the modified target chip.

[0073] It can be understood that the OTP control circuit 240 of this technical solution is driven by the xtal clock and will not be affected by other reset signals triggered by the internal software. In terms of the effect of modifying the input value of the target pin, it is equivalent to hardware modification (such as repackaging or re-soldering the pull-up / pull-down resistor).

[0074] It should be pointed out that the OTP unit 250 can be an existing circuit in the chip, and the control of the OTP unit is realized by the existing OTP controller in the chip. In order to modify the input value of the target pin, the embodiment of the present application can reuse the OTP unit, and select the OTP control circuit 240 to control the OTP unit 250 to generate and output the second input value of the target pin. Alternatively, the OTP unit 250 can also be a newly set circuit in the chip. In order to modify the input value of the target pin, the embodiment of the present application can directly add an OTP unit to generate and output the second input value of the target pin. Among them, the embodiment of the present application does not limit whether the chip originally has an OTP unit.

[0075] In practical applications, when the OTP unit 250 is an existing circuit in the chip, in order to reduce the impact on the original circuit of the chip, a fourth selector may be added to the chip to select the OTP control circuit 240 to control the original OTP unit 250 .

[0076] Specifically, if Figure 6 As shown, the chip 10 may further include an OTP controller 800 and a fourth selector 900 , the OTP controller 800 being connected to a first input terminal of the fourth selector 900 , the OTP control circuit 240 being connected to a second input terminal of the fourth selector 900 , and the output terminal of the fourth selector 900 being connected to the OTP unit 250 .

[0077] It can be understood that no changes are made to the original OTP controller 800 inside the chip. Only during the working stage of the OTP control circuit 240, the fourth selector 900 can select the access to the OTP unit 250 to be taken over by the OTP control circuit 240. After the OTP control circuit 240 finishes reading, the control of the OTP unit 250 is returned to the original OTP controller 800, which can reduce the impact on the OTP controller 800 and the OTP unit 250 in the original circuit of the chip.

[0078] In practical applications, such as Figure 8 As shown, in the chip provided in the embodiment of the present application, the target pin may include an input pin 110 and an input / output pin 120; the configuration module may include an OTP control circuit 240, an OTP unit 250, an OTP data cache register 210, an OTP data parsing unit 220 and an output unit 230; the selection module may include a first selector 310 and a second selector 320; the target module may include a first input unit 410, a third selector 421, a D flip-flop 422, a second input unit 430 and an input / output control unit 440.

[0079] In addition, the chip further includes a reset signal generating circuit 500 , a reset signal delay circuit 600 and an AND gate circuit 700 , which are used to provide a new reset signal for the D flip-flop 422 .

[0080] Furthermore, the chip further includes a fourth selector 900 for reducing the impact on the original OTP unit 250 and the OTP controller 800 of the chip.

[0081] In the embodiment of the present application, the present solution can utilize OTP to modify the input values ​​of the input pin 110 and the input / output pin 120. Specifically, the OTP control circuit 240 is used to read the relevant OTP data from the OTP unit 250 and save it in the OTP data cache register 210. Then, the OTP data parsing unit 220 parses the OTP data to obtain a parsing result. The output unit 230 then generates a control signal (including a second modification value and a target control signal) for the first selector 310 / the second selector 320 according to the parsing result. Furthermore, for different application scenarios, the user can flexibly configure the input value of the first selector 310 / the second selector 320, thereby realizing flexible configuration of the input value of the input pin 110 and the input / output pin 120. The input value of the chip pin can be modified without modifying the chip package and the hardware circuit, thereby solving the problem that the input value of the chip pin cannot be modified.

[0082] It should be pointed out that the chip structure provided in the embodiment of the present application is relatively simple and has little impact on the original circuit. Specifically, a selector is added to each target pin, a reset signal delay circuit is added, and a fourth selector is added to the control path of the original OTP unit. Other circuits inside the chip are not affected.

[0083] In addition, the chip provided in the embodiment of the present application obtains a new reset signal new_por_rstb by delaying the reset signal por_rstb. During the stage of modifying the input value of the target pin, the remaining circuits inside the chip remain in a reset state, and execution begins only after the input value of the target pin is modified, thereby achieving an effect that is almost completely equivalent to directly modifying the hardware circuit. Specifically, the new reset signal new_por_rstb is the reset source of the remaining circuits except the main circuit of this scheme (reset signal delay circuit and configuration module). The purpose of the delay is to complete all preparatory work for modifying the input value of the target pin first, and then release the subsequent circuits to allow the new input value of the target pin to take effect. Furthermore, all subsequent circuits do not need to be modified, and the modification of the input value of the target pin will not affect other circuits.

[0084] In addition, in actual applications, if the input value of the target module is directly configured using the OTP register, the input value of the target module cannot be switched freely due to the characteristic of OTP that it can only be burned once. However, the chip provided in the embodiment of the present application uses OTP to modify the input value of the target pin. For different application scenarios, the user can flexibly configure the first input value of the target pin or the second input value (i.e., the modified value) configured by OTP as the input value of the target module, and can freely switch different input values, so that the chip can be suitable for different application scenarios.

[0085] In addition, based on the same concept as the above chip embodiments, the embodiments of the present application also provide a chip pin control method, which is applied to the chip of any of the above embodiments.

[0086] like Fig. 9 As shown, an embodiment of the present application provides a chip pin control method, which is applied to a chip in any of the above embodiments. The control method may include: Step 910: The selection module obtains a target selection signal; Step 920: the selection module selects a target input value from the first input value of the target pin and the second input value configured by the configuration module based on the target selection signal, and uses the target input value as the input value of the target module; The first input value is different from the second input value.

[0087] According to the chip pin control method provided by the embodiment of the present application, a target selection signal is obtained through a selection module; based on the target selection signal, the selection module selects the target input value from the first input value of the target pin and the second input value configured by the configuration module, and uses the target input value as the input value of the target module; wherein the first input value is different from the second input value. In this way, since the selection module can select the target input value from the first input value of the target pin and the second input value configured by the configuration module as the input value of the target module, the first input value or the second input value can be flexibly configured as the input value of the target pin input to the target module for different application scenarios, thereby realizing flexible modification configuration of the input value of the target pin and solving the problem that the input value of the chip pin in the related art cannot be modified.

[0088] In actual applications, the chip pin control method provided in the embodiment of the present application can change the input value or initial input value of the chip pin without modifying the chip package and PCB hardware circuit. This method can be open to system manufacturers for use, or the chip company itself can use it. If it does not want to be open to system manufacturers, passwords can also be set for control. The embodiment of the present application does not limit the specific application scenarios.

[0089] It should be noted that the chip pin control method provided in the embodiment of the present application can realize the specific functions of the chip of any of the above embodiments and achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0090] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0091] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0092] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A chip, characterized in that: include: Target pins, configuration modules, selection modules, and target modules; The selection module has a first input terminal, a second input terminal and an output terminal, the target pin is connected to the first input terminal of the selection module, the configuration module is connected to the second input terminal of the selection module, and the output terminal of the selection module is connected to the target module; The selection module is used to select a target input value from a first input value of the target pin and a second input value configured by the configuration module, and use the target input value as an input value of the target module; the first input value is different from the second input value.

2. The chip according to claim 1, characterized in that: The selection module also has a control end, and the control end of the selection module is connected to the configuration module; The configuration module is used to output a target selection signal to the control end of the selection module; the target selection signal is a first selection signal or a second selection signal; Wherein, when the target selection signal received by the control end of the selection module is a first selection signal, the selection module is used to select the first input value of the target pin as the target input value; In a case where the target selection signal received by the control end of the selection module is a second selection signal, the selection module is configured to select the second input value configured by the configuration module as the target input value.

3. The chip according to claim 1, characterized in that: The target pin includes an input pin, the selection module includes a first selector, and the target module includes a first input unit; The first selector has a first input terminal, a second input terminal and an output terminal, the input pin is connected to the first input terminal of the first selector, the configuration module is connected to the second input terminal of the first selector, and the output terminal of the first selector is connected to the first input unit.

4. The chip according to claim 1, characterized in that: The target pin includes an input / output pin, the selection module includes a second selector, and the target module includes a latch unit and a second input unit; Among them, the input / output pin has an input end, the second selector has a first input end, a second input end and an output end, the input end of the input / output pin is connected to the first input end of the second selector, the configuration module is connected to the second input end of the second selector, and the output end of the second selector is connected to the second input unit via the latch unit.

5. The chip according to claim 4, characterized in that: The latch unit includes a third selector and a D flip-flop; Among them, the third selector has a first input terminal, a second input terminal and an output terminal, the output terminal of the second selector is connected to the first input terminal of the third selector, the output terminal of the third selector is connected to the input terminal of the D trigger, the output terminal of the D trigger is connected to the second input terminal of the third selector, and the output terminal of the D trigger is connected to the second input unit.

6. The chip according to claim 5, characterized in that: The chip also includes a reset signal generating circuit, a reset signal delay circuit and an AND gate circuit, and the D flip-flop also has a reset terminal; Among them, the reset signal generating circuit is connected to the input end of the reset signal delay circuit, the reset signal generating circuit is connected to the first input end of the AND gate circuit, the output end of the reset signal delay circuit is connected to the second input end of the AND gate circuit, and the output end of the AND gate circuit is connected to the reset end of the D trigger.

7. The chip according to any one of claims 1 to 6, characterized in that: The configuration module includes a one-time programmable OTP data cache register, an OTP data parsing unit and an output unit; The OTP data cache register is connected to the OTP data parsing unit, the OTP data parsing unit is connected to the output unit, and the output unit is connected to the second input end of the selection module; Wherein, in the case that the selection module also has a control end, the output unit is also connected to the control end of the selection module.

8. The chip according to claim 7, characterized in that: The configuration module further includes an OTP control circuit and an OTP unit, wherein the OTP control circuit is coupled to the OTP unit, and the OTP unit is connected to the OTP data cache register.

9. The chip according to claim 8, characterized in that: The chip also includes an OTP controller and a fourth selector, the OTP controller is connected to a first input end of the fourth selector, the OTP control circuit is connected to a second input end of the fourth selector, and an output end of the fourth selector is connected to the OTP unit.

10. A chip pin control method, applied to the chip according to any one of claims 1 to 9, characterized in that: include: The selection module obtains a target selection signal; The selection module selects a target input value from the first input value of the target pin and the second input value configured by the configuration module based on the target selection signal, and uses the target input value as the input value of the target module; The first input value is different from the second input value.

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