A verification device suitable for lightweight chip design
By designing verification equipment suitable for lightweight chip design, using high-performance logic resource chips and high-flexible FPGA controllers, the problems of high and inapplicable existing equipment are solved, and the effect of efficient verification and cost reduction is achieved.
Patent Information
- Application Number
- CN202411891056.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2025-04-04
AI Technical Summary
Existing chip verification equipment is costly and is not suitable for lightweight chip design, resulting in waste of resources and increased design costs, and the equipment is easily damaged and repair costs are high.
A verification device suitable for lightweight chip design is designed, using a high-performance logic resource chip and a high-flexible FPGA controller, combined with a host computer, provides a modular hardware design framework that supports IO expansion and high-speed data transmission.
It realizes efficient verification of lightweight chip design, reduces design and verification time, reduces equipment costs, is suitable for large-scale mass production and use, and reduces maintenance costs.
Smart Images
Figure CN119761275A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of chip design and chip verification, and in particular to a verification device suitable for lightweight chip design. Background Art
[0002] In today's technology product market, the scale of ASIC design is still expanding, and its complexity is far beyond people's expectations, which makes improving the efficiency of design and verification the primary challenge in product market competition. With the increase in FPGA chip logic density and the increase in the number of I / Os, a new generation of verification platforms has emerged, making it possible to further improve ASIC verification efficiency.
[0003] The chip verification equipment currently on the market generally has high-density integrated logic resources, mainly serves large-scale chip design verification, and is usually expensive; some lightweight chip designs do not need to use such large-scale chip verification equipment, resulting in waste of resources and increased design costs; and because there are many hardware changes during the chip design verification process, the chip verification equipment is more easily damaged. Once damaged, the core logic resource chip can only be replaced, and the maintenance cost is close to the expensive cost of the equipment itself.
[0004] In order to meet the verification needs of lightweight chip design and the cost control needs of verification equipment, it is urgent to design a lightweight and low-cost chip verification equipment. Summary of the invention
[0005] The purpose of the present invention is to provide a verification device suitable for lightweight chip design to solve the problems raised in the above background technology.
[0006] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a verification device suitable for lightweight chip design, comprising a high-performance logic resource chip, a high-flexibility FPGA controller and a host computer, wherein the high-performance logic resource chip comprises 2586K System Logic Cells, 2364KCLB Flip-Flops, 1182K CLB LUTs, 36.1Mb DistRAM, 75.9Mb Block RAM, 270Mb Ultra RAM, 6840DSP Slices, and has a high-density, high-speed transceiver as a data transmission interface, and the high-flexibility FPGA controller comprises a soft core system and a logic system.
[0007] Preferably, the soft core system is responsible for the onboard device configuration and the interaction with the host computer, and the logic system includes a control bus, Eth, INT, MISC, and PMBUS buses, including a high-speed Ethernet interface for interacting with the host computer, a control bus for CPU control peripherals, a multi-channel clock module, a status cache module, an external EEPROM memory module, and a self-test module.
[0008] Preferably, the control bus of the CPU-controlled peripherals: a data interaction bus inside the main control chip, one of which is responsible for interacting with Ethernet data, and the other is responsible for interacting with the peripheral bus interface;
[0009] Self-test module: reserved debugging interface between controller and logic resource chip;
[0010] Multi-channel clock module: The design includes two si-5345 drivers, each si-5345 outputs 10 clock signals;
[0011] Status cache module: controls five power supplies, corresponding to different BANK reference voltages of the logic resource chip, supporting 1.2V, 1.35V, 1.5V, and 1,8V;
[0012] External EEPROM memory module: responsible for storing the last configuration information of all peripherals. Each time the program is started and loaded, the configuration information is automatically read from the EEPROM and sent down.
[0013] Preferably, the status cache module: the soft core integrates the PMBUS command set, is compatible with all power chips supporting the PMBUS protocol, and the logic side supports two-way PMBUS switching.
[0014] Preferably, the soft core system is a Sapphire RISC-V soft box processor including a 32-bit processor bit width, 4-512KB dedicated storage, and a 20-400MHz operating frequency.
[0015] Preferably, the self-test module interacts with the host computer via UART and a high-flexibility FPGA controller.
[0016] Compared with the prior art, the present invention has the following beneficial effects:
[0017] The core of the present invention is to use Xilinx FPGA UltraScale+ TMThe platform uses high-performance logic resource chips in the series to achieve efficient verification of lightweight chip designs; the platform provides a stable and efficient evaluation environment for the design verification of lightweight system-on-chip (SoC) and application-specific integrated circuits (ASIC); the platform has a large number of user-assignable IO (input / output interfaces) and high-speed transceivers, which can support various modular peripherals and interfaces, maximize the user interface, and enhance the flexibility and scalability of the system; it can effectively shorten the user's design and verification time and accelerate the speed at which user products enter the market.
[0018] The modular hardware design framework of the present invention allows the functions of the chip verification equipment to be expanded by adding or replacing daughter cards. It is suitable for lightweight chip design and verification solutions, covers the entire chip design and verification development cycle, is cost-friendly, suitable for large-scale mass production, and is cost-friendly for chip verification and maintenance. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 is a system block diagram of the present invention;
[0020] Figure 2 is a block diagram of the controller system of the present invention;
[0021] Figure 3 The upper computer of the present invention displays an interface diagram;
[0022] Figure 4 This is a diagram showing the interface of the host computer of the status cache module of the present invention;
[0023] Figure 5 This is a read-back verification interface diagram of the host computer multi-channel clock configuration of the present invention;
[0024] Figure 6 The script is called to generate a configuration file message diagram for the present invention;
[0025] Figure 7 The Sapphire soft core logic diagram of the present invention;
[0026] Figure 8 This is a summary diagram of the logic resources of some models of the present invention;
[0027] Fig. 9 This is a diagram of the board self-test function interface of the present invention;
[0028] Fig.10 This is a diagram showing the self-test effect of the board of the present invention. DETAILED DESCRIPTION
[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0030] See also Figure 1-10 The present invention provides a technical solution: a verification device suitable for lightweight chip design, including a high-performance logic resource chip, a high-flexibility FPGA controller and a host computer. The host computer has application scenarios under the Windows 10 operating system, such as: actual operation steps of functions such as parameter configuration, IP configuration, PLL clock configuration, voltage configuration, board self-test, chip verification application loading, etc. The high-performance logic resource chip includes 2586K System Logic Cells, 2364K CLB Flip-Flops, 1182K CLB LUTs, 36.1Mb Dist RAM, 75.9Mb Block RAM, 270Mb Ultra RAM, 6840DSP Slices, and has high-density, high-speed transceivers as data transmission interfaces, such as 120 pairs of GTY32.75Gbps Transceiver, 100G Ethernet RS-FEC, 6 groups of PCIe In addition to Gen3*16 interfaces, we have designed 6 SlimSAS high-speed interfaces, logic configuration interfaces with the main control chip, and GPIO, etc. We use a highly flexible FPGA controller as the onboard main control. The highly flexible FPGA controller includes a soft core system and a logic system.
[0031] In the present invention, the soft core system is responsible for the configuration of onboard devices and the interaction with the host computer. The logic system includes a control bus, Eth, INT, MISC, and PMBUS buses, including a high-speed Ethernet interface for interacting with the host computer, a control bus for CPU control peripherals, a multi-channel clock module, a status cache module, an external EEPROM memory module, and a self-test module; the high-speed Ethernet interface for interacting with the host computer: the interface for interacting with the host computer uses the UDP protocol, supports custom IP and self-defined PORT ID, reports configuration information and self-test results, and is also used for controlling the sending of information.
[0032] In the present invention, the control bus of the CPU controlling the peripherals: the data interaction bus inside the main control chip, one of which is responsible for interacting with Ethernet data, and the other is responsible for interacting with the peripheral bus interface;
[0033] Self-test module: A reserved debugging interface between the controller and the logic resource chip, which can be developed according to the requirements and report the required debugging records. It is currently used as a self-test interface for the logic resource chip;
[0034] Multi-channel clock module: The design includes two si-5345 drivers, each si-5345 outputs 10 clock signals. Currently, one of the si-5345 outputs a fixed 156.25MHz clock, and the other can customize the clock frequency;
[0035] By driving two SPI buses, the driver configuration of the SI-534X series clock chip is performed. The clock frequency supports 50-750Mhz. At the same time, the host computer integrates the official configuration script, which can flexibly configure each output frequency and generate configuration files for distribution. The main controller soft core extracts and verifies the network protocol packet, decomposes the configuration file, distributes it to the internal control bus, and then converts it to SPI for peripheral driving through the logic side conversion module.
[0036] The host computer generates configuration documents with one click, sends and verifies configuration documents, realizes flexible configuration of 20 clocks, and supports external working status query and configuration parameter readback. The read-back parameters are analyzed and calculated and then reported to the host computer;
[0037] The clock configuration display interface is as follows Figure 5 As shown;
[0038] Status cache module: controls five power supplies, corresponding to different BANK reference voltages of the logic resource chip, supporting 1.2V, 1.35V, 1.5V, and 1,8V;
[0039] External EEPROM memory module: responsible for storing the last configuration information of all peripherals. Each time the program is started and loaded, the configuration information is automatically read from the EEPROM and sent down, so that each startup state is consistent with the previous power-off configuration.
[0040] In the present invention, the state cache module: the soft core integrates the PMBUS command set, is compatible with all power chips supporting the PMBUS protocol, and the logic side supports two-way PMBUS switching. In addition, the logic side supports EEPROM address mapping, and filters and records environmental status information in real time.
[0041] Through the PMBUS instruction set, the level and switch of each reference voltage, and even the voltage and current threshold range, can be flexibly configured, and then the power can be directly cut off when the voltage is abnormal, protecting the verification environment and the design to be verified. EEPROM makes corresponding address mapping for multiple power supplies and multiple clocks, and detects the configuration information of the host computer at the same time. Changes in configuration parameters of different channels automatically trigger address mapping and EEPROM write operations. In the case of abnormal power failure or reset, the last configuration parameters are saved, and the same design to be verified does not need to repeatedly configure the verification environment.
[0042] The PMBUS clock rate is configurable from 5 to 25MHz. The host computer currently supports 1.2V to 1.8V voltage configuration, which can be expanded to 0.5V to 3.3V by increasing the internal parameter library of the host computer. The maximum storage in the EEPROM is 256MB.
[0043] The upper computer display interface is as follows Figure 4 As shown:
[0044] The FMC voltage configuration function is divided into three parts:
[0045] 1>
Title bar
[0046] 2> [Parameter configuration area] The dark label 2 area is used to configure the FMC1#-5# voltage value and status.
[0047] 3>
Execution Area
[0048] Instructions:
[0049] After the software is running, click to enter the FMC voltage configuration interface. The interface displays the configuration area corresponding to FMC1#-5#. Each voltage configuration area has 4 fixed voltage values to choose from, namely 1.2, 1.35, 1.5, 1.8 and AutoRestore status. The light color is the currently selected item, and the white is unselected. After selecting the corresponding status according to actual needs, click the label 3 [Program] button to send the voltage parameters configured above to the lower computer. At the same time, the lower right status bar will display "Sending voltage configuration parameters...", indicating that the voltage configuration has been sent.
[0050] In the present invention, the soft core system is a Sapphire RISC-V soft box processor with a 32-bit processor width, 4-512KB dedicated storage, 20-400MHz operating frequency, responsible for startup loading, and also responsible for peripheral drivers, including multiple protocols and peripheral dependency libraries. It interacts with the host computer for network data, performs network protocol packet filtering and network data verification, performs command execution task control, and has multiple system operation logics such as interrupt shielding and interrupt processing control. The startup logic is as follows: Figure 7 .
[0051] In the present invention, the self-test module interacts with the host computer through UART and the high-flexibility FPGA controller. The self-test program runs on the logic resource chip and can be regarded as a verified code. It interacts with the host computer through UART and the controller. IO data loopback self-test is realized. The logic resource chip leads the IO to five FMCs according to different BANKs, groups the pins according to different BNAKs, generates square wave signals of various frequencies in the output group, performs edge detection in the receiving group, generates self-test reports and messages, reports to the controller through the debugging UART, and checks all IO connectivity. The details of the logic resources contained in some logic resource chips are as follows: Figure 8 .
[0052] The upper computer interface of the self-test results is as follows:
[0053] By clicking the [Board Self-Test] button on the interface, the user can view the results of the board self-test in the corresponding function area, such as Fig. 9 As shown, the clarity and repeatability of the operations in the examples are ensured.
[0054] The board self-test function interface is divided into 3 parts:
[0055] [Title bar] The dark label 1 area is mainly used to display the name of the functional module.
[0056] [Parameter configuration area] Dark label 2 and 3 areas are used to display real-time communication results and original communication status data. Fig.10 shown.
[0057] [Execution area] Label 4 area, including 4 function buttons [Start self-test] [Stop] [Save log] [Clear].
[0058] The present invention integrates all the functions and interfaces required by Ethernet, including clock synchronization, PHY driver configuration, data caching and interaction, etc., as follows:
[0059] 1: PTP synchronization.
[0060] 2: Support PTP synchronization, providing accurate time reference for each node in the network.
[0061] 3: PHY driver configuration: includes a set of SPI buses and multiple GPIOs, which can handle many operations such as external PHY chip initialization, configuration, reset, sleep, etc.
[0062] 4: Data caching and interaction.
[0063] 5: Data is read through the interrupt control bus, and a loopback mode is provided for data loopback.
[0064] The upper computer display interface is as follows Figure 3 As shown:
[0065] Label 4 is the connection parameter setting area. The interface initially displays the default communication parameters, which can be modified according to the actual connection parameters of the host computer. After the parameters are confirmed to be correct, click the [Connect] button to achieve communication connection with the host computer; when the software is finished, you can also return to the connection configuration page and click the [Disconnect] button to interrupt the communication connection with the host computer.
[0066] Label 5 is the custom IP setting area. When you first open the software, the [Configure] button is disabled. You need to click the [Connect] button on the upper label 4. The [Configure] button will become clickable after normal communication with the lower computer. After clicking the button, the relevant IP and port parameters in the interface are sent to the lower computer. After the lower computer IP setting takes effect, fill in the parameters just set in the label 4 board IP and port number, reconnect, and achieve mutual communication.
[0067] [Status bar] Red label 6, the left side displays the software version information; the middle part displays the status scroll bar of the test progress; the right side displays the current running status and results of the software.
[0068] The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in the field. Although the embodiments of the present invention have been shown and described, it is understood by ordinary technicians in the field that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present invention. The scope of the present invention is defined by the attached claims and their equivalents.
Claims
1. A verification device suitable for lightweight chip design, characterized in that: It includes a high-performance logic resource chip, a high-flexibility FPGA controller and a host computer. The high-performance logic resource chip includes 2586K System LogicCells, 2364K CLB Flip-Flops, 1182K CLB LUTs, 36.1Mb Dist RAM, 75.9Mb Block RAM, 270Mb Ultra RAM, 6840DSP Slices, and has a high-density, high-speed transceiver as a data transmission interface. The high-flexibility FPGA controller includes a soft core system and a logic system.
2. A verification device suitable for lightweight chip design according to claim 1, characterized in that: The soft core system is responsible for the configuration of onboard devices and the interaction with the host computer. The logic system includes a control bus, Eth, INT, MISC, and PMBUS buses, including a high-speed Ethernet interface for interacting with the host computer, a control bus for CPU control peripherals, a multi-channel clock module, a status cache module, an external EEPROM memory module, and a self-test module.
3. The verification device suitable for lightweight chip design according to claim 2, characterized in that: The control bus of the CPU controlling the peripherals: the internal data interaction bus of the main control chip, one of which is responsible for interacting with Ethernet data, and the other is responsible for interacting with the peripheral bus interface; Self-test module: reserved debugging interface between controller and logic resource chip; Multi-channel clock module: The design includes two si-5345 drivers, each si-5345 outputs 10 clock signals; Status cache module: controls five power supplies, corresponding to different BANK reference voltages of the logic resource chip, supporting 1.2V, 1.35V, 1.5V, and 1,8V; External EEPROM memory module: responsible for storing the last configuration information of all peripherals. Each time the program is started and loaded, the configuration information is automatically read from the EEPROM and sent down.
4. The verification device suitable for lightweight chip design according to claim 2, characterized in that: The state cache module: the soft core integrates the PMBUS command set, is compatible with all power chips that support the PMBUS protocol, and the logic side supports two-way PMBUS switching.
5. The verification device suitable for lightweight chip design according to claim 1, characterized in that: The soft core system is a Sapphire RISC-V soft box processor including a 32-bit processor bit width, 4-512KB dedicated storage, and a 20-400MHz operating frequency.
6. The verification device suitable for lightweight chip design according to claim 1, characterized in that: The self-check test module interacts with the host computer through UART and the high-flexibility FPGA controller.