A model mapping method, device, equipment and storage medium

Abstract

The present invention discloses a model mapping method, device, equipment and storage medium, including obtaining a large-capacity memory model from a chip register transfer level RTL source code; performing mapping operations of memory space reconstruction, mode restoration and port serialization on the large-capacity memory model on an off-chip memory mapping IP; reconnecting the module port to the off-chip memory mapping IP after the mapping operation, and performing port adaptation between the off-chip memory mapping IP and the off-chip memory through an off-chip memory controller. When a large-capacity memory model is identified, while restoring the basic features of the large-capacity memory model on the off-chip memory mapping IP, the parallel port is adjusted to a serial port, thereby automatically mapping the large-capacity memory model of the hardware description language to the off-chip memory without manual intervention, thereby reducing labor costs and improving the accuracy of chip simulation verification.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a model mapping method, device, equipment and storage medium. Background Art

[0002] With the rapid development of the chip industry, in the chip production process, in order to verify whether the produced chips are normal, chip simulation verification is usually required in the early stage of chip development, and in the simulation verification process, the chip hardware description language, such as the register transfer level (RTL) code, needs to be implemented on the FPGA to run. However, due to the limited memory resources on the FPGA chip, when there is a large-scale memory model in the chip hardware description language, the FPGA chip memory resources cannot be directly used.

[0003] Currently, large-capacity memory models in chips usually need to be mapped to off-chip memory in order to normally perform chip simulation acceleration and verification processes. However, currently the only way to map them to off-chip memory is to manually modify the design. This method not only increases labor costs, but also reduces the accuracy of chip simulation verification. Summary of the invention

[0004] The present invention provides a model mapping method to realize mapping of a large-capacity memory model to an off-chip memory, thereby improving the simulation accuracy of a chip.

[0005] According to a first aspect of the present invention, there is provided a model mapping method, comprising: obtaining a large-capacity memory model from a chip register transfer level RTL source code, wherein the large-capacity memory model includes a plurality of module ports;

[0006] Performing mapping operations of memory space reconstruction, mode restoration and port serialization on the large-capacity memory model on an off-chip memory mapping IP, wherein the off-chip memory mapping IP is connected to the off-chip memory;

[0007] The module port is reconnected to the off-chip memory mapping IP after the mapping operation, and the off-chip memory mapping IP is port-adapted with the off-chip memory through an off-chip memory controller.

[0008] Optionally, a large-capacity memory model is obtained from a chip register transfer level RTL source code, including: refining the RTL source code to obtain large-capacity memory parameters, wherein the large-capacity memory parameters include write-side signals and read-side signals; and identifying the large-capacity memory parameters to obtain the large-capacity memory model.

[0009] Optionally, mapping operations of memory space reconstruction, mode restoration and port serialization are performed on the large-capacity memory model on the off-chip memory mapping IP, including: obtaining specified parameters of the large-capacity memory model, wherein the specified parameters include data width, address depth, number of ports and operating mode, and reconstructing the memory space of the large-capacity memory model according to the data width and the address depth on the off-chip memory mapping IP; restoring the mode of the large-capacity memory model according to the operating mode on the off-chip memory mapping IP; and serializing the ports of the large-capacity memory model according to the number of ports on the off-chip memory mapping IP.

[0010] Optionally, the large-capacity memory model is restored on the off-chip memory mapping IP according to the operating mode, including: when it is determined that the operating mode is the synchronous mode, the large-capacity memory model is restored on the off-chip memory mapping IP to the original clock beating first and then processing; when it is determined that the operating mode is the asynchronous mode, the large-capacity memory model is restored on the off-chip memory mapping IP to directly process without beating.

[0011] According to another aspect of the present invention, a model mapping device is provided, the device comprising:

[0012] A large-capacity memory model acquisition module is used to acquire a large-capacity memory model from a chip register transfer level RTL source code, wherein the large-capacity memory model includes a plurality of module ports;

[0013] A mapping operation module, used for performing mapping operations of memory space reconstruction, mode restoration and port serialization on the large-capacity memory model on an off-chip memory mapping IP, wherein the off-chip memory mapping IP is connected to the off-chip memory;

[0014] The port reconnection module is used to reconnect the module port to the off-chip memory mapping IP after the mapping operation, and perform port adaptation between the off-chip memory mapping IP and the off-chip memory through an off-chip memory controller.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0016] at least one processor; and

[0017] a memory communicatively connected to the at least one processor; wherein,

[0018] The memory stores a computer program that can be executed by the at least one processor. The computer program is executed by the at least one processor so that the at least one processor can perform the method described in any embodiment of the present invention.

[0019] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method described in any embodiment of the present invention when executed.

[0020] The technical solution of the embodiment of the present invention, when a large-capacity memory model is identified, performs mapping operations of memory space reconstruction, mode restoration and port serialization on the off-chip memory mapping IP, thereby adjusting the parallel port to a serial port while realizing the restoration of the basic characteristics of the large-capacity memory model, and adapting the off-chip memory mapping IP to the port of the off-chip memory through the off-chip memory controller, thereby automatically mapping the large-capacity memory model of the hardware description language to the off-chip memory without human intervention, thereby reducing labor costs and improving the accuracy of chip simulation verification.

[0021] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 is a flow chart of a model mapping method provided according to the first embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of port serialization of an external memory mapping IP provided in Embodiment 1 of the present invention;

[0025] Figure 3 This is a schematic diagram of port reconnection provided according to Embodiment 1 of the present invention;

[0026] Figure 4 is a flow chart of a model mapping method provided according to Embodiment 2 of the present invention;

[0027] Figure 5 is a structural diagram of a model mapping device provided according to Embodiment 3 of the present invention;

[0028] Figure 6 It is a schematic diagram of the structure of an electronic device provided by Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] Embodiment 1

[0032] Figure 1 A flowchart of a model mapping method is provided for the first embodiment of the present invention. This embodiment is applicable to the case of mapping a large-capacity memory model to an off-chip memory. The method can be implemented by a large-capacity memory model mapping device in the form of hardware and / or software. Figure 1 As shown, the method includes:

[0033] Step S101, obtaining a large-capacity memory model from a chip register transfer level RTL source code.

[0034] Optionally, a large-capacity memory model is obtained from the chip register transfer level RTL source code, including: refining the RTL source code to obtain large-capacity memory parameters, wherein the large-capacity memory parameters include write-side signals and read-side signals; and identifying the large-capacity memory parameters to obtain the large-capacity memory model.

[0035] Specifically, the user's chip RTL source code includes memory parameters, write-side signals and read-side signals, wherein the write-side signal is composed of a write clock, write data, write address and write enable; the read-side signal is composed of a read clock, and the read clock is only in the synchronous mode, read data, read address and read enable. The large-capacity memory model is obtained by identifying the memory parameters, and the large-capacity memory model includes multiple module ports. In this embodiment, the large-capacity memory model is normalized to obtain a large-capacity memory model with a unified format, and a new module port is generated on the other side of the large-capacity memory model, and the format of the newly generated module port is unified and corresponds to the original module port one by one, wherein the types of the newly generated module ports include clock, write address, write data and write enable, and the types of module ports included in the large-capacity memory model are not limited in this embodiment.

[0036] Step S102, performing mapping operations of memory space reconstruction, mode restoration and port serialization on the large-capacity memory model on the off-chip memory mapping IP.

[0037] Optionally, mapping operations of memory space reconstruction, mode restoration and port serialization are performed on the large-capacity memory model on the off-chip memory mapping IP, including: obtaining specified parameters of the large-capacity memory model, wherein the specified parameters include data width, address depth, number of ports and operation mode, and reconstructing the memory space of the large-capacity memory model according to the data width and address depth on the off-chip memory mapping IP; restoring the mode of the large-capacity memory model according to the operation mode on the off-chip memory mapping IP; and serializing the ports of the large-capacity memory model according to the number of ports on the off-chip memory mapping IP.

[0038] Specifically, since the large-capacity memory model cannot be directly connected to the off-chip memory, an off-chip memory mapping IP is added in this embodiment, and the large-capacity memory model is mapped to the off-chip memory IP, that is, the memory space and mode of the large-capacity memory model are reconstructed and restored on the off-chip memory mapping IP, and the port connection mode is updated. And when the large-capacity memory model is mapped on the off-chip memory IP, it is necessary to extract the specified parameters in the model, such as data width, address depth, number of ports and operation mode, wherein the operation mode includes synchronous mode or asynchronous mode, and the above-mentioned memory space reconstruction, model restoration and port serialization are respectively performed based on different parameters.

[0039] Optionally, the large-capacity memory model is restored on the off-chip memory mapping IP according to the operating mode, including: when the operating mode is determined to be the synchronous mode, the large-capacity memory model is restored on the off-chip memory mapping IP to the original clock beating first and then processing; when the operating mode is determined to be the asynchronous mode, the large-capacity memory model is restored on the off-chip memory mapping IP to directly process without beating.

[0040] Optionally, the large-capacity memory model is serialized according to the number of ports on the off-chip memory mapping IP, including: introducing a fast clock according to the number of ports; and converting multi-port parallel processing of the large-capacity memory model into single-port serial processing on the off-chip memory mapping IP based on the fast clock.

[0041] In a specific implementation, an off-chip memory controller is used in this embodiment to reconstruct the memory space of a large-capacity memory model according to data width and address depth, that is, an off-chip memory model with the same capacity rule is reconstructed on an off-chip memory mapping IP, wherein the off-chip memory mapping IP is connected to the off-chip memory; the reconstructed off-chip memory model is restored according to the operation mode, specifically, according to the extracted synchronous mode or asynchronous mode, an equivalent replacement processing is performed on the off-chip memory mapping IP, for example, when it is a synchronous mode, the large-capacity memory model is restored on the off-chip memory mapping IP to the original clock first beating and then processing, and when it is an asynchronous mode, the large-capacity memory model is restored on the off-chip memory mapping IP to directly process without beating; the large-capacity memory model is serialized according to the number of ports, that is, by introducing a fast clock, multi-port parallel processing is converted into single-port serial processing, thereby converting low-speed multi-port memory reading and writing into high-speed off-chip storage.

[0042] For example, Figure 2 The figure shows a port serialization diagram of the external memory mapping IP. Port 1 and port 2 in the original large-capacity storage model are connected in parallel, and after the port serialization processing, port 1 and port 2 are converted into a serial connection, that is, port 1 and port 2 process data in a time sequence. Of course, in this embodiment, only two ports in the large-capacity storage model are used as an example for explanation. When the number of ports increases, the serialization processing method is roughly the same as the above method, and will not be repeated in this embodiment.

[0043] Step S103, reconnecting the module port to the off-chip memory mapping IP after the mapping operation, and performing port adaptation between the off-chip memory mapping IP and the off-chip memory through the off-chip memory controller.

[0044] Optionally, the off-chip memory mapping IP is port-adapted to the off-chip memory through the off-chip memory controller, including: obtaining the port type of the off-chip memory; performing port conversion on the off-chip memory mapping IP according to the port type through the off-chip memory controller to adapt the off-chip memory mapping IP to the port of the off-chip memory.

[0045] Specifically, in this implementation, after the original large-capacity memory model is mapped to the off-chip memory mapping IP, the initially newly generated module port will be reconnected to the off-chip memory mapping IP, wherein the connected ports include clock, write address, write data, and write enable, and the off-chip memory mapping IP is connected to the FPGA off-chip memory, thereby realizing the automatic mapping of the large-capacity storage model of the hardware description language to the FPGA off-chip memory through the off-chip memory mapping IP.

[0046] It should be noted that, in the present embodiment, when connecting with the off-chip memory through the off-chip memory mapping IP, even if the port of the off-chip memory mapping IP is inconsistent with the port type of the off-chip memory, the port of the off-chip memory mapping IP can be adjusted according to the type of the off-chip memory port by the off-chip memory controller, thereby realizing the connection between the off-chip memory mapping IP and the off-chip memory, that is, the communication between the reconstructed and restored large-capacity memory model and the off-chip memory. Of course, the present embodiment is only an example for illustration, and does not limit the specific communication method between the reconstructed and restored large-capacity memory model and the off-chip memory.

[0047] In the implementation mode of the present application, when a large-capacity memory model is identified, mapping operations of memory space reconstruction, mode restoration and port serialization are performed on the off-chip memory mapping IP, thereby adjusting the parallel port to a serial port while realizing the restoration of the basic characteristics of the large-capacity memory model, and adapting the off-chip memory mapping IP to the port of the off-chip memory through the off-chip memory controller, thereby automatically mapping the large-capacity memory model of the hardware description language to the off-chip memory without human intervention, thereby reducing labor costs and improving the accuracy of chip simulation verification.

[0048] Embodiment 2

[0049] Figure 4 This is a flow chart of a model mapping method provided in the second embodiment of the present invention. This embodiment is based on the above embodiment. After the mapping operations of memory space reconstruction, mode restoration and port serialization are performed on the large-capacity memory model on the off-chip memory mapping IP, it also includes: testing the off-chip memory mapping IP after the mapping operation; generating a test report according to the test results. Figure 4 As shown, the method includes:

[0050] Step S201, obtaining a large-capacity memory model from a chip register transfer level RTL source code.

[0051] Optionally, a large-capacity memory model is obtained from the chip register transfer level RTL source code, including: refining the RTL source code to obtain large-capacity memory parameters, wherein the large-capacity memory parameters include write-side signals and read-side signals; and identifying the large-capacity memory parameters to obtain the large-capacity memory model.

[0052] Step S202, performing mapping operations of memory space reconstruction, mode restoration and port serialization on the large-capacity memory model on the off-chip memory mapping IP.

[0053] Optionally, mapping operations of memory space reconstruction, mode restoration and port serialization are performed on the large-capacity memory model on the off-chip memory mapping IP, including: obtaining specified parameters of the large-capacity memory model, wherein the specified parameters include data width, address depth, number of ports and operation mode, and reconstructing the memory space of the large-capacity memory model according to the data width and address depth on the off-chip memory mapping IP; restoring the mode of the large-capacity memory model according to the operation mode on the off-chip memory mapping IP; and serializing the ports of the large-capacity memory model according to the number of ports on the off-chip memory mapping IP.

[0054] Optionally, the large-capacity memory model is restored on the off-chip memory mapping IP according to the operating mode, including: when the operating mode is determined to be the synchronous mode, the large-capacity memory model is restored on the off-chip memory mapping IP to the original clock beating first and then processing; when the operating mode is determined to be the asynchronous mode, the large-capacity memory model is restored on the off-chip memory mapping IP to directly process without beating.

[0055] Optionally, the large-capacity memory model is serialized according to the number of ports on the off-chip memory mapping IP, including: introducing a fast clock according to the number of ports; and converting multi-port parallel processing of the large-capacity memory model into single-port serial processing on the off-chip memory mapping IP based on the fast clock.

[0056] Step S203, testing the off-chip memory mapping IP after the mapping operation, and generating a test report according to the test result.

[0057] Among them, in this implementation, after the large-capacity memory model is mapped on the off-chip mapping memory mapping IP, the off-chip mapping IP after the mapping operation will be tested, and only when the test is determined to pass will the module port be connected to the off-chip memory mapping IP, thereby ensuring the accuracy of the chip simulation.

[0058] Specifically, in this embodiment, when testing, the specification, mode and port connection form of the large-capacity storage model restored on the off-chip memory mapping IP are specifically tested. When it is determined that the rules and modes are consistent with the original large-capacity storage model, and the port connection mode is in series, the test is determined to be passed. When any of the above items does not meet the requirements, the test is determined to be failed. And when the test is completed, a test report will be generated, and the test content will be displayed in the test report. For example, the test report includes the test results of the rules, the test results of the mode, the test results of the port connection form, the reasons for failure and the final test conclusion, etc., and the items that failed the test will be marked with a designated mark, such as a red font, etc. Of course, this embodiment is only an example, and does not limit the specific content included in the test report.

[0059] It should be noted that the test report generated in this embodiment can be displayed on the front-end interface or automatically sent to the monitoring personnel's mobile terminal, so that in the event of a test failure, the monitoring personnel can promptly perform software or hardware maintenance based on the content of the test report.

[0060] Step S204, reconnecting the module port to the off-chip memory mapping IP after the mapping operation, and performing port adaptation between the off-chip memory mapping IP and the off-chip memory through the off-chip memory controller.

[0061] Optionally, the off-chip memory mapping IP is port-adapted to the off-chip memory through the off-chip memory controller, including: obtaining the port type of the off-chip memory; performing port conversion on the off-chip memory mapping IP according to the port type through the off-chip memory controller to adapt the off-chip memory mapping IP to the port of the off-chip memory.

[0062] In the implementation mode of the present application, when a large-capacity memory model is identified, mapping operations of memory space reconstruction, mode restoration and port serialization are performed on the off-chip memory mapping IP, thereby adjusting the parallel port to a serial port while realizing the restoration of the basic characteristics of the large-capacity memory model, and adapting the off-chip memory mapping IP to the port of the off-chip memory through the off-chip memory controller, thereby automatically mapping the large-capacity memory model of the hardware description language to the off-chip memory without human intervention, thereby reducing labor costs and improving the accuracy of chip simulation verification.

[0063] Embodiment 3

[0064] Figure 5 This is a schematic diagram of the structure of a model mapping device provided in Embodiment 3 of the present invention. Figure 5As shown, the device includes: a large-capacity storage model acquisition module 310, a mapping operation module 320 and a port reconnection module 330.

[0065] A large-capacity memory model acquisition module 310 is used to acquire a large-capacity memory model from a chip register transfer level RTL source code, wherein the large-capacity memory model includes a plurality of module ports;

[0066] A mapping operation module 320, for performing mapping operations of memory space reconstruction, mode restoration and port serialization on a large-capacity memory model on an off-chip memory mapping IP, wherein the off-chip memory mapping IP is connected to the off-chip memory;

[0067] The port reconnection module 330 is used to reconnect the module port to the off-chip memory mapping IP after the mapping operation, and perform port adaptation between the off-chip memory mapping IP and the off-chip memory through the off-chip memory controller.

[0068] Optionally, a large-capacity memory model acquisition module is used to refine the RTL source code to obtain large-capacity memory parameters, wherein the large-capacity memory parameters include write-side signals and read-side signals;

[0069] The parameters of the large-capacity storage device are identified to obtain a large-capacity storage device model.

[0070] Optionally, the mapping operation module includes: a specified parameter acquisition unit, used to acquire specified parameters of the large-capacity memory model, wherein the specified parameters include data width, address depth, number of ports and operation mode,

[0071] A memory space reconstruction unit is used to reconstruct the memory space of a large-capacity memory model according to data width and address depth on an off-chip memory mapping IP;

[0072] A mode restoration unit, used for restoring the mode of the large-capacity memory model according to the operation mode on the off-chip memory mapping IP;

[0073] The port serialization unit is used to serialize the ports of the large-capacity memory model according to the number of ports on the off-chip memory mapping IP.

[0074] Optionally, a mode restoration unit is used to restore the large-capacity memory model to the original clock first and then process it on the off-chip memory mapping IP when the operating mode is determined to be the synchronous mode;

[0075] When the operation mode is determined to be the asynchronous mode, the large-capacity memory model is restored on the off-chip memory mapping IP to be directly processed without a beat.

[0076] Optionally, a port serialization unit for introducing a fast clock according to the number of ports;

[0077] Converts multi-port parallel processing of large memory models to single-port serial processing on off-chip memory-mapped IP based on a fast clock.

[0078] Optionally, a port reconnection module is used to obtain the port type of the off-chip memory;

[0079] The off-chip memory mapping IP is port-converted according to the port type through the off-chip memory controller, so that the off-chip memory mapping IP is adapted to the port of the off-chip memory.

[0080] Optionally, the device further comprises a testing module, which is used to test the off-chip memory mapping IP after the mapping operation;

[0081] Generate a test report based on the test results.

[0082] The model mapping device provided in the embodiment of the present invention can execute the model mapping method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0083] Embodiment 4

[0084] Figure 6 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0085] like Figure 6 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0086] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0087] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as the model mapping method.

[0088] In some embodiments, the model mapping method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the model mapping method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the model mapping method in any other appropriate manner (e.g., by means of firmware).

[0089] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0090] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0091] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0092] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0093] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0094] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0095] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0096] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A model mapping method, characterized in that: include: Acquire a large-capacity memory model from a chip register transfer level RTL source code, wherein the large-capacity memory model includes a plurality of module ports; Performing mapping operations of memory space reconstruction, mode restoration and port serialization on the large-capacity memory model on an off-chip memory mapping IP, wherein the off-chip memory mapping IP is connected to the off-chip memory; The module port is reconnected to the off-chip memory mapping IP after the mapping operation, and the off-chip memory mapping IP is port-adapted with the off-chip memory through an off-chip memory controller.

2. The method according to claim 1, characterized in that The method of obtaining a large-capacity memory model from a chip register transfer level RTL source code includes: Refining the RTL source code to obtain large-capacity memory parameters, wherein the large-capacity memory parameters include write-side signals and read-side signals; The mass storage device parameters are identified to obtain the mass storage device model.

3. The method according to claim 1, characterized in that The mapping operation of performing memory space reconstruction, mode restoration and port serialization on the large-capacity memory model on the off-chip memory mapping IP includes: Obtaining specified parameters of the mass storage model, wherein the specified parameters include data width, address depth, number of ports, and operation mode, Reconstructing the memory space of the large-capacity memory model on the off-chip memory mapping IP according to the data width and the address depth; Performing mode restoration on the large-capacity memory model according to the operation mode on the off-chip memory mapping IP; The large-capacity memory model is serialized on the off-chip memory mapping IP according to the number of ports.

4. The method according to claim 3, characterized in that: The performing mode restoration on the large-capacity memory model according to the operation mode on the off-chip memory mapping IP comprises: When it is determined that the operation mode is the synchronous mode, the large-capacity memory model is restored to the original clock on the off-chip memory mapping IP and then processed; When it is determined that the operation mode is the asynchronous mode, the large-capacity memory model is restored on the off-chip memory mapping IP to directly process without beating.

5. The method according to claim 3, characterized in that: The port serialization of the large-capacity memory model according to the number of ports on the off-chip memory mapping IP includes: Introducing a fast clock according to the number of ports; The multi-port parallel processing of the large-capacity memory model is converted into a single-port serial processing on the off-chip memory mapping IP based on the fast clock.

6. The method according to claim 1, characterized in that The method of performing port adaptation between the off-chip memory mapping IP and the off-chip memory through an off-chip memory controller includes: Obtaining the port type of the off-chip memory; The off-chip memory mapping IP is port-converted according to the port type by the off-chip memory controller, so that the off-chip memory mapping IP is adapted to the port of the off-chip memory.

7. The method according to claim 1, characterized in that After the mapping operations of memory space reconstruction, mode restoration and port serialization are performed on the large-capacity memory model on the off-chip memory mapping IP, the method further includes: Testing the off-chip memory mapping IP after the mapping operation; A test report is generated according to the test results.

8. A model mapping method and device, characterized in that: The device comprises: A large-capacity memory model acquisition module is used to acquire a large-capacity memory model from a chip register transfer level RTL source code, wherein the large-capacity memory model includes a plurality of module ports; A mapping operation module, used for performing mapping operations of memory space reconstruction, mode restoration and port serialization on the large-capacity memory model on an off-chip memory mapping IP, wherein the off-chip memory mapping IP is connected to the off-chip memory; The port reconnection module is used to reconnect the module port to the off-chip memory mapping IP after the mapping operation, and perform port adaptation between the off-chip memory mapping IP and the off-chip memory through an off-chip memory controller.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the method according to any one of claims 1 to 7 when executed.

Images