Signal link simulation method and device and electronic equipment

Abstract

The embodiment of the invention provides a signal link simulation method and device and electronic equipment, and the method comprises the steps: constructing a simulation optical module electric connector model and a BGA simulation system model based on a simulation PCB model in a simulation space; combining to obtain a full-link simulation model; performing simulation model signal integrity simulation on the full-link simulation model to obtain a target full-link simulation model; and obtaining full-link circuit design parameters meeting process requirements according to the target full-link simulation model. A simulation component model capable of reflecting characteristic parameters of components is constructed, and a full-link simulation model is constructed according to an actual target working environment. Compared with a component model provided by a manufacturer, the constructed simulation model is higher in precision, better simulation performance can be provided in simulation design work, and actual parameter characteristics of components are reflected; and meanwhile, targeted design can be carried out aiming at the target working environment in simulation design work, so that the design flexibility is improved, and the optimizability of a simulation design product is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of radio frequency technology, and in particular to a signal link simulation method, device and electronic equipment. Background Art

[0002] In the existing simulation design process, the stacking scheme provided by the printed circuit board (PCB) board factory and the model provided by the component manufacturer are generally used for modeling and simulation. According to the existing simulation design method, in the simulation design work, only the stacking scheme provided by the board factory can be verified, and the stacking design is not involved. It is impossible to carry out targeted design for different situations. The design is not flexible enough, which limits the optimizability of the simulation design product; for the accuracy of signal integrity simulation, it only relies on the parameters provided by the PCB manufacturer or the board manufacturer for simulation, and cannot accurately simulate the real channel characteristics. At the same time, the component model used in the existing simulation design method is provided by the manufacturer, and the manufacturer only provides simple structural parameters such as external dimensions. The electrical performance cannot be accurately characterized, the accuracy is limited, the simulation is poor, and the actual characteristic parameters of the components cannot be reflected. In order to solve the above problems, a new simulation design method is needed. Summary of the invention

[0003] The embodiments of the present disclosure provide a signal link simulation method, device and electronic device to solve the problems in existing simulation design methods, such as poor product optimizability, low design flexibility, poor simulation, and inability to reflect the actual characteristic parameters of components during the simulation process.

[0004] Based on the above problems, in a first aspect, an embodiment of the present disclosure provides a signal link simulation method, including: Construct a simulation PCB model, a simulation optical module electrical connector model, and a BGA simulation system model in the simulator respectively; The simulated PCB model, the simulated optical module electrical connector model and the BGA simulation system model are combined to obtain a full-link simulation model; The full-link simulation model is subjected to a simulation model signal integrity simulation to obtain target signal link design parameters corresponding to preset test indicators.

[0005] In combination with the first aspect, in a possible implementation manner, respectively constructing a simulated PCB model, a simulated optical module electrical connector model, and a ball grid array package (BGA) simulation system model in the simulator includes: Based on the first preset PCB parameters, a first connection area simulation PCB model representing the connection area where the optical module electrical connector is located in the PCB hardware environment is determined; wherein the first connection area simulation PCB model provides a PCB hardware environment for the basic functions of the optical module electrical connector; According to the gold finger of the optical module to be plugged and connected with the electrical connector of the optical module, a gold finger model of the simulated optical module is constructed; In the first simulation space of the simulator, a first simulated optical module electrical connector model is constructed based on the first connection area simulated PCB model, the simulated optical module gold finger model and the optical module electrical connector parameters; wherein the optical module electrical connector parameters include at least one of the three-dimensional image data, physical structure composition and technical data of the corresponding optical module electrical connector, so that the obtained first simulated optical module electrical connector model includes a hardware structure and can realize a preset simulation function.

[0006] In combination with the first aspect, in a possible implementation manner, after building the first simulated optical module electrical connector model, the method further includes: According to the preset simulation function, a first simulation test is performed on the first simulation optical module electrical connector model to obtain simulation data; Comparing the simulation data with technical parameters of the corresponding preset simulation function to obtain a comparison result; According to the comparison result, the first simulated optical module electrical connector model is adjusted, and a second simulation test is performed until the simulation data obtained by the adjusted first simulated optical module electrical connector model meets the technical parameters of the corresponding preset simulation function, thereby obtaining a simulated optical module electrical connector model; The first simulation test and the second simulation test respectively include at least one of the following: time domain reflectometry (TDR) test, insertion loss scattering (S, Scatter) 21 test, group delay test, and channel isolation test.

[0007] In combination with the first aspect, in a possible implementation manner, adjusting the first simulated optical module electrical connector model according to the comparison result includes: According to the comparison result, the hardware structure of the first simulated optical module electrical connector model is adjusted; wherein the hardware structure includes at least one of the following: the size of the solder pad inside the first simulated optical module electrical connector model, the size of the transmission line inside the first simulated optical module electrical connector model, the size of the anti-pad inside the first simulated optical module electrical connector model, and the PCB design of the first simulated optical module electrical connector model.

[0008] In combination with the first aspect, in a possible implementation manner, respectively constructing a simulated PCB model, a simulated optical module electrical connector model, and a BGA simulated system model in the simulator includes: Obtaining target PCB parameters; the target PCB parameters include: target operating frequency, number of differential signals, integrated circuit (IC) pin type, and IC pin distribution; In a second simulation space of the simulator, the simulated PCB model is constructed based on the target PCB parameters.

[0009] In combination with the first aspect, in a possible implementation manner, constructing the simulated PCB model based on the target PCB parameters includes: According to the target operating frequency, based on the corresponding relationship between the operating frequency and the PCB material, determining the PCB material to be used; According to the number of differential signals and based on the differential signal line routing principle, determining the differential line width and spacing; According to the IC pin type and IC pin distribution, based on the PCB fan-out principle, fan-out routing solution; Determine the PCB stacking layout based on the PCB material, the differential trace width and spacing, and the trace scheme; The simulated PCB model is constructed based on the PCB stacking layout and target finite conductor boundary conditions.

[0010] In combination with the first aspect, in a possible implementation manner, before constructing the simulated PCB model based on the PCB stacking layout and the target finite conductor boundary condition, the method further includes: Obtaining, in a hardware environment, a first insertion loss value of a transmission line of a first length in a through transmission line test board corresponding to a second preset PCB parameter at a first frequency; Constructing a simulated straight-through transmission line model in a third simulation space of the simulator; wherein the simulated straight-through transmission line model is constructed based on the second preset PCB parameters; and the simulated straight-through transmission line model includes at least one simulated transmission line with a first length; Perform at least two third simulation tests on the simulated straight-through transmission line model at a first frequency, set a finite conductor boundary condition corresponding to the third simulation test for the test transmission line for each third simulation test, and determine an insertion loss value corresponding to the finite conductor boundary condition in the third simulation test according to the power of an input signal of the test transmission line and the power of an output signal of the transmission line in the third simulation test, to obtain multiple sets of finite conductor boundary conditions and insertion loss values; Based on multiple groups of finite conductor boundary conditions and insertion loss values, an insertion loss curve reflecting the relationship between the finite conductor boundary conditions and the insertion loss value is obtained by fitting; The target finite conductor boundary condition corresponding to the first insertion loss value is obtained through the insertion loss curve.

[0011] In combination with the first aspect, in a possible implementation manner, respectively constructing a simulated PCB model, a simulated optical module electrical connector model, and a BGA simulated system model in the simulator includes: Based on the third preset PCB parameter, a second connection area simulation PCB model representing the connection area where the BGA minimum system is located in the PCB hardware environment is determined; wherein the BGA minimum system is a basic unit capable of realizing a signal transmission function; In a fourth simulation space of the simulator, based on the simulation PCB model of the second connection area, a BGA minimum system simulation model is constructed; Based on the BGA minimum system simulation model, a signal transmission characteristic test is performed to obtain a communication test result, and a BGA simulation system model parameter is determined according to the communication test result; and The BGA simulation system model is constructed based on the BGA simulation system model parameters.

[0012] In combination with the first aspect, in a possible implementation manner, based on the BGA minimum system simulation model, a signal transmission characteristic test is performed to obtain a communication test result, and a BGA simulation system model parameter is determined according to the communication test result; and the BGA simulation system model is constructed based on the BGA simulation system model parameters, including: Based on the BGA minimum system simulation model, a signal transmission characteristic test is performed between the minimum simulation communication peer end arranged above the BGA minimum system simulation model to obtain a communication test result; Comparing the communication test result with the preset target communication parameter, and adjusting the BGA minimum system simulation model according to the obtained comparison result to obtain the target BGA minimum system simulation model; Based on the target BGA minimum system simulation model, BGA simulation system model parameters are obtained, and the BGA simulation system model is constructed.

[0013] In combination with the first aspect, in a possible implementation, adjusting the BGA minimum system simulation model includes: adjusting at least one of a differential pair wiring distance, a via number, a via structure, and a pad size.

[0014] In combination with the first aspect, in a possible implementation manner, the minimum simulated communication peer end is of a coaxial type; and / or the size of the minimum simulated communication peer end corresponds to the pad size in the BGA minimum system simulation model.

[0015] In combination with the first aspect, in a possible implementation manner, performing simulation model signal integrity simulation on the full-link simulation model to obtain target signal link design parameters corresponding to preset test indicators includes: Performing simulation model signal integrity simulation on the full-link simulation model to obtain a simulation result; The simulation result is compared with the preset test index, and according to the obtained comparison result, the full-link simulation model is adjusted to obtain a target full-link simulation model; wherein the adjustment of the full-link simulation model includes at least one of the following: pad size, transmission line size, anti-pad size, PCB stacking design structure; Based on the target full-link simulation model, target signal link design parameters corresponding to preset test indicators are obtained.

[0016] According to a second aspect of the present disclosure, a signal link simulation device is provided, including: A first model building module, wherein the first model building module is used to obtain a full-link simulation model in the simulator; wherein the full-link simulation model is based on a combination of the simulated PCB model, the simulated optical module electrical connector model and the BGA simulation system model; The first simulation test module is used to perform a simulation model signal integrity simulation test on the full-link simulation model to obtain target signal link design parameters corresponding to preset test indicators.

[0017] A third aspect of the embodiments of the present disclosure provides an electronic device, including: a signal link simulation device as described in the second aspect.

[0018] The beneficial effects of the embodiments of the present disclosure include: The present disclosure provides a signal link simulation method, device and electronic device, including: Construct a simulated PCB model in the first simulation space of the simulator; based on the simulated PCB model, construct a simulated optical module electrical connector model and a BGA simulation system model; combine the simulated PCB model, the simulated optical module electrical connector model and the BGA simulation system model to obtain a full-link simulation model; wherein, the simulated PCB model is constructed according to the PCB hardware environment when the optical module electrical connector is working; the BGA simulation system model is constructed according to the controller connected to the PCB hardware environment; according to the preset test indicators, the simulation model signal integrity simulation is performed on the full-link simulation model to obtain a first simulation test result; the first simulation test result is compared with the corresponding indicator requirement, and according to the comparison result, the full-link simulation model is adjusted; and the simulation test is re-performed until the simulation data obtained by the adjusted full-link simulation model meets the corresponding target technical parameters to obtain the target full-link simulation model; according to the target full-link simulation model, the full-link circuit design parameters that meet the process requirements are obtained.

[0019] A signal link simulation method, device and electronic device in the disclosed embodiments constructs a simulation component model that can reflect the characteristic parameters of the component itself, constructs a simulation PCB model according to the actual target working environment, and constructs a simulation optical module electrical connector model and a BGA simulation system model on this basis. The simulation model constructed according to this method is more accurate than the component model provided by the manufacturer, and can provide better simulation performance in the simulation design work, reflecting the actual parameter characteristics of the components; at the same time, targeted design can be carried out for the target working environment in the simulation design work, improving the flexibility of the design and increasing the optimizability of the simulation design product. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flow chart of a signal link simulation method provided by an embodiment of the present disclosure; Figure 2a A schematic diagram of a through transmission line test board provided in an embodiment of the present disclosure; Figure 2b A schematic diagram of a simulated straight-through transmission line model provided by an embodiment of the present disclosure; Figure 3 A schematic diagram of a BGA minimum system simulation model provided by an embodiment of the present disclosure; Figure 4 A schematic diagram of the structure of a signal link simulation device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The embodiments of the present disclosure provide a signal link simulation method, device and electronic device. The preferred embodiments of the present disclosure are described below in conjunction with the drawings of the specification. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure. In addition, the embodiments in the present application and the features in the embodiments can be combined with each other if there is no conflict.

[0022] The present disclosure provides a signal link simulation method. Figure 1 As shown, including: S101, respectively constructing a simulation PCB model, a simulation optical module electrical connector model, and a BGA simulation system model in the simulator; S102, combining the simulated PCB model, the simulated optical module electrical connector model, and the BGA simulation system model to obtain a full-link simulation model; S103, performing simulation model signal integrity simulation on the full-link simulation model to obtain target signal link design parameters corresponding to preset test indicators.

[0023] In the disclosed embodiment, the optical module electrical connector is used to connect the optical module to the relevant instrument. During implementation, the optical module can be connected to the corresponding optical module electrical connector, and communicate with other components on the PCB board through the optical module electrical connector. The PCB board connected to the optical module electrical connector can also be provided with a main control chip, and the main control chip can be set on the PCB board through BGA. The optical module related instruments may include optical module testers, spectrometers, optical switches and other equipment. There are few simulation schemes for optical module electrical connectors in the related art, especially for the full-link simulation of PCB boards provided with optical module electrical connectors and BGA. In addition, the optical module related instruments can set multiple optical module electrical connectors to perform related operations on multiple optical modules at the same time, and here the simulation is performed for one of the optical module electrical connectors.

[0024] In the disclosed embodiment, the simulated PCB model, the simulated optical module electrical connector model and the BGA simulation system model are combined in the simulation space of the simulator, the simulated optical module electrical connector model pins are connected to the corresponding simulated optical module electrical connector pad positions on the simulated PCB model, the BGA simulation system model is placed in the BGA area of ​​the simulated PCB model, and a coaxial model is established at the opposite end of the BGA simulation system model. The target finite conductor condition is applied to the simulated PCB model to form a full-link simulation model.

[0025] Furthermore, the full-link simulation model is subjected to simulation model signal integrity simulation. During the test, the simulated optical module gold finger model is connected to the corresponding position of the simulated optical module electrical connector model to perform a simulation signal test to obtain a simulation result.

[0026] Furthermore, the simulation results are compared with the corresponding index requirements, and based on the comparison results, the corresponding positions of the full-link model are adjusted so that the data obtained from the simulation test meet the corresponding target technical parameters, the target full-link simulation model is completed, and the target full-link circuit design parameters that meet the process requirements are obtained based on the target full-link simulation model.

[0027] In another embodiment provided by the present disclosure, in the above step S101 “respectively constructing a simulated PCB model, a simulated optical module electrical connector model and a BGA simulated system model in the simulator”, “constructing a simulated PCB model” can be implemented as follows: Step 1: Based on the first preset PCB parameters, determine a first connection area simulation PCB model representing the connection area where the optical module electrical connector is located in the PCB hardware environment; wherein the first connection area simulation PCB model provides a PCB hardware environment for the basic functions of the optical module electrical connector; Step 2: construct a simulated optical module gold finger model according to the optical module gold finger to be plugged and connected to the optical module electrical connector; Step three, in the first simulation space of the simulator, based on the first connection area simulation PCB model, the simulation optical module gold finger model and the optical module electrical connector parameters, construct a first simulated optical module electrical connector model; wherein the optical module electrical connector parameters include at least one of the three-dimensional image data, physical structure composition and technical data of the corresponding optical module electrical connector, so that the obtained first simulated optical module electrical connector model includes a hardware structure and can realize the preset simulation function.

[0028] In the related art, the simulation model of the optical module electrical connector is provided by the manufacturer. The simulation model provided by the manufacturer is a black box model, which only has the corresponding appearance. Its simulation function is realized by preset parameters, and it cannot simulate the internal hardware structure of the optical module electrical connector. In the embodiment of the present disclosure, the simulation model of the optical module electrical connector is constructed using the three-dimensional image model, physical structure composition and technical data provided by the manufacturer. In terms of hardware, the three-dimensional image model is used to construct the overall structural appearance; the product structure diagram and the disassembly of the physical product are used to obtain its internal hardware structure composition, and the hardware simulation structure is constructed according to its hardware structure composition; in terms of software, the preset simulation function is simulated according to the functions and technical data that the optical module electrical connector needs to support.

[0029] In actual applications, the optical module electrical connector needs to be connected to the PCB board where it is located. When the optical module is inserted into the optical module electrical connector, it also needs to be connected to the optical module through the gold finger. The hardware environment of the visible optical module electrical connector is composed of the PCB board where it is located and the gold finger connected to the optical module. In order to make the simulation test more accurate and reasonable, it is also necessary to establish a first connection area simulation PCB model of the optical module electrical connector connection area and an optical module gold finger model to characterize the PCB hardware environment of the optical module electrical connector in the PCB hardware environment. The first preset PCB parameters can be the PCB parameters of the target working environment of the optical module electrical connector.

[0030] It should be noted that, in the process of simulating and testing the optical module electrical connector model, the first connection area simulation PCB model can construct a pad connected to the pin of the optical module electrical connector model and a transmission line connected to the pad. The pin of the optical module electrical connector model is connected to the corresponding transmission line on the first connection area simulation PCB model through the pad; the optical module gold finger model is established based on the packaging standard of the optical module connected to the optical module electrical connector. Insert the simulated optical module gold finger model into the corresponding connection area of ​​the simulated optical module electrical connector model, so that the transmission line of the simulated optical module gold finger model is connected to the corresponding transmission line in the simulated optical module electrical connector model. That is, the construction of the corresponding hardware environment of the optical module electrical connector is completed.

[0031] As for the preset simulation function, during the simulation test of the constructed simulated optical module electrical connector model, the obtained simulation test results can be compared with the corresponding technical parameters in the technical data provided by the manufacturer. The simulated optical module electrical connector model is adjusted according to the comparison results, and the adjusted simulated optical module electrical connector model is re-simulated and tested until the difference between the technical parameters of the simulated optical module electrical connector model and the technical parameters of the manufacturer is within the preset range, and the target simulated optical module electrical connector model is obtained.

[0032] It can be seen that in the embodiments of the present disclosure, both the hardware level and the software level can be flexibly designed and adjusted according to actual needs, which can provide better simulation performance in the simulation design work and reflect the actual parameter characteristics of the components; at the same time, in the simulation design work, targeted design can be carried out for the target working environment, providing design flexibility and increasing the optimizability of the simulation design product.

[0033] In another embodiment provided by the present disclosure, after the step of “building a first simulated optical module electrical connector model” in the above step three, the following further comprises: Step 1: performing a first simulation test on the first simulation optical module electrical connector model according to a preset simulation function to obtain simulation data; Step 2: Compare the simulation data with the technical parameters of the corresponding preset simulation function to obtain a comparison result; Step 3: According to the comparison result, the first simulated optical module electrical connector model is adjusted, and a second simulation test is performed until the simulation data obtained by the adjusted first simulated optical module electrical connector model meets the technical parameters of the corresponding preset simulation function, thereby obtaining the simulated optical module electrical connector model; The first simulation test and the second simulation test respectively include at least one of the following: a TDR test, an insertion loss S21 test, a group delay test, and an inter-channel isolation test.

[0034] In the disclosed embodiment, the TDR test is a test method that uses the reflected signal to infer the impedance of the optical module electrical connector model, and is used to verify whether the impedance of the simulated optical module electrical connector model is consistent with the impedance parameter in the corresponding technical parameters. During the TDR test, a short pulse signal can be sent by the simulated signal generator to be transmitted to the input end of the simulated optical module electrical connector model through the optical module gold finger model, and the reflected signal at different times during the propagation of the signal in the simulated optical module electrical connector model is monitored. According to the reflection principle, the reflection coefficient ;in is the amplitude of the reflected signal at a certain moment; is the incident signal amplitude; is the impedance of the device to be tested, and in this embodiment, is the impedance of the electrical connector model of the simulated optical module; is the input impedance of the TDR, which is 50Ω in this embodiment. During the TDR test, and can be measured by a simulated oscilloscope and and The reflection coefficient is obtained by comparing , and thus the impedance of the device under test is obtained This impedance value reflects the impedance value of the pulse signal at a certain moment, and an impedance change curve is formed according to the corresponding relationship between time and impedance value. The location where the impedance change curve shows obvious changes is the impedance discontinuity point, which corresponds to the location where the transmission line size changes in the PCB, the routing corners, and the pads and anti-pads.

[0035] The corresponding impedance discontinuity point is adjusted, and the simulated impedance curve of the simulated optical module electrical connector model is adjusted to be close to the impedance curve of the corresponding optical module electrical connector.

[0036] Furthermore, the insertion loss S21 test is to determine the loss of load power of the optical module electrical connector by monitoring the input signal and output signal value of the simulated optical module electrical connector model. During the insertion loss S21 test, a signal is sent by the simulated signal transmitter and transmitted to the input end of the simulated optical module electrical connector model through the optical module gold finger model, and the input power of the signal and the power of the output simulated optical module electrical connector model are monitored. ,in is the signal input power value, is the signal output power value, is the S21 parameter. The insertion loss value and the S21 parameter are compared with the insertion loss value and the S21 parameter value of the corresponding optical module electrical connector to obtain the corresponding difference. Based on the comparison result, the corresponding part of the simulated optical module electrical connector model is adjusted so that the corresponding difference is less than the preset range.

[0037] Furthermore, the group delay test is used to measure the relative delay between signals when the signals pass through the simulated optical module electrical connector model, and the distortion of the signal system is determined by the group delay.

[0038] Furthermore, the inter-channel isolation test is to determine the degree of signal leakage between different signal channels by measuring the impact of the input signal in any signal channel on other signal channels. During the inter-channel isolation test, the simulated signal generator transmits a signal to any signal channel input end of the simulated optical module electrical connector model through the optical module gold finger model, and monitors the amplitude of the input signal, and monitors the output signal amplitude at the output end of other signal channels. Isolation parameters ,in is the amplitude of the input signal, The isolation parameter is compared with the target channel isolation parameter of the corresponding optical module electrical connector, and the corresponding part of the simulated optical module electrical connector model is adjusted based on the comparison result.

[0039] In another embodiment provided by the present disclosure, in the above step 3, “adjusting the first simulated optical module electrical connector model according to the comparison result” can be implemented as follows: According to the comparison results, the hardware structure of the first simulated optical module electrical connector model is adjusted; wherein the hardware structure includes at least one of the following: the size of the solder pad inside the first simulated optical module electrical connector model, the size of the transmission line inside the first simulated optical module electrical connector model, the size of the anti-pad inside the first simulated optical module electrical connector model, and the PCB design of the first simulated optical module electrical connector model.

[0040] In the disclosed embodiment, the position of the optical module electrical connector corresponding to different impedance discontinuities in the impedance curve is determined according to the comparison between the simulated impedance curve obtained by TDR test and the impedance curve of the corresponding optical module electrical connector. For different positions, the position can be adjusted according to the corresponding adjustment method to obtain the required impedance. For the pad position in the simulated optical module electrical connector model, the diameter of the pad will affect the size of the capacitive load, thereby affecting the impedance value; the larger the pad diameter, the larger the capacitive load and the smaller the impedance; the smaller the pad diameter, the smaller the capacitive load and the larger the impedance. For the anti-pad position in the simulated optical module electrical connector model, the larger the anti-pad, the smaller the capacitive load at the via position and the smaller the via impedance; the smaller the anti-pad, the larger the capacitive load at the via position and the larger the impedance. For the transmission line size in the simulated optical module electrical connector model, increasing the transmission line width can reduce the impedance, and reducing the transmission line width can increase the impedance. For the via position in the simulated optical module electrical connector model, for vias with residual holes, grounding holes are added around to reduce impedance.

[0041] Optionally, according to the comparison results obtained from the aforementioned insertion loss S21 test, the corresponding position of the simulated optical module electrical connector model is adjusted. For the anti-pad position in the simulated optical module electrical connector model, the anti-pad size can be increased to reduce the insertion loss and increase the S21 parameter; the anti-pad size can be reduced to increase the insertion loss and reduce the S21 parameter. For the PCB stacking design in the simulated optical module electrical connector model, the width between transmission lines can be increased to reduce the insertion loss; the stacking combination of the signal layer and the ground layer can be adjusted to reduce crosstalk and reduce insertion loss. In the actual PCB production process, the finite conductor boundary conditions after the transmission line processing can be changed by selecting a suitable low-roughness transmission line and treating the transmission line with a browning solution to optimize the insertion loss.

[0042] Optionally, the distortion of the signal system is determined by the group delay test, which is used to measure the relative delay between signals when the signals pass through the electrical connector of the simulated optical module.

[0043] Optionally, according to the comparison results obtained from the isolation test between channels, the corresponding position of the simulated optical module electrical connector model is adjusted to adjust the isolation within the target range. For the distance between the transmission lines corresponding to the signal channels, the closer the spacing between the transmission lines of different channels, the higher the coupling and the lower the isolation; the farther the spacing between the transmission lines of different channels, the lower the coupling and the higher the isolation. The closer the spacing between the transmission lines in the same channel, the higher the isolation between different channels; the farther the spacing between the transmission lines in the same channel, the lower the isolation between different channels. For the dielectric structure of the PCB in the simulated optical module electrical connector model, shielding materials can be added between the signal channels to improve the isolation. For the dielectric constant of the PCB in the simulated optical module electrical connector model, the dielectric constant of the PCB substrate can be reduced to improve the isolation.

[0044] Optionally, the impedance curve of the optical module electrical connector model is changed to match the target impedance by modifying the pin structure and connection mode of the optical module electrical connector model.

[0045] In another embodiment provided by the present disclosure, in the above step S101 of "respectively constructing a simulated PCB model, a simulated optical module electrical connector model and a BGA simulation system model in the simulator", "constructing a simulated PCB model" includes: Step 1: Obtain target PCB parameters; target PCB parameters include: target operating frequency, number of differential signals, IC pin type, and IC pin distribution; Step 2: In the second simulation space of the simulator, a simulated PCB model is constructed based on the target PCB parameters.

[0046] In the disclosed embodiment, the target PCB parameters are determined based on the requirements of the target product. For the target operating frequency, the selection guide of substrate material and operating frequency provided by the manufacturer of the relevant PCB substrate material can be referred to for selection. For high-frequency links, materials with smaller dielectric constant and dielectric loss factor can be considered.

[0047] In another embodiment provided by the present disclosure, in the above step 1, "building a simulated PCB model based on target PCB parameters" can be implemented as follows: Step 1: Determine the PCB material to be used based on the target operating frequency and the corresponding relationship between the operating frequency and the PCB material; Step 2: Determine the differential trace width and spacing based on the number of differential signals and the differential signal line routing principles; Step 3: According to the IC pin type and IC pin distribution, based on the PCB fan-out principle, fan-out routing solution; Step 4: Determine the PCB stackup layout based on the PCB material, differential trace width and spacing, and trace plan; Step 5: Build a simulation PCB model based on the PCB stack-up layout and target finite conductor boundary conditions.

[0048] In the disclosed embodiment, step 1, based on the target operating frequency, select the PCB substrate material, the PCB substrate material includes polytetrafluoroethylene resin (PTFE), epoxy resin (EP), bismaleimide triazine resin (BT), thermosetting cyanate resin (CE), etc. For PCBs with higher target operating frequencies, materials with lower dielectric constants are selected; step 2, according to the number of differential signals, design the differential trace width and spacing, a pair of differential traces are equal in length and width, and are located on the same layer, and different differential line pairs are isolated by grounding points or maintained at a preset distance. For the case where there are a large number of differential signals, the number of signal layers can be increased accordingly to avoid too many differential transmission lines in a single signal layer; Step 3, according to the IC pin type and IC pin distribution, adjust the transmission line width and spacing at the IC pin, as well as the aperture of the via; Step 4, more stacked PCBs can provide a complete ground layer and power plane, decoupling capacitor grounding is convenient, the voltage drop of the power distribution network is lower, and the routing of the transmission line in the layer is simpler, which also has a positive effect on suppressing interference and signal leakage between transmission lines; PCBs with fewer stacking numbers have lower costs; Step 5, set finite conductor boundary conditions for the transmission lines of the simulated PCB model, where the finite conductor boundary conditions can be described by roughness parameters, which are a series of parameters that describe the unevenness of the conductor surface, and they have an important influence on the signal transmission characteristics in the high-frequency link. In high-frequency signal transmission, the skin effect causes the signal to tend to be transmitted on the conductor surface, so the roughness of the conductor surface will directly affect the transmission efficiency and loss of the signal. In order to better simulate the impact of the signal link on the corresponding signal transmission in a high-frequency working environment, it is necessary to add the roughness parameter value in the simulated PCB model; According to the above steps, a simulated PCB model is constructed.

[0049] In another embodiment provided by the present disclosure, the above step 5 "building a simulated PCB model based on the PCB stacking layout and the target finite conductor boundary conditions" also includes the following steps: Step 1: obtaining a first insertion loss value of a transmission line of a first length in a through transmission line test board corresponding to a second preset PCB parameter at a first frequency in a hardware environment; Step 2: constructing a simulated straight-through transmission line model in a third simulation space of the simulator; wherein the simulated straight-through transmission line model is constructed based on a second preset PCB parameter; and the simulated straight-through transmission line model includes at least one simulated transmission line having a first length; Step 3: Perform at least two third simulation tests on the simulated straight-through transmission line model at the first frequency. For each third simulation test, set a finite conductor boundary condition corresponding to the third simulation test for the test transmission line, and determine an insertion loss value corresponding to the finite conductor boundary condition in the third simulation test according to the input power of the input signal of the test transmission line and the output power of the transmission output signal of the third simulation test, and obtain multiple sets of finite conductor boundary conditions and insertion loss values; Step 4: Based on multiple sets of finite conductor boundary conditions and insertion loss values, an insertion loss curve reflecting the relationship between the finite conductor boundary conditions and the insertion loss value is obtained by fitting; Step 5: Obtain the target finite conductor boundary condition corresponding to the first insertion loss value through the insertion loss curve.

[0050] In the disclosed embodiments, PCB manufacturers have different recommended products for different operating frequencies. PCB manufacturers generally provide parameters including loss tangent value, substrate material, transmission line material, substrate dielectric constant, etc., but these parameters do not include finite conductor boundary conditions. Failure to use accurate finite conductor boundary conditions for simulation testing will have an adverse effect on the realism of simulation results in high-frequency working environments. The disclosed embodiments provide a method for obtaining finite conductor boundary conditions using a fitting method.

[0051] In the disclosed embodiment, the acquisition of the first insertion loss value needs to be performed based on a straight-through transmission line test board in a hardware environment. The straight-through transmission line test board is constructed in the hardware environment based on the second preset PCB parameters; wherein the second preset PCB parameters may be parameters provided by the PCB manufacturer, including loss tangent value, substrate material, transmission line material, substrate dielectric constant, etc. The straight-through transmission line test board is provided with multiple transmission lines, wherein the length of at least one transmission line is the first length, and the lengths of the remaining transmission lines are 20% of the first length. Times. Figure 2a As shown: a first length transmission line 2 and a first length transmission line 3 are arranged on a through transmission line test board 3. times the first length of transmission line 1.

[0052] After the board is manufactured, the insertion loss values ​​of transmission lines of different lengths are measured on the straight-through transmission line test board, and the insertion loss value of the transmission line of the first length is calculated. There are two transmission lines on the straight-through transmission line test board, one of which is , and the other transmission line is Take the insertion loss of two transmission lines at the first frequency as an example; and ,in for The insertion loss value of the transmission line, for Insertion loss value of the transmission line; ,in is the insertion loss value of the first length unit transmission line (i.e., the first insertion loss value). In this example, the first length is , N is 2. The insertion loss value measured by this method eliminates the common error in measuring the insertion loss value of the transmission line. The first frequency may be the operating frequency of the target product.

[0053] Furthermore, the loss of a conductor is mainly composed of three factors, namely dielectric loss, conductor loss and radiation loss. Generally speaking, the dielectric loss (df, Dissipation Factor) is the df value, which is usually provided directly by the manufacturer, while the conductor loss and radiation loss cannot be provided by the manufacturer. However, the influence of conductor loss and radiation loss on the insertion loss value in a high-frequency working environment exceeds that of dielectric loss. Therefore, how to accurately simulate and obtain an effective and accurate insertion loss value has always been a difficult problem.

[0054] In the embodiment of the present disclosure, in the third simulation space in the simulator, based on the second preset parameters, a Figure 2b The simulated straight-through transmission line model shown, the simulated straight-through transmission line model 4 is provided with a simulated transmission line of a first length. The simulated straight-through transmission line model 4 is subjected to multiple simulation tests, and each simulation test inputs a signal with the same input power and different finite conductor boundary conditions. The finite conductor boundary condition can be characterized by a roughness model, and the roughness model can be a sawtooth (Hammerstad) model, a snowball (Hall-Huray) model, etc. Taking the Hall-Huray model as an example, the finite conductor boundary condition can be changed by adjusting the model sphere size a and the surface ratio SR. The output power obtained from each simulation test is recorded, and the insertion loss value is calculated according to the following formula (1), where is the signal input power value, is the signal output power value, The finite conductor boundary conditions of each simulation test are matched with the insertion loss value obtained according to this simulation test, and an insertion loss curve reflecting the relationship between the finite conductor boundary conditions and the insertion loss value at the first frequency is formed by fitting.

[0055] (1) Furthermore, by substituting the first insertion loss value into the insertion loss curve, a finite conductor boundary condition corresponding to the first insertion loss value at the first frequency can be obtained.

[0056] In this process, the simulation test of the simulated through transmission line model 4 and the insertion loss measurement of the through transmission line test board are both performed at the same frequency (i.e., the first frequency). This can avoid the influence of the finite conductor boundary condition on the insertion loss value at different frequencies, which is conducive to solving the insertion loss uncertainty problem in the simulation process.

[0057] Furthermore, a finite conductor boundary condition is applied to the transmission line on the simulated PCB model to obtain the simulated PCB model.

[0058] In another embodiment provided by the present disclosure, in the above step S101 of “respectively constructing a simulated PCB model, a simulated optical module electrical connector model and a BGA simulation system model in the simulator”, “constructing a BGA simulation system model” includes: Step 1: Based on the third preset PCB parameters, determine a second connection area simulation PCB model representing the connection area where the BGA minimum system is located in the PCB hardware environment; wherein the BGA minimum system is a basic unit capable of realizing a signal transmission function; Step 2: In the fourth simulation space of the simulator, based on the simulation PCB model of the second connection area, construct a BGA minimum system simulation model; Step 3: Based on the BGA minimum system simulation model, perform a signal transmission characteristic test to obtain a communication test result, and determine the BGA simulation system model parameters according to the communication test result; and Construct a BGA simulation system model based on BGA simulation system model parameters.

[0059] In the disclosed embodiment, the simulation PCB model may also be provided with a BGA simulation system model for connecting the target main control chip. The simulation PCB model provides a hardware environment for the BGA simulation system model. In order to make the BGA simulation system model more accurate and reasonable, a simulation model of the second connection area where the BGA minimum system is located in the PCB hardware environment may be established based on the third preset PCB parameters. The third preset PCB parameters may be parameters of the target product or parameters of the simulation PCB model established based on the target parameters.

[0060] Furthermore, if Figure 3 As shown, a BGA minimum system simulation model including only a TX differential pair 5, an RX differential pair 6, a ground pad 7, and a differential signal line 8 can be established in the simulation space.

[0061] Furthermore, during the full-link simulation process, one end of the transmission line on the simulated PCB model is connected to the pad of the BGA simulation system model in the BGA connection area, and the other end of the transmission line on the simulated PCB model is connected to the optical module electrical connector. The BGA connection area can be a configuration position of the BGA simulation system model on the simulated PCB model.

[0062] In another embodiment provided by the present disclosure, the above step 3 of "based on the BGA minimum system simulation model, perform a signal transmission characteristic test to obtain a communication test result, determine the BGA simulation system model parameters according to the communication test result; and construct a BGA simulation system model based on the BGA simulation system model parameters" can be implemented as follows: Step 1: Based on the BGA minimum system simulation model, a signal transmission characteristic test is performed between the minimum simulation communication peer end arranged above the BGA minimum system simulation model to obtain a communication test result; Step 2: Compare the communication test results with the preset target communication parameters, and adjust the BGA minimum system simulation model according to the comparison results to obtain the target BGA minimum system simulation model; Step 3: Obtain BGA simulation system model parameters based on the target BGA minimum system simulation model, and construct a BGA simulation system model.

[0063] In the disclosed embodiment, the minimum simulation communication counterpart is a simulation model which is disposed above the BGA minimum system simulation model during the simulation process and has the functions of receiving simulation signals and sending simulation signals to differential pairs.

[0064] The signal transmission characteristic test of the BGA minimum system simulation model is performed. A simulated differential signal is sent from the TX differential pair 5, and the signal is monitored at the corresponding differential signal line 8 port; a differential signal is sent from the differential signal line 8 port corresponding to the RX differential pair 6, and the signal is monitored at the RX differential pair 6; the communication test result is obtained based on the monitored signal.

[0065] Furthermore, the communication test results are compared with the target parameters, the differences between the communication test results and the target parameters are analyzed, and the BGA minimum system simulation model is adjusted to make the communication test results consistent with the target parameters, thereby obtaining the BGA simulation system model parameters.

[0066] Furthermore, a BGA simulation system model including multiple groups of differential pairs is constructed, wherein the number and positional relationship of the differential pairs are determined based on the I / O interface of the target main control chip, and at least one item including the number of vias, via structure and pad size in the BGA simulation system model is determined based on the BGA simulation system model parameters.

[0067] In another embodiment provided by the present disclosure, "adjusting the BGA minimum system simulation model" in the above step 2 includes: adjusting at least one of the differential pair wiring distance, the number of vias, the via structure, and the pad size.

[0068] In the disclosed embodiment, adjusting the differential pair wiring distance can change the characteristic impedance of the routing, so that the impedance between the differential signals matches the target impedance.

[0069] Optionally, adjust the number of vias and plan reasonable routing; appropriately add ground vias around the signal vias to reduce impedance discontinuity.

[0070] Optionally, adjust the via structure and reasonably select blind vias, through vias, and buried vias; the anti-electromagnetic interference and anti-RF interference performance of blind vias and buried vias are better than those of through vias, and selecting blind vias and buried vias can reduce impedance discontinuity.

[0071] Optionally, the pad size is adjusted to reduce the impedance discontinuity and match the impedance curve to the target impedance.

[0072] In another embodiment provided by the present disclosure, the minimum simulated communication counterpart is of a coaxial type; and / or the size of the minimum simulated communication counterpart corresponds to the pad size in the BGA minimum system simulation model.

[0073] In the disclosed embodiment, the minimum simulated communication peer uses a solder ball model to connect the coaxial port on the differential pair to simulate the communication peer model. The coaxial port is a differential coaxial transmission mode. The inner conductor of the differential pair contacts the differential pair pad through the solder ball, and the outer conductor of the differential contacts the differential external ground pad. By optimizing the differential coaxial parameters, the RF port characteristics in the real BGA can be simulated.

[0074] Further, the minimum simulated communication peer size is adjusted to correspond to the pad size in the BGA minimum system simulation model.

[0075] In another embodiment provided by the present disclosure, in the above step S103, "simulating the signal integrity of the full-link simulation model to obtain the target signal link design parameters corresponding to the preset test indicators" includes: Perform simulation model signal integrity simulation on the full-link simulation model to obtain simulation results; The simulation results are compared with the preset test indicators, and the full-link simulation model is adjusted according to the comparison results to obtain the target full-link simulation model; wherein the adjustment of the full-link simulation model includes at least one of the following: pad size, transmission line size, anti-pad size, PCB stacking design structure; Based on the target full-link simulation model, the target signal link design parameters corresponding to the preset test indicators are obtained.

[0076] In the disclosed embodiment, the signal integrity simulation of the full-link simulation model can be performed through at least one simulation test including an S parameter test and an eye diagram test, and a simulation result can be obtained.

[0077] Among them, the S parameter test uses the optical module gold finger model to input the simulation signal to the optical module electrical connector model, outputs the simulation signal from the coaxial port on the other end of the BGA area, monitors the values ​​of the output signal and the input signal, and calculates the S parameters to determine the gain, loss and reflection coefficient of the full-link simulation model.

[0078] Furthermore, the eye diagram test uses a simulation signal to input the optical module electrical connector model through the optical module gold finger model, output the simulation signal from the coaxial port on the other end of the BGA area, and use a simulation oscilloscope to receive the output signal to form a waveform that reflects the signal within a certain time period. The signal level, overshoot, jitter and bit error rate of the simulation signal are determined based on this waveform.

[0079] Optionally, the S parameters and eye diagram waveform of the test results can be adjusted by adjusting the pad size of the full-link simulation model, adjusting the transmission line size of the full-link simulation model, adjusting the anti-pad size of the full-link simulation model, adjusting the PCB stacking design structure of the full-link simulation model, etc.

[0080] The present disclosure also provides a signal link simulation device, such as Figure 4 As shown, including: The first model building module 401 is used to obtain a full-link simulation model in the simulator; wherein the full-link simulation model is based on a combination of a simulated PCB model, a simulated optical module electrical connector model and a BGA simulation system model; The first simulation test module 402 is used to perform a simulation model signal integrity simulation test on the full-link simulation model to obtain target signal link design parameters corresponding to preset test indicators.

[0081] An embodiment of the present disclosure also provides an electronic device, including: a signal link simulation device as described in any of the above embodiments.

[0082] Through the description of the above implementation methods, those skilled in the art can clearly understand that the embodiments of the present disclosure can be implemented by hardware, or by means of software plus a necessary general hardware platform. Based on such an understanding, the technical solution of the embodiments of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.), including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present disclosure.

[0083] Those skilled in the art will appreciate that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the modules or processes in the accompanying drawings are not necessarily required for implementing the present disclosure.

[0084] Those skilled in the art can understand that the modules in the device in the embodiment can be distributed in the device in the embodiment according to the description of the embodiment, or can be changed accordingly and located in one or more devices different from the present embodiment. The modules in the above embodiment can be combined into one module, or can be further divided into multiple sub-modules.

[0085] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0086] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to include these modifications and variations.

Claims

1. A signal link simulation method, characterized in that: include: Construct a simulation PCB model, a simulation optical module electrical connector model, and a BGA simulation system model in the simulator respectively; The simulated PCB model, the simulated optical module electrical connector model and the BGA simulation system model are combined to obtain a full-link simulation model; The full-link simulation model is subjected to a simulation model signal integrity simulation to obtain target signal link design parameters corresponding to preset test indicators.

2. The signal link simulation method according to claim 1, characterized in that: The simulation PCB model, the simulation optical module electrical connector model and the BGA simulation system model are respectively constructed in the simulator, including: Based on the first preset PCB parameters, a first connection area simulation PCB model representing the connection area where the optical module electrical connector is located in the PCB hardware environment is determined; wherein the first connection area simulation PCB model provides a PCB hardware environment for the basic functions of the optical module electrical connector; According to the gold finger of the optical module to be plugged and connected with the electrical connector of the optical module, a gold finger model of the simulated optical module is constructed; In the first simulation space of the simulator, a first simulated optical module electrical connector model is constructed based on the first connection area simulated PCB model, the simulated optical module gold finger model and the optical module electrical connector parameters; wherein the optical module electrical connector parameters include at least one of the three-dimensional image data, physical structure composition and technical data of the corresponding optical module electrical connector, so that the obtained first simulated optical module electrical connector model includes a hardware structure and can realize a preset simulation function.

3. The signal link simulation method according to claim 2, characterized in that: After the first simulation optical module electrical connector model is constructed, the method further includes: According to the preset simulation function, a first simulation test is performed on the first simulation optical module electrical connector model to obtain simulation data; Comparing the simulation data with technical parameters of the corresponding preset simulation function to obtain a comparison result; According to the comparison result, the first simulated optical module electrical connector model is adjusted, and a second simulation test is performed until the simulation data obtained by the adjusted first simulated optical module electrical connector model meets the technical parameters of the corresponding preset simulation function, thereby obtaining a simulated optical module electrical connector model; The first simulation test and the second simulation test respectively include at least one of the following: TDR test, insertion loss S21 test, group delay test, and channel isolation test.

4. The signal link simulation method according to claim 3, characterized in that: The adjusting the first simulated optical module electrical connector model according to the comparison result includes: According to the comparison result, the hardware structure of the first simulated optical module electrical connector model is adjusted; wherein the hardware structure includes at least one of the following: the size of the solder pad inside the first simulated optical module electrical connector model, the size of the transmission line inside the first simulated optical module electrical connector model, the size of the anti-pad inside the first simulated optical module electrical connector model, and the PCB design of the first simulated optical module electrical connector model.

5. The signal link simulation method according to claim 1, characterized in that: The simulation PCB model, the simulation optical module electrical connector model and the BGA simulation system model are respectively constructed in the simulator, including: Obtaining target PCB parameters; the target PCB parameters include: target operating frequency, number of differential signals, IC pin type, and IC pin distribution; In a second simulation space of the simulator, the simulated PCB model is constructed based on the target PCB parameters.

6. The signal link simulation method according to claim 5, characterized in that: The step of constructing the simulated PCB model based on the target PCB parameters includes: According to the target operating frequency, based on the corresponding relationship between the operating frequency and the PCB material, determining the PCB material to be used; According to the number of differential signals and based on the differential signal line routing principle, determining the differential line width and spacing; According to the IC pin type and IC pin distribution, based on the PCB fan-out principle, fan-out routing solution; Determine the PCB stacking layout based on the PCB material, the differential trace width and spacing, and the trace scheme; The simulated PCB model is constructed based on the PCB stacking layout and target finite conductor boundary conditions.

7. The signal link simulation method according to claim 6, characterized in that: Before constructing the simulation PCB model based on the PCB stacking layout and the target finite conductor boundary condition, the method further includes: Obtaining, in a hardware environment, a first insertion loss value of a transmission line of a first length in a through transmission line test board corresponding to a second preset PCB parameter at a first frequency; Constructing a simulated straight-through transmission line model in a third simulation space of the simulator; wherein the simulated straight-through transmission line model is constructed based on the second preset PCB parameters; and the simulated straight-through transmission line model includes at least one simulated transmission line with a first length; Perform at least two third simulation tests on the simulated straight-through transmission line model at a first frequency, set a finite conductor boundary condition corresponding to the third simulation test for the test transmission line for each third simulation test, and determine an insertion loss value corresponding to the finite conductor boundary condition in the third simulation test according to the power of an input signal of the test transmission line and the power of an output signal of the transmission line in the third simulation test, to obtain multiple sets of finite conductor boundary conditions and insertion loss values; Based on multiple groups of finite conductor boundary conditions and insertion loss values, an insertion loss curve reflecting the relationship between the finite conductor boundary conditions and the insertion loss value is obtained by fitting; The target finite conductor boundary condition corresponding to the first insertion loss value is obtained through the insertion loss curve.

8. The signal link simulation method according to claim 1, characterized in that: The simulation PCB model, the simulation optical module electrical connector model and the BGA simulation system model are respectively constructed in the simulator, including: Based on the third preset PCB parameters, a second connection area simulation PCB model representing the connection area where the BGA minimum system is located in the PCB hardware environment is determined; wherein the BGA minimum system is a basic unit capable of realizing a signal transmission function; In a fourth simulation space of the simulator, based on the simulation PCB model of the second connection area, a BGA minimum system simulation model is constructed; Based on the BGA minimum system simulation model, a signal transmission characteristic test is performed to obtain a communication test result, and a BGA simulation system model parameter is determined according to the communication test result; and The BGA simulation system model is constructed based on the BGA simulation system model parameters.

9. The signal link simulation method according to claim 8, characterized in that: The method of performing a signal transmission characteristic test based on the BGA minimum system simulation model to obtain a communication test result, and determining a BGA simulation system model parameter according to the communication test result; and constructing the BGA simulation system model based on the BGA simulation system model parameter includes: Based on the BGA minimum system simulation model, a signal transmission characteristic test is performed between the minimum simulation communication peer end arranged above the BGA minimum system simulation model to obtain a communication test result; Comparing the communication test result with the preset target communication parameter, and adjusting the BGA minimum system simulation model according to the obtained comparison result to obtain the target BGA minimum system simulation model; Based on the target BGA minimum system simulation model, BGA simulation system model parameters are obtained, and the BGA simulation system model is constructed.

10. The signal link simulation method according to claim 9, characterized in that: The adjusting of the BGA minimum system simulation model includes: adjusting at least one of the differential pair wiring distance, the number of vias, the via structure, and the pad size.

11. The signal link simulation method according to claim 9, characterized in that: The minimum simulated communication counterpart is of a coaxial type; and / or the size of the minimum simulated communication counterpart corresponds to the pad size in the BGA minimum system simulation model.

12. The signal link simulation method according to claim 1, characterized in that: The performing simulation model signal integrity simulation on the full-link simulation model to obtain target signal link design parameters corresponding to preset test indicators includes: Performing simulation model signal integrity simulation on the full-link simulation model to obtain a simulation result; The simulation result is compared with the preset test index, and according to the obtained comparison result, the full-link simulation model is adjusted to obtain a target full-link simulation model; wherein the adjustment of the full-link simulation model includes at least one of the following: pad size, transmission line size, anti-pad size, PCB stacking design structure; Based on the target full-link simulation model, target signal link design parameters corresponding to preset test indicators are obtained.

13. A signal link simulation device, characterized in that: include: A first model building module, wherein the first model building module is used to obtain a full-link simulation model in the simulator; wherein the full-link simulation model is based on a combination of the simulated PCB model, the simulated optical module electrical connector model and the BGA simulation system model; The first simulation test module is used to perform a simulation model signal integrity simulation test on the full-link simulation model to obtain target signal link design parameters corresponding to preset test indicators.

14. An electronic device, characterized in that: include: A signal link simulation device as described in claim 13.

Images