Circuit design method based on ADC / DAC test related analog source quality optimization in ATE test

Abstract

The invention provides a circuit design method based on ADC / DAC test related analog source quality optimization in an ATE test, and belongs to the technical field of analog source quality optimization. Through the methods of power supply optimization, external signal source optimization, PCB analog signal path noise filtering and the like, a high-precision and low-noise signal source can be ensured, and a stable and excellent low-noise environment can be provided.

Description

Technical Field

[0001] The present invention relates to the technical field of analog source quality optimization, and in particular to a circuit design method based on analog source quality optimization related to ADC / DAC testing in ATE testing. Background Art

[0002] In ATE large-scale integrated circuit testing, the testing of analog-to-digital converters (ADCs) requires analog signals with higher precision and lower noise for testing. Therefore, high-precision and low-noise signal sources are the main issues in high-precision ADC testing.

[0003] Therefore, there is an urgent need in the art for an optimized analog signal circuit design method that can generate a high-precision, low-noise signal source.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide an optimized analog signal circuit design method capable of generating a high-precision and low-noise signal source.

[0006] To achieve the above object, the present invention provides the following solutions:

[0007] A circuit design method based on quality optimization of analog sources related to ADC / DAC testing in ATE testing, comprising:

[0008] Power supply optimization;

[0009] External signal source optimization;

[0010] PCB board analog signal path noise filtering.

[0011] Optionally, the power supply optimization includes:

[0012] The power pin is connected in parallel with multiple capacitors of different magnitudes. The power supply is supplied by the ADP7104 series LDO ultra-low noise low dropout linear regulator, and the front and back ends of the LDO are decoupled and filtered.

[0013] Optionally, the power pin is connected in parallel with a plurality of capacitors of different magnitudes, including:

[0014] For high frequency noise, use 0.1μF~1nF ceramic capacitors, and for low frequency noise, use 10μF~100μF capacitors.

[0015] Optionally, the decoupling filtering of the LDO front end and the back end includes:

[0016] Add 0.1uf ceramic capacitors and 10uf tantalum capacitors for filtering.

[0017] Optionally, the external signal source optimization includes:

[0018] The APX555 audio analyzer is used as the signal source, supporting single-ended output and two-channel differential output, with a bandwidth of 1MHz and an output sinusoidal signal of 1kHz with a THD of at least -120dB. Differential equal-length routing is used in the PCB design of the analog signal path, and the signal line is grounded with a line width ≥ 5 times the signal line dielectric thickness. The distance between the power layer and the ground layer is <4mil to enhance coupling. The sensitive nodes of the analog signal path are shielded. If relay switching is required, a shielded signal relay is used.

[0019] Optionally, the PCB board analog signal path noise filtering includes:

[0020] Add RC filter circuit to the analog signal input of PCB board, and the frequency is f The input sine signal is low-pass filtered to ensure that the signal does not contain high-frequency noise and prevent high-frequency noise from affecting the creation in the FFT spectrum. f = 1 / (2πRC) to derive the specific values ​​of R and C, where f is the signal center frequency; in this filter circuit, R must be less than 10Ω, and the specific capacitance value of C is calculated accordingly.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] The present invention provides a circuit design method based on optimizing the quality of analog sources related to ADC / DAC testing in ATE testing. The present invention can ensure a high-precision and low-noise signal source and provide a stable and excellent low-noise environment through methods such as power supply optimization, external signal source optimization, and noise filtering of PCB board analog signal paths. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0024] Figure 1 A schematic diagram of a power pin circuit provided by an embodiment of the present invention.

[0025] Figure 2 A schematic diagram of a 5V power supply circuit provided in an embodiment of the present invention.

[0026] Figure 3 A schematic diagram of a 3.3V power supply circuit provided in an embodiment of the present invention.

[0027] Figure 4 A schematic diagram of a noise filtering circuit for an analog signal path of a PCB board provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] The object of the present invention is to provide an optimized analog signal circuit design method capable of generating a high-precision and low-noise signal source.

[0030] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0031] In testing high-precision ADC / DAC, the circuit board is usually required to have a low-noise environment as a whole (i.e., there is no other noise interference on the board), and the spectrum noise THD of the sine source signal of the signal source source is at least 5dB lower than that of the ADC to be tested to ensure that the dynamic parameters SNR, SINAD, and THD parameters measured by the chip meet the accuracy required for the test.

[0032] The method designed in the present invention can be applied in high-precision ADC testing to optimize the quality of analog source signals and reduce other noise interference in the overall circuit, thereby meeting the testing requirements of high-precision ADC / DAC.

[0033] Embodiment 1:

[0034] This embodiment provides a circuit design method based on optimizing the quality of analog sources related to ADC / DAC testing in ATE testing, including:

[0035] Power supply optimization;

[0036] External signal source optimization;

[0037] PCB board analog signal path noise filtering.

[0038] In one embodiment, power supply optimization specifically includes:

[0039] a. For the power pins, the capacitor-inductor-resistance decoupling filtering method is used, and multiple capacitors of different orders of magnitude are connected in parallel. Ceramic capacitors (0.1μF~1nF) are used for high-frequency noise, and tantalum capacitors (10μF~100μF) are used for low-frequency noise. The capacitors are located close enough to the pins. The schematic diagram is as follows: Figure 1 , decoupling and filtering the VCC pin, where C1 is a tantalum capacitor of 10μF, C2 is a ceramic capacitor of 0.1μF, and C3 is a ceramic capacitor of 0.01μF.

[0040] b. For power supply and 3.3V power supply, ADP7104 series LDO ultra-low noise low voltage dropout linear regulator is used for power supply, and the front and back ends of LDO are decoupled and filtered, and 0.1uf ceramic capacitors and 10uf tantalum capacitors are added for filtering respectively.

[0041] 5V and 3.3V power supplies are Figure 2 and Figure 3 Two circuit diagrams.

[0042] C1 is a 0.1μF ceramic capacitor, C2 is a 10μF tantalum capacitor, R1 is a 100K PG feedback resistor, and the EN pin is connected to a pull-up resistor to ensure that the output can be turned on when the LDO is powered on. C3 is a 10μF tantalum capacitor, and C4 is a 0.1μF ceramic capacitor.

[0043] C1 and C2 are decoupling capacitors for the power pins of the chip under test to prevent the introduction of output noise from the LDO.

[0044] C3 and C4 are LDO power input decoupling capacitors to prevent the introduction of output noise from external power supplies.

[0045] Purpose: To reduce the interference of power supply noise on analog signals.

[0046] In one embodiment, the external signal source optimization specifically includes:

[0047] The APX555 audio analyzer is used as the signal source. It supports single-ended output and two-channel differential output, with a bandwidth of 1MHz. The THD of the output sine signal at 1kHz is at least -120dB, so this device can be used as an analog signal source. Differential equal-length routing is used in the PCB design of the analog signal path, and the signal line is grounded. The line width is ≥5 times the signal line dielectric thickness, and the distance between the power layer and the ground layer is <4mil to enhance coupling. The shielding design of sensitive nodes in the analog signal path (copper foil + grounding ring) is used. If relay switching is required, a shielded signal relay is used.

[0048] The layout method on the PCB board is:

[0049] A. Differential equal length routing

[0050] Purpose: Reduce common mode noise and suppress electromagnetic interference (EMI).

[0051] Implementation points:

[0052] Symmetrical wiring: The two lines of the differential pair need to be parallel, equal in width, and equal in spacing.

[0053] Equal length control: The length error is less than 1 / 10 of the signal rising edge (for example: 1GHz signal error <0.3mm).

[0054] Reference plane: A complete ground plane is required under the differential pair to avoid cross-splitting.

[0055] Spacing rules: Spacing within a differential pair is ≤ 2 times the line width, and spacing outside a differential pair is ≥ 3 times the line width.

[0056] A. Signal line grounding treatment

[0057] Purpose: To isolate noise and prevent crosstalk.

[0058] Ground trace surround: Ground traces (Guard Trace) are laid on both sides of the sensitive signal line and connected to the ground layer through vias. The line width should be ≥ 5 times the thickness of the signal line medium.

[0059] Ground plane shielding: Set up a complete ground plane above and below the signal layer.

[0060] Via spacing: Drill ground vias every λ / 20 (λ is the signal wavelength) along the ground line.

[0061] B. Other key layout rules:

[0062] Power and ground:

[0063] The analog power supply and digital power supply are separated and grounded at a single point.

[0064] The power line is widened (≥20mil) and adopts a star topology.

[0065] The distance between the power layer and the ground layer is <4mil to enhance coupling.

[0066] Keep sensitive signals away from noise sources:

[0067] Analog signals should be kept away from clock lines, switching power supplies, and high-speed digital signals.

[0068] Filter capacitor layout:

[0069] Place 0.1μF ceramic capacitors + 10μF tantalum capacitors close to the analog device power pins.

[0070] In one embodiment, the noise filtering of the analog signal path of the PCB board specifically includes:

[0071] An RC filter circuit is added to the analog signal input of the board to perform low-pass filtering on the input sine signal with a frequency of f to ensure that the signal does not contain high-frequency noise and prevent high-frequency noise from affecting the creation in the FFT spectrum diagram.

[0072] Function: Allow low-frequency signals to pass, attenuate high-frequency signals, and filter out high-frequency noise.

[0073] Circuit structure: It consists of a resistor (R) and a capacitor (C) in series, and the output signal is drawn from both ends of the capacitor.

[0074] Transfer function:

[0075] in f is the signal frequency, j Is an imaginary unit.

[0076] Cut-off frequency calculation:

[0077] Cut-off frequency ( fc ): The signal amplitude is attenuated to the input value (about -3dB).

[0078]

[0079] Parameter selection steps:

[0080] 1. Determine the cut-off frequency: select according to your needs fc (For example: 1kHz).

[0081] 2. Choose the typical value of R or C:

[0082] The resistor R is usually 1Ω-50Ω (to avoid load effect caused by too large a value, which can cause amplitude attenuation).

[0083] The common range of capacitor C is: 1pF-10μF (ceramic capacitors or film capacitors are preferred).

[0084] 3. Calculate another parameter: For example, if fc =1kHz, choose R=10Ω, then:

[0085] Design considerations:

[0086] Impedance matching: ensure that the output impedance of the front stage is much smaller than R, and the input impedance of the rear stage is much larger than the capacitive reactance;

[0087]

[0088] High frequency attenuation slope: The attenuation slope of the RC low-pass filter is -20dB / decade.

[0089] Capacitor type: Low ESR capacitors (such as ceramic capacitors) are preferred in high-frequency scenarios.

[0090] In this filter circuit, R must be less than 50Ω, and the specific capacitance of C is calculated accordingly. Figure 4 shown.

[0091] The present invention selects high-quality analog sources, designs reasonable analog signal circuits, and optimizes board noise in the ADC / DAC test part of ATE testing, so that the tested static parameters DNL / INL and dynamic parameters SNR / SFDR / THD / ENOB can be better.

[0092] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0093] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A circuit design method based on the optimization of analog source quality related to ADC / DAC testing in ATE testing, characterized in that: include: The power supply is optimized, and multiple capacitors of different magnitudes are connected in parallel to the power pins. The power supply is supplied by the ADP7104 series LDO ultra-low noise low-dropout linear regulator, and the LDO front-end and back-end are decoupled and filtered. Optimize the external signal source, use APX555 audio analyzer as the signal source, support single-ended output and two-channel differential output, bandwidth is 1MHz, output sinusoidal signal 1kHz THD is at least -120dB, use differential equal-length routing in the analog signal path PCB design, and do grounding on the signal line, the line width is ≥5 times the signal line medium thickness, the power layer and the ground layer spacing is <4mil to enhance coupling, the analog signal path sensitive nodes are shielded, if relay switching is required, use shielded signal relays; Noise filtering of analog signal paths on PCB boards; Add RC filter circuit to the analog signal input of PCB board, and the frequency is f The input sine signal is low-pass filtered to ensure that the signal does not contain high-frequency noise and prevent high-frequency noise from affecting the creation in the FFT spectrum. f = 1 / (2πRC) to derive the specific values ​​of R and C, where f is the signal center frequency; in this filter circuit, R must be less than 10Ω, and the specific capacitance value of C is calculated accordingly.

2. The circuit design method based on the quality optimization of analog sources related to ADC / DAC testing in ATE testing according to claim 1 is characterized in that: The power pin is connected in parallel with a plurality of capacitors of different magnitudes, including: For high frequency noise, use 0.1μF~1nF ceramic capacitors, and for low frequency noise, use 10μF~100μF capacitors.

3. The circuit design method based on the quality optimization of analog sources related to ADC / DAC testing in ATE testing according to claim 1 is characterized in that: The decoupling filtering of the LDO front end and the back end includes: Add 0.1uf ceramic capacitors and 10uf tantalum capacitors for filtering.

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