Semiconductor device and method for detecting semiconductor wafer centered on tape

Abstract

A semiconductor manufacturing apparatus has a wafer tape including a plurality of alignment holes formed therethrough. A semiconductor wafer is disposed over the wafer tape. The semiconductor wafer includes a circular or rectangular form factor. A light source is disposed below the wafer ribbon. The semiconductor wafer is misaligned on the wafer ribbon with light passing through the one or more alignment holes. The semiconductor wafer is centered on the wafer ribbon without light passing through the one or more alignment holes. The wafer tape has a plurality of wafer alignment marks for semiconductor wafers of different sizes. A light detector is disposed over the semiconductor wafer to detect light passing through the wafer ribbon. A control arm may be attached to the semiconductor wafer to provide the ability to move the semiconductor wafer in response to a control signal from the light detector.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices and, more particularly, to semiconductor devices and methods for inspecting semiconductor wafers centered on a tape. Background Art

[0002] Semiconductor devices are common in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, sending and receiving electromagnetic signals, controlling electrical devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices can also be found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor wafers typically contain multiple semiconductor dies separated by saw streets. Semiconductor wafers are typically mounted to a tape to hold the wafer in place during various manufacturing operations, such as cleaning and cutting. The semiconductor wafer should be centered on the tape to be properly aligned relative to a fixture or other cutting tool. The semiconductor wafer can be moved by hand in an attempt to find the center of the tape. However, manual centering is at best an estimate because the tape is opaque. Improper centering can result in inaccurate cutting of the wafer and lead to lower yields and higher manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1a-1d illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0005] Figure 2a-2i A wafer tape having alignment holes for centering a semiconductor wafer is illustrated;

[0006] Figure 3 illustrates a semiconductor wafer undergoing a manufacturing operation;

[0007] Figure 4 illustrates a semiconductor wafer of a second size centered on the wafer strip through the alignment holes;

[0008] Figure 5 illustrates a semiconductor wafer of a third size centered on a wafer strip through alignment holes;

[0009] Figure 6 A rectangular semiconductor wafer is illustrated centered on a wafer strip by alignment holes;

[0010] Figure 7 A control arm for moving a semiconductor wafer to the center of a wafer strip is illustrated;

[0011] Figure 8a-8h illustrates a wafer tape having alignment holes for centering a reconstructed wafer; and

[0012] Fig. 9 The diagram illustrates a printed circuit board (PCB) with different types of packages arranged on a surface of the PCB. DETAILED DESCRIPTION

[0013] The present invention is described in one or more embodiments in the following description with reference to the figures, wherein the same numerals represent the same or similar elements. Although the present invention is described according to the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present invention as defined by the appended claims and their equivalents, as supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. Elements having similar functions in the figures are assigned the same reference numerals. The term "semiconductor die" as used herein refers to both the singular and plural forms of the term, and therefore may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0014] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create the relationship between voltage and current that is necessary to perform the circuit function.

[0015] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor die, and encapsulating the semiconductor die for structural support, electrical interconnection and environmental isolation. In order to singulate the semiconductor die, the wafer is scored and broken along the non-functional area of ​​the wafer (referred to as saw road or scribing line). The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die is arranged on a package substrate, and the package substrate includes pins or contact pads for interconnection with other system components. Then, the contact pad formed on the semiconductor die is connected to the contact pad in the package. Electrical connection can be achieved using a conductive layer, a bump, a columnar bump, a conductive paste or a bonding wire. Encapsulant or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functions of the semiconductor device are made available to other system components.

[0016] Figure 1aA semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide or other bulk materials for structural support. A plurality of semiconductor dies, or electrical components 104, are formed on the wafer 100, which are separated by a non-active inter-die wafer region or saw street 106. The saw street 106 provides a cutting area to singulate the semiconductor wafer 100 into individual semiconductor dies 104. The semiconductor wafer 100 has a circular form factor. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0017] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface or inactive surface 108 and an active surface 110, which contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, or other signal processing circuits. The semiconductor die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0018] Conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, chemical plating, or other suitable metal deposition processes. Conductive layer 112 may be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layer 112 serves as a contact pad electrically connected to the circuit on active surface 110.

[0019] Figure 2a A backside coating (BSC) or wafer strip 120 made of a polymer or epoxy with silver, silica or alumina fillers is shown. Figure 2b 1 is a top view of the BSC tape 120. The BSC tape 120 provides support and protection for the semiconductor wafer 100. The BSC tape 120 is 110 micrometers (mm) thick and is wider than the largest wafer application. Figure 2cFurther details of the BSC 120 are shown, including a polyethylene terephthalate (PET) release film 121 having a thickness of 38 mm, a double-sided tape 123 having a PVC base film and having a thickness of 60 mm, a thermosetting type back coating film 125 having a thickness of 25 mm, an acrylic release layer 127 having a thickness of 5 mm, and a polyolefin base film 129 having a thickness of 80 mm. The BSC tape 120 is opaque and blocks infrared light (IR).

[0020] exist Figure 2b , a first wafer alignment circle or mark 122 is shown for a wafer having a diameter of 200 mm. A second wafer alignment circle or mark 124 is shown for a wafer having a diameter of 300 mm. A third wafer alignment circle or mark 126 is shown for a wafer having a diameter of 450 mm. A plurality of alignment openings or holes are formed in the BSC tape 120 for each wafer alignment circle by a template and a stamping, laser direct ablation (LDA) or etching process. Each wafer alignment circle typically has at least three alignment holes. The four alignment holes 130a, 130b, 130c and 130d are equally spaced around the wafer alignment circuit 122, i.e., spaced in 90 degree increments. There are four alignment holes 132a, 132b, 132c and 132d, which are equally spaced around the wafer alignment circuit 124, and six alignment holes 134a, 134b, 134c, 134d, 134e and 134f, which are equally spaced around the wafer alignment circuit 126 because of its larger size. For a circular wafer, the alignment holes 130-134 are typically circular with a diameter of 5.0 mm, although the alignment holes may have other geometries depending on the wafer. There may be any number of alignment holes per alignment circle. The alignment holes 130-134 are formed exactly within the wafer alignment circle, so that if the semiconductor wafer 100 is placed on the alignment circle and centered on the center 128, then the alignment circuit will be visible, but all the alignment holes for that particular alignment circle will not be visible because they will be covered by the semiconductor wafer. In this case, the semiconductor wafer 100 will be considered to be perfectly aligned with the center 128 of the BSC tape 120.

[0021] exist Figure 2d In, from Figure 1b The semiconductor wafer 100 is disposed on the BSC belt 120. In this example, the diameter of the semiconductor wafer 100 is 450 mm. Figure 2e The active surface 110 of the semiconductor wafer 100 is shown disposed above and in contact with the surface 136 of the BSC tape 120. In another embodiment, Figure 2f The back surface 108 of the semiconductor wafer 100 is shown disposed over and in contact with the surface 136 of the BSC tape 120. Any orientation of the semiconductor wafer 100 is suitable.

[0022] Figure 2g A light source 140 is shown positioned below the BSC tape 120. The light source 140 emits a light wave 142 onto a surface 144 of the BSC tape 120. Depending on the position of the semiconductor wafer 100, the light wave 142 may or may not be transmitted through the alignment holes 134a-134f. Assume that the semiconductor wafer 100 is off-center relative to the center 128. Likewise, the alignment holes 134a-134f are formed exactly within the wafer alignment circle 126. Any material misalignment of the semiconductor wafer 100 relative to the center 128 will allow the light wave 142 to pass through one or more of the alignment holes 134a-134f. In other words, if misaligned relative to the center 128, the semiconductor wafer 100 will not cover all of the alignment holes 134a-134f, and the light wave 142 will be transmitted through one or more uncovered alignment holes. Figure 2h In the top view of FIG. 1 , the semiconductor wafer 100 is off-center relative to the center 128, and the semiconductor wafer 100 does not cover the alignment holes 134e and 134f. The light wave 142 will be transmitted through the alignment holes 134e and 134f and can be observed or detected from the opposite side of the BSC tape 120, that is, above the surface 136. The light wave 142 can be observable by human vision or detected by a light detector 146. After passing through one or more of the alignment holes 134a-134f, the light detector 146 can give a visible or audible signal indicating that the light wave 142 has been detected above the surface 136. The alignment holes 130a-130d and 132a-132d are intended for smaller semiconductor wafers and should not be relevant to 450 mm semiconductor wafers.

[0023] Assume that the semiconductor wafer 100 is Figure 2b If the center 128 in the alignment hole 134a is off-center, the position of the semiconductor wafer relative to the center 128 can be moved or adjusted until the semiconductor wafer covers all the alignment holes 134a-134f. In that case, no light is observed or detected through any of the alignment holes 134a-134f. When no light is observed or detected through any of the alignment holes 134a-134f, such as Figure 2i As in , the semiconductor wafer 100 is considered to be centered relative to the center 128.

[0024] Once centered, the semiconductor wafer 100 can be subjected to various semiconductor manufacturing processes. As an example, the semiconductor wafer 100 is singulated along the saw streets 106, such as Figure 3 As described above, alignment of the semiconductor wafer 100 relative to the center 128 provides precise control over the location of the dicing operation. Alternatively, the semiconductor wafer 100 may be subjected to a pick and place operation, cleaning, and inspection.

[0025] Figure 41 shows a semiconductor wafer 100 mounted on a BSC tape 120. In this case, the diameter of the semiconductor wafer 100 is 300 mm. If the semiconductor wafer 100 is off-center relative to the center 128, the light wave 142 passes through one or more alignment holes 132a-132d within the wafer alignment circle 124. In other words, if misaligned relative to the center 128, the semiconductor wafer 100 will not cover all of the alignment holes 132a-132d, and the light wave 142 will be transmitted through the uncovered alignment holes, similar to Figure 2h Light wave 142 will be transmitted through the uncovered alignment holes and may be observed or detected from the opposite side of BSC strip 120, i.e., above surface 136. Likewise, light wave 142 may be observable by human vision or detectable by photodetector 146. Light wave 142 is focused on alignment holes 132a-132d, so any light passing through alignment holes 134a-134f will be negligible or ignored.

[0026] If the semiconductor wafer 100 is off-center relative to the center 128, the position of the semiconductor wafer relative to the center 128 may be moved or adjusted until the semiconductor wafer covers all of the alignment holes 132a-132d. In that case, no light is observed or detected through any of the alignment holes 132a-132d. Figure 4 As shown, when no light is observed or detected through any of the alignment holes 132a-132d, the semiconductor wafer 100 is considered centered relative to the center 128. The alignment holes 130a-130d are intended for smaller semiconductor wafers and should not be associated with 300 mm semiconductor wafers.

[0027] Figure 5 A semiconductor wafer 100 is shown mounted on a BSC tape 120. In this case, the diameter of the semiconductor wafer 100 is 200 mm. If the semiconductor wafer 100 is off-center relative to the center 128, the light wave 142 passes through one or more alignment holes 130a-130d within the wafer alignment circle 122. In other words, if misaligned relative to the center 128, the semiconductor wafer 100 will not cover all of the alignment holes 130a-130d, and the light wave 142 will be transmitted through one or more uncovered alignment holes, similar to Figure 2h Light wave 142 will be transmitted through the uncovered alignment holes and may be observed or detected from the opposite side of BSC strip 120, i.e., above surface 136. Likewise, light wave 142 may be observable by human vision or detectable by photodetector 146. Light wave 142 is focused on alignment holes 130a-130d, so any light passing through alignment holes 134a-134f and 132a-132d will be negligible or disregarded.

[0028] If the semiconductor wafer 100 is off-center relative to the center 128, the position of the semiconductor wafer relative to the center 128 may be moved or adjusted until the semiconductor wafer covers all of the alignment holes 130a-130d. In that case, no light is observed or detected through any of the alignment holes 130a-102d. Figure 5 As shown, when no light is observed or detected through any of the alignment holes 130 a - 130 d , the semiconductor wafer 100 is considered to be centered relative to the center 128 .

[0029] In another embodiment, Figure 6 As shown, the semiconductor wafer 100 can be moved or adjusted by a control arm 148 in response to the light detector 146. The control arm 148 is attached to the semiconductor wafer 100. If the light detector 146 detects the light wave 142, a control signal is sent to the control arm 148 to move the semiconductor wafer 100 to make a wafer position adjustment. Given the alignment holes in which the light was detected, the control arm 148 will have information about where to move the semiconductor wafer 100. For example, if light is detected through the alignment holes 134e-134f, as shown in FIG. Figure 2h As shown, the light detector 164 sends a control signal to the control arm 148 to move the semiconductor wafer 100 downward relative to the center 128. Once the adjustment is made, the light detector 146 takes another reading and further adjustments are made in a similar manner if necessary until the semiconductor wafer 100 covers all of the alignment holes 134a-134f and no light waves 142 are transmitted through the BSC 120.

[0030] In another embodiment, the semiconductor wafer 200 has a rectangular form factor. The semiconductor wafer 200 is fabricated similarly to Figure 1a-1b . Figure 7 A rectangular semiconductor wafer 200 is shown disposed on a BSC tape 120. In this case, the wafer alignment marks will be rectangular. The semiconductor wafer 200 follows a similar description as FIGS. 2-6, having a rectangular form factor. Figure 2h-2i If the semiconductor wafer 200 is misaligned, the light waves will be transmitted through one or more alignment holes and corrective action will be taken. If the semiconductor wafer 200 is properly aligned, no light waves will pass through any of the alignment holes of the BSC tape 120 and the semiconductor wafer is considered to be properly centered.

[0031] Back to Figure 1c, depositing conductive bump material on conductive layer 112 using evaporation, electrolytic plating, chemical plating, drop or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, and optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 114. In one embodiment, bump 114 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesive layer. Bump 114 can also be compression bonded or thermocompressed bonded to conductive layer 112. Bump 114 represents a type of interconnect structure that can be formed on conductive layer 112. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, microbumps or other electrical interconnects.

[0032] exist Figure 1d , semiconductor wafer 100 is singulated through saw streets 106 using a saw blade or laser cutting tool 118 into individual semiconductor die 104. Individual semiconductor die 104 may be inspected and electrically tested to be identified as known good die or known good units (KGD / KGU) after singulation.

[0033] Figure 8a A temporary substrate or carrier 150 is shown that includes a sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support. Substrate 150 has a major surface 152 and a major surface 154 opposite surface 152. In one embodiment, carrier 150 is a support structure having a temporary bonding layer 158 formed on the carrier. Temporary bonding layer 158 can be a film or foil bonded to surface 152.

[0034] exist Figure 8b In FIG. 1 , electrical components 156 a-156 c are disposed on surface 152 of substrate 150. Electrical components 156 a-156 c may be similar to those from Figure 1d The semiconductor die 104 or similar is made of gas, where the bumps 114 are oriented toward the surface 152 of the substrate 150. Alternatively, the electrical components 156a-156c may include other semiconductor dies, semiconductor packages, surface mount devices, RF components, discrete electrical devices, or integrated passive devices (IPDs).

[0035] The electrical components 156a-156c are positioned over the substrate 150 using a pick and place operation. The electrical components 156a-156b are in contact with the bonding layer 158. Figure 8cElectrical components 156 a - 156 c are illustrated bonded to substrate 150 as a reconstituted wafer level package (WLP) 160 . Figure 8d is a top view of a reconstructed WLP 160 with electrical components 156a-156c bonded to substrate 150. In this example, the diameter of the reconstructed WLP 160 is 450 mm.

[0036] exist Figure 8e In, similar to Figure 2d , the reconstructed WLP 160 is disposed above the BSC strip 120. Components having similar functions are assigned the same reference numerals. Figure 8f Surface 154 of reconstructed WLP 160 is shown disposed over and in contact with surface 136 of BSC tape 120 .

[0037] Light source 162 is located below BSC strip 120. Light source 162 emits light wave 164 onto surface 144 of BSC strip 120. Depending on the position of reconstructed WLP 160, light wave 164 may or may not be transmitted through alignment holes 134a-134f. Assume that reconstructed WLP 160 is off-center relative to center 128, as shown in FIG. Figure 8g As shown. Likewise, the alignment holes 134a-134f are formed exactly within the wafer alignment circle 126. Any material misalignment of the reconstructed WLP 160 relative to the center 128 will allow the light wave 164 to pass through one or more of the alignment holes 134a-134f. In other words, if there is a misalignment relative to the center 128, the reconstructed WLP 160 will not cover all of the alignment holes 134a-134f, and the light wave 164 will be transmitted through one or more uncovered alignment holes. In this case, the light wave 164 transmitted through the alignment holes 134e and 134f will be observable or detectable from the opposite side of the BSC tape 120, that is, above the surface 136. The light wave 164 may be observable by human vision or detectable by a light detector 166. After passing through one or more of the alignment holes 134a-134f, the light detector 166 may give a visible or audible signal indicating that the light wave 164 has been detected above the surface 136.

[0038] Assuming that the reconstructed WLP 160 is off-center relative to the center 128, the position of the reconstructed WLP 160 relative to the center 128 can be moved or adjusted until the reconstructed WLP 160 covers all of the alignment holes 134a-134f. In that case, no light is observed or detected through any of the alignment holes 134a-134f. When no light is observed or detected through any of the alignment holes 134a-134f, as shown in FIG. Figure 8h As in , the reconstructed WLP 160 is considered to be centered relative to the center 128.

[0039] Once centered, semiconductor wafer 160 can be subjected to various semiconductor manufacturing processes. As an example, similar to Figure 3 , the semiconductor wafer 100 is singulated along the saw streets 106. As described above, alignment of the semiconductor wafer 100 relative to the center 128 provides precise control over the location of the sawing operation.

[0040] Fig. 9 An electrical device 400 is illustrated having a chip carrier substrate or PCB 402 with a plurality of semiconductor packages disposed on a surface of the PCB 402, including semiconductor die 104. Electrical device 400 may have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application.

[0041] The electrical device 400 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electrical device 400 may be a subcomponent of a larger system. For example, the electrical device 400 may be a part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electrical device. Alternatively, the electrical device 400 may be a graphics card, a network interface card, or other signal processing cards that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density.

[0042] exist Fig. 9 In the embodiment of the present invention, PCB 402 provides a common substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed on the surface or in layers of PCB 402 using evaporation, electrolytic plating, chemical plating, screen printing or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components and other external system components. Traces 404 also provide power and ground connections for each of the semiconductor packages.

[0043] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching an intermediate substrate to a PCB. In other embodiments, the semiconductor device may have a first level packaging, wherein the die is mechanically and electrically directly disposed on the PCB. For purposes of illustration, several types of first level packaging are shown on PCB 402, including bonding wire packaging 406 and flip chip 408. In addition, several types of second level packaging including ball grid array (BGA) 410, bump chip carrier (BCC) 412, plane grid array (LGA) 416, multi-chip module (MCM) or SIP module 418, quad flat no-lead package (QFN) 420, quad flat package 422, embedded wafer level ball grid array (eWLB) 424 and wafer level chip size package (WLCSP) 426 are shown to be disposed on PCB 402. In one embodiment, the eWLB 424 is a fan-out wafer level package (Fo-WLP) and the WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured with any combination of first-level and second-level package types, as well as other electrical components, can be connected to the PCB 402. In some embodiments, the electrical device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electrical devices and systems. Because semiconductor packages include complex functions, electrical devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is cheaper to manufacture, resulting in lower costs for consumers.

[0044] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor manufacturing equipment, comprising: a wafer tape including a plurality of alignment holes formed through the wafer tape; a semiconductor wafer disposed on a wafer strip; and A light source is disposed beneath the wafer strip, wherein the semiconductor wafers are misaligned on the wafer strip when light passes through the one or more alignment holes.

2. The semiconductor manufacturing equipment according to claim 1, wherein: The semiconductor wafer is centered on the wafer strip in the absence of light passing through the one or more alignment holes.

3. The semiconductor manufacturing equipment according to claim 1, wherein: The wafer strip includes a plurality of wafer alignment marks for semiconductor wafers of different sizes.

4. The semiconductor manufacturing equipment according to claim 3, wherein: The alignment holes are respectively located in the wafer alignment marks.

5. The semiconductor manufacturing equipment according to claim 1, further comprising a light detector disposed above the semiconductor wafer to detect light passing through the wafer strip.

6. A semiconductor manufacturing device comprising: a wafer tape including a plurality of alignment holes formed through the wafer tape; a semiconductor wafer disposed over the wafer tape to cover the alignment holes; and A light source is disposed beneath the wafer strip, wherein the semiconductor wafer is centered on the wafer strip without light passing through the one or more alignment holes.

7. The semiconductor manufacturing equipment according to claim 6, wherein: In the event that light passes through one or more alignment holes, the semiconductor wafers are misaligned on the wafer strip.

8. The semiconductor manufacturing equipment according to claim 6, wherein: The wafer strip includes a plurality of wafer alignment marks for semiconductor wafers of different sizes.

9. The semiconductor manufacturing equipment according to claim 8, wherein: The alignment holes are respectively located in the wafer alignment marks.

10. The semiconductor manufacturing equipment according to claim 6, further comprising a light detector disposed above the semiconductor wafer to detect light passing through the wafer strip.

11. A method for manufacturing a semiconductor device, comprising: providing a wafer tape including a plurality of alignment holes formed through the wafer tape; placing a semiconductor wafer over the wafer tape to cover the alignment holes; and A light source is positioned below the wafer strip with the semiconductor wafer centered on the wafer strip without light passing through the one or more alignment holes.

12. The method according to claim 11, wherein: In the event that light passes through one or more alignment holes, the semiconductor wafers are misaligned on the wafer strip.

13. The method according to claim 11, wherein: The wafer strip includes a plurality of wafer alignment marks for semiconductor wafers of different sizes.

14. The method of claim 11, further comprising positioning a light detector over the semiconductor wafer to detect light passing through the wafer strip.

15. The method of claim 14, further comprising attaching a control arm to the semiconductor wafer to provide the ability to move the semiconductor wafer in response to the control signal from the light detector.

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