Package substrate and manufacturing method thereof

Abstract

The invention provides a package substrate and a manufacturing method thereof. According to the package substrate, a circuit structure is formed on one side of a core board body with a core layer, and the other side of the core board body is used as a ball mounting side, so that the number of layers of the package substrate is reduced, and the total thickness of the package substrate is reduced.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging technology, and in particular to a packaging substrate that can meet thinning requirements and a manufacturing method thereof. Background Art

[0002] With the booming development of the electronics industry, electronic products tend to be thinner, lighter, shorter and smaller in shape, and their functions are developing towards high performance, high functionality and high speed. Therefore, in order to meet the needs of high integration and miniaturization of semiconductor devices, packaging substrates with thinner, low warpage and high-density wiring designs are often used in the packaging process.

[0003] However, in the existing method of manufacturing packaging substrates, there is a risk of damage to the board thickness conditions in existing equipment, thereby limiting its processing capabilities for thinner substrates. Therefore, when producing packaging substrates that meet the designs of thinning and low warping, special equipment with special specifications must be set up, making it difficult to reduce production costs.

[0004] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the invention

[0005] An object of the present invention is to provide a packaging substrate and a manufacturing method thereof to solve at least one of the above problems.

[0006] In view of the defects of the above-mentioned prior art, the present invention provides a packaging substrate, including: a core board body, including a core layer having a first side and a second side opposite to each other, a plurality of through holes connecting the first side and the second side, a dielectric layer formed on the opposite sides of the core layer and in the through holes, a plurality of through holes respectively formed in the dielectric layer of the through holes and corresponding to each of the through holes, a plurality of hollow conductive pillars respectively formed in the corresponding through holes, a plugging material formed in the hollow conductive pillars, and a first wiring layer and a second wiring layer respectively formed on the dielectric layer on the first side and the second side and electrically connected to the hollow conductive pillars, wherein the first wiring layer formed on the dielectric layer on the first side has a plurality of ball pads; an insulating layer formed on the dielectric layer on the first side of the core layer, so that the first wiring layer on the first side of the core board body is buried in the insulating layer; and a circuit structure, which is arranged on the dielectric layer on the second side of the core layer and electrically connected to the second wiring layer on the second side of the core board body.

[0007] The present invention also provides a method for manufacturing a packaging substrate, comprising: providing a plurality of core boards, wherein each of the core boards comprises a core layer having a first side and a second side opposite to each other, a plurality of through-holes connecting the first side and the second side of the core layer, a dielectric layer formed on opposite sides of the core layer and the through-holes, a through-hole formed in the dielectric layer of the through-holes and corresponding to each of the through-holes, a hollow conductive column formed in each of the through-holes, a plugging material formed in the hollow conductive column, and a first wiring layer and a second wiring layer electrically connected to the hollow conductive column formed on the dielectric layer on the first side and the second side, respectively, wherein the first wiring layer formed on the dielectric layer on the first side has a plurality of ball pads; pressing the core boards on opposite sides of a carrier respectively by means of an insulating layer so that the first wiring layer on the first side of the core board is buried in the insulating layer; forming a circuit structure on the dielectric layer on the second side of the core layer, and electrically connecting the circuit structure to the second wiring layer on the second side of the core board; and removing the carrier to expose the insulating layer.

[0008] In a specific embodiment of the aforementioned packaging substrate and the manufacturing method thereof, the material of the dielectric layer is different from the via plugging material.

[0009] In a specific embodiment of the aforementioned packaging substrate and the manufacturing method thereof, the dielectric layer includes an ABF film (Ajinomoto build-up film).

[0010] In a specific embodiment of the aforementioned packaging substrate and the manufacturing method thereof, the thickness of the dielectric layer formed on the opposite sides of the core layer and on the wall surface of the through hole is ≥50 μm.

[0011] In a specific embodiment of the aforementioned packaging substrate and the manufacturing method thereof, the circuit structure includes at least one dielectric layer formed on the core board and at least one circuit layer formed on the dielectric layer.

[0012] In a specific embodiment of the aforementioned packaging substrate and the manufacturing method thereof, the material of the dielectric layer is the same as the material of the dielectric layer.

[0013] In a specific embodiment of the aforementioned package substrate, the insulating layer is formed with a plurality of insulating layer openings penetrating the insulating layer to expose the ball pads on the first side of the core board body. Accordingly, in a specific embodiment of the aforementioned method for making the package substrate, after removing the carrier, a plurality of insulating layer openings penetrating the insulating layer to expose the ball pads on the first side of the core board body are formed, so that the insulating layer can be used as a solder mask.

[0014] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, a first solder mask layer is formed on the circuit structure.

[0015] In a specific embodiment of the aforementioned packaging substrate, the insulating layer is formed with a plurality of insulating layer openings penetrating the insulating layer to expose the ball pads on the first side of the core board body, and the packaging substrate also includes a second solder mask formed on the insulating layer and having openings corresponding to the insulating layer openings, so that the ball pads are exposed in the insulating layer openings and the openings. Correspondingly, in a specific embodiment of the aforementioned method for making the packaging substrate, it also includes, after removing the carrier, forming a plurality of insulating layer openings penetrating the insulating layer to expose the ball pads on the first side of the core board body; and forming a second solder mask having an opening corresponding to the insulating layer opening on the insulating layer, so that the ball pads are exposed in the insulating layer openings and the openings.

[0016] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the core board body also includes a bonding layer formed on the surfaces of the opposite first and second sides of the core layer and the perforated surface to be located between the core layer and the dielectric layer.

[0017] In a specific embodiment of the aforementioned packaging substrate and the manufacturing method thereof, the bonding layer is an organic coating or an inorganic coating.

[0018] In a specific embodiment of the aforementioned packaging substrate and the manufacturing method thereof, the material forming the organic coating is a polymer.

[0019] In a specific embodiment of the aforementioned packaging substrate and the method for manufacturing the same, the polymer is selected from at least one of the group consisting of polyoxyxylene, polyamide and polyparaxylene.

[0020] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the material forming the inorganic coating layer includes silica sand with a diameter of 20 to 50 microns and a roughness Ra of 1 to 200 microns.

[0021] As can be seen from the above, the packaging substrate and the manufacturing method thereof of the present invention mainly use the first side of the core layer as the ball implanting side to reduce the number of layers of the packaging substrate. Therefore, compared with the prior art, the total thickness of the packaging substrate is advantageously reduced.

[0022] Furthermore, through the ball grid array design on the first side of the core layer, the core board has a conventional ball planting side pad size, conductive column spacing and perforation diameter. Therefore, no matter how the wiring of the circuit structure is designed, the substrate with perforations can be made into the core board for use in a BGA specification packaging substrate, thereby saving process time.

[0023] In addition, because the cracks on the perforated surface of the core layer have been covered by the dielectric layer, the dielectric layer can provide a barrier and protection function to prevent metal ions from diffusing into the core layer during the subsequent electroplating process and avoid crack expansion. The present invention first fills the perforation with a dielectric layer and then drills the dielectric layer to form a through hole, which is beneficial for the metal of the conductive layer to adhere to the dielectric layer and be used as a seed layer.

[0024] In addition, the present invention uses the first side of the core layer as the ball-planting side so that solder balls are directly contacted with the circuit board, thereby shortening the conductive path and reducing signal loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figures 1A to 1H It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing a packaging substrate of the present invention.

[0026] Figure 1H-1 FIG. 4 is a cross-sectional schematic diagram of a package substrate with a bonding layer according to a first embodiment of the present invention.

[0027] FIG. 2A to FIG. 2D It is a cross-sectional schematic diagram of a second embodiment of a method for manufacturing a packaging substrate of the present invention.

[0028] Figure 2D-1 FIG. 4 is a cross-sectional schematic diagram of a packaging substrate with a bonding layer according to a second embodiment of the present invention.

[0029] The reference numerals are as follows: 1,2 Package substrate 1a Core board 10 Core Layer 10a First side 10b Second side 100 Perforation 101 Crack 11 Dielectric layer 110 Through hole 12 Conductive layer 13 Plug material 14a First wiring layer 14b Second wiring layer 140 Ball Planting Pad 15 Hollow conductive column 16 Line structure 160 Dielectric layer 161 Circuit layer 17 First solder mask 27 Second solder mask 170 Solder mask opening 720 Insulation layer opening 270 Opening 22. Binding layer 7 Bearing 70 plate body 71 Copper Foil 72 Insulation layer 8. Substrate. DETAILED DESCRIPTION

[0030] The following describes the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0031] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0032] Figures 1A to 1H It is a cross-sectional schematic diagram of a first embodiment of a method for manufacturing a packaging substrate 1 of the present invention.

[0033] like Figure 1A As shown, a core layer 10 is provided, which has a first side 10a and a second side 10b opposite to each other. A plurality of through holes 100 connecting the first side 10a and the second side 10b are formed in the core layer 10 , and a dielectric layer 11 is formed on opposite sides of the core layer 10 and in the through holes 100 .

[0034] In this embodiment, the core layer 10 is made of a high-hardness dielectric material, such as glass, ceramic, silicon carbide (SiC), AlO 2 or a composite material with a high rigidity and a modulus of 50 to 100 GPa, to avoid the problem of warping of the package substrate 1 .

[0035] Furthermore, the first side 10 a and the second side 10 b of the core layer 10 may be penetrated by laser burning, hydrofluoric acid (HF) etching, plasma etching, mechanical drilling, etc. to form a plurality of through holes 100 .

[0036] In addition, the dielectric layer 11 can be an ABF film (Ajinomoto build-up film), prepreg (PP), polybenzoxazole (PBO), polyimide (PI), etc. or other dielectric materials, which can be formed on the first side 10a and the second side 10b of the core layer 10 by lamination or molding, and filled into the through hole 100.

[0037] like Figure 1B As shown, a plurality of through holes 110 corresponding to each of the through holes 100 are formed in the dielectric layer 11 of each of the through holes 100 by means such as laser or mechanical drilling, and a conductive layer 12 is formed on the dielectric layer 11 on opposite sides of the core layer 10 and in each of the through holes 110, wherein the conductive layer 12 can be a metal layer such as copper material to serve as a seed layer.

[0038] In this embodiment, the through hole 100 is in a straight cylindrical shape, and the through hole 110 is in a double cone-shaped hole shape such as an hourglass shape. It should be understood that the through hole 100 and the through hole 110 may also be other hole shapes. In addition, the dielectric layer 11 covers the core layer 10, so the depth of the through hole 110 is greater than that of the through hole 100, and the aperture of the through hole 110 is smaller than that of the through hole 100.

[0039] Furthermore, the thickness of the dielectric layer 11 on the opposite sides of the core layer 10 should be ≥50 μm, and after the through hole 110 is formed, the thickness of the dielectric layer 11 on the wall of the through hole 100 should also be maintained at ≥50 μm.

[0040] like Figure 1C As shown, a plugging material 13 is formed in the through hole 110 to form a substrate 8. By filling the through hole 110 with the plugging material 13, the cost of process and material consumption can be reduced.

[0041] In this embodiment, the plugging material 13 may be an ink material formed by filling methods such as injection, plugging or coating. For example, after the paste ink material is injected into the through hole 110, it is heated for several hours to cross-link the molecules in the ink material and evaporate the solvent. After the ink is solidified, it is polished and leveled with a ceramic roller to remove the surface of the conductive layer 12 on the opposite sides of the core layer 10 and the excess ink protruding from the conductive layer 12 in the through hole 110, so that the ink only fills the through hole 110 without covering the surface of the conductive layer 12.

[0042] Furthermore, the ink material is mainly composed of epoxy ink composites, and has physical properties such as viscosity of 25 to 55 Pa.s, glass transition temperature (Tg) of 145 to 180°C, and / or Young's modulus ≥ 3 GPa. Furthermore, the epoxy ink composite can be cured by heating at 180°C for 2 hours to form the plugging material 13.

[0043] like Figure 1D As shown, a patterned wiring process is performed on the conductive layer 12 on the dielectric layer 11 to form a first wiring layer 14a and a second wiring layer 14b on the dielectric layer 11 on the first side 10a and the second side 10b of the core layer 10, respectively, and the conductive layer 12 in the through hole 110 serves as a hollow conductive column 15 to form a core board body 1a.

[0044] like Figure 1E As shown, the core board 1 a is respectively combined on two opposite sides of a carrier 7 , wherein the core board 1 a is combined with the carrier 7 at its first side 10 a .

[0045] In this embodiment, the carrier 7 is a double capacity bonding material, such as a copper clad laminate (CCL), and the core board 1a is pressed on the copper foils 71 on both sides of the board 70 through the insulating layer 72, so that the first wiring layer 14a of the first side 10a of the core board 1a is buried in the insulating layer 72. For example, the insulating layer 72 is polybenzoxazole (PBO), polyimide (PI), glass fiber prepreg (PP) or other dielectric materials.

[0046] Therefore, in the production process of the package substrate 1 of this embodiment, the design of the carrier 7 allows the subsequent patterning circuit layer build-up operation to be performed in a symmetrical manner, which helps to improve the yield of fine line width / fine line spacing (L / S).

[0047] Furthermore, if a thinner substrate 8 is used, the configuration of the carrier 7 not only facilitates handling or transportation during the process, but also doubles the output.

[0048] like Figure 1F As shown, a patterned circuit build-up operation is performed in a symmetrical manner to form a circuit structure 16 electrically connected to the second wiring layer 14b on the second side 10b of each core board 1a. Next, a first solder mask 17 is formed on the circuit structure 16.

[0049] In this embodiment, the circuit structure 16 includes at least one dielectric layer 160 formed on the core board 1a and at least one circuit layer 161 formed on the dielectric layer 160 and electrically connected to the second wiring layer 14b. For example, the circuit structure 16 with two dielectric layers 160 and two circuit layers 161 as in this embodiment is manufactured by a build-up process by electroplating metal (such as copper) or other methods.

[0050] Furthermore, the dielectric layer 160 can be made of the same material as the dielectric layer 11 , such as ABF film (Ajinomoto build-up film) or other dielectric materials, and the circuit layer 161 is made of copper, such as using a redistribution layer (RDL) specification.

[0051] In addition, a portion of the surface of the circuit layer 161 is exposed from the first solder resist layer 17 to serve as an electrical contact pad. For example, a plurality of solder resist openings 170 are formed on the first solder resist layer 17 to expose the circuit layer 161 .

[0052] In addition, the circuit structure 16 and the core board 1a have four layers of wiring, and the line width / line spacing (L / S) of the three layers from the outermost circuit layer 161 to the second wiring layer 14b of the second side 10b are respectively configured as 5 / 5, 8 / 10 and 15 / 15 microns (um), and the first wiring layer 14a of the first side 10a includes a plurality of ball pads 140. It should be understood that the number of wiring layers of the circuit structure 16 can be determined according to demand and is not limited to the above two layers.

[0053] like Figure 1G As shown, the plate body 70 of the carrier 7 is removed to retain the copper foil 71 on the insulating layer 72 .

[0054] In this embodiment, the first side 10a of the core board 1a is used as the ball implant side, and the second side 10b thereof is used as the build-up side. For example, the width of the first wiring layer 14a (ball implant pad 140 ) of the first side 10a is greater than, less than or equal to the width of the through hole 100 .

[0055] like Figure 1H As shown, the copper foil 71 is first removed to expose the insulating layer 72 , and then a plurality of insulating layer openings 720 are formed on the insulating layer 72 to expose the first wiring layer 14 a (ball planting pad 140 ).

[0056] In this embodiment, the insulating layer 72 can be used as a solder mask, so there is no need to form another solder mask layer.

[0057] Therefore, the package substrate 1 and the manufacturing method thereof of the present embodiment mainly use the first side 10a of the core layer 10 as the ball implanting side to reduce the number of layers of the package substrate 1. Therefore, compared with the prior art, the total thickness of the package substrate 1 is advantageously reduced.

[0058] Furthermore, by means of the ball grid array design of the first side 10a of the core layer 10, the core board body 1a has the conventional ball implant side pad size, the hollow conductive column 15 spacing and the diameter of the through hole 100. Therefore, no matter how the wiring of the circuit structure 16 is designed, the substrate 8 with the through hole 100 and the through hole 110 can be made into the core board body 1a for use in the BGA specification packaging substrate 1, thereby saving process time.

[0059] In addition, because the cracks on the surface of the through hole 100 of the core layer 10 have been covered by the dielectric layer 11, the dielectric layer 11 can provide a barrier and protection function to prevent metal ions from diffusing into the core layer 10 during the subsequent electroplating process and avoid crack expansion. In addition, the present invention first fills the through hole 100 with the dielectric layer 11, and then drills the dielectric layer 11 to form a through hole 110, which is beneficial for the metal of the conductive layer 12 to adhere to the dielectric layer 11 and be used as a seed layer.

[0060] In addition, by using the first side 10 a of the core layer 10 as the ball implantation side, a solder ball (not shown) is used thereon to directly contact the circuit board, thereby shortening the conductive path and reducing signal loss.

[0061] FIG. 2A to FIG. 2D 1 is a cross-sectional view of a second embodiment of the method for manufacturing a package substrate 2 of the present invention. The difference between this embodiment and the first embodiment lies in the configuration of the solder mask layer, so the same points will not be described in detail below.

[0062] like Figure 2A As shown in Figure 1F In the process shown, only the circuit structure 16 is manufactured, and the first solder resist layer 17 is not formed on the circuit structure 16 .

[0063] like Figure 2B As shown, the plate body 70 of the carrier 7 is removed to retain the copper foil 71 on the insulating layer 72 .

[0064] like Figure 2C As shown, the copper foil 71 is first removed to expose the insulating layer 72 , and then a plurality of insulating layer openings 720 are formed on the insulating layer 72 to expose the first wiring layer 14 a (ball planting pad 140 ).

[0065] like Figure 2D As shown, a first solder mask layer 17 and a second solder mask layer 27 are formed on the circuit structure 16 and the insulating layer 72 respectively.

[0066] In this embodiment, a portion of the surface of the circuit layer 161 exposes the first solder mask 17, and the first wiring layer 14a (ball pad 140) exposes the second solder mask 27. For example, a plurality of openings 270 exposing the first wiring layer 14a (ball pad 140) are formed on the second solder mask 27, and the openings 270 correspond to the following: Figure 2C The insulating layer 72 is shown with an insulating layer opening 720, and a plurality of solder mask openings 170 are formed on the first solder mask layer 17 to expose the circuit layer 161, so that the exposed surface of the circuit layer 161 serves as an electrical contact pad.

[0067] In some specific embodiments, according to the above two embodiments, in order to improve the adhesion between the surface of the core layer 10 and the wall of the through hole 100, a bonding layer 22 can be formed on the opposite sides of the core layer 10 and the wall of the through hole 100 as needed, and then the dielectric layer 11 is bonded by the bonding layer 22.

[0068] Furthermore, the bonding layer 22 may be an organic coating formed by a chemical process, for example, depositing an organic polymer such as polyphenylene oxide (PPO), polyamide or poly-dimethylbenzene (PD). Further, a thinner organic coating may be formed by a chemical vapor deposition (CVD) method to improve isolation, corrosion resistance and protection of the surface of the high-rigidity core layer 10, and the thickness thereof may be, for example, 1 nanometer to 100 micrometers, and the organic coating may penetrate into the crack 101 to limit the expansion of the crack 101, such as Figure 1H-1 and Figure 2D-1 As shown, the bonding layer 22 of the organic coating penetrates into the cracks 101 of the core layer 10 and reduces the dielectric constant (Dk) of the core layer 10 to 2.5 to 5 (1 GHz), for example, 2.5, 2.65, 2.7, 2.8, 2.9, 3.0, 3.2, 3.5, 3.7, 4.0, 4.2, 4.5, 4.7 and 5.0 (1 GHz).

[0069] On the other hand, the bonding layer 22 may also be an inorganic coating formed by a physical process to form a Van der Waals force. For example, sandblasting with silica sand having a diameter of 20 to 50 microns and a roughness Ra of 1 to 200 microns can not only remove oxides and impurities on the core layer 10, but also increase the surface area of ​​the core layer 10, thereby helping to improve the adhesion of the dielectric layer 11 formed on the core layer 10 of high hardness material. Therefore, in a specific embodiment, the bonding layer 22 is formed by silica sand having a diameter of 20 to 50 microns and a roughness Ra of 1 to 200 microns.

[0070] The present invention also provides a packaging substrate 1 , 2 , including: a core board 1 a , an insulating layer 72 and a circuit structure 16 .

[0071] The core board 1a includes a core layer 10, a plurality of through holes 100, a dielectric layer 11, a plurality of through holes 110, a plurality of hollow conductive pillars 15, a plugging material 13, a first wiring layer 14a and a second wiring layer 14b.

[0072] The core layer 10 has a first side 10 a and a second side 10 b opposite to each other.

[0073] The through hole 100 is formed in the core layer 10 and connects the first side 10 a and the second side 10 b .

[0074] The dielectric layer 11 is formed on two opposite sides of the core layer 10 and on the wall surface of the through hole 100 .

[0075] The through holes 110 are formed in the dielectric layer 11 on the wall of the through holes 100 and correspond to each of the through holes 100 .

[0076] The hollow conductive pillars 15 are each formed in the corresponding through hole 110 .

[0077] The plugging material 13 is formed in the hollow conductive column 15 .

[0078] The first wiring layer 14a and the second wiring layer 14b are respectively formed on the dielectric layer 11 on the first side 10a and the second side 10b and electrically connected to the hollow conductive pillar 15, wherein the first wiring layer 14a on the dielectric layer 11 on the first side 10a has a plurality of ball pads 140.

[0079] The insulating layer 72 is formed on the dielectric layer 11 of the first side 10 a of the core layer 10 , so that the first wiring layer 14 a of the first side 10 a of the core board body 1 a is buried in the insulating layer 72 .

[0080] The circuit structure 16 is disposed on the dielectric layer 11 of the second side 10 b of the core layer 10 and is electrically connected to the second wiring layer 14 b of the second side 10 b of the core board body 1 a.

[0081] In one embodiment, the material of the dielectric layer 11 is different from that of the plugging material 13 .

[0082] In one embodiment, the dielectric layer 11 includes an ABF film (Ajinomoto build-up film).

[0083] In one embodiment, the thickness of the dielectric layer 11 formed on the opposite sides of the core layer 10 and the wall surface of the through hole 100 is ≥50 μm.

[0084] In one embodiment, the circuit structure 16 includes at least one dielectric layer 160 formed on the core board 1 a and at least one circuit layer 161 formed on the dielectric layer 160 .

[0085] In one embodiment, the material of the dielectric layer 160 is the same as the material of the dielectric layer 11 .

[0086] In one embodiment, the insulating layer 72 is formed with a plurality of insulating layer openings 720 penetrating the insulating layer 72 to expose the ball pads 140 on the first side 10 a of the core board 1 a , so that the insulating layer 72 can be used as a solder mask.

[0087] In one embodiment, the package substrate 1 , 2 further includes a first solder mask layer 17 formed on the circuit structure 16 .

[0088] In one embodiment, the insulating layer 72 is formed with a plurality of insulating layer openings 720 that penetrate the insulating layer 72 to expose the ball planting pad 140 on the first side 10a of the core board body 1a; and the packaging substrate 1, 2 also includes a second solder mask layer 27 formed on the insulating layer 72 and having an opening 270 corresponding to the insulating layer opening 720, so that the ball planting pad 140 is exposed in the insulating layer opening 720 and the opening 270.

[0089] In one embodiment, the core board 1 a further includes a bonding layer 22 formed on the surfaces of the opposite first side 10 a and second side 10 b of the core layer 10 and the surface of the through hole 100 to be located between the core layer 10 and the dielectric layer 11 .

[0090] In one embodiment, the bonding layer 22 is an organic coating or an inorganic coating.

[0091] In one embodiment, the material forming the organic coating is a polymer, and the thickness of the organic coating is, for example, 1 nanometer to 100 micrometers.

[0092] In one embodiment, the polymer is selected from at least one of the group consisting of polyoxyxylene, polyamide and polyparaxylene.

[0093] In one embodiment, the material forming the inorganic coating includes silica sand with a diameter of 20 to 50 micrometers and a roughness Ra of 1 to 200 micrometers.

[0094] In summary, the package substrate and the manufacturing method thereof of the present invention mainly use the first side of the core layer as the ball implanting side to reduce the number of layers of the package substrate, so the total thickness of the package substrate is advantageously reduced.

[0095] Furthermore, through the ball grid array design on the first side of the core layer, the core board has a conventional ball planting side pad size, conductive column spacing and through-hole diameter. Therefore, no matter how the wiring of the circuit structure is designed, the substrate with through-holes and through-holes can be made into the core board for use in a BGA specification packaging substrate, thereby saving process time.

[0096] In addition, the present invention covers the cracks on the perforated surface of the core layer with a dielectric layer. The dielectric layer can serve as a barrier between the core layer and the conductive layer to prevent metal ions from diffusing into the core layer during the electroplating process. The dielectric layer can also provide a protective function to prevent the package substrate from breaking due to crack expansion. In addition, the present invention first fills the perforation with a dielectric layer, and then drills the dielectric layer to form a through hole, which is conducive to the metal of the conductive layer being attached to the dielectric layer for use as a seed layer.

[0097] In addition, the present invention uses the first side of the core layer as the ball-planting side so that solder balls are directly contacted with the circuit board, thereby shortening the conductive path and reducing signal loss.

[0098] The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Those skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A packaging substrate, characterized in that: include: The core board includes: A core layer having a first side and a second side opposite to each other; A plurality of through holes connecting the first side and the second side; a dielectric layer formed on opposite sides of the core layer and in the through hole; A plurality of through holes are respectively formed in the dielectric layer of the through hole and correspond to each of the through holes; A plurality of hollow conductive pillars, each formed in the corresponding through hole; A plugging material is formed in the hollow conductive column; and A first wiring layer and a second wiring layer are respectively formed on the dielectric layer on the first side and the second side and electrically connected to the hollow conductive pillar, wherein the first wiring layer formed on the dielectric layer on the first side has a plurality of ball pads; An insulating layer is formed on the dielectric layer on the first side of the core layer, so that the first wiring layer on the first side of the core board is buried in the insulating layer; and The circuit structure is arranged on the dielectric layer on the second side of the core layer and is electrically connected to the second wiring layer on the second side of the core board.

2. The packaging substrate according to claim 1, wherein: The material of the dielectric layer is different from that of the plugging material.

3. The packaging substrate according to claim 2, wherein: The dielectric layer includes an ABF film.

4. The packaging substrate according to claim 1, wherein: The thickness of the dielectric layer formed on the opposite sides of the core layer and on the wall surface of the through hole is ≥50 μm.

5. The packaging substrate according to claim 1, wherein: The circuit structure comprises at least one dielectric layer formed on the core board and at least one circuit layer formed on the dielectric layer.

6. The packaging substrate according to claim 5, characterized in that The material of the medium layer is the same as that of the dielectric layer.

7. The packaging substrate according to claim 1, wherein: The insulating layer is formed with a plurality of insulating layer openings penetrating through the insulating layer to expose the ball-planting pads on the first side of the core board body, so that the insulating layer can be used as solder-proof.

8. The packaging substrate according to claim 1, wherein: The packaging substrate also includes a first solder mask formed on the circuit structure.

9. The packaging substrate according to claim 1, wherein: The insulating layer is formed with a plurality of insulating layer openings penetrating the insulating layer to expose the ball planting pad on the first side of the core board body, and the packaging substrate also includes a second solder mask layer formed on the insulating layer and having openings corresponding to the insulating layer openings, so that the ball planting pad is exposed in the insulating layer openings and the openings.

10. The packaging substrate according to claim 1, wherein: The core board also includes a bonding layer formed on the surfaces of the first side and the second side opposite to the core layer and the surface of the through hole so as to be located between the core layer and the dielectric layer.

11. The packaging substrate according to claim 10, wherein: The bonding layer is an organic coating or an inorganic coating, wherein the material forming the organic coating is selected from at least one of the group consisting of polyoxyxylene, polyamide and polyparaxylene, and the material forming the inorganic coating includes silica sand with a diameter of 20 to 50 microns and a roughness Ra of 1 to 200 microns.

12. A method for manufacturing a packaging substrate, characterized in that: include: A plurality of core boards are provided, wherein each of the core boards comprises a core layer having a first side and a second side opposite to each other, a plurality of through-holes connecting the first side and the second side of the core layer, a dielectric layer formed on opposite sides of the core layer and the through-holes, a through-hole formed in the dielectric layer of the through-holes and corresponding to each of the through-holes, a hollow conductive column formed in each of the through-holes, a plugging material formed in the hollow conductive column, and a first wiring layer and a second wiring layer electrically connected to the hollow conductive column formed on the dielectric layer on the first side and the second side, respectively, wherein the first wiring layer formed on the dielectric layer on the first side has a plurality of ball pads; The core board is pressed on two opposite sides of a carrier through insulating layers, so that the first wiring layer on the first side of the core board is buried in the insulating layer; forming a circuit structure on the dielectric layer on the second side of the core layer, and electrically connecting the circuit structure to the second wiring layer on the second side of the core board; and The carrier is removed to expose the insulating layer.

13. The method for manufacturing a packaging substrate according to claim 12, wherein: The material of the dielectric layer is different from that of the plugging material.

14. The method for manufacturing a packaging substrate according to claim 13, wherein: The dielectric layer includes an ABF film.

15. The method for manufacturing a packaging substrate according to claim 12, wherein: The thickness of the dielectric layer formed on the opposite sides of the core layer and on the wall surface of the through hole is ≥50 μm.

16. The method for manufacturing a packaging substrate according to claim 12, wherein: The circuit structure comprises at least one dielectric layer formed on the core board and at least one circuit layer formed on the dielectric layer.

17. The method for manufacturing a packaging substrate according to claim 16, wherein: The material of the medium layer is the same as that of the dielectric layer.

18. The method for manufacturing a packaging substrate according to claim 12, wherein: The manufacturing method further comprises, after removing the carrier, forming a plurality of insulating layer openings penetrating the insulating layer to expose the ball-planting pads on the first side of the core board, so that the insulating layer can be used as a solder mask.

19. The method for manufacturing a packaging substrate according to claim 12, wherein: The manufacturing method also includes forming a first solder resist layer on the circuit structure.

20. The method for manufacturing a packaging substrate according to claim 12, wherein: The manufacturing method also includes, after removing the carrier, forming a plurality of insulating layer openings penetrating the insulating layer to expose the ball planting pad on the first side of the core board; and forming a second solder mask layer on the insulating layer having openings corresponding to the insulating layer openings to expose the ball planting pad in the insulating layer openings.

21. The method for manufacturing a packaging substrate according to claim 12, wherein: The core board also includes a bonding layer formed on the surfaces of the first side and the second side opposite to the core layer and the surface of the through hole so as to be located between the core layer and the dielectric layer.

22. The method for manufacturing a packaging substrate according to claim 21, wherein: The bonding layer is an organic coating or an inorganic coating, wherein the material forming the organic coating is selected from at least one of the group consisting of polyoxyxylene, polyamide and polyparaxylene, and the material forming the inorganic coating includes silica sand with a diameter of 20 to 50 microns and a roughness Ra of 1 to 200 microns.

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