Anti-low-ripple overcurrent protection circuit

Abstract

The invention relates to the technical field of integrated circuits, and provides an anti-low-ripple overcurrent protection circuit, which comprises a power supply, a biasing circuit, a comparator circuit, a Schmidt circuit and a driver circuit, the power supply is electrically connected with the biasing circuit, the comparator circuit, the Schmidt circuit and the driver circuit respectively; the input end of the bias circuit is connected with the power supply, the output end of the bias circuit is connected with the input end of the comparator circuit, and the bias circuit is used for providing bias voltage for the comparator circuit; the output end of the comparator circuit is connected with the input end of the Schmidt circuit, the output end of the Schmidt circuit is connected with the input end of the driver circuit, and the output end of the driver circuit is connected with a load. According to the overcurrent protection circuit capable of preventing low ripple, overcurrent protection false triggering is avoided, the overcurrent protection function of the CMOS circuit is improved, and the user experience and reliability are further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an overcurrent protection circuit capable of preventing low ripple. Background Art

[0002] With the continuous advancement of science and technology and the popularization of electronic products, power semiconductor chips play a vital role in the electronics industry. The acceptable over-current short-circuit time of commonly used power semiconductors is extremely short, only within microseconds or nanoseconds. If the power semiconductor chip cannot disconnect the power supply in time within the acceptable over-current short-circuit time, the power semiconductor chip will be damaged.

[0003] With the rapid development of large-scale integrated circuits, portable electronic products have sprung up and entered people's lives at an amazing speed. In power management chips, overcurrent protection measures are even more important. Overcurrent protection circuits, the basic circuits were relatively simple in the past, but in practical applications, they are prone to bottom ripple problems, which can lead to false triggering.

[0004] However, when the above-mentioned power management chip is used in electronic equipment, especially outdoors, there are many influencing factors, such as false triggering of overcurrent protection, which makes the chip overcurrent protection have no anti-bottom ripple function, which will affect the product usage experience and poor reliability. Summary of the invention

[0005] The present invention provides an overcurrent protection circuit for preventing low ripple, aiming to solve the problems of poor reliability of existing semiconductor chips and poor user experience.

[0006] An embodiment of the present invention provides an overcurrent protection circuit for low ripple protection, comprising: a power supply, a bias circuit, a comparator circuit, a Schmidt circuit and a driver circuit; the power supply is electrically connected to the bias circuit, the comparator circuit, the Schmidt circuit and the driver circuit respectively;

[0007] The input end of the bias circuit is connected to the power supply, and the output end of the bias circuit is connected to the input end of the comparator circuit, so as to provide a bias voltage for the comparator circuit; the output end of the comparator circuit is connected to the input end of the Schmitt circuit, the output end of the Schmitt circuit is connected to the input end of the driver circuit, and the output end of the driver circuit is connected to a load;

[0008] The Schmitt circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor and a second resistor;

[0009] The source of the first PMOS tube is connected to the power supply, the gate of the first PMOS tube is respectively connected to the gate of the second PMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube and serves as the input end of the Schmitt circuit, the drain of the first PMOS tube is respectively connected to the source of the second PMOS tube and the source of the third PMOS tube, the drain of the third PMOS tube is connected to the first end of the first resistor, and the second end of the first resistor is grounded; the drain of the second PMOS tube is respectively connected to the drain of the first NMOS tube, the gate of the fourth PMOS tube and the gate of the fourth NMOS tube;

[0010] The source of the first NMOS tube is connected to the drain of the second NMOS tube and the source of the third NMOS tube respectively, and the source of the second NMOS tube is grounded; the gate of the third NMOS tube is connected to the gate of the third PMOS tube, the drain of the third NMOS tube is connected to the first end of the second resistor, and the second end of the second resistor is grounded;

[0011] The source of the fourth PMOS tube is connected to the power supply, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube and serves as the output end of the Schmitt circuit; the source of the fourth NMOS tube is grounded.

[0012] Preferably, the bias circuit includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a third resistor, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube;

[0013] The source of the fifth PMOS tube is respectively connected to the source of the sixth PMOS tube and the source of the seventh PMOS tube and connected to the power supply; the gate of the fifth PMOS tube is connected to the gate of the fifth PMOS tube, and the gate of the sixth PMOS tube is respectively connected to the gate of the seventh PMOS tube and the drain of the sixth PMOS tube;

[0014] The drain of the fifth PMOS tube is connected to the first end of the third resistor, and the second end of the third resistor is respectively connected to the gate of the eighth PMOS tube and the drain of the seventh NMOS tube; the drain of the eighth PMOS tube is connected to the source of the seventh NMOS tube and grounded; the source of the eighth PMOS tube is respectively connected to the drain of the sixth PMOS tube and the drain of the fifth NMOS tube; the source of the fifth NMOS tube is grounded;

[0015] The gate of the fifth NMOS tube is respectively connected to the gate of the seventh NMOS tube and the gate of the sixth NMOS tube; the drain of the sixth NMOS tube is respectively connected to the gate of the sixth NMOS tube and the drain of the seventh PMOS tube; the source of the sixth NMOS tube is grounded.

[0016] Preferably, the comparator circuit includes a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a fourth resistor, a fifth resistor, a first diode, a seventh NMOS tube and an eighth NMOS tube;

[0017] The source of the ninth PMOS tube and the source of the twelfth PMOS tube are connected and connected to the power supply; the gate of the ninth PMOS tube and the gate of the twelfth PMOS tube are used to access the bias voltage output by the bias circuit; the drain of the ninth PMOS tube is respectively connected to the source of the tenth PMOS tube and the source of the eleventh PMOS tube;

[0018] The gate of the tenth PMOS tube is connected to the bias voltage of the bias circuit; the drain of the tenth PMOS tube is connected to the drain of the seventh NMOS tube, the gate of the seventh NMOS tube is respectively connected to the drain of the seventh NMOS tube and the gate of the eighth NMOS tube, and the source of the seventh NMOS tube is grounded;

[0019] The gate of the eleventh PMOS tube is respectively connected to the first end of the fourth resistor and the first end of the fifth resistor, and the second end of the fourth resistor is connected to the drain of the twelfth PMOS tube; the drain of the twelfth PMOS tube is also connected to the cathode of the first diode, and the anode of the first diode is grounded;

[0020] The second end of the fifth resistor is grounded; the drain of the eleventh PMOS tube is connected to the drain of the eighth NMOS tube and serves as the output end of the comparator circuit;

[0021] The source of the eighth NMOS tube is grounded.

[0022] Preferably, the driver circuit includes a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube and an eleventh NMOS tube;

[0023] The source of the thirteenth PMOS tube is connected to the power supply, and the drain of the thirteenth PMOS tube is respectively connected to the source of the fourteenth PMOS tube, the source of the fifteenth PMOS tube and the source of the sixteenth PMOS tube; the gate of the thirteenth PMOS tube is connected to the gate of the fourteenth PMOS tube, and the drain of the fourteenth PMOS tube is respectively connected to the gate of the fifteenth PMOS tube, the drain of the ninth NMOS tube and the gate of the tenth NMOS tube; the gate of the ninth NMOS tube serves as the input end of the driver circuit, and the source of the ninth NMOS tube is connected to the source of the tenth NMOS tube and the source of the eleventh NMOS tube and is grounded;

[0024] The drain of the fifteenth PMOS tube is respectively connected to the drain of the tenth NMOS tube, the gate of the sixteenth PMOS tube and the gate of the eleventh NMOS tube; the drain of the sixteenth PMOS tube is connected to the drain of the eleventh NMOS tube and serves as the output end of the driver circuit.

[0025] Compared with the prior art, the beneficial effects of the present invention lie in that the power supply is electrically connected to the bias circuit, the comparator circuit, the Schmidt circuit and the driver circuit respectively; the input end of the bias circuit is connected to the power supply, and the output end of the bias circuit is connected to the input end of the comparator circuit, so as to provide a bias voltage for the comparator circuit; the output end of the comparator circuit is connected to the input end of the Schmidt circuit, the output end of the Schmidt circuit is connected to the input end of the driver circuit, and the output end of the driver circuit is connected to the load; through the bias circuit, the comparator circuit, the Schmidt circuit and the driver circuit that are electrically connected in sequence, the current output by the comparator circuit is processed by the Schmidt circuit, so as to avoid false triggering of overcurrent protection, improve the overcurrent protection function of the CMOS circuit, and further improve the user experience and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings:

[0027] Figure 1 is a circuit diagram of an overcurrent protection circuit for preventing low ripple provided by an embodiment of the present invention;

[0028] Figure 2 is a circuit diagram of a bias circuit provided by an embodiment of the present invention;

[0029] Figure 3 is a circuit diagram of a comparator circuit provided by an embodiment of the present invention;

[0030] Figure 4 is a circuit diagram of a Schmitt circuit and a driver circuit provided by an embodiment of the present invention;

[0031] Figure 5 Schematic diagram of the overcurrent protection effect of the falsely triggered overcurrent voltage provided by the embodiment of the present invention;

[0032] Figure 6 It is a schematic diagram of the effect of the overcurrent protection voltage provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0034] Combined with Figure 1-Figure 6 As shown, an embodiment of the present invention provides an overcurrent protection circuit for low ripple protection, comprising: a power supply VDD, a bias circuit 1, a comparator circuit 2, a Schmitt circuit 3 and a driver circuit 4; the power supply VDD is electrically connected to the bias circuit 1, the comparator circuit 2, the Schmitt circuit 3 and the driver circuit 4 respectively.

[0035] The input end of the bias circuit 1 is connected to the power supply VDD, and the output end of the bias circuit 1 is connected to the input end of the comparator circuit 2, so as to provide a bias voltage for the comparator circuit 2; the output end of the comparator circuit 2 is connected to the input end of the Schmitt circuit 3, the output end of the Schmitt circuit 3 is connected to the input end of the driver circuit 4, and the output end of the driver circuit 4 is connected to a load; by electrically connecting the power supply VDD to the bias circuit 1, the comparator circuit 2, the Schmitt circuit 3 and the driver circuit 4 respectively; the input end of the bias circuit 1 is connected to the power supply VDD, The output end of the bias circuit 1 is connected to the input end of the comparator circuit 2, so as to provide a bias voltage for the comparator circuit 2; the output end of the comparator circuit is connected to the input end of the Schmidt circuit 3, the output end of the Schmidt circuit 3 is connected to the input end of the driver circuit 4, and the output end of the driver circuit 4 is connected to the load; through the bias circuit 1, the comparator circuit 2, the Schmidt circuit 3 and the driver circuit 4 which are electrically connected in sequence, the current output by the comparator circuit 2 is processed by the Schmidt circuit 3 to avoid false triggering of the overcurrent protection, thereby improving the overcurrent protection function of the CMOS circuit, and further improving the user experience and reliability.

[0036] Specifically, the Schmitt circuit 3 includes a first PMOS transistor M1, a second PMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a first resistor R1 and a second resistor R2; the source of the first PMOS transistor M1 is connected to the power supply VDD, the gate of the first PMOS transistor M1 is respectively connected to the gate of the second PMOS transistor M2, the gate of the first NMOS transistor N1 and the gate of the second NMOS transistor N2 and serves as the input end of the Schmitt circuit 3, the drain of the first PMOS transistor M1 is respectively connected to the source of the second PMOS transistor M2 and the source of the third PMOS transistor M3, the drain of the third PMOS transistor M3 is connected to the first end of the first resistor R1, and the second end of the first resistor R1 is grounded; the drain of the second PMOS transistor M2 is respectively connected to the drain of the first NMOS transistor N1, the gate of the fourth PMOS transistor M4 and the gate of the fourth NMOS transistor N4.

[0037] The source of the first NMOS tube N1 is respectively connected to the drain of the second NMOS tube N2 and the source of the third NMOS tube N3, and the source of the second NMOS tube N2 is grounded; the gate of the third NMOS tube N3 is connected to the gate of the third PMOS tube M3, the drain of the third NMOS tube N3 is connected to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded.

[0038] The source of the fourth PMOS tube M4 is connected to the power supply VDD, the drain of the fourth PMOS tube M4 is connected to the drain of the fourth NMOS tube N4 and serves as the output end of the Schmitt circuit 3; the source of the fourth NMOS tube N4 is grounded.

[0039] Specifically, in order to prevent the output signal from being affected by noise and other signal clutter;

[0040] VTH+ is mainly affected by the width-to-length ratio of the NMOS tube;

[0041] VTH- is mainly affected by the width-to-length ratio of the PMOS tube;

[0042] The influence of the MOS tube width-to-length ratio on the threshold voltage gradually decreases as the ratio increases;

[0043] The change in the width-to-length ratio of the fourth PMOS tube M4 and the first NMOS tube N1 has little effect on the threshold voltage, and the threshold voltage remains basically unchanged. The width-to-length ratio of the first NMOS tube N1 increases, and the positive threshold voltage increases slightly; the width-to-length ratio of the fourth PMOS tube M4 increases, and the negative threshold voltage decreases slightly. M4&N1 acts as a turning point for the positive and negative threshold voltages to flip (similar to the effect of a switch).

[0044] In the six-transistor Schmitt circuit 3, the negative threshold voltage is mainly affected by M1 / M3, and the positive threshold voltage is mainly affected by N2 / N3.

[0045] To increase / decrease the threshold voltage:

[0046] By increasing / decreasing the width-to-length ratio of the first PMOS tube M1 or decreasing / increasing the width-to-length ratio of the third PMOS tube M3;

[0047] If the width-to-length ratios of the first PMOS tube M1 and the third PMOS tube M3 are changed at the same time, the increase / decrease range of the width-to-length ratio of the first PMOS tube M1 must be greater than / less than the decrease / increase range of the width-to-length ratio of the third PMOS tube M3.

[0048] To increase / decrease the positive threshold voltage and keep the negative threshold voltage unchanged:

[0049] By increasing / decreasing the width-to-length ratio of the third NMOS tube N3;

[0050] On the premise that the positive threshold voltage rises / falls and the negative threshold voltage remains unchanged, the width-to-length ratio of the third PMOS tube M3 is increased / decreased until the negative threshold voltage falls / rises to the initial value.

[0051] To decrease / increase the negative threshold voltage while keeping the positive threshold voltage unchanged:

[0052] Increase / decrease the width-to-length ratio of the third PMOS tube M3;

[0053] Under the above premise, the width-to-length ratio of the third NMOS transistor N3 is increased / decreased until the forward threshold voltage rises / falls to the initial value.

[0054] In this embodiment, the bias circuit 1 includes a fifth PMOS transistor M5, a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a third resistor R3, a fifth NMOS transistor N5, a sixth NMOS transistor N6 and a seventh NMOS transistor N7;

[0055] The source of the fifth PMOS tube M5 is respectively connected to the source of the sixth PMOS tube M6 and the source of the seventh PMOS tube M7 and is connected to the power supply VDD; the gate of the fifth PMOS tube M5 is connected to the gate of the fifth PMOS tube M5, and the gate of the sixth PMOS tube M6 is respectively connected to the gate of the seventh PMOS tube M7 and the drain of the sixth PMOS tube M6;

[0056] The drain of the fifth PMOS tube M5 is connected to the first end of the third resistor R3, and the second end of the third resistor R3 is respectively connected to the gate of the eighth PMOS tube M8 and the drain of the seventh NMOS tube N7; the drain of the eighth PMOS tube M8 is connected to the source of the seventh NMOS tube N7 and grounded; the source of the eighth PMOS tube M8 is respectively connected to the drain of the sixth PMOS tube M6 and the drain of the fifth NMOS tube N5; the source of the fifth NMOS tube N5 is grounded;

[0057] The gate of the fifth NMOS tube N5 is respectively connected to the gate of the seventh NMOS tube N7 and the gate of the sixth NMOS tube N6; the drain of the sixth NMOS tube N6 is respectively connected to the gate of the sixth NMOS tube N6 and the drain of the seventh PMOS tube M7; the source of the sixth NMOS tube N6 is grounded.

[0058] Specifically, the bias voltage VB output by the bias circuit 1 is generated by the fifth PMOS tube M5, the sixth PMOS tube M6, the seventh PMOS tube M7; the fifth NMOS tube N5, the sixth NMOS tube N6, and the third resistor R3. The fifth PMOS tube M5 and the third resistor R3 act as a branch voltage divider, the sixth PMOS tube M6 and the seventh PMOS tube M7 become a current mirror; the fifth NMOS tube N5 and the sixth NMOS tube N6 form a current mirror.

[0059] The sixth PMOS transistor M6 and the sixth NMOS transistor N6 are diode-connected, and when they are turned on, they are in a saturation state. As shown in the formula Vds>Vgs-Vth(1);

[0060] Vds drain-source voltage, vgs gate-source voltage, vth threshold voltage.

[0061]

[0062] I is the drain-source current, μn is the electron mobility, which reflects the speed at which electrons move in the semiconductor. Cox is the capacitance of the gate oxide layer. W is the width of the channel. L is the length of the channel.

[0063] VGS is the voltage between the gate and the source. Vth is the threshold voltage of the MOS tube.

[0064] Since the sixth PMOS tube M6 and the seventh PMOS tube M7; the fifth NMOS tube N5 and the sixth NMOS tube N6 are current mirrors, the current between them is the width-to-length ratio.

[0065]

[0066] IDS2, IDS3 is the drain-source current, W / L is the width-to-length ratio of mos2, mos3.

[0067] The seventh PMOS tube M7 and the fifth NMOS tube N5 are in the linear region;

[0068]

[0069] I is the drain-source current, μn is the electron mobility, which reflects the speed at which electrons move in the semiconductor.

[0070] Cox is the capacitance of the gate oxide. W is the width of the channel. L is the length of the channel.

[0071] VGS is the voltage between the gate and the source. Vth is the threshold voltage of the MOS tube. λ is the channel length modulation parameter, and VDS is the voltage from the drain to the source.

[0072] Adjust I by aspect ratio DS2 =I DS3 , that is, the currents of the two branches are equal. The bias voltage VB can be adjusted by adjusting the width-to-length ratio of the sixth NMOS transistor N6 and the seventh PMOS transistor M7.

[0073] The sixth NMOS tube N6 is in saturation state. Due to the stable current, the width-to-length ratio is increased, and V GS The gate voltage of the sixth NMOS transistor N6 decreases. The fifth NMOS transistor N5 is in the linear region, the current is equal, the width-to-length ratio does not change, the fifth NMOS transistor N5 and the sixth NMOS transistor N6 are interconnected by a common gate, and as the V GS N5 decreases, V DS As N5 increases, VB also increases in voltage.

[0074] The seventh PMOS tube M7 is a linear region, increasing the width-to-length ratio, V DS M7 increases, V GS As the gate voltage of N7 increases, the fifth NMOS tube N5 is in the linear region, the current is equal, and the width-to-length ratio does not change. The fifth NMOS tube N5 and the sixth NMOS tube N6 are interconnected with the same gate. As the V GS N5 increases, V DS As N5 decreases, VB both increases and decreases.

[0075] In this embodiment, the comparator circuit 2 includes a ninth PMOS transistor M9, a tenth PMOS transistor M10, an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a fourth resistor R4, a fifth resistor R5, a first diode D1, a seventh NMOS transistor N7 and an eighth NMOS transistor N8.

[0076] The source of the ninth PMOS tube M9 and the source of the twelfth PMOS tube M12 are connected and connected to the power supply VDD; the gate of the ninth PMOS tube M9 and the gate of the twelfth PMOS tube M12 are used to access the bias voltage output by the bias circuit 1; the drain of the ninth PMOS tube M9 is respectively connected to the source of the tenth PMOS tube M10 and the source of the eleventh PMOS tube M11.

[0077] The gate of the tenth PMOS tube M10 is connected to the bias voltage of the bias circuit 1; the drain of the tenth PMOS tube M10 is connected to the drain of the seventh NMOS tube N7, the gate of the seventh NMOS tube N7 is respectively connected to the drain of the seventh NMOS tube N7 and the gate of the eighth NMOS tube N8, and the source of the seventh NMOS tube N7 is grounded.

[0078] The gate of the eleventh PMOS tube M11 is respectively connected to the first end of the fourth resistor R4 and the first end of the fifth resistor R5, and the second end of the fourth resistor R4 is connected to the drain of the twelfth PMOS tube M12; the drain of the twelfth PMOS tube M12 is also connected to the cathode of the first diode D1, and the anode of the first diode D1 is grounded.

[0079] The second end of the fifth resistor R5 is grounded; the drain of the eleventh PMOS tube M11 is connected to the drain of the eighth NMOS tube N8 and serves as the output end of the comparator circuit 2; the source of the eighth NMOS tube N8 is grounded.

[0080] Specifically, the twelfth PMOS tube M12, the fourth resistor R4, the fifth resistor R5, and the first diode D1 form a sampling circuit. The parallel circuit divides the voltage. The D1 voltage regulator diode stabilizes the fixed voltage. By adjusting the size of the fourth resistor R4 and the fifth resistor R5, different sampling voltages can be output.

[0081] The value of the bias voltage VB is just enough to conduct, the thirteenth PMOS tube M13 and the fourteenth PMOS tube M14 make Vout1 output a low voltage and operate normally, Vout2 is at a high level, and the signal is given to the next circuit module.

[0082] VA is the input port of the external signal. When an overcurrent signal is input, it flows through the resistor to form a high-voltage signal, which is given to the comparator composed of the ninth PMOS tube M9, the tenth PMOS tube M10, the eleventh PMOS tube M11, the seventh NMOS tube N7, and the eighth NMOS tube N8.

[0083] In the comparator, the seventh NMOS tube N7 and the eighth NMOS tube N8 are set to have the same width-to-length ratio, and I DS N4=I DSN5, the currents in the two branches are equal.

[0084] M10 V G M10 changes from small to large, and a linear region appears. V GS M10 becomes larger, pushing V DS M10 decreases, the gate voltages of the seventh NMOS tube N7 and the eighth NMOS tube N8 decrease, and V DS N8 increases the output high level.

[0085] It flows through the Schmitt circuit and has the function of resisting ripple. The high level is output to the sixth NMOS tube N6 to turn on, pulling down the voltage of the thirteenth and fourth PMOS tube M14, so that Vout1 outputs a high voltage, shuts down the operation, Vout2 is at a low level, and the signal is given to the next circuit module.

[0086] In this embodiment, the driver circuit 4 includes a thirteenth PMOS tube M13, a fourteenth PMOS tube M14, a fifteenth PMOS tube M15, a sixteenth PMOS tube M16, a ninth NMOS tube N9, a tenth NMOS tube N10 and an eleventh NMOS tube N11;

[0087] The source of the thirteenth PMOS tube is connected to the power supply VDD, and the drain of the thirteenth PMOS tube M13 is respectively connected to the source of the fourteenth PMOS tube M14, the source of the fifteenth PMOS tube M15 and the source of the sixteenth PMOS tube M16; the gate of the thirteenth PMOS tube M13 is connected to the gate of the fourteenth PMOS tube M14, and the drain of the fourteenth PMOS tube M14 is respectively connected to the gate of the fifteenth PMOS tube M15, the drain of the ninth NMOS tube N9 and the gate of the tenth NMOS tube N10; the gate of the ninth NMOS tube N9 serves as the input end of the driver circuit 4, and the source of the ninth NMOS tube N9 is connected to the source of the tenth NMOS tube N10 and the source of the eleventh NMOS tube N11 and is grounded;

[0088] The drain of the fifteenth PMOS tube M15 is respectively connected to the drain of the tenth NMOS tube N10, the gate of the sixteenth PMOS tube M16 and the gate of the eleventh NMOS tube N11; the drain of the sixteenth PMOS tube M16 is connected to the drain of the eleventh NMOS tube N11 and serves as the output end of the driver circuit 4.

[0089] Specifically, the fifteenth PMOS tube M15, the sixteenth PMOS tube M16, the tenth NMOS tube N10, and the eleventh NMOS tube N11 constitute a driver to enhance the driving capability of the signal and improve the signal integrity, while providing two functions of in-phase and inverting. First, enhance the signal: enable the signal to be transmitted to the subsequent circuit more effectively, and avoid the signal from being weakened due to factors such as attenuation or load during the transmission process. Second, improve the signal integrity: reduce the distortion and distortion of the signal to ensure the quality of the signal.

[0090] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, article or device. In the absence of more restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, article or device including the element.

[0091] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A low ripple overcurrent protection circuit, characterized in that: include: Power supply, bias circuit, comparator circuit, Schmitt circuit and driver circuit; The power supply is electrically connected to the bias circuit, the comparator circuit, the Schmitt circuit and the driver circuit respectively; The input end of the bias circuit is connected to the power supply, and the output end of the bias circuit is connected to the input end of the comparator circuit, so as to provide a bias voltage for the comparator circuit; the output end of the comparator circuit is connected to the input end of the Schmitt circuit, the output end of the Schmitt circuit is connected to the input end of the driver circuit, and the output end of the driver circuit is connected to a load; The Schmitt circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first resistor and a second resistor; The source of the first PMOS tube is connected to the power supply, the gate of the first PMOS tube is respectively connected to the gate of the second PMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube and serves as the input end of the Schmitt circuit, the drain of the first PMOS tube is respectively connected to the source of the second PMOS tube and the source of the third PMOS tube, the drain of the third PMOS tube is connected to the first end of the first resistor, and the second end of the first resistor is grounded; the drain of the second PMOS tube is respectively connected to the drain of the first NMOS tube, the gate of the fourth PMOS tube and the gate of the fourth NMOS tube; The source of the first NMOS tube is connected to the drain of the second NMOS tube and the source of the third NMOS tube respectively, and the source of the second NMOS tube is grounded; the gate of the third NMOS tube is connected to the gate of the third PMOS tube, the drain of the third NMOS tube is connected to the first end of the second resistor, and the second end of the second resistor is grounded; The source of the fourth PMOS tube is connected to the power supply, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube and serves as the output end of the Schmitt circuit; the source of the fourth NMOS tube is grounded.

2. The low ripple overcurrent protection circuit according to claim 1, characterized in that: The bias circuit includes a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a third resistor, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube; The source of the fifth PMOS tube is respectively connected to the source of the sixth PMOS tube and the source of the seventh PMOS tube and connected to the power supply; the gate of the fifth PMOS tube is connected to the gate of the fifth PMOS tube, and the gate of the sixth PMOS tube is respectively connected to the gate of the seventh PMOS tube and the drain of the sixth PMOS tube; The drain of the fifth PMOS tube is connected to the first end of the third resistor, and the second end of the third resistor is respectively connected to the gate of the eighth PMOS tube and the drain of the seventh NMOS tube; the drain of the eighth PMOS tube is connected to the source of the seventh NMOS tube and grounded; the source of the eighth PMOS tube is respectively connected to the drain of the sixth PMOS tube and the drain of the fifth NMOS tube; the source of the fifth NMOS tube is grounded; The gate of the fifth NMOS tube is respectively connected to the gate of the seventh NMOS tube and the gate of the sixth NMOS tube; the drain of the sixth NMOS tube is respectively connected to the gate of the sixth NMOS tube and the drain of the seventh PMOS tube; the source of the sixth NMOS tube is grounded.

3. The low ripple overcurrent protection circuit according to claim 1, characterized in that: The comparator circuit includes a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a fourth resistor, a fifth resistor, a first diode, a seventh NMOS tube and an eighth NMOS tube; The source of the ninth PMOS tube and the source of the twelfth PMOS tube are connected and connected to the power supply; the gate of the ninth PMOS tube and the gate of the twelfth PMOS tube are used to access the bias voltage output by the bias circuit; the drain of the ninth PMOS tube is respectively connected to the source of the tenth PMOS tube and the source of the eleventh PMOS tube; The gate of the tenth PMOS tube is connected to the bias voltage of the bias circuit; the drain of the tenth PMOS tube is connected to the drain of the seventh NMOS tube, the gate of the seventh NMOS tube is respectively connected to the drain of the seventh NMOS tube and the gate of the eighth NMOS tube, and the source of the seventh NMOS tube is grounded; The gate of the eleventh PMOS tube is respectively connected to the first end of the fourth resistor and the first end of the fifth resistor, and the second end of the fourth resistor is connected to the drain of the twelfth PMOS tube; the drain of the twelfth PMOS tube is also connected to the cathode of the first diode, and the anode of the first diode is grounded; The second end of the fifth resistor is grounded; the drain of the eleventh PMOS tube is connected to the drain of the eighth NMOS tube and serves as the output end of the comparator circuit; The source of the eighth NMOS tube is grounded.

4. The low ripple overcurrent protection circuit according to claim 1, characterized in that: The driver circuit includes a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a ninth NMOS tube, a tenth NMOS tube and an eleventh NMOS tube; The source of the thirteenth PMOS tube is connected to the power supply, and the drain of the thirteenth PMOS tube is respectively connected to the source of the fourteenth PMOS tube, the source of the fifteenth PMOS tube and the source of the sixteenth PMOS tube; the gate of the thirteenth PMOS tube is connected to the gate of the fourteenth PMOS tube, and the drain of the fourteenth PMOS tube is respectively connected to the gate of the fifteenth PMOS tube, the drain of the ninth NMOS tube and the gate of the tenth NMOS tube; the gate of the ninth NMOS tube serves as the input end of the driver circuit, and the source of the ninth NMOS tube is connected to the source of the tenth NMOS tube and the source of the eleventh NMOS tube and is grounded; The drain of the fifteenth PMOS tube is respectively connected to the drain of the tenth NMOS tube, the gate of the sixteenth PMOS tube and the gate of the eleventh NMOS tube; the drain of the sixteenth PMOS tube is connected to the drain of the eleventh NMOS tube and serves as the output end of the driver circuit.

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