Amplifier

Abstract

A receiver front end (300) having a low noise amplifier (LNA) and an amplifier are disclosed herein. A cascode having an input FET configured with a "common source" and an output FET configured with a "common gate" can be turned on or off using the gate of the output FET. A first switch (235) is provided that allows a connection to be made or broken between the source terminals of the input FETs of each LNA. A drain switch (260) is provided between the drain terminals of the input FETs to place the input FETs in parallel. This increases the g of the input stage of the amplifier. m , thereby improving the noise figure of the amplifier.

Description

[0001] This application is a divisional application of Chinese patent application No. 201980011004.0, filed on July 30, 2020, entitled “Drain Shared Split LNA.” The corresponding PCT international application had an international filing date of January 28, 2019, and international application number PCT / US2019 / 015477.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to U.S. Patent Application No. 15 / 887,816, filed on February 2, 2018, entitled “Drain Shared Split LNA,” the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] Various embodiments described herein relate to amplifiers, and more particularly, to low noise amplifiers and drain-shared split LNAs for use in communication devices. Background Art

[0005] The front end of a communications receiver typically includes a low-noise amplifier (LNA), which provides the first stage of amplification for the signals received within the receiver. The LNA's operating specifications are crucial to the overall quality of the receiver. Any noise or distortion introduced by the LNA degrades overall receiver performance. Therefore, receiver sensitivity is largely determined by the quality of the front end, particularly the LNA.

[0006] In some cases, an LNA is required to operate over a relatively wide frequency band and amplify signals having several different modulated baseband or modulated intermediate frequency (IF) signals. An example of a situation where an LNA is required to amplify a received signal having multiple modulated IF or baseband signals is when receiving an intra-band non-contiguous carrier aggregate (CA) signal. A CA signal may have two channels (or IF carriers) having frequencies that are non-adjacent to each other but within a frequency range that can be processed by a single LNA amplifier. For example, a CA signal may have two non-adjacent channels within a cellular frequency band defined by the Third Generation Partnership Project (3GPP). 3GPP is a well-known industry standards-setting organization.

[0007] Where a receiver is required to receive a CA signal, such as a cellular telephone compliant with Release 11 of the 3GPP communications industry standard, an LNA typically amplifies the received signal and provides the amplified output signal to a passive splitter. Figure 1FIG1 is a diagram of a portion of a cellular telephone front end in which an LNA 101 is coupled to a variable attenuator 103. A bypass switch 105 allows the variable attenuator to be selectively shunted. The signal is then coupled to a single-pole, triple-throw selector switch 107, which allows the output of the LNA 101 to be selectively coupled to only a first downconverter and baseband circuitry (DBC) 109, a second DBC 111, or both the first and second DBCs 109, 111.

[0008] When mode selector switch 107 is in a first position (i.e., single-channel mode 1), the output of LNA 101 is directly coupled to first DBC 109. In a second position (i.e., split mode), the output of LNA 101 is coupled to first DBC 109 and second DBC 111 through passive power splitter 113. In a third position (i.e., single-channel mode 2), the output of LNA 101 is coupled only to second DBC 111.

[0009] Existence by Figure 1 The architecture shown imposes several limitations. The first limitation is the amount of isolation that can be achieved between the first DBC 109 and the second DBC 111. Typically, a well-made 3dB splitter can achieve approximately 18 to 20dB of isolation between the outputs at the center frequency at which the splitter 113 is designed to operate. Signals cross-coupling from one DBC to the other will typically result in interference and distortion, which will lead to an overall reduction in the sensitivity of the receiver.

[0010] Furthermore, passive splitters are typically designed to operate optimally within a relatively narrow frequency range. That is, passive splitters are inherently narrowband devices. When the frequency of the signal coupled through splitter 113 deviates from the splitter's optimal design frequency, output-to-output isolation degrades. Due to the limitations of currently available splitters, and because receivers designed to process CA signals must operate within a relatively wide frequency range, achieving the desired isolation between DBCs 109 and 111 is difficult.

[0011] In addition, power splitters such as Figure 1The splitter 113 shown in FIG has significant loss. Since a 3dB power splitter splits the power in half, even an ideal splitter will result in a 3dB reduction in the power provided to DBCs 109 and 111 in split mode compared to single-channel mode. In addition, most splitters will have an additional insertion loss of 1.0 to 1.5dB. Insertion loss, such as output-to-output isolation, will generally worsen as the frequency of the applied signal deviates from the center frequency for which the splitter is designed to operate.

[0012] Furthermore, more gain is required due to the losses encountered in the mode select switch 107 and splitter 113. This results in reduced linearity (as typically characterized by measuring the "third order intercept") and a degradation of the receiver's noise figure when operating in splitter mode.

[0013] Therefore, there is a need for a CA-capable receiver front-end that can operate in split mode with high output-to-output isolation without degrading the third-order intercept and noise figure, and with relatively low front-end loss. Summary of the Invention

[0014] One aspect of an embodiment of the present disclosure provides an amplifier including: (a) a plurality of low-noise amplifiers (LNAs), each of the LNAs including an input transistor and an output transistor; (b) at least two control input terminals, each of the control input terminals coupled to an output transistor of a corresponding one of the LNAs; and (c) at least one drain switch having a first terminal and a second terminal, the first terminal being directly connected to a source of a first of the output transistors and a drain of a first of the input transistors, and the second terminal being directly connected to a source of a second of the output transistors and a drain of a second of the input transistors, the at least one drain switch directly connecting the drain terminals of the first and second input transistors of at least two of the LNAs in a first operating mode and disconnecting the drain terminals in a second operating mode.

[0015] Yet another aspect of embodiments of the present disclosure provides an amplifier comprising: (a) a first low-noise amplifier (LNA) and a second LNA, each LNA including an input transistor and an output transistor, the input transistor having a control input, a source, and a drain, the control input being configured to couple to an applied input signal, the output transistor having a source coupled in series to the drain of the input transistor at a common connection point and a drain that provides an amplified version of the applied input signal when the output transistor is turned on; and (b) a drain switch that connects the common connection point of the first and second LNAs in a single operation mode and disconnects the common connection point of the first and second LNAs in a split operation mode, wherein in the single operation mode, one of the output transistors is off and the other of the output transistors is on, and in the split operation mode, both of the output transistors are on.

[0016] Yet another aspect of embodiments of the present disclosure provides an amplifier comprising: (a) a first low-noise amplifier (LNA) including an input transistor having a drain coupled in series to a source of an output transistor at a common connection point; (b) a second LNA including an input transistor having a drain coupled in series to a source of an output transistor at a common connection point; and (c) a drain switch connecting the common connection point of the first and second LNAs during a single operation mode such that a current through the conductive output transistors is a sum of currents through the input transistors, and disconnecting the common connection point of the first and second LNAs during a split operation mode, wherein in the single operation mode, one of the output transistors is off and the other of the output transistors is on, and in the split operation mode, both of the output transistors are on.

[0017] Yet another aspect of embodiments of the present disclosure provides an amplifier comprising: (a) a plurality of low-noise amplifiers (LNAs), each LNA including an input transistor and an output transistor, the input transistor having a drain coupled in series to a source of the output transistor at a common connection point, wherein the input transistor is configured to couple to an applied input signal and the output transistor is configured to provide an amplified version of the applied input signal when the output transistor is turned on; and (b) at least one drain switch that, in a single operation mode, connects the common connection point of at least two of the plurality of LNAs such that a current through one of the output transistors is a sum of currents through the input transistors, and disconnects the common connection point in a split operation mode, wherein in the single operation mode, all but one of the output transistors of the plurality of LNAs are off, and in the split operation mode, the output transistors of at least two of the plurality of LNAs are turned on.

[0018] Yet another aspect of embodiments of the present disclosure provides an amplifier comprising: (a) a first low-noise amplifier (LNA) and a second LNA, each LNA including an input transistor and an output transistor, the input transistor having a control input, a source, and a drain, the control input being configured to couple to an applied input signal, the output transistor having a source coupled in series to the drain of the input transistor at a common connection point and a drain that provides an amplified version of the applied input signal when the output transistor is turned on; (b) a drain switch that connects the common connection point of the first and second LNAs in a single operation mode and disconnects the common connection point of the first and second LNAs in a split operation mode, wherein in the single operation mode, only one of the output transistors is turned on, and in the split operation mode, both of the output transistors are turned on; and (c) a source switch that connects the sources of the first and second LNAs in the single operation mode and disconnects the sources of the first and second LNAs in the split operation mode.

[0019] Yet another aspect of an embodiment of the present disclosure provides an amplifier including: (a) a first low-noise amplifier (LNA) including an input transistor having a drain coupled in series to a source of an output transistor at a common connection point; (b) a second LNA including an input transistor having a drain coupled in series to a source of an output transistor at a common connection point; and (c) a drain switch connecting the common connection point of the first and second LNAs during a single operation mode and disconnecting the common connection point of the first and second LNAs during a split operation mode, wherein in the single operation mode, one of the output transistors is off and the other of the output transistors is on, and in the split operation mode, both of the output transistors are on; and (d) a source switch connecting the sources of the first and second LNAs in the single operation mode and disconnecting the sources of the first and second LNAs in the split operation mode.

[0020] Yet another aspect of embodiments of the present disclosure provides an amplifier comprising: (a) a plurality of low noise amplifiers (LNAs), each of the LNAs comprising an input transistor and an output transistor, the input transistor having a drain coupled in series to a source of the output transistor at a common connection point, wherein the input transistor is configured to couple to an applied input signal and the output transistor is configured to provide an amplified version of the applied input signal when the output transistor is turned on; and (b) at least one drain switch, the at least one drain switch connecting the common connection point of at least two of the plurality of LNAs in a single operating mode so that the output transistor is electrically connected to the source of the output transistor. a current through one of the output transistors being the sum of the currents through the input transistors and disconnecting the common connection point in a split operation mode, wherein in the single operation mode, all but one of the output transistors of the plurality of LNAs are off, and in the split operation mode, the output transistors of at least two of the plurality of LNAs are on; and (c) at least one source switch that connects sources of at least two of the plurality of LNAs in the single operation mode and disconnects sources of at least two of the plurality of LNAs in the split operation mode.

[0021] Disclosed herein is a receiver front end capable of receiving and processing in-band non-contiguous carrier aggregation (CA) signals using multiple low noise amplifiers (LNAs). According to some embodiments of the disclosed method and apparatus, each of the multiple amplifiers is an LNA configured as a cascode (i.e., a two-stage amplifier having two transistors, a first transistor configured as a "common source" input transistor such as an input field effect transistor (FET), and a second transistor configured as an output transistor (e.g., an output FET) in a "common gate" configuration. In other embodiments, the LNA may have additional transistors (i.e., more than two stages and / or stacked transistors). The output transistor of each LNA can be turned on or off (i.e., by using the gate of the output FET or opening a switch 254, 252 in the source of the input FET). The gates of the input FETs are coupled together to form a common input. However, in some embodiments, the gates of the two FETs can be separated to allow independent control of which output transistor is turned off (i.e., the FET is not conducting current from the drain terminal to the source terminal). The amplifier is configured to connect the gate of an input FET of an LNA (with an output FET turned off) to the source terminal of the input FET of the LNA. A first switch is provided that allows a connection to be established or broken between the source terminals of the input FETs of each LNA. Furthermore, a second switch enables a switchable gate-to-source and / or gate-to-ground capacitor to be selectively applied to the input FETs of at least one of the LNAs. In some embodiments, an additional switch is provided that enables a source-to-ground degeneration inductor to be disconnected from the source terminal of the input FET of the LNA whose output FET is turned off. Selectively turning the output FET on and off enables the amplifier to operate in both single mode and split mode. Furthermore, the use of the switch ensures that the input impedance to the amplifier is the same in both single mode and split mode. Furthermore, a drain switch is provided that couples the drain terminals of each input FET together during single mode. In split mode, the switch is opened to decouple the drain terminals.

[0022] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a diagram of a portion of a cellular telephone front end in which an LNA is coupled to a variable attenuator, which is prior art.

[0024] Figure 2 is a diagram of a front-end amplifier having a degenerate switch, a gate capacitor module, and using multiple LNAs operating in a single mode or a split mode.

[0025] Figure 3is a simplified schematic diagram of another embodiment of an amplifier having a source-split LNA and a drain switch and including a resistor that can be selectively placed in parallel across the inductor and capacitor in each output load matching circuit.

[0026] Figure 4 is a graph showing the improvement in noise figure achieved by using drain switches.

[0027] Figure 5 The noise figure and current I according to the input frequency are shown DD Graphs and tables showing the relationships between them.

[0028] Figure 6 A method according to one embodiment for amplifying a signal (eg, a CA signal) using more than one amplifier is shown.

[0029] Figure 7 is an illustration of another embodiment of a method including removing a parallel drain resistor during single mode.

[0030] Like reference numbers and designations in the various drawings represent like elements. DETAILED DESCRIPTION

[0031] Figure 2FIG2 is a diagram of a front-end amplifier 200 for a communications receiver, in which multiple low-noise amplifiers (LNAs) 202 and 204 are used to amplify signals. The signal to be amplified is coupled through a front-end signal input terminal 206. In a first mode, referred to as "single mode," one of the output FETs 208 and 212 associated with the LNA 202 and 204 is turned on (i.e., actively amplifying the signal applied to the input of the LNA 202 and 204). The amplified output of the active LNA 202 and 204 is coupled to output terminals 232 and 234. The output FET 208 and 212 of the other LNA 204 and 202 is turned off (i.e., current is not allowed to flow from the drain to the source). In one embodiment of the disclosed method and apparatus, each LNA 202 and 204 includes a pair of field-effect transistors (FETs) 208 and 210, and 212 and 214. Each pair forms a two-stage LNA in a cascode architecture. However, those skilled in the art will appreciate that other types of transistors may be used, including but not limited to bipolar junction transistors. Furthermore, any type of FET may be used to implement an LNA, including but not limited to metal oxide semiconductors (MOSFETs), junction field effect transistors (JFETs), insulated gate FETs (IGFETs), metal semiconductor FETs (MESFETs), and the like. While some types of transistors may be better suited for specific applications, the concepts associated with the disclosed methods and apparatus do not preclude the use of any particular type of transistor. Furthermore, additional transistors may be included within an LNA (e.g., LNAs 202, 204), either as additional amplifier stages or stacked with the FETs 208, 212 shown. Furthermore, in some embodiments, the particular type of transistor, as well as the number of such transistors, may vary from one LNA 202, 204 to another or within each LNA 202, 204.

[0032] LNA control signals applied to control input terminals 216, 218 coupled to the gates of the output transistors (e.g., FETs) of the LNAs implemented by FETs 208, 212 control whether the output FETs 208, 212 of each LNA 202, 204 are turned on or off (i.e., conduct a significant amount of current from the drain terminal to the source terminal). In one embodiment, the LNA control signals are generated by a control module, such as an LNA controller 217. The LNA controller 217 can generate the LNA control signals based on information about the type of signal to be received by the amplifier 200, the content carried by the signal, or based on a user command selecting one or more channels. The LNA controller 217 can be a general-purpose processor capable of receiving commands and processing them to generate control signals for the LNAs and associated switches disclosed throughout this disclosure. Alternatively, the LNA controller 217 is a dedicated processor specifically designed to generate control signals. Those skilled in the art will understand how to enable such a processor to receive commands to enter a first mode, such as a split mode, and determine the specific configuration of switch control signals and LNA control signals to be generated. In some cases, the LNA controller 217 may be as simple as a logic block with a lookup table.Alternatively, in some embodiments, the LNA controller 217 may also rely on additional information in determining the state of the switch control signal and the LNA control signal.

[0033] In single mode, the LNA control signal to one of the LNAs 202, 204 turns on the output FETs 208, 212 of that LNA 202, 204. The LNA control signal to the other LNA 204, 202 turns off the output FETs 212, 208 of that LNA 202, 204. In split mode, the output FETs 208, 212 of both LNAs 202, 204 are turned on. As will be appreciated by those skilled in the art, Figure 2 Additional LNAs not shown in FIG. 4 may similarly be coupled to expand the amplifier to select additional channels using additional modes of operation.

[0034] Output load matching circuits 220, 222 coupled to the output ports 224, 226 of each LNA 202, 204 provide a means by which the output impedance can be matched to the load. In one embodiment, an input matching circuit 228 is provided to match the input impedance of the amplifier to the source terminal. The input matching circuit 228 includes an input matching inductor 229 and an input DC blocking capacitor 233. In some embodiments, the output shunt capacitors 230, 231 provide relatively low capacitance to ground for signals within the frequency range of the input signal applied to the input of the LNA 202, 204, respectively. In some embodiments, a separate V DDSupply voltage source to increase isolation between LNAs 202, 204. In other embodiments, the same supply terminal can be used to provide V to two or more of the LNAs. DD .

[0035] Figure 2 The isolation achieved by front-end 200, shown in FIG, is enhanced by the fact that there is significant isolation between output port 232 of first LNA 202 and output port 234 of second LNA 204. In amplifier 200, the isolation between the outputs of the front-end improves for signals separated by intervening channels. That is, as the frequency separation increases, the level of gain-versus-frequency overlap between one narrowband tuned output and another narrowband tuned output decreases. This reduction enhances isolation between the outputs. In lower gain operating modes, output isolation is improved.

[0036] One issue that needs to be addressed when using two LNAs in this manner is that the input impedance of the front-end amplifier 200 will vary depending on the mode in which the receiver is operating. That is, the input impedance presented in single mode will be significantly different from the impedance presented in split mode due to the difference in the gate-to-source capacitance Cgs of the FET transistor when the LNA's output FET is on and when the LNA's output FET is off. The large difference in input impedance will result in a large input mismatch, which in turn has a significant adverse effect on almost every aspect of the amplifier 200. This effect can result in an increase in noise figure, a decrease in gain, and a degradation in linearity, such as measured by third-order intercept (IP3). The Cgs of the input FETs 210, 214 of each LNA 202, 204 from the conducting state to the non-conducting state are significantly different. gs The relatively large change in impedance results in large variations in both the real and imaginary components of the input impedance of amplifier 200 when operating in single mode versus split mode. A source switch 235 is provided that can be closed in single mode to couple the source of first input FET 210 to the source of second input FET 214 to reduce this effect. Closing switch 235 during single mode to connect the sources of both input FETs 210, 214 results in an input impedance in split mode (i.e., when both output FETs 208, 212 of LNAs 202, 204 are on) that is closer to the input impedance presented during single mode with switch 235 open. However, this still represents a significant impedance change compared to split mode. In split mode, source switch 235 is open. Opening source switch 235 during split mode improves noise isolation between output terminals 216, 218.

[0037] In addition to source switch 235, in some embodiments, front-end amplifier 200 includes at least one gate capacitance module 240 comprising a gate capacitor 242 and a gate switch 244 connected in series between first and second terminals of module 240. When second LNA 204 is off, gate switch 244 can be switched to insert gate capacitor 242 in parallel with the gate and source of input FET 210, thereby providing additional input capacitance. By adding the additional capacitance of gate capacitor 242, the input impedance during single mode more closely matches the input impedance during split mode. Thus, with both gate switch 244 and source switch 235 closed during single mode, the input impedance will very closely match the input impedance presented during split mode (during split mode, both switches 244 and 235 are open). In single mode, gate switch 244 and source switch 235 are closed. In split mode, gate switch 244 and source switch 235 are open.

[0038] In addition, the front-end amplifier 200 has at least a first degeneration switch 252 to disconnect a degeneration component, such as the first degeneration inductor 238, from the second LNA 204 during single-mode operation. In some embodiments, the second degeneration switch 254 is placed between the source of the first FET 210 and a second degeneration component, such as the second degeneration inductor 236, to allow the degeneration inductor 236 to be removed from the LNA 202. Thus, it is possible to select which inductor 236, 238 is removed during single-mode operation. It will be apparent to one skilled in the art that either of the two degeneration switches 252, 254 can be provided separately, or both switches 252, 254 can be provided together.

[0039] When source switch 235 is closed, degeneration inductors 236, 238 are disconnected. Thus, when source switch 235 is open during split mode, each LNA 202, 204 sees the inductance of only one degeneration inductor 236, 238, which is coupled to the respective source of the input FET 210, 214 associated with that LNA 202, 204. By opening one of the degeneration switches 252, 254 in single mode, an active LNA 202, 214 operating in single mode has an inductive load between the source and ground that is equal to the inductance of only one of the degeneration inductors 236, 238, thereby more closely matching the inductance presented during split mode. Providing the second degeneration switch 254 provides flexibility as to which inductance is presented at the source of the active input FET 210 , 214 regardless of which output FET 208 , 212 is turned on during the single mode.

[0040] In addition to switches 235, 244, 252, 254, a drain switch 260 is provided to enable the drain terminal of input FET 210 to be coupled to the drain terminal of input FET 214 during single-mode operation. In an amplifier operating in single-mode operation without drain switch 260, the input of one of input FETs 210, 214 is essentially unused. Closing drain switch 260 places the two input FETs 210, 214 in parallel. By placing the two input FETs 210, 214 in parallel, the unused input FETs 210, 214 are added to the g of the input stage of the front-end amplifier 200. m (i.e., transconductance). Transconductance is the change in drain current divided by a small change in gate-to-source voltage when the drain-to-source voltage is constant. In this case, the drain current is the sum of the currents through each input FET 210, 214 (i.e., the current through the conducting FETs 208, 212). The amplifier's g m The increase in the noise figure of the amplifier increases. The switching frequency is f T ≈g m (2πC gs ). Therefore, due to C gs The value of is basically unchanged, so the conversion frequency (f T )With g m increases with the increase of .

[0041] When a signal is sent to the output of LNA 1, the LNA 1 control signal applied to the input 216 of FET 208 provides a bias to allow FET 208 to conduct. The LNA 2 control signal applied to the input of FET 212 is at ground potential to prevent FET 212 from conducting. By closing drain switch 260, the drain terminal of input FET 214 conducts in parallel with input FET 210, causing some of the current flowing through FET 208 to be shunted away. As can be seen, since both input FETs 210, 214 are conducting (assuming R of drain switch 260 is 0. on is relatively low, and the two LNAs 202, 204 are essentially identical), so essentially twice the current will flow through FET 208. This doubles the total current consumption while maintaining the same current through both input FETs 210, 214, thereby making the effective input device f T However, the input FET 214 requires additional DC bias current to generate g m , and thus the amplifier 200 will consume more power with both input FETs 210, 214 turned on. The bias of the input FETs 210, 214 can be set to optimize f TThus, amplifier 200 is flexible in its operation, allowing the user to determine how to balance the tradeoff between power consumption and noise figure in a single mode.

[0042] Since drain switch 260 is open (ie, non-conductive) during split mode, drain switch 260 has minimal effect on the operation of amplifier 200 in split mode. Since LNAs 202, 204 operate in common mode, C off The capacitance of drain switch 260 when non-conducting has minimal impact on the forward signal. However, if drain switch 260 is too large, it can negatively impact the isolation of the outputs, LNA Output 1 and LNA Output 2, in split mode. Furthermore, a large drain switch 260 increases shunt capacitance to the substrate on which the components of amplifier 200 are fabricated. This increase in shunt capacitance can increase the noise contribution from the cascode amplifier. Because the added additional shunt capacitance is typically relatively small for silicon-on-insulator (SOI) integrated circuits, the use of SOI integrated circuit systems mitigates this effect to some extent.

[0043] In addition, the size of the drain switch 260 may have an impact on the noise figure. If the drain switch 260 is too small, the R on The DC voltage drop across the switch (i.e., across the resistance of the switch when it is closed) results in a voltage V across the input FET 214. DS This results in a lower efficiency of g m , which will have a negative impact on the noise figure. However, because R on is in g m It appears after the stage, so R on The contribution to the noise figure is not very significant.

[0044] Figure 3 FIG2 is a simplified schematic diagram of another embodiment of an amplifier 300 having source-split LNAs 202, 204 and drain switches 260. The amplifier 300 includes resistors that can be selectively placed in parallel across the inductor and capacitor in each output load matching circuit 220, 222. Within each output load matching circuit 220, 222, switches 302, 304 and drain resistors 306, 308 are connected between the drain terminal of one of the output ports 224, 226 and V DD In single mode, the output impedance of amplifier 300 decreases because input FETs 210, 214 are placed in parallel when drain switch 260 is closed. Opening switches 302, 304 increases the resistance by removing the parallel path through each drain resistor 306, 308.

[0045] Figure 4 is a graph showing the improvement in noise figure achieved by using the drain switch 260. The first curve 402 shows the difference between the voltage source V DD The current drawn at each level I DD The associated noise figure (NF). Figure 3 In the embodiment shown, the current I DD is: (1) the current I flowing through the first LNA 202 when the LNA1 control signal is set to turn on the output FET 208 of LNA1 DD1 and any leakage current I flowing through the second LNA 204 DD2 or (2) the current I flowing through the second LNA 204 when the LNA2 control signal is set to turn on the output FET 212 of LNA2 DD2 and any leakage current I flowing through the first LNA 202 DD1 The second curve 404 shows the single mode in which the drain switch is closed and the voltage source V DD The current drawn at each level I DD It can be seen that at point 406 on curve 402, at which the current I DD = 6mA - the noise figure with the drain switch open is about 1.55dB. In comparison, at point 408, the noise figure with the drain switch 260 closed is about 1.46dB. The improvement in noise figure increases with I DD The current I DD At 16 mA, the noise figure when drain switch 260 is open is shown at point 410 to be approximately 1.53 dB. In contrast, the noise figure when drain switch 260 is closed, shown at point 412, is approximately 1.23 dB. It should be noted that these curves are plotted based on amplifier 300 with nominal component values ​​and are only meant to give a relative scale of the amount of improvement that can be achieved. An amplifier including components with specific values ​​and characteristics may differ from these values.

[0046] Figure 5 The noise figure and current I according to the input frequency are shown DD . Four curves 502, 504, 506, 508 are plotted over a frequency range from 2 GHz to 3 GHz. The first curve 502 represents a current I equal to 9.1 mA when the drain switch is turned on over a frequency range from 2 GHz to 3 GHz. DD The second curve 504 shows the current I of 3.9 mA when the drain switch 260 is closed. DDThe third curve 506 shows the noise figure of the entire frequency range when the drain switch 260 is closed and the current I DD The fourth curve 508 shows the noise figure of the MOSFET over the entire frequency range when the drain switch 260 is closed and the current I DD The noise figure over the entire frequency range. It can be seen that with the drain switch 260 closed, only 7.5 mA of I is used, compared to 9.1 mA when the drain switch 260 is open. DD You can achieve nearly the same noise figure.

[0047] According to some embodiments of the disclosed methods and apparatus, switches 235, 244, 252, 254, 260, 302, 304 can be fabricated according to the techniques provided in U.S. Patent No. 6,804,502 (the "'502 patent"), which is incorporated herein by reference, and can be fabricated according to techniques disclosed in other related patents. Further improvements in the performance of one or more of switches 235, 244, 252, 254, 260, 302, 304 can be achieved by implementing the techniques provided in U.S. Patent No. 7,910,993 (the "'993 patent"), which is incorporated herein by reference, and can be achieved by implementing techniques disclosed in other related patents. The use of such high-performance switches reduces the nonlinearity of the switches and, therefore, reduces the adverse effects of such switches on the performance of the receiver. However, in many implementations, switches may be used that have performance characteristics (i.e., linearity, return loss, switching speed, ease of integration, etc.) that are not as good as the characteristics of switches fabricated according to the techniques disclosed in the '502 and '993 patents. Thus, each or some of the switches disclosed above may be implemented using any combination of one or more transistors, including FETs, bipolar junction transistors (BJTs), or any other semiconductor switches. Alternatively, the switches may be implemented using electromechanical or MEMs (microelectromechanical systems) technology.

[0048] Furthermore, it will be understood by those skilled in the art that each of the switches 235, 244, 252, 254, 260, 302, 304 can be controlled by a control signal generated by the LNA controller 217 or other such controller to select the state of each switch depending on the operating mode of the amplifier (i.e., whether in single mode or split mode). For simplicity, such control signals and inputs to the switches are not shown in the figures, but are well within the purview of those skilled in the art.

[0049] method

[0050] Figure 6is an illustration of a method according to one embodiment of amplifying a signal (e.g., a CA signal) using more than one amplifier. A signal is applied to the input of the amplifier [step 601]. In some embodiments, the signal includes first and second non-adjacent channels. A first channel and a second channel are considered non-adjacent if there is at least a narrow frequency range between the end of the frequency range defined for the first channel and the beginning of the frequency range defined for the second channel. Typically, at least a third channel is defined within the frequency range between the end of the first channel and the beginning of the second channel. The frequency range of the channels is typically defined by an industry standard, but in some cases can be defined by the 3dB frequency range of a filter typically used to receive signals transmitted on the channels.

[0051] The method also includes selecting between single mode or split mode [step 603]. In one embodiment, the selection between single mode and split mode is performed by turning on the output FET 208 in the first LNA 202 and turning off the second output FET 212 in the second LNA 204 to select the single mode [step 605]. In one such embodiment, by providing a FET coupled to the output FET such as Figures 2 to 5 The first output FET 208 is shown to be turned on by applying an LNA control signal to the first control input terminal 216 of the gate of the FET 208. The second output FET 212 is turned off by applying an LNA control signal to the second control input terminal 218. Similarly, the split mode is selected by applying an LNA control signal to the control terminals 216, 218 to turn on both output FETs 208, 212 [step 607].

[0052] The method also includes coupling the source of the input FET of the first LNA 202, such as FET 210, with the source of the input FET of the second LNA 204, such as FET 214, during single mode (step 609), and decoupling the two sources during split mode (step 611). In one such embodiment, source switch 235 is closed during single mode and opened during split mode. When source switch 235 is closed, it couples the two sources of input FETs 210 and 214. Additionally, drain switch 260 is closed during single mode (step 613) and opened during split mode (step 615).

[0053] Figure 7is an illustration of another embodiment of a method that includes removing parallel drain resistors 306, 308 during single mode (step 713). In one embodiment, the drain resistors are removed by opening switches 302, 304. Resistors 306, 308 are added during split mode by closing switches 302, 304 (step 715). One such embodiment further includes selecting the resistance value of the drain resistors such that the output impedance is substantially the same during single mode and split mode.

[0054] Regarding the implementation methods including the above embodiments, the following technical solutions are also disclosed:

[0055] Solution 1. An amplifier comprising:

[0056] a plurality of low noise amplifiers (LNAs), each of the low noise amplifiers comprising an input transistor and an output transistor;

[0057] at least two control input terminals, each coupled to an output transistor of a respective one of the LNAs; and

[0058] At least one drain switch connects drain terminals of input transistors of at least two of the LNAs during a first operating mode and disconnects the drain terminals during at least a second operating mode.

[0059] Option 2. The amplifier of Option 1 further comprises at least one source switch that connects source terminals of input transistors of at least two of the LNAs during a first operating mode and disconnects the source terminals during at least a second operating mode.

[0060] Option 3. The amplifier of Option 1, wherein a signal coupled to the control input terminal turns the corresponding output transistor on and off.

[0061] Option 4. The amplifier according to Option 1 further includes a gate capacitance module having a first terminal and a second terminal, the first terminal being coupled to the gate of an associated one of the input transistors, and the second terminal being coupled to the source of the associated input transistor.

[0062] Embodiment 5. The amplifier of embodiment 4 further comprises a control module having at least one switch control signal output, wherein each drain switch has a switch control signal input to which the corresponding switch control signal output is coupled.

[0063] Embodiment 6. The amplifier of embodiment 4, wherein each gate capacitance module comprises a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module.

[0064] Embodiment 7. The amplifier of embodiment 6, wherein the gate switch is open when the associated transistor is conductive, and the gate switch is closed when the associated transistor is non-conductive.

[0065] Embodiment 8. The amplifier of embodiment 1 further comprises at least one gate capacitance module, each gate capacitance module having a first terminal and a second terminal, the first terminal being coupled to the gate of an associated one of the input transistors, and the second terminal being coupled to ground.

[0066] Embodiment 9. The amplifier of embodiment 8, further comprising a control module having at least one switch control signal output, wherein each gate capacitance module has a switch control signal input to which the corresponding switch control signal output is coupled.

[0067] Embodiment 10. The amplifier of embodiment 8, wherein each gate capacitance module comprises a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module.

[0068] Embodiment 11. The amplifier of embodiment 10, wherein the gate switch is open when the associated input transistor is on, and the gate switch is closed when the associated input transistor is off.

[0069] Option 12. The amplifier according to Option 1, further comprising:

[0070] Degenerate components; and

[0071] A degenerative switch is coupled in series with the degenerative component, the series combination of the degenerative component and the degenerative switch being coupled between a source of one of the input transistors and circuit ground.

[0072] Embodiment 13. The amplifier according to embodiment 12, wherein the degenerate component is a degenerate inductor.

[0073] Embodiment 14. The amplifier of embodiment 12, wherein when the drain switch is closed, the degenerative switch is open, and when the drain switch is open, the degenerative switch is closed.

[0074] Embodiment 15. The amplifier according to embodiment 12 further includes at least a second degenerative component and a second degenerative switch, wherein the second degenerative component and the second degenerative switch are coupled in series between the source of the second input transistor and ground, and when the first degenerative switch is opened, the second degenerative switch is closed.

[0075] Embodiment 16. The amplifier of embodiment 12, further comprising a control module having a switch control signal output, wherein the degeneration switch has a switch control signal input to which the switch control signal output is coupled.

[0076] Option 17. The amplifier according to Option 4, further comprising:

[0077] Degenerate components; and

[0078] A degenerative switch is coupled in series with the degenerative component, the series combination of the degenerative component and the degenerative switch being coupled between a source of one of the input transistors and ground.

[0079] Embodiment 18. The amplifier of embodiment 17, wherein the degenerate component is an inductor.

[0080] Solution 19. The amplifier according to Solution 17,

[0081] Each gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module,

[0082] wherein when the drain switch is closed, the degenerative switch is open, and when the drain switch is open, the degenerative switch is closed, and

[0083] When the drain switch is closed, the gate switch is closed, and when the drain switch is open, the gate switch is open.

[0084] Embodiment 20. The amplifier of embodiment 17, further comprising at least a second degeneration inductor and a second degeneration switch,

[0085] Each gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module,

[0086] wherein when the drain switch is closed, the degenerative switch is open, and when the drain switch is open, the degenerative switch is closed,

[0087] wherein, when the drain switch is closed, the gate switch is closed, and when the drain switch is open, the gate switch is open, and

[0088] The second degeneration inductor and the second degeneration switch are coupled in series between the source of the second input transistor and the ground, and when the first degeneration switch is opened, the second degeneration switch is closed.

[0089] Option 21. The amplifier according to Option 17 further includes a control module having a switch control signal output, wherein the degeneration switch has a switch control signal input to which one of the switch control signal outputs is coupled, and each gate capacitance module has a switch control signal input to which one of the switch control signal outputs is coupled.

[0090] Embodiment 22. A method for amplifying a signal in more than one amplifier, comprising:

[0091] coupling a signal to be amplified to inputs of at least a first LNA and a second LNA, each LNA having an input transistor and an output transistor, each transistor having a first terminal, a second terminal, and a third terminal;

[0092] coupling a second terminal of an output transistor of the first LNA to a third terminal of an input transistor of the first LNA;

[0093] coupling a second terminal of the output transistor of the second LNA to a third terminal of the input transistor of the second LNA;

[0094] turning on output transistors of the first and second LNAs during a first mode;

[0095] during the first mode, opening a switch between a third terminal of the input transistor of the first LNA and a third terminal of the input transistor of the second LNA;

[0096] turning off one of the output transistors during a second mode; and

[0097] A switch between the third terminal of the first input transistor and the third terminal of the second input transistor is closed in the second mode.

[0098] Option 23. The method according to Option 22, further comprising:

[0099] opening a switch between the second terminal of the first transistor and the second terminal of the second transistor during the first mode; and

[0100] A switch between the second terminal of the first transistor and the second terminal of the second transistor is closed in the second mode.

[0101] Option 24. The method of option 22 further includes closing a gate switch to place a capacitor between a first terminal of the first transistor and a second terminal of the first transistor during the second mode when the LNA having the first transistor is turned off.

[0102] Option 25. The method of option 24 further includes opening the switch during the first mode to remove the capacitor from between the first terminal of the first transistor and the second terminal of the first transistor.

[0103] Embodiment 26. The method of embodiment 25, wherein the capacitance of the capacitor is selected so that the input impedance seen by the LNA is substantially the same during the first mode and during the second mode.

[0104] Option 27. The method according to Option 25, wherein the first transistor and the second transistor are field effect transistors, and the first terminal is a gate, the second terminal is a source, and the third terminal is a drain.

[0105] Option 28. The method of option 22 further includes closing a gate switch during the second mode to place a capacitor between the first terminal of the first transistor and ground if the LNA having the first transistor is turned off.

[0106] Embodiment 29. The method of embodiment 28 further comprises opening a switch during the first mode to disconnect a capacitor from between the first terminal of the first transistor and ground.

[0107] Embodiment 30. The method of embodiment 29, wherein the capacitance of the capacitor is selected so that the input impedance seen by the LNA is substantially the same during the first mode and during the second mode.

[0108] Option 31. A method according to Option 29, wherein the first transistor and the second transistor are field effect transistors, and the first terminal is a gate, the second terminal is a source, and the third terminal is a drain.

[0109] Option 32. The method according to Option 22 further includes opening a first degeneration switch to disconnect the second terminal of one of the first transistor and the second transistor from ground when changing from the first mode to the second mode.

[0110] Option 33. The method of Option 32 further includes closing a gate switch to place a capacitor between the first terminal of the first transistor and the second terminal of the first transistor during the second mode.

[0111] Embodiment 34. The method of embodiment 32 further includes, during the first mode, opening a switch to disconnect a capacitor from between the first terminal of the first transistor and the second terminal of the first transistor.

[0112] Embodiment 35. The method of embodiment 32 further comprising, during the second mode, closing a gate switch to place a capacitor between the first terminal and the ground.

[0113] Embodiment 36. The method of embodiment 32 further includes, during the first mode, opening a switch to disconnect a capacitor from between the first terminal of the first transistor and ground.

[0114] Manufacturing Techniques and Options

[0115] It should be apparent to those skilled in the art that various embodiments of the claimed invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, the selection of appropriate component values ​​is a matter of design choice, and the various embodiments of the claimed invention can be implemented in any suitable IC technology (including but not limited to MOSFET and IGFET structures) or in hybrid or discrete circuit form. Integrated circuit embodiments can be manufactured using any suitable substrate and process, including but not limited to standard bulk silicon, silicon on insulator (SOI), silicon on sapphire (SOS), GaN HEMT, GaAs pHEMT, and MESFET technologies. However, in some cases, the claimed inventive concepts may be particularly useful for SOI-based manufacturing processes (including SOS) and manufacturing processes with similar characteristics.

[0116] A number of embodiments of the claimed invention have been described. It will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be sequence-independent and therefore may be performed in an order different from that described. In addition, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, or parallel manner. It will be understood that the foregoing description is intended to illustrate and not to limit the scope of the claimed invention, which is defined by the scope of the appended claims, and that other embodiments are within the scope of the claims.

Claims

1. An amplifier, comprising: (a) a plurality of low noise amplifiers (LNAs), each of the LNAs comprising an input transistor and an output transistor; (b) at least two control input terminals, each of the control input terminals coupled to an output transistor of a respective one of the LNAs; as well as (c) at least one drain switch having a first terminal and a second terminal, the first terminal being directly connected to a source of a first output transistor of the output transistors and a drain of a first input transistor of the input transistors, and the second terminal being directly connected to a source of a second output transistor of the output transistors and a drain of a second input transistor of the input transistors, the at least one drain switch directly connecting drain terminals of the first input transistor and the second input transistor of at least two of the LNAs in a first operating mode and disconnecting the drain terminals in a second operating mode.

2. The amplifier of claim 1 , further comprising at least one source switch that connects source terminals of input transistors of at least two of the LNAs during a first operating mode and disconnects the source terminals during at least a second operating mode.

3. The amplifier according to claim 1, wherein A signal coupled to the control input terminal turns the corresponding output transistor on and off.

4. The amplifier of claim 1 , further comprising a gate capacitance module having a first terminal coupled to a gate of an associated one of the input transistors and a second terminal coupled to a source of the associated one of the input transistors.

5. The amplifier of claim 4, further comprising a control module having at least one switch control signal output, wherein: Each drain switch has a switch control signal input to which a corresponding switch control signal output is coupled.

6. The amplifier according to claim 4, wherein: Each gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module.

7. The amplifier according to claim 6, wherein The gate switch is open when the associated transistor is conducting, and is closed when the associated transistor is not conducting.

8. The amplifier of claim 1, further comprising at least one gate capacitance module, each gate capacitance module having a first terminal coupled to a gate of an associated one of the input transistors and a second terminal coupled to ground.

9. The amplifier of claim 8, further comprising a control module having at least one switch control signal output, wherein: Each gate capacitance module has a switch control signal input to which a corresponding switch control signal output is coupled.

10. The amplifier according to claim 8, wherein Each gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module.

11. The amplifier according to claim 10, wherein The gate switch is open when the associated input transistor is turned on, and the gate switch is closed when the associated input transistor is turned off.

12. The amplifier of claim 1, further comprising: (a) Degenerate parts; as well as (b) a degenerative switch coupled in series with the degenerative component, the series combination of the degenerative component and the degenerative switch coupled between a source of one of the input transistors and circuit ground.

13. The amplifier according to claim 12, wherein The degenerative component is a degenerative inductor.

14. The amplifier according to claim 12, wherein: When the drain switch is closed, the degenerative switch is open, and when the drain switch is open, the degenerative switch is closed.

15. The amplifier of claim 12, further comprising at least a second degenerative component and a second degenerative switch, the second degenerative component and the second degenerative switch being coupled in series between the source of the second input transistor and ground, and the second degenerative switch being closed when the first degenerative switch is open.

16. The amplifier of claim 12, further comprising a control module having a switch control signal output, wherein: The degenerative switch has a switch control signal input to which the switch control signal output is coupled.

17. The amplifier of claim 4, further comprising: (a) Degenerate parts; as well as (b) a degenerative switch coupled in series with the degenerative component, the series combination of the degenerative component and the degenerative switch coupled between a source of one of the input transistors and ground.

18. The amplifier of claim 17, wherein: The degenerate component is an inductor.

19. The amplifier according to claim 17, in, Each gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module, wherein when the drain switch is closed, the degenerative switch is opened, and when the drain switch is opened, the degenerative switch is closed, and Wherein, when the drain switch is closed, the gate switch is closed, and when the drain switch is opened, the gate switch is opened.

20. The amplifier of claim 17, further comprising at least a second degeneration inductor and a second degeneration switch, in, Each gate capacitance module includes a gate capacitor and a gate switch coupled in series between a first terminal and a second terminal of the gate capacitance module, wherein when the drain switch is closed, the degenerative switch is opened, and when the drain switch is opened, the degenerative switch is closed, wherein when the drain switch is closed, the gate switch is closed, and when the drain switch is opened, the gate switch is opened, and The second degeneration inductor and the second degeneration switch are coupled in series between the source of the second input transistor and the ground, and when the first degeneration switch is opened, the second degeneration switch is closed.

21. The amplifier of claim 17, further comprising a control module having a switch control signal output, wherein: The degeneration switch has a switch control signal input to which one of the switch control signal outputs is coupled, and each gate capacitance module has a switch control signal input to which one of the switch control signal outputs is coupled.

22. An amplifier, comprising: (a) a first low noise amplifier LNA and a second LNA, each LNA comprising an input transistor and an output transistor, the input transistor having a control input, a source and a drain, the control input being configured to be coupled to an applied input signal, and the output transistor having a source coupled in series to the drain of the input transistor at a common connection point and a drain providing an amplified version of the applied input signal when the output transistor is turned on; as well as (b) a drain switch that connects a common connection point of the first LNA and the second LNA in a single operation mode in which one of the output transistors is off and the other of the output transistors is on, and disconnects the common connection point of the first LNA and the second LNA in a split operation mode in which both of the output transistors are on.

23. The amplifier of claim 22, wherein: In the single operation mode, the current through the conductive output transistor is the sum of the currents through the input transistors of the first and second LNAs.

24. The amplifier of claim 22, further comprising a source switch that connects sources of the first LNA and the second LNA in the single operation mode and disconnects sources of the first LNA and the second LNA in the split operation mode.

25. The amplifier of claim 22, further comprising a switchable gate capacitance module coupled between the source of the input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode.

26. The amplifier of claim 25, wherein The capacitance of the switchable gate capacitance module is selected such that an input impedance of the first LNA is substantially the same in the single operation mode and the split operation mode.

27. The amplifier of claim 22, further comprising a first switchable degeneration component coupled to a source of an input transistor of the first LNA and a second switchable degeneration component coupled to a source of an input transistor of the second LNA, wherein: The first and second switchable degenerative components are configured to couple a degeneration inductance to respective sources of input transistors of the first and second LNAs in the split operation mode, and to disconnect the degeneration inductance of at least one of the first and second switchable degenerative components in the single operation mode.

28. The amplifier of claim 22, further comprising a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein: The first and second switchable load impedance components are configured to couple load impedances to respective drains of output transistors of the first and second LNAs in the split operation mode and disconnect the load impedances from respective drains of output transistors of the first and second LNAs in the single operation mode.

29. The amplifier of claim 22, further comprising: (a) a source switch that connects the sources of the first LNA and the second LNA in the single operation mode and disconnects the sources of the first LNA and the second LNA in the split operation mode; as well as (b) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode.

30. The amplifier of claim 22, further comprising: (a) a source switch that connects the sources of the first LNA and the second LNA in the single operation mode and disconnects the sources of the first LNA and the second LNA in the split operation mode; (b) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; as well as (c) a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein the first switchable load impedance component and the second switchable load impedance component are configured to couple a load impedance to the respective drains of the output transistors of the first LNA and the second LNA in the split operation mode and disconnect the load impedance from the respective drains of the output transistors of the first LNA and the second LNA in the single operation mode.

31. The amplifier of claim 22, further comprising: (a) a source switch that connects the sources of the first LNA and the second LNA in the single operation mode and disconnects the sources of the first LNA and the second LNA in the split operation mode; (b) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; as well as (c) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode.

32. The amplifier of claim 22, further comprising: (a) a source switch that connects the sources of the first LNA and the second LNA in the single operation mode and disconnects the sources of the first LNA and the second LNA in the split operation mode; (b) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; (c) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode; and (d) a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein the first switchable load impedance component and the second switchable load impedance component are configured to couple a load impedance to the respective drains of the output transistors of the first LNA and the second LNA in the split operation mode and disconnect the load impedance from the respective drains of the output transistors of the first LNA and the second LNA in the single operation mode.

33. The amplifier of claim 22, further comprising: (a) a source switch that connects the sources of the first LNA and the second LNA in the single operation mode and disconnects the sources of the first LNA and the second LNA in the split operation mode; (b) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode; and (c) a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein the first switchable load impedance component and the second switchable load impedance component are configured to couple a load impedance to the respective drains of the output transistors of the first LNA and the second LNA in the split operation mode and disconnect the load impedance from the respective drains of the output transistors of the first LNA and the second LNA in the single operation mode.

34. The amplifier of claim 22, further comprising: (a) a source switch that connects the sources of the first LNA and the second LNA in the single operation mode and disconnects the sources of the first LNA and the second LNA in the split operation mode; as well as (b) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode.

35. The amplifier of claim 22, further comprising: (a) a source switch that connects the sources of the first LNA and the second LNA in the single operation mode and disconnects the sources of the first LNA and the second LNA in the split operation mode; as well as (b) a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein the first switchable load impedance component and the second switchable load impedance component are configured to couple a load impedance to the respective drains of the output transistors of the first LNA and the second LNA in the split operation mode and disconnect the load impedance from the respective drains of the output transistors of the first LNA and the second LNA in the single operation mode.

36. The amplifier of claim 22, further comprising: (a) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; (b) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode; and (c) a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein the first switchable load impedance component and the second switchable load impedance component are configured to couple a load impedance to the respective drains of the output transistors of the first LNA and the second LNA in the split operation mode and disconnect the load impedance from the respective drains of the output transistors of the first LNA and the second LNA in the single operation mode.

37. The amplifier of claim 22, further comprising: (a) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; as well as (b) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode.

38. The amplifier of claim 22, further comprising: (a) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; as well as (b) a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein the first switchable load impedance component and the second switchable load impedance component are configured to couple a load impedance to the respective drains of the output transistors of the first LNA and the second LNA in the split operation mode and disconnect the load impedance from the respective drains of the output transistors of the first LNA and the second LNA in the single operation mode.

39. The amplifier of claim 22, further comprising: (a) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degenerative inductance to the respective sources of the input transistors of the first and second LNAs in the split operation mode and to disconnect the degenerative inductance of at least one of the first and second switchable degenerative components in the single operation mode; and (b) a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein the first switchable load impedance component and the second switchable load impedance component are configured to couple a load impedance to the respective drains of the output transistors of the first LNA and the second LNA in the split operation mode and disconnect the load impedance from the respective drains of the output transistors of the first LNA and the second LNA in the single operation mode.

40. An amplifier, comprising: (a) a first low noise amplifier LNA comprising an input transistor having a drain coupled in series to a source of an output transistor at a common connection point; (b) a second LNA comprising an input transistor having a drain coupled in series to a source of an output transistor at a common connection point; as well as (c) a drain switch that connects a common connection point of the first LNA and the second LNA during a single operation mode in which one of the output transistors is off and the other of the output transistors is on, so that a current through the output transistors that are turned on is the sum of currents through the input transistors, and disconnects the common connection point of the first LNA and the second LNA during a split operation mode in which one of the output transistors is off and the other of the output transistors is on, and in which both of the output transistors are on.

41. An amplifier, comprising: (a) a plurality of low noise amplifiers (LNAs), each of the LNAs comprising an input transistor and an output transistor, the input transistor having a drain coupled in series to a source of the output transistor at a common connection point, wherein the input transistor is configured to couple to an applied input signal and the output transistor is configured to provide an amplified version of the applied input signal when the output transistor is turned on; (b) at least one drain switch that connects a common connection point of at least two of the plurality of LNAs in a single operation mode so that a current through one of the output transistors is the sum of currents through the input transistors, and disconnects the common connection point in a split operation mode, wherein in the single operation mode, all output transistors of the plurality of LNAs except one output transistor are off, and in the split operation mode, the output transistors of at least two of the plurality of LNAs are on.

42. An amplifier, comprising: (a) a first low noise amplifier LNA and a second LNA, each LNA comprising an input transistor and an output transistor, the input transistor having a control input, a source and a drain, the control input being configured to be coupled to an applied input signal, and the output transistor having a source coupled in series to the drain of the input transistor at a common connection point and a drain providing an amplified version of the applied input signal when the output transistor is turned on; (b) a drain switch that connects a common connection point of the first LNA and the second LNA in a single operation mode in which only one of the output transistors is conductive, and disconnects the common connection point of the first LNA and the second LNA in a split operation mode in which both of the output transistors are conductive; as well as (c) a source switch that connects the sources of the first LNA and the second LNA in the single operation mode and disconnects the sources of the first LNA and the second LNA in the split operation mode.

43. An amplifier according to claim 42, wherein In the single operation mode, the current through the conductive output transistor is the sum of the currents through the input transistors of the first and second LNAs.

44. The amplifier of claim 42, further comprising a switchable gate capacitance module coupled between the source of the input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and to disconnect the capacitance in the split operation mode.

45. An amplifier according to claim 44, wherein The capacitance of the switchable gate capacitance module is selected such that an input impedance of the first LNA is substantially the same in the single operation mode and the split operation mode.

46. ​​The amplifier of claim 44, wherein The switchable gate capacitance module includes a capacitor coupled in series with a switch.

47. The amplifier of claim 42, further comprising a first switchable degenerate component coupled to a source of an input transistor of the first LNA and a second switchable degenerate component coupled to a source of an input transistor of the second LNA, wherein: The first and second switchable degenerative components are configured to couple a degeneration inductance to respective sources of input transistors of the first and second LNAs in the split operation mode, and to disconnect the degeneration inductance of at least one of the first and second switchable degenerative components in the single operation mode.

48. An amplifier according to claim 47, wherein The first switchable degenerative component and the second switchable degenerative component each include an inductor coupled in series with a switch.

49. The amplifier of claim 42, further comprising a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein: The first and second switchable load impedance components are configured to couple load impedances to respective drains of output transistors of the first and second LNAs in the split operation mode and disconnect the load impedances from respective drains of output transistors of the first and second LNAs in the single operation mode.

50. The amplifier of claim 49, wherein The first switchable load impedance component and the second switchable load impedance component each include an inductor coupled in parallel with a capacitor, and a resistor selectively coupled in parallel with the inductor and the capacitor.

51. The amplifier of claim 42, further comprising: (a) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; (b) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode; and (c) a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein the first switchable load impedance component and the second switchable load impedance component are configured to couple a load impedance to the respective drains of the output transistors of the first LNA and the second LNA in the split operation mode and disconnect the load impedance from the respective drains of the output transistors of the first LNA and the second LNA in the single operation mode.

52. The amplifier of claim 42, further comprising: (a) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; as well as (b) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degeneration inductance to the respective sources of the input transistors of the first LNA and the second LNA in the split operation mode and to disconnect the degeneration inductance of at least one of the first switchable degenerative component and the second switchable degenerative component in the single operation mode.

53. The amplifier of claim 42, further comprising: (a) a switchable gate capacitance module coupled between a source of an input transistor of the first LNA and a control input and configured to couple a capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and disconnect the capacitance in the split operation mode; as well as (b) a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein the first switchable load impedance component and the second switchable load impedance component are configured to couple a load impedance to the respective drains of the output transistors of the first LNA and the second LNA in the split operation mode and disconnect the load impedance from the respective drains of the output transistors of the first LNA and the second LNA in the single operation mode.

54. The amplifier of claim 42, further comprising: (a) a first switchable degenerative component coupled to a source of an input transistor of the first LNA and a second switchable degenerative component coupled to a source of an input transistor of the second LNA, wherein the first switchable degenerative component and the second switchable degenerative component are configured to couple a degenerative inductance to the respective sources of the input transistors of the first and second LNAs in the split operation mode and to disconnect the degenerative inductance of at least one of the first and second switchable degenerative components in the single operation mode; and (b) a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein the first switchable load impedance component and the second switchable load impedance component are configured to couple a load impedance to the respective drains of the output transistors of the first LNA and the second LNA in the split operation mode and disconnect the load impedance from the respective drains of the output transistors of the first LNA and the second LNA in the single operation mode.

55. An amplifier, comprising: (a) a first low noise amplifier LNA comprising an input transistor having a drain coupled in series to a source of an output transistor at a common connection point; (b) a second LNA comprising an input transistor having a drain coupled in series to a source of an output transistor at a common connection point; as well as (c) a drain switch that connects a common connection point of the first LNA and the second LNA during a single operation mode in which one of the output transistors is off and the other of the output transistors is on, and disconnects the common connection point of the first LNA and the second LNA during a split operation mode in which both of the output transistors are on; (d) a source switch that connects the sources of the first LNA and the second LNA in the single operation mode and disconnects the sources of the first LNA and the second LNA in the split operation mode.

56. The amplifier of claim 55, wherein In the single operation mode, the current through the conductive output transistor is the sum of the currents through the input transistors of the first and second LNAs.

57. The amplifier of claim 55, further comprising a switchable gate capacitance module coupled between the source of the input transistor of the first LNA and a control input and configured to couple capacitance between the source of the input transistor of the first LNA and the control input in the single operation mode and to disconnect capacitance in the split operation mode.

58. The amplifier of claim 57, wherein The capacitance of the switchable gate capacitance module is selected such that an input impedance of the first LNA is substantially the same in the single operation mode and in the split operation mode.

59. The amplifier of claim 55, further comprising a first switchable degeneration component coupled to a source of an input transistor of the first LNA and a second switchable degeneration component coupled to a source of an input transistor of the second LNA, wherein: The first and second switchable degenerative components are configured to couple a degeneration inductance to respective sources of input transistors of the first and second LNAs in the split operation mode, and to disconnect the degeneration inductance of at least one of the first and second switchable degenerative components in the single operation mode.

60. The amplifier of claim 55, further comprising a first switchable load impedance component coupled to a drain of an output transistor of the first LNA and a second switchable load impedance component coupled to a drain of an output transistor of the second LNA, wherein: The first and second switchable load impedance components are configured to couple load impedances to respective drains of output transistors of the first and second LNAs in the split operation mode and disconnect the load impedances from respective drains of output transistors of the first and second LNAs in the single operation mode.

61. An amplifier, comprising: (a) a plurality of low noise amplifiers (LNAs), each of the LNAs comprising an input transistor and an output transistor, the input transistor having a drain coupled in series to a source of the output transistor at a common connection point, wherein the input transistor is configured to couple to an applied input signal and the output transistor is configured to provide an amplified version of the applied input signal when the output transistor is turned on; (b) at least one drain switch that connects a common connection point of at least two of the plurality of LNAs in a single operation mode so that a current through one of the output transistors is a sum of currents through the input transistors, and disconnects the common connection point in a split operation mode, wherein in the single operation mode, all but one of the output transistors of the plurality of LNAs are off, and in the split operation mode, the output transistors of at least two of the plurality of LNAs are on; and (c) at least one source switch that connects sources of at least two of the plurality of LNAs in the single operation mode and disconnects sources of at least two of the plurality of LNAs in the split operation mode.

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