Multi-event time-to-digital converter capable of expanding measuring range

Abstract

The invention relates to a multi-event time-to-digital converter capable of expanding a measuring range, and the converter comprises a T trigger array which is used for coding an end signal according to the time sequence of a collection event, so as to enable the end signal to generate an edge change signal; the TDC delay chain is used for generating a time stamp of the edge change signal in each delay unit according to the edge change signal; the exclusive-OR gate module is used for carrying out logical judgment according to the time stamp of the edge change signal so as to determine the event distribution of the collected events; the D trigger array is used for latching the event distribution of the collected events in each coarse counting clock period and storing the event distribution into the corresponding storage unit; and the histogram statistics module is used for distributing a time difference between an end signal and a start signal of the acquisition event to each time interval range so as to generate a statistical histogram of event distribution of the acquisition events of the M coarse counting clock periods. According to the invention, the range of the multi-event time-to-digital converter can be greatly improved, and high time measurement precision can be maintained.

Description

Technical Field

[0001] The present application relates to the field of signal acquisition circuits, and in particular to a multi-event time-to-digital converter with an expandable measurement range. Background Art

[0002] Time-to-Digital Converter (TDC) is an electronic device used to measure the time interval between two signals and convert it into a digital output. It has a wide range of applications in photon flight time measurement, medical imaging, particle detection, and industrial automation control. Time-to-digital converters are often combined with single-photon detectors for time-correlated single photon counting (TCSPC) measurements. According to the number of events received by the TDC end (STOP) in the same signal cycle during TCSPC measurement, it can be divided into two categories: single-event time-to-digital converters and multi-event time-to-digital converters. A single-event time-to-digital converter only measures the arrival time of the first event encountered at the STOP end after the start (START) signal, while ignoring all events that arrive after the first event. This acquisition method will cause the time domain distribution of the measured signal under high photon flux to deviate seriously from the real signal (often called pile-up effect distortion), and its event sampling rate is limited to one event per signal cycle. The multi-event time-to-digital converter can measure the time interval (i.e., arrival time) of multiple events arriving at the STOP end within the same signal cycle relative to the START signal, which can effectively overcome the limitations of the single-event time-to-digital converter.

[0003] The implementation of a multi-event time-to-digital converter requires more hardware resources than a single-event time-to-digital converter, which limits the design of the available range (i.e., the range of measurable time intervals) of the multi-event time-to-digital converter to a certain extent. At present, the maximum range of high-sampling-rate multi-event time-to-digital converters is mostly limited to less than 100ns, which cannot meet many applications with wide range requirements, such as medium- and long-range laser radars, and analysis of long-life fluorescent species. In order to expand the scope of application of multi-event time-to-digital converters, their range needs to be further increased.

[0004] Existing multi-event time-to-digital converters mainly have two structures: flash delay chain and circular delay chain. Expanding the range of flash delay chain multi-event time-to-digital converters can be achieved by increasing the number of delay chain stages, but this method consumes a large amount of on-chip resources (such as CARRY4 resources in FPGA or inverter resources in ASIC), and it is difficult to significantly increase its range when hardware resources are limited. In addition, a delay chain that is too long will cause the performance at the end of the delay chain to degrade due to the continuous accumulation of integral nonlinearity. Increasing the range of circular delay chain multi-event time-to-digital converters can be achieved by increasing the number of times the delay chain is recycled, but since this type of multi-event time-to-digital converter requires a certain amount of time to read out each event (i.e., readout dead time), it seriously restricts the further improvement of the sampling rate of this type of multi-event time-to-digital converter.

[0005] The traditional histogram statistical function is often implemented in a time addressing manner, that is, a storage array is pre-set, and a storage unit address represents a time value. When the TDC measures a time information, the time information is used as the storage unit address to store the detection result. This method is used for a multi-event time-to-digital converter, which requires multiple addressing and storage operations for multiple time information, which will increase the dead time of the multi-event time-to-digital converter, thereby limiting the event sampling rate of the multi-event time-to-digital converter.

[0006] To sum up, the multi-event time-to-digital converter in the prior art has a short range, and the traditional histogram statistical function is often implemented using a time addressing method. This method is used for the multi-event time-to-digital converter, and it requires multiple addressing and storage operations for multiple time information respectively, which will increase the dead time of the multi-event time-to-digital converter, thereby limiting the event sampling rate of the multi-event time-to-digital converter. In order to solve this problem, the applicant has made corresponding explorations. Summary of the invention

[0007] The purpose of the present application is to solve the above-mentioned problem and provide a multi-event time-to-digital converter with an expandable range.

[0008] In order to meet the various objectives of this application, this application adopts the following technical solutions:

[0009] A multi-event time-to-digital converter with an extendable range is proposed to meet one of the purposes of the present application, comprising:

[0010] A synchronization signal generation module, which is used to generate a start signal and a synchronization signal, wherein the start signal is used to trigger the TDC delay chain to generate a coarse counting clock signal, and the synchronization signal is used to trigger an external application to generate end signals corresponding to multiple acquisition events;

[0011] A T flip-flop array, which is used to encode the end signal according to the timing of the acquisition event to generate an edge change signal from the end signal, wherein the rising edge and the falling edge of the edge change signal both represent the arrival time of the acquisition event;

[0012] A TDC delay chain, which is used to generate a time mark corresponding to the edge change signal in each delay unit from the edge change signal, wherein the time mark represents the arrival time of the acquisition event;

[0013] An XOR gate module, which is used to perform logic judgment according to the time mark corresponding to the edge change signal to determine the event distribution corresponding to the acquisition event;

[0014] A D flip-flop array is used to latch and store the event distribution corresponding to the acquisition event in a corresponding storage unit in each coarse counting clock cycle until the measurement of M coarse counting clock cycles is completed, wherein the event distribution represents the time difference between the end signal and the start signal corresponding to the acquisition event in each coarse counting clock cycle;

[0015] A histogram statistics module is used to distribute the time difference between the end signal and the start signal corresponding to the acquisition event to each time interval range to generate a statistical histogram of event distribution corresponding to the acquisition event of M coarse counting clock cycles.

[0016] Optionally, the multi-event time-to-digital converter includes M coarse counting clock cycles; the TDC delay chain includes N delay units; the histogram statistics module is constructed by a storage module array, wherein the storage module array includes N storage modules, wherein each storage module includes M storage units, the delay units in the TDC delay chain correspond to the storage modules in the histogram statistics module, and each storage unit in the histogram statistics module corresponds to each coarse counting clock cycle.

[0017] Optionally, when entering the second coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the first coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address of 0 corresponding to the first coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address of 0 in the third coarse counting clock cycle;

[0018] When entering the third coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the second coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address of 1 corresponding to the second coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address of 1 in the fourth coarse counting clock cycle;

[0019] By analogy, in the M+1th coarse counting clock cycle, the D flip-flop and the XOR gate module capture the event distribution within the Mth coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address M-1 corresponding to the Mth coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address M-1 in the M+2th coarse counting clock cycle, until the event distribution storage of M coarse counting clock cycles is completed, so as to complete one measurement of the range of the multi-event time-to-digital converter.

[0020] Optionally, the event distribution of the first storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the first coarse counting clock cycle, and the event distribution of the second storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the second coarse counting clock cycle, and the reading is done in sequence until the event distribution of the Mth storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the Mth coarse counting clock cycle, so as to complete the histogram statistical data output of a measurement in the statistical histogram module.

[0021] Optionally, the range of the multi-event time-to-digital converter is expressed as:

[0022] K=M×T=M×N×Δt,

[0023] Wherein, K represents the range of the multi-event time-to-digital converter, M represents the number of coarse counting clock cycles, T represents the time length of the coarse counting clock cycle, N represents the number of delay units, and Δt is the width of the delay unit, which represents the delay time length of the delay unit.

[0024] Optionally, the multi-event time-to-digital converter is implemented based on a field programmable gate array or an application-specific integrated circuit.

[0025] Optionally, the synchronization signal generating module is implemented by an MMCM clock management unit in a field programmable gate array.

[0026] Optionally, the storage module array is implemented by BLOCK RAM storage resources in a field programmable gate array.

[0027] Optionally, the external applications include single photon detectors or medium and long-range lidars.

[0028] Compared with the prior art, the present application aims at realizing the traditional histogram statistical function in the prior art by using a time addressing method. This method is used for a multi-event time-to-digital converter, which requires multiple addressing and storage operations for multiple time information, which will increase the dead time of the multi-event time-to-digital converter, thereby limiting the event sampling rate of the multi-event time-to-digital converter. The present application includes but is not limited to the following beneficial effects:

[0029] First, in the multi-event time-to-digital converter with scalable range of the present application, each delay unit is paired with a storage module to synchronously store the arrival times of multiple events. This design allows continuous time sampling of multiple events in a delay chain without the need to provide a separate time tracking unit for each event. By multiplexing the delay units in the delay chain, the range of the TDC can be effectively expanded, allowing multiple events to be processed simultaneously. Each multiplexing increases the measurement time range of a delay chain (also equal to the coarse count clock cycle), and more events can be tracked at the same time, improving the sampling capability of the system.

[0030] Secondly, the time accuracy of the multi-event time-to-digital converter with scalable range of the present application is determined by the delay chain, which means that the time resolution of the system directly depends on the accuracy of the delay chain. The delay chain is composed of multiple delay units, and the accuracy of each delay unit will determine the sampling accuracy of the system for time. Using the "first in, first out" (FIFO) storage mode, the storage module will hardly introduce additional dead time. The FIFO storage mode allows instant storage of events when they arrive, reducing the time delay or "dead time" in traditional storage systems, thereby maintaining high sampling rate and time accuracy in multi-event TDC designs.

[0031] Thirdly, the multi-event time-to-digital converter with scalable range of the present application can control the increase of the range of the multi-event time-to-digital converter by the number of times the delay chain is reused. Each time the delay chain is reused, a delay chain measurement time range can be added, thereby expanding the range of the multi-event time-to-digital converter. This method neither sacrifices time accuracy nor affects the sampling rate of the event. By controlling the number of times the delay chain is reused, the range of the TDC can be accurately adjusted.

[0032] Fourth, each storage module is designed with sufficient depth to store statistical information of multiple events. This depth enables the system to perform long-term, continuous on-chip histogram statistics. Histogram statistics is a data processing process that generates a histogram of time distribution by collecting the arrival time of each event and classifying it into corresponding time intervals. This statistical method is very useful for analyzing the arrival time of events and the working status of the system. Compared with traditional external memory, on-chip storage can provide faster read and write operations and reduce data transmission latency. This enables this method to continuously perform statistics on event data without relying on external storage, which is suitable for application scenarios that require high speed and high precision.

[0033] Furthermore, the multi-event time-to-digital converter with scalable range of the present application can not only greatly improve the range of the multi-event time-to-digital converter by optimizing the storage structure (FIFO mode) and delay chain multiplexing, but also maintain high time resolution without sacrificing the sampling rate of the event. Through the design of on-chip histogram statistics, the system can collect data over a long period of time and quickly generate the distribution of event arrival times, which is of great significance for scenarios such as high-performance timing applications, experimental data collection, and high-frequency transient event monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0035] Figure 1 This is an exemplary architecture of a multi-event time-to-digital converter with an expandable range in an embodiment of the present application;

[0036] Figure 2 A schematic diagram of a T flip-flop and its typical input and output waveforms in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of a delay chain and a D flip-flop-XOR gate readout circuit architecture in an embodiment of the present application;

[0038] Figure 4 Schematic diagram of the state transition process of the histogram statistics module in the embodiment of the present application.

[0039] Figure 5 A schematic diagram of a structural diagram corresponding to a storage module array and a delay unit in an embodiment of the present application;

[0040] Figure 6 A schematic diagram of the time series of histogram statistics in an embodiment of the present application;

[0041] Figure 7 Schematic diagram of the timing of reading out the histogram data in the embodiment of the present application.

[0042] Figure 8 It is a schematic diagram of the time domain line shape of two LED emission pulses measured by the multi-event time-to-digital converter with expandable range implemented based on FPGA in the embodiment of the present application. DETAILED DESCRIPTION

[0043] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.

[0044] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0045] Unless the mutually exclusive relationship between the embodiments to be disclosed in this application is explicitly stated, the relevant technical features involved in each embodiment can be cross-combined to flexibly construct a new embodiment, as long as such combination does not deviate from the creative spirit of this application and can meet the needs of the prior art or solve certain deficiencies in the prior art. Those skilled in the art should be aware of this flexibility.

[0046] In one embodiment of the multi-event time-to-digital converter with expandable range of the present application, the multi-event time-to-digital converter with expandable range includes: a synchronization signal generation module, a T trigger array, a TDC delay chain, an XOR gate module, a D trigger array, and a histogram statistics module, etc.

[0047] A synchronization signal generation module, which is used to generate a start signal and a synchronization signal, wherein the start signal is used to trigger the TDC delay chain to generate a coarse counting clock signal, and the synchronization signal is used to trigger an external application to generate end signals corresponding to multiple acquisition events;

[0048] A T flip-flop array, which is used to encode the end signal according to the timing of the acquisition event to generate an edge change signal from the end signal, wherein the rising edge and the falling edge of the edge change signal both represent the arrival time of the acquisition event;

[0049] A TDC delay chain, which is used to generate a time mark corresponding to the edge change signal in each delay unit from the edge change signal, wherein the time mark represents the arrival time of the acquisition event;

[0050] An XOR gate module, which is used to perform logic judgment according to the time mark corresponding to the edge change signal to determine the event distribution corresponding to the acquisition event;

[0051] A D flip-flop array is used to latch and store the event distribution corresponding to the acquisition event in a corresponding storage unit in each coarse counting clock cycle until the measurement of M coarse counting clock cycles is completed, wherein the event distribution represents the time difference between the end signal and the start signal corresponding to the acquisition event in each coarse counting clock cycle;

[0052] A histogram statistics module is used to distribute the time difference between the end signal and the start signal corresponding to the acquisition event to each time interval range, so as to generate a statistical histogram of the event distribution corresponding to the acquisition event of M coarse counting clock cycles. The multi-event time-to-digital converter includes M coarse counting clock cycles, and the range of the multi-event time-to-digital converter can be controlled by controlling the size of M; the TDC delay chain includes N delay units; the histogram statistics module is constructed by a storage module array, wherein the storage module array includes N storage modules, wherein each storage module includes M storage units, the delay unit in the TDC delay chain corresponds to the storage module in the histogram statistics module, each storage unit in the histogram statistics module corresponds to each coarse counting clock cycle, and the XOR gate module can be an XOR array.

[0053] The coarse count clock cycle is the basic unit used to capture event timing in TDC. Each coarse count clock cycle can capture the event distribution that occurs within the cycle. These event distributions will be stored in the storage module in the histogram statistics module. In each coarse count clock cycle, the output of the XOR gate (i.e., the synthesis result of multiple delay units) will be sent to the storage module. The storage module accumulates the stored value with the current XOR gate output, which is equivalent to combining the event data in the current clock cycle with the previous accumulated data, thereby realizing data accumulation. The address of each storage unit is dynamically adjusted, that is, as the coarse count clock advances, the read and write addresses of the storage module will be updated in sequence. This ensures that the data is gradually accumulated and stored in the time sequence of the event occurrence. Each storage module has multiple storage units, and each unit stores a (event distribution data) time distribution data (for example: the time position of multiple events in a certain period of time).

[0054] In each coarse counting clock cycle, the first storage module and the second storage module will process the data output by an XOR gate respectively. These data are stored in different storage units by gradual accumulation, and each storage unit corresponds to event information within a time period.

[0055] The main function of the XOR gate is to combine the outputs of multiple delay units to generate a new timing information. These signals can be synthesized by feeding the outputs of every two delay units into an XOR gate. The result of each XOR gate output reflects the synthesis result of certain timing information. For example, if the time difference between two delay units is critical data, the XOR gate can synthesize these time differences through its logical operation (usually). For example, the output of 423 XOR gates corresponds to the synthesis result of 424 delay units after pairing them in pairs, and these output results reflect the timing information captured from the input event data.

[0056] In each coarse counting clock cycle, the output of the XOR gate is accumulated with the previously accumulated data in the storage module. This ensures that data in multiple clock cycles can be accumulated and finally generate complete timing data in the storage module.

[0057] In the first coarse counting clock cycle, the first storage unit of the storage module receives and accumulates the event data in the first clock cycle. Similarly, with the arrival of each new coarse counting clock cycle, the storage module gradually reads and accumulates the event data.

[0058] Ultimately, all event time series data are gradually stored in different storage units, and finally these data can be used for statistics and analysis, such as generating statistical histograms.

[0059] In some embodiments, a delay chain is used to generate a fine count of a multi-event time-to-digital converter, and the delay time length of each delay unit (called a bin) of the delay chain is used as the minimum resolution time unit of the multi-event time-to-digital converter. Assume that the delay chain includes N bins, and the width of each delay unit (bin) is Δt. The measurement range of the multi-event time-to-digital converter includes M coarse count clock cycles, and the length of the coarse count clock cycle is T. The expression of the range of the multi-event time-to-digital converter is:

[0060] K=M×T=M×N×Δt,

[0061] Wherein, K represents the range of the multi-event time-to-digital converter, M represents the number of coarse counting clock cycles, T represents the time length of the coarse counting clock cycle, N represents the number of delay units, and Δt is the width of the delay unit, which represents the delay time length of the delay unit.

[0062] In some embodiments, the input signal is encoded by a T flip-flop with the T port set to "1", such as Figure 2 As shown, the rising edges of multiple events arriving at different times are converted into edge change signals, and the rising edge and falling edge of the edge change signal both represent the time when the event arrives; the signal encoded by the T trigger (i.e., the edge change signal) enters the TDC delay chain for time measurement.

[0063] The XOR gate output data "0" and "1" represent "no event" and "event presence" of this delay chain unit.

[0064] The clock signal is used as the coarse counting clock of the multi-event TDC, and the rising edge of the clock signal is used as the starting point of the multi-event TDC measurement range.

[0065] In some embodiments, the multi-event time-to-digital converter is implemented based on a field programmable gate array or an application-specific integrated circuit; the synchronization signal generation module is implemented by the MMCM clock management unit in the field programmable gate array; the storage module array is implemented by the BLOCK RAM storage resource in the field programmable gate array; the external applications include but are not limited to single photon detectors and medium and long-range laser radars.

[0066] Specifically, the multi-event time-to-digital converter with an extendable range of the present application can be implemented by a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). The present application selects the multi-event time-to-digital converter with an extendable range based on a field programmable gate array as an example, which does not constitute a limitation on the present application.

[0067] See also Figure 1 The basic structure of the multi-event time-to-digital converter with an expandable range of the present application is as follows: Figure 1 As shown, the synchronization signal generation module is implemented by the MMCM clock management unit in the field programmable gate array (FPGA), wherein the MMCM clock management unit generates a clock signal with a coarse counting clock period of 5.0ns as the coarse counting clock signal of the multi-event time-to-digital converter (TDC); the CARRY4 module in the field programmable gate array is used as the basic delay unit, and the TDC delay chain of the multi-event time-to-digital converter is constructed by cascading CARRY4. The entire TDC delay chain has a total of 424 delay units, and the output interface of each delay unit is the CO port of CARRY4. The delay time (i.e., bin width) of each delay unit determines the accuracy of the multi-event time-to-digital converter (TDC) measuring time. The use of advanced process FPGA chips can realize a delay unit with an average delay time of 12.0ps, which can realize a multi-event time-to-digital converter (TDC) with a time measurement accuracy of 12.0ps.

[0068] See also Figure 2 , use the D flip-flop module in the field programmable gate array to build a T flip-flop, and input the end signal (STOP signal) corresponding to the acquisition event into the clock port of the T flip-flop to convert it into an edge change signal; Figure 3 As shown, the output port of the T flip-flop is connected to the D flip-flop, and the output state of the T flip-flop is latched at the rising edge of the coarse counting clock; the two-input XOR gate module is built using LUT resources, and the output ends of the adjacent D flip-flops are connected to the XOR gate. The output state of the XOR gate represents the moment when the event arrives, that is, the event distribution corresponding to the acquisition event.

[0069] The synchronous pulse signal generated by the coarse counting clock is used as the start signal (START signal) of the multi-event time-to-digital converter (TDC). The pulse width of the start signal is 5.0ns, which means that the duration of each triggering start signal is 5.0ns. It is used to determine the time window for the multi-event time-to-digital converter to start timing. The period of the start signal is the number of coarse counting periods of the multi-event time-to-digital converter M multiplied by the length of the coarse counting clock period, wherein the length of the coarse counting clock period is 5.0ns. The external input signal is used as the end signal (STOP signal) of the multi-event time-to-digital converter (TDC); wherein the external input signal can be a signal from a single photon detector or a control signal from a controller.

[0070] The BLOCKRAM resources inside the field programmable gate array are used to build a storage module array (i.e., histogram statistics module). Since the TDC delay chain has a total of 424 delay units, and the outputs of two adjacent delay units are sent to an XOR gate module, it can be seen that there are a total of 423 storage modules in the storage module array. Each storage module reserves space for 8192 (or more) storage units for adjusting the storage depth and the range of the multi-event time-to-digital converter. Each storage unit is set to 32 bits, and can store a maximum of 2 32 -1 event.

[0071] More specifically, each delay unit does not directly correspond to a single storage module. Since the outputs of two adjacent delay units are fed into the same XOR gate, this design means that in each coarse count clock cycle, the outputs of two adjacent delay units will be merged and processed. Therefore, the outputs of 424 delay units are actually mapped to 423 storage modules in a one-to-one manner.

[0072] In a further embodiment, the range of the multi-event time-to-digital converter can be set according to the requirements of external applications such as single-photon detectors, and the value of the number of coarse counting cycles M of the multi-event time-to-digital converter can be set. For example, assuming that the single-photon detector requires a measurement range of 1000.0ns, the value of the number of coarse counting cycles M of the multi-event time-to-digital converter is set to 200, that is, each storage module initializes 200 storage units for storing measurement results. At the same time, this also means that the TDC delay chain is reused 200 times, so that the maximum range of the multi-event time-to-digital converter reaches 5.0ns×200=1000.0ns. The number of measurements is input to the measurement number register of the multi-event time-to-digital converter, which means that the histogram statistics are repeated P times to obtain statistically significant results, where the P value is usually set at 10 3 above.

[0073] In some embodiments, when entering the second coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the first coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address of 0 corresponding to the first coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address of 0 in the third coarse counting clock cycle;

[0074] When entering the third coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the second coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address of 1 corresponding to the second coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address of 1 in the fourth coarse counting clock cycle;

[0075] By analogy, in the M+1th coarse counting clock cycle, the D flip-flop and the XOR gate module capture the event distribution within the Mth coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address M-1 corresponding to the Mth coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address M-1 in the M+2th coarse counting clock cycle, until the event distribution storage of M coarse counting clock cycles is completed, so as to complete one measurement of the range of the multi-event time-to-digital converter.

[0076] Specifically, in the first coarse counting clock cycle of the multi-event time-to-digital converter, its rising edge serves as the starting point of the multi-event time-to-digital converter's range. This signal can also be used as a synchronization signal for external instruments, such as being output to the outside as a trigger signal for an external light source to cause it to emit a light pulse; the light pulse emitted by the light source acts on the sample, and the light signal reflected or re-emitted is detected by the single-photon detector; multiple events detected by the single-photon detector within the same signal cycle are sent to the end (STOP end) of the multi-event time-to-digital converter to achieve time-correlated single photon counting (TCSPC) measurement.

[0077] See also Figures 4 to 6 After the measurement is turned on, in the second coarse counting clock cycle of the multi-event time-to-digital converter, the coarse counting clock captures the event distribution in the first coarse counting clock cycle. At this time, the read address of the first storage module is set to 0, that is, the address of the first storage unit, and the data in this unit is read out, accumulated with the output data of the first XOR gate, and input to the address unit in the third coarse counting clock cycle. The read address of the second storage module is also set to 0, accumulated with the output data of the second XOR gate, and re-input to the address unit;

[0078] In the third coarse count clock cycle of the multi-event time-to-digital converter, the coarse count clock captures the event distribution in the second clock cycle. At this time, the read address of the first storage module is set to 1, that is, the address of the second storage unit. The data in this unit is read out and accumulated with the output data of the first XOR gate, and input to the address unit in the fourth coarse count clock. The read address of the second storage module is also set to 1, accumulated with the output data of the second XOR gate, and re-input to the address unit. Repeat the above process M times to complete the statistics of all event distributions within the range of the multi-event time-to-digital converter. And so on, complete the storage of all 423 XOR gate data to complete the measurement of the range of the multi-event time-to-digital converter.

[0079] After completing a multi-event time-to-digital converter range measurement, the measurement times counter of the multi-event time-to-digital converter range is increased by one, and the above steps are repeated until the measurement times counter value of the multi-event time-to-digital converter is equal to the set value P of the measurement times register of the multi-event time-to-digital converter, thereby completing the histogram statistical measurement of the time domain distribution of the incident signal.

[0080] The output of each XOR gate represents the synthesis result of a timing information. The data of each XOR gate is sent to the storage module and accumulated with the previously stored event data. The storage process is carried out in the order of the coarse counting clock cycle: the first storage module and the second storage module will store the output data of each XOR gate respectively, and gradually accumulate them in each coarse counting clock cycle. The 423 XOR gate data are obtained by pairing 424 delay units in pairs through an XOR gate, and finally the timing information of the event is captured and stored through the output result of the XOR gate. In this way, the timing data of each event in the multi-event time-to-digital converter can be effectively merged and stored, providing a data basis for further statistics and analysis.

[0081] In a further embodiment, the event distribution of the first storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the first coarse counting clock cycle, and the event distribution of the second storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the second coarse counting clock cycle, and the reading is sequentially performed until the event distribution of the Mth storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the Mth coarse counting clock cycle, so as to complete the histogram statistical data output of a measurement in the statistical histogram module.

[0082] Specifically, see Figure 7 After completing the required P histogram statistics, the histogram statistical data is output, the histogram data is output, and the event distribution of the first storage unit of the 423 storage modules in the statistical histogram module is read to determine the event distribution within the first rough counting clock cycle, and the event distribution of the second storage unit of the 423 storage modules in the statistical histogram module is read to determine the event distribution within the second rough counting clock cycle. The reading is done in sequence until the event distribution of the Mth storage unit of the 423 storage modules in the statistical histogram module is read to determine the event distribution within the Mth rough counting clock cycle, and so on. The data in the 423 storage modules in all the statistical histogram modules are output to complete the statistical histogram data output.

[0083] In some embodiments, see Figure 8 , the single photon detector comprises a single photon avalanche diode detector, Figure 8The time domain linear shape of two light emitting diodes (LEDs) emitting light pulses under pulse drive was measured by combining a multi-event time-to-digital converter with an expandable range implemented based on FPGA with a single-photon avalanche diode detector, verifying that the multi-event time-to-digital converter with an expandable range in this application has a range of up to 1000.0ns.

[0084] It can be seen from the above embodiments that, compared with the prior art, the present application aims at solving the problems that the multi-event time-to-digital converter in the prior art has a short range and the traditional histogram statistical function is often implemented by using a time addressing method. This method is used for the multi-event time-to-digital converter, which requires multiple addressing and storage operations for multiple time information, which will increase the dead time of the multi-event time-to-digital converter, thereby limiting the event sampling rate of the multi-event time-to-digital converter. The present application includes but is not limited to the following beneficial effects:

[0085] First, in the multi-event time-to-digital converter with scalable range of the present application, each delay unit works in pairs with a storage module to synchronously store the arrival times of multiple events. This design allows continuous time sampling of multiple events in a delay chain without the need to provide a separate time tracking unit for each event. By multiplexing the delay units in the delay chain, the range of the TDC can be effectively expanded, allowing multiple events to be processed simultaneously. Each multiplexing increases the measurement time range of a delay chain, and more events can be tracked at the same time, improving the sampling capability of the system.

[0086] Secondly, the time accuracy of the multi-event time-to-digital converter with scalable range of the present application is determined by the delay chain, which means that the time resolution of the system directly depends on the accuracy of the delay chain. The delay chain is composed of multiple delay units, and the accuracy of each delay unit will determine the sampling accuracy of the system for time. Using the "first-in-first-out" (FIFO) storage mode, the storage module will hardly introduce additional dead time. The FIFO storage mode allows instant storage of event arrival time, reducing the time delay or "dead time" in traditional storage systems, thereby maintaining high sampling rate and time accuracy in multi-event TDC designs.

[0087] Thirdly, the multi-event time-to-digital converter with scalable range of the present application can control the increase of the range of the multi-event time-to-digital converter by the number of times the delay chain is reused. Each time the delay chain is reused, a delay chain measurement time range can be added, thereby expanding the range of the multi-event time-to-digital converter. This method neither sacrifices time accuracy nor affects the sampling rate of the event. By controlling the number of times the delay chain is reused, the range of the TDC can be accurately adjusted.

[0088] Fourth, each storage module is designed to have sufficient depth to store statistical information of enough events. This storage depth enables the system to perform long-term, continuous on-chip histogram statistics. Histogram statistics is a data processing process that generates a histogram of time distribution by collecting the arrival time of each event and classifying it into corresponding time intervals. This statistical method is very useful for analyzing the arrival time of events and the working status of the system. Compared with traditional external memory, on-chip storage can provide faster read and write operations and reduce data transmission delays. This enables this method to continuously perform statistics on event data without relying on external storage, which is suitable for application scenarios that require high speed and high precision.

[0089] Furthermore, the multi-event time-to-digital converter with scalable range of the present application can not only greatly improve the range of the multi-event time-to-digital converter by optimizing the storage structure (FIFO mode) and delay chain multiplexing, but also maintain high time resolution without sacrificing the sampling rate of the event. Through the design of on-chip histogram statistics, the system can collect data over a long period of time and quickly generate the distribution of event arrival times, which is of great significance for scenarios such as high-performance timing applications, experimental data collection, and high-frequency transient event monitoring.

[0090] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A multi-event time-to-digital converter with an expandable range, characterized in that: include: A synchronization signal generation module, which is used to generate a start signal and a synchronization signal, wherein the start signal is used to trigger the TDC delay chain to generate a coarse counting clock signal, and the synchronization signal is used to trigger an external application to generate end signals corresponding to multiple acquisition events; A T flip-flop array, which is used to encode the end signal according to the timing of the acquisition event to generate an edge change signal from the end signal, wherein the rising edge and the falling edge of the edge change signal both represent the arrival time of the acquisition event; A TDC delay chain, which is used to generate a time mark corresponding to the edge change signal in each delay unit from the edge change signal, wherein the time mark represents the arrival time of the acquisition event; An XOR gate module, which is used to perform logic judgment according to the time mark corresponding to the edge change signal to determine the event distribution corresponding to the acquisition event; A D flip-flop array is used to latch and store the event distribution corresponding to the acquisition event in a corresponding storage unit in each coarse counting clock cycle until the measurement of M coarse counting clock cycles is completed, wherein the event distribution represents the time difference between the end signal and the start signal corresponding to the acquisition event in each coarse counting clock cycle; A histogram statistics module is used to distribute the time difference between the end signal and the start signal corresponding to the acquisition event to each time interval range to generate a statistical histogram of event distribution corresponding to the acquisition event of M coarse counting clock cycles.

2. The multi-event time-to-digital converter with an expandable range according to claim 1, characterized in that: The multi-event time-to-digital converter includes M coarse counting clock cycles; the TDC delay chain includes N delay units; The histogram statistics module is constructed by a storage module array, wherein the storage module array includes N storage modules, wherein each storage module includes M storage units, the delay units in the TDC delay chain correspond to the storage modules in the histogram statistics module, and each storage unit in the histogram statistics module corresponds to each coarse counting clock cycle.

3. The multi-event time-to-digital converter with expandable range according to claim 2, characterized in that: When entering the second coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the first coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address of 0 corresponding to the first coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address of 0 in the third coarse counting clock cycle; When entering the third coarse counting clock cycle of the multi-event time-to-digital converter, the D flip-flop and the XOR gate module capture the event distribution in the second coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address of 1 corresponding to the second coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address of 1 in the fourth coarse counting clock cycle; By analogy, in the M+1th coarse counting clock cycle, the D flip-flop and the XOR gate module capture the event distribution within the Mth coarse counting clock cycle, and read the event distribution of the storage unit with the storage unit address M-1 corresponding to the Mth coarse counting clock cycle, add the event distribution output by the corresponding XOR gate module, and store it back to the storage unit with the storage unit address M-1 in the M+2th coarse counting clock cycle, until the event distribution storage of M coarse counting clock cycles is completed, so as to complete one measurement of the range of the multi-event time-to-digital converter.

4. The multi-event time-to-digital converter with an expandable range according to claim 3, characterized in that: The event distribution of the first storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the first coarse counting clock cycle, and the event distribution of the second storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the second coarse counting clock cycle. The reading is performed sequentially until the event distribution of the Mth storage unit of each storage module in the statistical histogram module is read to determine the event distribution within the Mth coarse counting clock cycle, so as to complete the histogram statistical data output of a measurement in the statistical histogram module.

5. The multi-event time-to-digital converter with expandable range according to claim 2, characterized in that: The expression of the range of the multi-event time-to-digital converter is: K=M×T=M×N×Δt, Wherein, K represents the range of the multi-event time-to-digital converter, M represents the number of coarse counting clock cycles, T represents the time length of the coarse counting clock cycle, N represents the number of delay units, and Δt is the width of the delay unit, which represents the delay time length of the delay unit.

6. The multi-event time-to-digital converter with an expandable range according to any one of claims 1, characterized in that: The multi-event time-to-digital converter is implemented based on a field programmable gate array or a dedicated integrated circuit.

7. The multi-event time-to-digital converter with an extendable range according to any one of claims 1, characterized in that: The synchronization signal generation module is implemented by an MMCM clock management unit in a field programmable gate array.

8. The multi-event time-to-digital converter with an extendable range according to any one of claims 1, characterized in that: The storage module array is implemented by BLOCK RAM storage resources in a field programmable gate array.

9. The multi-event time-to-digital converter with expandable range according to claim 1, characterized in that: The external applications include single photon detectors or medium and long-range lidars.

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