Preparation method of charge trapping memory with TiN-doped Si3N4 storage layer

Abstract

The present invention relates to the field of semiconductor technology and proposes a method for preparing a charge-trapping memory (CTM) with a TiN-doped Si3N4 storage layer. The method comprises the following steps: S1, cleaning the substrate, and then depositing a tunneling layer on the substrate surface; S2, depositing m layers of Si3N4 film and p layers of TiN film on the tunneling layer surface, repeating this process x times, and finally depositing n layers of Si3N4 film to obtain a TiN-doped Si3N4 storage layer, wherein 25≤m≤50, 25≤n≤50, p=1, 5≤x≤11; S3, depositing a barrier layer on the storage layer surface, and then evaporating an Al electrode on the barrier layer surface. By doping the Si3N4 storage layer with TiN, the present invention provides more charge traps and increases the charge trap density of the storage layer. Compared with an undoped control group, the CTM exhibits a larger storage window, better device fatigue characteristics, and excellent retention performance, greatly improving the reliability of the CTM.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a charge-trapping memory having a TiN-doped Si3N4 storage layer. Background Art

[0002] Digitalization and the development of integrated circuits have profoundly changed our lives. The emergence of mobile phones, computers, and artificial intelligence has generated vast amounts of data, driving the development of various memory devices. Flash memory, as a non-volatile memory, holds a significant market share due to its high density, speed, durability, and low cost. The transition of flash memory from 2D to 3D structures has significantly increased storage density, pushing the limits of semiconductor processing.

[0003] The core of 3D flash memory is charge trap memory. Currently, the primary storage unit in 3D NAND flash memory is charge trap memory, with the storage layer made of Si3N4. However, shallow trap levels in Si3N4 reduce device reliability, especially in 3D structures. Charge trapped in these shallow trap levels in the storage layer is susceptible to lateral and vertical diffusion, leading to reduced device reliability. Therefore, reducing shallow trap levels in Si3N4 and increasing the number of charge traps in the storage layer are current research priorities. Atomic doping can modify material band gaps and defect energy levels, and has been widely used in electronic devices. In charge trap memory, there has been extensive research on improving device storage performance through atomic doping, including with elements such as Hf, Al, Zr, Ti, and Y. However, the experimental procedures for metal doping and the amount of metal to be added are not well understood. Therefore, experimentally doping the storage layer of charge trap memory is a challenge that needs to be addressed. Summary of the Invention

[0004] To address the aforementioned issues of how to increase the charge trap density, reduce shallow trap levels, and incorporate metal elements in the Si3N4 memory layer, the present invention proposes a method for doping the Si3N4 memory layer with TiN using a PEALD process. This method involves doping the TiN dielectric grown using NH3 plasma during the PEALD process. This method incorporates metallic Ti during the TiN-doped Si3N4 film, replacing shallow trap levels in the Si3N4 film while increasing the number of charge traps in the Si3N4 film and thereby improving the device's memory window. The incorporation of metallic Ti modulates the Si3N4 film's trap levels, introducing deeper charge trap levels and enhancing the device's retention performance. Furthermore, by treating the Si3N4 film's interface with NH3 plasma during the TiN growth process, the film's boundary state density and shallow trap levels are reduced, improving the Si3N4 film's quality and significantly enhancing the device's endurance and retention characteristics. Furthermore, NH3 plasma treatment of the Si3N4 film effectively reduces the oxygen content in the film, improving the quality of the nitride film. Finally, the dielectric film was subjected to high-temperature rapid thermal annealing treatment, which promoted the filling of shallow trap energy levels in the Si3N4 film by Ti elements and the fusion between TiN and Si3N4 dielectric, repaired the lattice defects generated during the film deposition process, further improved the film quality, reduced leakage, and increased the breakdown voltage.

[0005] The technical solution of the present invention is achieved as follows: The present invention provides a method for preparing a charge trapping memory with a TiN-doped Si3N4 storage layer, comprising the following steps:

[0006] S1, cleaning the substrate and then depositing a tunneling layer on the substrate surface;

[0007] S2, depositing m layers of Si3N4 film and p layers of TiN film on the surface of the tunneling layer, repeating this process x times, and finally depositing n layers of Si3N4 film to obtain a TiN-doped Si3N4 storage layer;

[0008] Where 25≤m≤50, 25≤n≤50, p=1, 5≤x≤11;

[0009] S3, depositing a barrier layer on the surface of the storage layer, and then evaporating an Al electrode on the surface of the barrier layer.

[0010] Specifically, the present invention adopts a doping method of first depositing an m-layer Si3N4 film and a p-layer TiN film, repeating this process x times, and then depositing an n-layer Si3N4 film, so that the TiN and Si3N4 are fully mixed, so that the Ti element can better fill the shallow trap energy levels in the Si3N4 film, provide deep trap energy levels, increase the charge trap density of the storage layer, and further improve the storage window and retention characteristics of the storage device.

[0011] On the basis of the above technical solution, preferably, m=n=25, x=11, and p=1.

[0012] Based on the above technical solution, preferably, during the deposition of the storage layer in step S2, the Si3N4 film growth precursor is bis(diethylamino)silane and N2 plasma, and the TiN film growth precursor is titanium tetrachloride and NH3 plasma; the growth temperature of the two films is 300℃-400℃, and the gas atmosphere and purge gas are argon.

[0013] Specifically, Si3N4 thin films are grown using N2 plasma to nitride the silicon source, while TiN thin films are grown using NH3 plasma to nitride the titanium source. Because the TiN thin film requires fewer growth cycles, the use of hazardous NH3 gas is reduced, making the preparation method safer and more environmentally friendly. Furthermore, the small amount of NH3 plasma nitrides the Si3N4 thin film interface, reducing the interface state density and shallow trap energy levels, thereby improving film quality.

[0014] Based on the above technical solution, preferably, in step S3, the device on which the three dielectric thin films of the tunneling layer, the storage layer and the barrier layer are deposited is annealed and then an Al electrode is evaporated, the annealing temperature is 750° C.-850° C., and the time is 60-90 seconds.

[0015] On the basis of the above technical solution, preferably, in step S3, the device after the Al electrode is evaporated is annealed in an annealing furnace at 250° C.-350° C. for 15-25 minutes.

[0016] On the basis of the above technical solution, preferably, the materials of the tunneling layer and the barrier layer are the same or different, and the materials of the tunneling layer and the barrier layer are selected from one or more combinations of SiO2, Al2O3, HfO2 and ZrO2.

[0017] Based on the above technical solution, preferably, the tunnel layer and the barrier layer are deposited at a temperature of 100°C-300°C.

[0018] Based on the above technical solution, preferably, the thickness of the tunneling layer is 2-10 nm.

[0019] Based on the above technical solution, preferably, the thickness of the storage layer is 5-20 nm.

[0020] Based on the above technical solution, preferably, the thickness of the barrier layer is 10-30 nm.

[0021] The method for preparing a charge trapping memory with a TiN-doped Si3N4 storage layer of the present invention has the following beneficial effects compared with the prior art:

[0022] (1) The storage layer material of the conventional charge trap memory is Si3N4. However, the present invention dopes the storage layer Si3N4 thin film with TiN, which brings the following benefits:

[0023] ①TiN doping provides more charge traps for the Si3N4 film, increasing the charge trap density in the storage layer and thus increasing the device memory window. Furthermore, as the amount of TiN dielectric doping in the storage layer Si3N4 film increases, the device memory window increases significantly.

[0024] ② During the TiN doping process of Si3N4 film, the metallic Ti element provides a deeper trap energy level, replacing the shallow trap energy level in the Si3N4 film. Therefore, the doping of the metallic Ti element regulates the trap energy level of the Si3N4 film, so that the charge in the storage layer is better captured by the deep trap energy level, less likely to leak, and improves the retention characteristics of the storage device. At the same time, during the TiN doping process, the NH3 plasma used in TiN growth nitrides the interface of the Si3N4 film, reducing the interface state density of the film, reducing the interface shallow trap energy level, and improving the film quality and voltage resistance. Therefore, by using TiN doped Si3N4 film as the storage layer, the fatigue characteristics and retention characteristics of the device are improved.

[0025] ③ In the process of using N2 plasma to grow Si3N4 film in the PEALD process, a small amount of NH3 plasma is used to grow TiN doping step, which can significantly reduce the oxide component in the Si3N4 film grown by the PEALD process using N2 plasma and increase the proportion of Si-N content.

[0026] (2) The TiN-doped Si3N4 storage layer film of the present invention is grown at 300°C using the PEALD process, which has a relatively low growth temperature. The Si3N4 film growth precursor is bis(diethylamino)silane and N2 plasma. These two precursors do not contain dangerous and harmful elements such as Cl and NH3, and are safe to grow and environmentally friendly. The TiN film growth precursor is titanium tetrachloride and NH3 plasma. Since the number of TiN growth cycles is small, the environmental pollution is small. Therefore, the growth process of the storage layer of the device of the present invention is safer and more environmentally friendly.

[0027] (3) In the charge trapping memory of the present invention, the functional layers (tunneling layer-storage layer-barrier layer) of the thin films are all grown using the ALD process. The device can complete the growth and preparation of all thin films on the same device, avoiding the contamination of the interface caused by the device during the transfer process between different devices. This is conducive to improving the quality of the thin films and further improving the performance of the prepared device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0029] Figure 1 The process flow of preparing the charge trap memory of the present invention is shown in FIG.

[0030] Figure 2 Schematic diagram of the TiN-doped Si3N4 storage layer film structure;

[0031] Figure 3 Schematic diagram of the effect of TiN-doped Si3N4 storage layer on the device storage window, (a) is the storage layer without TiN doping, (b) is the storage layer doped with 5 cycles of TiN, (c) is the storage layer doped with 9 cycles of TiN, and (d) is the storage layer doped with 11 cycles of TiN;

[0032] Figure 4 Comparison of storage window sizes for devices with undoped TiN and storage layers doped with 5, 9, and 11 TiN cycles;

[0033] Figure 5 Schematic diagram of the effect of TiN-doped Si3N4 storage layer on device fatigue characteristics, (a) is the storage layer without TiN doping, (b) is the storage layer doped with 5 cycles of TiN, (c) is the storage layer doped with 9 cycles of TiN, and (d) is the storage layer doped with 11 cycles of TiN.

[0034] Figure 6 Schematic diagram of the effect of TiN-doped Si3N4 storage layer on device retention characteristics, (a) is the storage layer without TiN doping, (b) is the storage layer doped with 5 cycles of TiN, (c) is the storage layer doped with 9 cycles of TiN, and (d) is the storage layer doped with 11 cycles of TiN;

[0035] Figure 7 Schematic diagram of XPS test results of storage layer Si3N4 and 9-cycle doped TiN film. (a)-(c) are N of 300-cycle Si3N4 film without TiN doping. 1s 、Si 2p , O 1s Peak spectra, (d)-(f) are N peaks of 300-cycle Si3N4-doped 9-cycle TiN films. 1s 、Si 2p 、Ti 2p Peak spectrum. DETAILED DESCRIPTION

[0036] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0037] Example 1

[0038] The method for preparing a charge trapping memory device with a TiN-doped Si3N4 storage layer comprises the following steps:

[0039] S1, substrate cleaning:

[0040] The present invention utilizes a p-Si substrate with a resistivity of 1-10 Ω·cm. The Si wafer is cleaned using a standard RCA cleaning process to remove organic and inorganic impurities from the Si wafer surface and obtain a clean surface. The cleaning method comprises sequential ultrasonic cleaning with acetone and anhydrous ethanol. After rinsing with deionized water, the wafer is placed in a solution of 29% NH4OH (mass fraction): 30% H2O2 (mass fraction): H2O in a ratio of 1:1:5 (v / v), boiled at 70°C for 10 minutes, and then repeatedly rinsed with deionized water. The wafer is then placed in a solution of 37% HCl (mass fraction): 30% H2O2 (mass fraction): H2O in a ratio of 1:1:6 (v / v), boiled at 75°C for 10 minutes, and then repeatedly rinsed with deionized water. The wafer, which has undergone two soakings, is then immersed in a 5% v / v HF solution (HF:H2O = 10:70) for 2 minutes to remove the natural oxide layer on the surface of the wafer. Finally, rinse repeatedly with deionized water to remove the HF solution remaining on the surface of the Si wafer, and then use N2 to blow dry the Si wafer.

[0041] S2, ALD deposition of tunneling layer Al2O3 film:

[0042] Al2O3 thin films were grown using a thermal atomic layer deposition (TALD) system. A cleaned Si substrate was placed in the TALD chamber to grow a 3nm thick Al2O3 film. Al2O3 was used as the tunneling layer material, and the growth temperature was 200°C. Trimethylaluminum (TMA) and water (H2O) were used as precursors.

[0043] The deposition sequence for growing one Al2O3 film is TMA-N2-H2O-N2, with a corresponding deposition time of 0.02s-15s-0.015s-15s. The Al2O3 thickness grown in one cycle is 0.1nm, so a 3nm Al2O3 tunneling layer requires 30 ALD cycles.

[0044] S3, PEALD deposition of storage layer Si3N4 (TiN) film:

[0045] Si3N4 thin films were grown using a plasma-enhanced atomic layer deposition (PEALD) system. A Si substrate, already coated with an Al2O3 tunneling layer, was placed in a PEALD chamber to grow a 6nm Si3N4 film. The Si3N4 growth temperature was 300°C, and the precursors were bis(diethylamino)silane (BDEAS) and N2 plasma (50 sccm, 200W power).

[0046] The deposition sequence for growing a single Si3N4 film is BDEAS-Ar-N2 Plasma-Ar, with a duration of 0.2s-15s-15s-15s. The Si3N4 thickness grown in one cycle is 0.02nm, so a 6nm Si3N4 storage layer requires 300 ALD cycles.

[0047] The TiN film was grown at 300°C using titanium tetrachloride (TiCl4) as the precursor and NH3 plasma (10 sccm flow rate, 200 W power). The deposition sequence for one cycle of TiN film growth was TiCl4-Ar-NH3Plasma-Ar, with a deposition time of 0.1s-30s-10s-30s.

[0048] The storage layer Si3N4 (TiN) film structure is as follows Figure 2 As shown, it is prepared by growing a 300-cycle Si3N4 film and uniformly doping it with x cycles of TiN film. The deposition sequence for the storage layer Si3N4 (TiN) film is [(BDEAS-Ar-Plasma N2-Ar) × m-(TiCl4-Ar-Plasma NH3-Ar) × p] × x-(BDEAS-Ar-Plasma N2-Ar) × n. The deposition time is [(0.2s-15s-15s-15s) × m-(0.1s-30s-10s-30s) × p] × x-(0.2s-15s-15s-15s) × n.

[0049] In this embodiment, 5 cycles of TiN film are doped during the growth of 300 cycles of Si3N4 film, so m=50, p=1, x=5, and n=50.

[0050] S4, ALD deposition of barrier layer Al2O3 film:

[0051] Al2O3 thin films were grown using a thermal atomic layer deposition (TALD) system. A Si substrate, already coated with an Al2O3 tunneling layer and a Si3N4 (TiN) storage layer, was placed in the TALD chamber to grow a 13nm Al2O3 film. Al2O3 was selected as the barrier layer material. The Al2O3 growth temperature was 200°C, and the precursors used were trimethylaluminum (TMA) and water (H2O).

[0052] The deposition sequence for growing one Al2O3 film is TMA-N2-H2O-N2, with a deposition time of 0.02s-15s-0.015s-15s. The Al2O3 thickness grown in one cycle is 0.1nm, so a 13nm Al2O3 tunneling layer requires 130 ALD cycles.

[0053] S5, rapid thermal annealing of dielectric film:

[0054] The device with three dielectric thin films of tunneling layer, storage layer and barrier layer deposited by ALD was placed in a rapid thermal annealing furnace, annealed at 800℃ in N2 atmosphere for 60s, and then naturally cooled to room temperature and taken out.

[0055] S6, Metal Electrode Preparation:

[0056] There are no special requirements for the preparation of metal electrodes. The present invention only provides a method for evaporating a circular Al electrode with a diameter of 100um and a thickness of 100nm. First, AZ5214 photoresist is spin-coated on the surface of the device at 4000r / 60s and baked at 110°C for 10min. Then, a circular electrode mask with a diameter of 100um is selected, exposed for 5.5s under a photolithography machine, and developed for 70s. Finally, deionized water is used to remove excess developer, and the device after photolithography is evaporated with a 100nm Al electrode in a thermal evaporator. After evaporation, acetone is used to remove excess photoresist. Finally, the device with the evaporated Al electrode is annealed in an annealing furnace at 300°C in an N2 atmosphere for 20min to improve the contact characteristics between the metal Al electrode and the medium.

[0057] Example 2

[0058] The difference between this embodiment and embodiment 1 is that 9 cycles of TiN film are added during the growth of 300 cycles of Si3N4 film, m=30, p=1, x=9, n=30. The rest of the contents are the same as embodiment 1.

[0059] Example 3

[0060] The difference between this embodiment and embodiment 1 is that 11 cycles of TiN film are added during the growth of 300 cycles of Si3N4 film, m=25, p=1, x=11, n=25. The rest of the contents are the same as embodiment 1.

[0061] In some embodiments of the present invention, the materials of the tunneling layer and the barrier layer are selected from one or more combinations of SiO2, Al2O3, HfO2 and ZrO2.

[0062] In some embodiments of the present invention, the thickness of the tunneling layer is 2-10 nm.

[0063] In some embodiments of the present invention, the thickness of the storage layer is 5-20 nm.

[0064] In some embodiments of the present invention, the thickness of the barrier layer is 10-30 nm.

[0065] As the tunneling layer thickness increases, the device fatigue characteristics improve; as the storage layer thickness increases, the device memory window becomes larger; and as the barrier layer thickness increases, the device retention characteristics improve. However, as the thickness of each layer increases, the device operating voltage increases, and the programming / erase speed slows down.

[0066] In some embodiments of the present invention, the materials of the tunneling layer and the barrier layer are selected from one or more combinations of SiO2, Al2O3, HfO2 and ZrO2.

[0067] When SiO2 is used as a barrier / tunneling layer material, its large bandgap can improve device retention and fatigue characteristics. High-k materials such as Al2O3, HfO2, and ZrO2 have large dielectric constants and, when used as tunneling / barrier layers, can facilitate device scalability and increase programming / erase speeds.

[0068] In some embodiments of the present invention, the growth temperature of the Si3N4 film and the TiN film is 300°C-400°C, and the deposition temperature of the tunneling layer and the barrier layer is 100°C-300°C.

[0069] Deposition temperature has little impact on device storage performance, but primarily affects the film growth rate. As the deposition temperature increases, the film deposition rate increases and eventually reaches saturation.

[0070] In some embodiments of the present invention, a device having three dielectric thin films of a tunneling layer, a storage layer, and a barrier layer is annealed and then an Al electrode is evaporated. The annealing temperature is 750° C.-850° C. and the time is 60-90 seconds.

[0071] In some embodiments of the present invention, the device after the Al electrode is evaporated is annealed in an annealing furnace at 250° C. to 350° C. for 15 to 25 minutes.

[0072] For thin-film dielectric annealing, in this example, a higher annealing temperature and appropriate annealing time facilitate the mixing of TiN and Si3N4 and the doping of Ti, reducing lattice damage during thin-film deposition. However, annealing at too high a temperature or for too long can damage the film, so it is important to select the appropriate annealing temperature and time.

[0073] Regarding electrode annealing, in this example, a suitable annealing temperature and time (e.g., 300°C, 20 minutes) are beneficial for improving the contact characteristics between the Al electrode and the dielectric. However, if the annealing temperature is too high or the time is too long, the interface contact characteristics will be damaged.

[0074] Comparative Example 1

[0075] The storage layer without TiN film doping is grown with only 300 cycles of Si3N4 film, then m=300, x=1, p=n=0. The rest of the contents are the same as in Example 1.

[0076] 1. The impact of TiN-doped storage layer on the device storage window size

[0077] The memory windows of the charge trapping memory prepared in the embodiment and the comparative example at ±10V, ±12V and ±15V operating voltages were tested respectively. The results are shown in FIG. Figure 3 .

[0078] like Figure 3 As shown, when the storage layer Si3N4 film is not doped with TiN dielectric (see Figure 3 a), the device storage window is the smallest, as the storage layer Si3N4 film TiN dielectric doping amount increases (see Figure 3 b-3d), the device storage window increases significantly. Figure 4 Increasing the amount of TiN dielectric doping increases the slope of the device's memory window as it changes with operating voltage, which facilitates the device's multi-valued storage capability. At different operating voltages, the amount of charge stored in the storage layer varies. Therefore, the above memory window comparison demonstrates that doping Si3N4 thin films with TiN dielectric can increase the charge trap density in the storage layer, thereby increasing the device's memory window.

[0079] 2. Influence of TiN-doped storage layer on device fatigue characteristics

[0080] A +10V_1s / -10V_1s periodic rectangular pulse was applied to the device, and the flat-band voltage offset of the device was tested after 1, 10, 100, 1000, and 5000 pulses, respectively, to obtain the device fatigue performance. Figure 5 .

[0081] from Figure 5 It can be seen that the fatigue performance of the device without TiN dielectric doping in the storage layer Si3N4 film is poor (see Figure 5a), after 1000 rectangular pulse operations, the flat band voltage shifts significantly and the storage window is severely reduced. As the amount of TiN dielectric doping increases, the device fatigue performance improves (see Figure 5 b-5d). Especially when the Si3N4 film is doped with TiN dielectric for 11 cycles, after 5000 rectangular pulse operations, the flat band voltage of the device does not shift significantly compared to the initial value, and the memory window has almost no change (see Figure 5 d).

[0082] Therefore, through the above fatigue characteristics analysis, the Si3N4 film grown using N2 plasma has poor quality, more interface states, and poor voltage resistance of the film. After multiple pulse voltage operations, the film is damaged. The fatigue characteristics of the Si3N4 film doped with TiN dielectric become better, and as the amount of doping increases, the fatigue characteristics become better. This is because during the TiN dielectric doping process, the NH3 plasma used for TiN film growth performs a certain degree of nitridation treatment on the interface of the Si3N4 film, which reduces the interface state density, improves the quality of the Si3N4 film, and further improves the voltage resistance of the film, so that it can withstand more voltage operations without damage. Therefore, in the present invention, the quality of the storage layer Si3N4 film and the fatigue characteristics of the device as a whole are improved by the treatment of NH3 plasma during the TiN film doping process.

[0083] 3. Influence of TiN-doped storage layer on device retention characteristics

[0084] The retention characteristics of the charge trapping memory prepared in the embodiment and the comparative example were tested respectively by applying pulse voltages of +10V_1s and -10V_1s to the device, and then measuring its CV curve after 1s, 10s, 100s, 500s, 1000s, 1500s, and 2000s to extract the flat band voltage. The flat band voltage of the device after programming / erasing was plotted over time, and then extrapolated for 10 years to obtain the device retention performance. The results are shown in Figure 6 .

[0085] Depend on Figure 6 It can be seen that the charge trap energy level of Si3N4 film grown using BDEAS silicon source and N2 plasma is low and the charge retention capability is poor. The charge trapping memory prepared with it as the storage layer has poor retention characteristics (see Figure 6 a). The stored charge loses quickly over time. After 10 years, the stored charge is completely leaked, which cannot meet the requirements of a memory. However, after doping the storage layer Si3N4 film with TiN dielectric, the device retention performance is greatly improved (see Figure 6 b-6d). Especially when the TiN doping number reaches 11 cycles, the charge loss after 10 years is only 1.17% (see Figure 6d), greatly improving the reliability of the device.

[0086] Analysis of the reasons:

[0087] On the one hand, this is because the metallic Ti element provides charge traps at deeper energy levels during the TiN doping process, and the Ti element replaces the shallow trap energy levels in the original Si3N4 film, reducing the number of these unstable trap energy levels and better maintaining the charge captured by the storage layer.

[0088] Furthermore, the NH₃ plasma during the TiN doping process nitridates the Si₃N₄ film interface, reducing the interface state density and the shallow trap levels at the Si₃N₄ film interface, making the trapped charge less likely to leak. In summary, TiN doping of Si₃N₄ films grown using a BDEAS silicon source and N₂ plasma significantly improves device retention, further enhancing memory reliability and having a significant impact on actual device production.

[0089] 4. XPS test of storage layer Si3N4 and doped TiN film

[0090] 300 cycles Si3N4 and 300 cycles Si3N4+9 cycles TiN films were deposited on p-Si substrates, and annealed at 800℃ for 60s. Finally, their XPS spectra were tested. The results are shown in Figure 7 .

[0091] Figure 7 The XPS test results confirm that the TiN doping method provided by this patent successfully introduced metallic Ti elements into the Si3N4 film. Figure 7 b and 7e two pictures Si 2p Peak comparison shows that the Si element in the Si3N4 film without TiN doping mainly forms Si-N bonds, with obvious O 1s The Si element in the TiN-doped Si3N4 film mainly forms Si-N bonds, with a content of 94.71%, and no obvious Si-O bond peak appears.

[0092] Therefore, the method of TiN doping Si3N4 film proposed in this patent effectively reduces the oxygen content in Si3N4 film and improves its ability to capture charge as a storage layer, which can also be reflected in the excellent storage performance of the prepared device. Figure 7 fTi 2pPeak spectrum shows that the TiN doping method proposed in this patent successfully introduced the metal Ti element into the Si3N4 film, achieving the purpose of metal doping to regulate the energy level. At the same time, due to the incorporation of metal Ti, more traps and deeper trap energy levels are provided, which explains Figure 3 、 4 The reasons why TiN doping improves the device storage window and retention characteristics in 6.

[0093] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a charge trapping memory with a TiN-doped Si3N4 storage layer, characterized in that: The following steps are involved: S1, cleaning the substrate and then depositing a tunneling layer on the substrate surface; S2, depositing m layers of Si3N4 film and p layers of TiN film on the surface of the tunneling layer, repeating this process x times, and finally depositing n layers of Si3N4 film to obtain a TiN-doped Si3N4 storage layer; Where 25≤m≤50, 25≤n≤50, p=1, 5≤x≤11; S3, depositing a barrier layer on the surface of the storage layer, and then evaporating an Al electrode on the surface of the barrier layer.

2. The method for preparing a charge trapping memory having a TiN-doped Si3N4 storage layer according to claim 1, wherein: Said m=n=25, x=11, p=1.

3. The method for preparing a charge trapping memory with a TiN-doped Si3N4 storage layer according to claim 1, wherein: During the deposition of the storage layer in step S2, the precursors for the growth of the Si3N4 film are bis(diethylamino)silane and N2 plasma, and the precursors for the growth of the TiN film are titanium tetrachloride and NH3 plasma; the growth temperature of the two films is 300°C-400°C, and the gas atmosphere and purge gas are argon.

4. The method for preparing a charge trapping memory having a TiN-doped Si3N4 storage layer according to claim 1, wherein: In step S3, the device on which the three dielectric thin films of the tunneling layer, the storage layer and the barrier layer are deposited is annealed and then an Al electrode is evaporated. The annealing temperature is 750° C.-850° C. and the time is 60-90 seconds.

5. The method for preparing a charge trapping memory having a TiN-doped Si3N4 storage layer according to claim 4, wherein: In step S3, the device after the Al electrode is evaporated is annealed in an annealing furnace at 250° C. to 350° C. for 15 to 25 minutes.

6. The method for preparing a charge trapping memory with a TiN-doped Si3N4 storage layer according to claim 1, wherein: The materials of the tunneling layer and the barrier layer are the same or different, and the materials of the tunneling layer and the barrier layer are selected from one or more combinations of SiO2, Al2O3, HfO2 and ZrO2.

7. The method for preparing a charge trapping memory having a TiN-doped Si3N4 storage layer according to claim 6, wherein: The deposition temperature of the tunneling layer and the barrier layer is 100°C-300°C.

8. The method for preparing a charge trapping memory having a TiN-doped Si3N4 storage layer according to claim 1, wherein: The thickness of the tunneling layer is 2-10 nm.

9. The method for preparing a charge trapping memory having a TiN-doped Si3N4 storage layer according to claim 1, wherein: The thickness of the storage layer is 5-20 nm.

10. The method for preparing a charge trapping memory with a TiN-doped Si3N4 storage layer according to claim 1, wherein: The thickness of the barrier layer is 10-30 nm.

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