A depletion-mode GaN device and its manufacturing method

Abstract

The present invention belongs to the field of semiconductor technology, and specifically discloses a depletion-mode GaN device and a preparation method thereof. The depletion-mode GaN device includes a source electrode, a drain electrode, a gate electrode, a gate structure, a field plate unit, a gate connection component, a field plate connection component, a gate driving resistor, a field plate driving resistor, a first dielectric layer and a second dielectric layer. There are multiple gate structures, and the field plate unit includes multiple field plates; one ends of the multiple gate structures are electrically connected to one end of the gate connection component, and the other end of the gate connection component is electrically connected to one end of the gate driving resistor; one ends of the multiple field plates of the field plate unit are all connected to one end of the field plate connection component, and the other end of the field plate connection component is electrically connected to one end of the field plate driving resistor; the gate driving resistor and the field plate driving resistor are both connected in parallel with the gate electrode. In the depletion-mode GaN device of the present invention, the gate structure and the field plate unit respectively have their own driving circuits, which is convenient for voltage division adjustment.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and particularly relates to a depletion-mode GaN device and a method for manufacturing the same. Background Art

[0002] Cascaded GaN devices are formed by cascading depletion-mode GaN devices with low-voltage MOSs, and have high reliability. Currently, they are widely used in various switching power supplies. However, in cascaded devices, since the gate electrode of the depletion-mode GaN is often directly wire-bonded to the source electrode of the device during packaging, it is not convenient to adjust. As a result, the switching speed of the device can only be adjusted by the gate terminal drive resistance of the low-voltage MOS during application, and the adjustment ability is weak. Therefore, in practical applications of cascaded GaN devices, the problem of too fast switching speed often occurs, which makes it difficult to adjust electromagnetic interference (EMI). Seriously, it will cause waveform oscillation and even device breakdown.

[0003] To solve this problem, the industry has proposed to design a drive resistance at the GaN gate terminal to reduce the switching speed; or design it as a dual parallel circuit, one path is a diode in series with a relatively low resistance, and the other path is a relatively high resistance, to achieve separate adjustment of the GaN turn-on and turn-off speeds. However, high-voltage depletion-mode GaN devices have a gate and multiple field plates, which is equivalent to multiple depletion-mode devices with different thresholds connected in series. The gate electrodes of each device are short-circuited together. When the drive resistance of the GaN device is increased, the capacitance charging and discharging speeds of each series-connected depletion-mode device will be reduced; but due to the differences in the capacitances of each series-connected device, there will be a large difference in the actual switching speed, which will further lead to potential problems such as uneven voltage division among several depletion-mode devices, too high voltage division at the instant of turn-off of the low-voltage MOS device, and large switching losses. Summary of the Invention

[0004] In view of this, in order to overcome the defects of the prior art, the purpose of the present invention is to provide a depletion-mode GaN device and a method for manufacturing the same, by separately designing respective drive circuits for the gate structure and the field plate unit to achieve refined adjustment of the switching speed and turn-off speed, facilitate voltage division adjustment, and improve the reliability of the device.

[0005] To achieve the above purpose, the present invention adopts the following technical solutions:

[0006] A depletion-mode GaN device includes a source electrode, a drain electrode, a gate electrode, a gate structure, a field plate unit, a gate connection component, a field plate connection component, a gate drive resistance, a field plate drive resistance, and a substrate, a stacked structure, a first dielectric layer, and a second dielectric layer arranged in sequence from bottom to top. The gate structure is located in the first dielectric layer, the field plate unit is located in the second dielectric layer, there are multiple gate structures, the field plate unit includes multiple field plates, and the number of field plates in the field plate unit is equal to the number of gate structures;

[0007] One end of each of the plurality of gate structures is electrically connected to one end of the gate connection component, and the other end of the gate connection component is electrically connected to one end of the gate driving resistor; one end of each of the plurality of field plates in the field plate unit is connected to one end of the field plate connection component, and the other end of the field plate connection component is electrically connected to one end of the field plate driving resistor; both the gate driving resistor and the field plate driving resistor are connected in parallel with the gate electrode.

[0008] According to some preferred embodiments of the present invention, the resistance value of the gate driving resistor is less than or equal to the resistance value of the field plate driving resistor.

[0009] According to some preferred embodiments of the present invention, the stacked structure sequentially includes a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a cap layer from bottom to top. Source electrode ohmic metal, drain electrode ohmic metal, first ohmic metal, second ohmic metal, third ohmic metal, and fourth ohmic metal are provided in the barrier layer and the cap layer. The first ohmic metal and the second ohmic metal are respectively located on both sides of the gate driving resistor, and the third ohmic metal and the fourth ohmic metal are respectively located on both sides of the field plate driving resistor.

[0010] According to some preferred embodiments of the present invention, it further includes a fifth ohmic metal and a Schottky metal. The field plate driving resistor includes a first resistor portion and a second resistor portion connected to each other. Both the fifth ohmic metal and the Schottky metal are located in the barrier layer and the cap layer. The fourth ohmic metal is located on a side of the first resistor portion away from the second resistor portion. The third ohmic metal is electrically connected to the fifth ohmic metal or the Schottky metal. The Schottky metal is used to form a diode, and the diode is connected in parallel with the second resistor portion. In some embodiments of the present invention, the first resistor portion and the second resistor portion are connected in series. The Schottky metal is used to form a diode structure, and the diode is connected in parallel with the second resistor portion. Such a setting enables the driving current of the field plate to flow through the second resistor portion of the field plate driving resistor when the depletion-mode GaN device is turned on, and the driving current of the field plate to flow through the diode when the device is turned off, which can make the turn-off speed faster and is more suitable for flyback applications, etc. In addition, in some other embodiments of the present invention, the direction of the diode can be set to be opposite to make the turn-on speed of the device faster and more suitable for high-power half-bridge circuits.

[0011] According to some preferred embodiments of the present invention, it further includes a gate driving loop connection segment and a field plate driving loop connection segment. The source electrode, the drain electrode, the gate driving loop connection segment, and the field plate driving loop connection segment are all located above the second dielectric layer.

[0012] According to some preferred implementation aspects of the present invention, a first metal connection bar and a second metal connection bar are provided in the first dielectric layer and the second dielectric layer. One end of the first metal connection bar is connected to the source electrode, and the other end of the first metal connection bar is ohmically connected to the source electrode. One end of the second metal connection bar is connected to the drain electrode, and the other end of the second metal connection bar is ohmically connected to the drain electrode. In some embodiments of the present invention, the first metal connection bar is electrically connected between the source electrode and the source electrode ohmic metal, and the second metal connection bar is also electrically connected between the drain electrode and the drain electrode ohmic metal.

[0013] According to some preferred implementation aspects of the present invention, the gate connection assembly includes a gate connection head, a gate connection segment, and a plurality of first connection segments. One end of the gate connection segment is connected to the gate connection head, and the plurality of first connection segments are respectively arranged corresponding to the plurality of gate structures. One end of each first connection segment is connected to a corresponding one of the gate structures, and the other end of each first connection segment is connected to the gate connection segment. The gate connection segment and the plurality of first connection segments are used to connect the plurality of gate structures in parallel;

[0014] The field plate connection assembly includes a field plate connection head, a field plate connection segment, and a plurality of second connection segments. One end of the field plate connection segment is connected to the field plate connection head, and the plurality of second connection segments are respectively arranged corresponding to the plurality of field plates in the field plate unit. One end of each second connection segment is connected to a corresponding one of the field plates, and the other end of each second connection segment is connected to the field plate connection segment. The field plate connection segment and the plurality of second connection segments are used to connect the plurality of field plates in the field plate unit in parallel.

[0015] According to some preferred implementation aspects of the present invention, the gate connection head is located in the first dielectric layer. A third metal connection bar and a fourth metal connection bar are provided in the first dielectric layer and the second dielectric layer. One ends of the third metal connection bar and the fourth metal connection bar are both connected to the gate drive circuit connection segment. The other end of the third metal connection bar is connected to the gate connection head, and the other end of the fourth metal connection bar is connected to the first ohmic metal. In some embodiments of the present invention, the third metal connection bar is electrically connected between the gate drive circuit connection segment and the gate connection head, and the fourth metal connection bar is also electrically connected between the gate drive circuit connection segment and the first ohmic metal.

[0016] According to some preferred implementation aspects of the present invention, the field plate connection end is located in the second dielectric layer. A fifth metal connection bar and a sixth metal connection bar are provided in the first dielectric layer and the second dielectric layer. One ends of the fifth metal connection bar and the sixth metal connection bar are both connected to the field plate driving circuit connection segment. The other end of the fifth metal connection bar is connected to the field plate connection end, and the other end of the sixth metal connection bar is connected to the third ohmic metal. In some embodiments of the present invention, the fifth metal connection bar is electrically connected to both the field plate driving circuit connection segment and the field plate connection end, and the sixth metal connection bar is also electrically connected to both the field plate driving circuit connection segment and the third ohmic metal.

[0017] According to some preferred implementation aspects of the present invention, the first ohmic metal is located on the side of the gate driving resistor close to the gate connection end, the third ohmic metal is located on the side of the field plate driving resistor close to the field plate connection end, the first extension segment is provided at one end of the second ohmic metal far from the gate driving resistor, the second extension segment is provided at one end of the fourth ohmic metal far from the field plate driving resistor, and one ends of the first extension segment and the second extension segment are both connected to the gate electrode. In some embodiments of the present invention, by providing the first extension segment and the second extension segment, the second ohmic metal and the fourth ohmic metal are connected in parallel.

[0018] According to some preferred implementation aspects of the present invention, a plurality of field plate units are provided, and multiple layers of the second dielectric layer are provided. One field plate unit is provided in each second dielectric layer; the field plate driving resistor, the field plate connection component, and the field plate driving circuit connection segment are all provided in one-to-one correspondence with the field plate unit.

[0019] According to some preferred implementation aspects of the present invention, the resistance value of the gate driving resistor is less than or equal to the resistance value of the field plate driving resistor corresponding to the field plate unit in the second dielectric layer closest to the first dielectric layer, and the resistance values of the field plate driving resistors corresponding to the respective field plate units in each layer of the second dielectric layer gradually increase in the direction from the second dielectric layer closest to the first dielectric layer to the second dielectric layer farthest from the first dielectric layer.

[0020] The present invention also provides a preparation method of the above depletion-type GaN device, including the following steps:

[0021] Form an active region, a gate driving resistor, and a field plate driving resistor on the stacked structure through photoresist protection; or, form an active region, a gate driving resistor, a field plate driving resistor, and a diode implantation protection region; the setting of the diode implantation protection region is for forming a Schottky metal equivalent to a diode subsequently.

[0022] A source electrode ohmic metal, a drain electrode ohmic metal, a first ohmic metal, a second ohmic metal, a third ohmic metal, and a fourth ohmic metal are formed above the stacked structure; or, a source electrode ohmic metal, a drain electrode ohmic metal, a first ohmic metal, a second ohmic metal, a third ohmic metal, a fourth ohmic metal, a fifth ohmic metal, and a Schottky metal are formed;

[0023] The stacked structure is filled with metal and etched to form a gate structure and a gate connection component;

[0024] A first dielectric layer is deposited above the gate structure, and a field plate and a field plate connection component are formed above the first dielectric layer;

[0025] A second dielectric layer is deposited above the field plate, vias are etched downward from the second dielectric layer and filled with metal to form a first metal connection bar, a second metal connection bar, a third metal connection bar, a fourth metal connection bar, a fifth metal connection bar, and a sixth metal connection bar;

[0026] A source electrode, a drain electrode, a gate drive loop connection segment, and a field plate drive loop connection segment are formed above the second dielectric layer to obtain the depletion-mode GaN device. Among them, the gate drive loop connection segment is used to connect the third metal connection bar and the fourth metal connection bar; the field plate drive loop connection segment is used to connect the fifth metal connection bar and the sixth metal connection bar.

[0027] Due to the adoption of the above technical solutions, compared with the prior art, the beneficial effects of the present invention are as follows: In a depletion-mode GaN device and its manufacturing method of the present invention, one end of a gate drive resistor is electrically connected to the gate structure, and the other end of the gate drive resistor is connected to the gate electrode; and one end of a field plate drive resistor is electrically connected to the field plate in the field plate unit, and the other end of the field plate drive resistor is also connected to the gate electrode, and the gate drive resistor and the field plate drive resistor are both connected in parallel with the gate electrode. Such a structural design is equivalent to designing different drive loops for the gate structure and the field plate unit respectively, which is convenient for voltage division adjustment, so as to facilitate the voltage division control of the low-voltage MOS device to a safe range, while prolonging the turn-on time and shortening the turn-off time, especially suitable for flyback circuits, etc., which is beneficial to improving EMI, and at the same time will not cause high turn-off losses, improving a series of problems caused by too fast switching in practical applications, and effectively improving the reliability of the device. Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0029] Figure 1Schematic top view structure of the depletion-mode GaN device in Embodiment 1 of the present invention;

[0030] Figure 2 is Figure 1 Schematic cross-sectional view along the direction of dashed line A;

[0031] Figure 3 is Figure 1 Schematic cross-sectional view along the direction of dashed line B;

[0032] Figure 4 is Figure 1 Schematic cross-sectional view along the direction of dashed line C;

[0033] Figure 5 is Figure 1 Schematic cross-sectional view along the direction of dashed line D;

[0034] Figure 6 Schematic top view structure of the depletion-mode GaN device in Embodiment 2 of the present invention;

[0035] Figure 7 is Figure 6 Schematic cross-sectional view along the direction of dashed line E;

[0036] Figure 8 Schematic top view structure of the depletion-mode GaN device in Embodiment 3 of the present invention;

[0037] Figure 9 is Figure 8 Schematic cross-sectional view along the direction of dashed line F;

[0038] Figure 10 Equivalent circuit diagram of the depletion-mode GaN device in Embodiment 1 of the present invention;

[0039] Figure 11 Equivalent circuit diagram of the depletion-mode GaN device in Embodiment 2 of the present invention;

[0040] Figure 12 Equivalent circuit diagram of the depletion-mode GaN device in Embodiment 3 of the present invention;

[0041] Figure 13 Graph showing the relationship between the voltage division of each structure and the driving resistance in Embodiment 1 of the present invention;

[0042] Among them, the reference numerals are:

[0043] Substrate - 1, stacked structure - 2, nucleation layer - 3, buffer layer - 4, channel layer - 5, barrier layer - 6, capping layer - 7, first dielectric layer - 8, second dielectric layer - 9, source electrode - 10, gate electrode - 11, gate structure - 12, field plate - 13, gate driving resistor - 14, field plate driving resistor - 15, source electrode ohmic metal - 16, drain electrode ohmic metal - 17, first ohmic metal - 18, second ohmic metal - 19, third ohmic metal - 20, fourth ohmic metal - 21, fifth ohmic metal - 22, Schottky metal - 23, first metal connection bar - 24, third metal connection bar - 25, fourth metal connection bar - 26, fifth metal connection bar - 27, sixth metal connection bar - 28, gate driving loop connection segment - 29, field plate driving loop connection segment - 30, gate connection end - 31, gate connection segment - 32, first connection segment - 33, field plate connection end - 34, field plate connection segment - 35, second connection segment - 36, first extension segment - 37, second extension segment - 38, diode implantation protection region - 39, active region - 40, second metal connection bar - 41, drain electrode - 42, first resistance portion - R1, second resistance portion - R2. Detailed implementation mode

[0044] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0045] The depletion-mode GaN device of the present invention includes a source electrode 10, a drain electrode 42, a gate electrode 11, a gate structure 12, a field plate unit, a gate connection component, a field plate connection component, a gate driving resistor 14, a field plate driving resistor 15, a source electrode ohmic metal 16, a drain electrode ohmic metal 17, a first ohmic metal 18, a second ohmic metal 19, a third ohmic metal 20, a fourth ohmic metal 21, a gate driving loop connection segment 29, a field plate driving loop connection segment 30, a first metal connection strip 24, a second metal connection strip 41, a third metal connection strip 25, a fourth metal connection strip 26, a fifth metal connection strip 27, a sixth metal connection strip 28, and a substrate 1, a stacked structure 2, a first dielectric layer 8, and a second dielectric layer 9 arranged in sequence from bottom to top. Among them, a plurality of gate structures 12 are provided, and the plurality of gate structures 12 are all located in the first dielectric layer 8; the field plate unit is located in the second dielectric layer 9, and the field plate unit includes a plurality of field plates 13, and the number of field plates 13 in the field plate unit is equal to the number of gate structures 12. One ends of the plurality of gate structures 12 are all electrically connected to one end of the gate connection component, and the other end of the gate connection component is electrically connected to one end of the gate driving resistor 14; one ends of the plurality of field plates 13 in the field plate unit are all connected to one end of the field plate connection component, and the other end of the field plate connection component is electrically connected to one end of the field plate driving resistor 15; and the gate driving resistor 14 and the field plate driving resistor 15 are both connected in parallel with the gate electrode 11.

[0046] Further, the stacked structure 2 includes a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6, and a cap layer 7 arranged in sequence from bottom to top. Among them, the source electrode 10, the drain electrode 42, the gate driving loop connection segment 29, and the field plate driving loop connection segment 30 are all located above the second dielectric layer 9, and the source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20, and the fourth ohmic metal 21 are all located in the barrier layer 6 and the cap layer 7; the first ohmic metal 18 and the second ohmic metal 19 are respectively located on both sides of the gate driving resistor 14, and the third ohmic metal 20 and the fourth ohmic metal 21 are respectively located on both sides of the field plate driving resistor 15.

[0047] Furthermore, the gate connection component includes a gate connection end 31, a gate connection segment 32, and a plurality of first connection segments 33. The gate connection end 31 is located in the first dielectric layer 8. One end of the gate connection segment 32 is connected to the gate connection end 31. The plurality of first connection segments 33 are respectively arranged in one-to-one correspondence with the plurality of gate structures 12. One end of each first connection segment 33 is connected to a corresponding gate structure 12, and the other end of each first connection segment 33 is connected to the gate connection segment 32. The gate connection segment 32 and the plurality of first connection segments 33 are used to connect the plurality of gate structures 12 in parallel. The field plate connection component includes a field plate connection end 34, a field plate connection segment 35, and a plurality of second connection segments 36. The field plate connection end 34 is located in the second dielectric layer 9. One end of the field plate connection segment 35 is connected to the field plate connection end 34. The plurality of second connection segments 36 are respectively arranged in one-to-one correspondence with the plurality of field plates 13 in the field plate unit. One end of each second connection segment 36 is connected to a corresponding field plate 13, and the other end of each second connection segment 36 is connected to the field plate connection segment 35. The field plate connection segment 35 and the plurality of second connection segments 36 are used to connect the plurality of field plates 13 in the field plate unit in parallel. The first ohmic metal 18 is located on the side of the gate driving resistor 14 close to the gate connection end 31. The third ohmic metal 20 is located on the side of the field plate driving resistor 15 close to the field plate connection end 34. One end of the second ohmic metal 19 far from the gate driving resistor 14 is provided with a first extension segment 37. One end of the fourth ohmic metal 21 far from the field plate driving resistor 15 is provided with a second extension segment 38. One ends of the first extension segment 37 and the second extension segment 38 are both connected to the gate electrode 11.

[0048] In addition, both the first metal connection bar 24 and the second metal connection bar 41 are located in the first dielectric layer 8 and the second dielectric layer 9. Moreover, the first metal connection bar 24 is located between the source electrode 10 and the source electrode ohmic metal 16. One end of the first metal connection bar 24 is connected to the source electrode 10, and the other end of the first metal connection bar 24 is connected to the source electrode ohmic metal 16. The second metal connection bar 41 is located between the source electrode 10 and the source electrode ohmic metal 16. One end of the second metal connection bar 41 is connected to the drain electrode 42, and the other end of the second metal connection bar 41 is connected to the drain electrode ohmic metal 17. The third metal connection bar 25 and the fourth metal connection bar 26 are also located in the first dielectric layer 8 and the second dielectric layer 9. Furthermore, the third metal connection bar 25 is located between the gate drive circuit connection section 29 and the gate connection end 31. One end of the third metal connection bar 25 is connected to the gate drive circuit connection section 29, and the other end of the third metal connection bar 25 is connected to the gate connection end 31. The fourth metal connection bar 26 is located between the gate drive circuit connection section 29 and the first ohmic metal 18. One end of the fourth metal connection bar 26 is connected to the gate drive circuit connection section 29, and the other end of the fourth metal connection bar 26 is connected to the first ohmic metal 18. The fifth metal connection bar 27 is located in the second dielectric layer 9, and the sixth metal connection bar 28 is located in the first dielectric layer 8 and the second dielectric layer 9. The fifth metal connection bar 27 is located between the field plate drive circuit connection section 30 and the field plate connection end 34. One end of the fifth metal connection bar 27 is connected to the field plate drive circuit connection section 30, and the other end of the fifth metal connection bar 27 is connected to the field plate connection end 34. The sixth metal connection bar 28 is located between the field plate drive circuit connection section 30 and the third ohmic metal 20. One end of the sixth metal connection bar 28 is connected to the gate drive circuit connection section 29, and the other end of the sixth metal connection bar 28 is connected to the third ohmic metal 20.

[0049] In some embodiments of the present invention, the field plate unit can be set to one or more. When the field plate unit is set to multiple, the second dielectric layer 9 is also provided with multiple layers, and one field plate unit is provided in each second dielectric layer 9. The field plate drive resistor 15, the field plate connection assembly, and the field plate drive circuit connection section 30 are all provided in one-to-one correspondence with the field plate unit.

[0050] In some other embodiments of the present invention, regardless of whether one or more field plate units are provided, the depletion-mode GaN device may further include a fifth ohmic metal 22 and a Schottky metal 23. The Schottky metal 23 is used to form a diode structure, and the diode is connected in parallel with the second resistor portion R2. At this time, the field plate driving resistor 15 may be set to include a first resistor portion R1 and a second resistor portion R2 connected to each other. Both the fifth ohmic metal 22 and the Schottky metal 23 are located in the barrier layer 6 and the cap layer 7. The fourth ohmic metal 21 is located on a side of the first resistor portion R1 away from the second resistor portion R2. The third ohmic metal 20 is electrically connected to the fifth ohmic metal 22 or the Schottky metal 23, and the second resistor portion R2 is connected in parallel with the Schottky metal 23.

[0051] Embodiment 1 Device Structure

[0052] As Figures 1 to 5 shown, the depletion-mode GaN device in this embodiment includes a source electrode 10, a drain electrode 42, a gate electrode 11, a gate structure 12, a field plate unit, a gate connection component, a field plate connection component, a gate driving resistor 14, a field plate driving resistor 15, a source electrode ohmic metal 16, a drain electrode ohmic metal 17, a first ohmic metal 18, a second ohmic metal 19, a third ohmic metal 20, a fourth ohmic metal 21, a gate driving loop connection segment 29, a field plate driving loop connection segment 30, a first metal connection bar 24, a second metal connection bar 41, a third metal connection bar 25, a fourth metal connection bar 26, a fifth metal connection bar 27, a sixth metal connection bar 28, and a substrate 1, a stack structure 2, a first dielectric layer 8, and a second dielectric layer 9 sequentially arranged from bottom to top. Among them, a plurality of gate structures 12 are provided, and the plurality of gate structures 12 are all located in the first dielectric layer 8. Two field plate units are provided in this embodiment, and two second dielectric layers 9 are provided. The two field plate units are respectively located in the two second dielectric layers 9. Each field plate unit includes a plurality of field plates 13, and the number of field plates 13 in each field plate unit is equal to the number of gate structures 12. Correspondingly, the field plate driving resistor 15, the field plate connection component, and the field plate driving loop connection segment 30 are all provided in one-to-one correspondence with the field plate unit.

[0053] Furthermore, the stack structure 2 includes a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6, and a cap layer 7 sequentially arranged from bottom to top. The source electrode 10, the drain electrode 42, the gate driving loop connection segment 29, and the field plate driving loop connection segment 30 are all located above the second dielectric layer 9. The source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20, and the fourth ohmic metal 21 are all located in the barrier layer 6 and the cap layer 7, and the first ohmic metal 18 and the second ohmic metal 19 are respectively located on both sides of the gate driving resistor 14. One third ohmic metal 20 and one fourth ohmic metal 21 are respectively provided on both sides of each field plate driving resistor 15.

[0054] Further, the gate connection component includes a gate connection end 31, a gate connection segment 32, and a plurality of first connection segments 33. The gate connection end 31 is located in the first dielectric layer 8. One end of the gate connection segment 32 is connected to the gate connection end 31. The plurality of first connection segments 33 are respectively arranged in one-to-one correspondence with the plurality of gate structures 12, such that one end of each first connection segment 33 is connected to a corresponding gate structure 12, and the other end of each first connection segment 33 is connected to the gate connection segment 32. The gate connection segment 32 and the plurality of first connection segments 33 are used to connect the plurality of gate structures 12 in parallel. Each field plate connection component includes a field plate connection end 34, a field plate connection segment 35, and a plurality of second connection segments 36. A field plate connection end 34 is located in a corresponding layer of the second dielectric layer 9. One end of the field plate connection segment 35 is connected to the field plate connection end 34. The plurality of second connection segments 36 are respectively arranged in one-to-one correspondence with the plurality of field plates 13 in each field plate unit, such that one end of each second connection segment 36 is connected to a corresponding field plate 13, and the other end of each second connection segment 36 is connected to a corresponding field plate connection segment 35 in a field plate unit. The field plate connection segment 35 and the plurality of second connection segments 36 are used to connect the plurality of field plates 13 in the field plate unit in parallel.

[0055] The first ohmic metal 18 is located on a side of the gate driving resistor 14 close to the gate connection end 31. The third ohmic metal 20 is located on a side of the field plate driving resistor 15 close to the field plate connection end 34. One end of the second ohmic metal 19 far from the gate driving resistor 14 is provided with a first extension segment 37. One end of the fourth ohmic metal 21 far from the field plate driving resistor 15 is provided with a second extension segment 38. In this embodiment, two second extension segments 38 are provided in total. One end of the first extension segment 37 and one end of the second extension segment 38 are both connected to the gate electrode 11. In addition, the first metal connection bar 24 and the second metal connection bar 41 in this embodiment both penetrate through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The first metal connection bar 24 is located between the source electrode 10 and the source electrode ohmic metal 16, and one end of the first metal connection bar 24 is connected to the source electrode 10, and the other end of the first metal connection bar 24 is connected to the source electrode ohmic metal 16; the second metal connection bar 41 is located between the drain electrode 42 and the drain electrode ohmic metal 17, and one end of the second metal connection bar 41 is connected to the drain electrode 42, and the other end of the second metal connection bar 41 is connected to the drain electrode ohmic metal 17.

[0056] In this embodiment, both the third metal connection bar 25 and the fourth metal connection bar 26 penetrate through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The third metal connection bar 25 is located between the gate drive circuit connection segment 29 and the gate connection end 31. One end of the third metal connection bar 25 is connected to the gate drive circuit connection segment 29, and the other end of the third metal connection bar 25 is connected to the gate connection end 31. The fourth metal connection bar 26 is located between the gate drive circuit connection segment 29 and the first ohmic metal 18. One end of the fourth metal connection bar 26 is connected to the gate drive circuit connection segment 29, and the other end of the fourth metal connection bar 26 is connected to the first ohmic metal 18. Such an arrangement enables one end of the gate drive resistor 14 to be electrically connected to the gate structure 12, and the other end of the gate drive resistor 14 to be electrically connected to the gate electrode 11 through the first extension segment 37.

[0057] In this embodiment, the arrangement of other structures corresponding to a field plate unit in the second dielectric layer 9 adjacent to the first dielectric layer 8 is as follows: The fifth metal connection bar 27 penetrates through the thickness direction of the two second dielectric layers 9. The fifth metal connection bar 27 is located between a field plate drive circuit connection segment 30 and a corresponding field plate connection end 34. One end of the fifth metal connection bar 27 is connected to the field plate drive circuit connection segment 30, and the other end of the fifth metal connection bar 27 is connected to the field plate connection end 34. The sixth metal connection bar 28 penetrates through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The sixth metal connection bar 28 is located between the same field plate drive circuit connection segment 30 and the third ohmic metal 20. One end of the sixth metal connection bar 28 is connected to the gate drive circuit connection segment 29, and the other end of the sixth metal connection bar 28 is connected to the third ohmic metal 20.

[0058] The arrangement of other structures corresponding to a field plate unit in the second dielectric layer 9 away from the first dielectric layer 8 is as follows: The fifth metal connection bar 27 penetrates through the thickness direction of the second dielectric layer 9 away from the first dielectric layer 8. The fifth metal connection bar 27 is located between another field plate drive circuit connection segment 30 and a corresponding another field plate connection end 34. One end of the fifth metal connection bar 27 is connected to the field plate drive circuit connection segment 30, and the other end of the fifth metal connection bar 27 is connected to the field plate connection end 34. The sixth metal connection bar 28 penetrates through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The sixth metal connection bar 28 is located between the same field plate drive circuit connection segment 30 and the third ohmic metal 20. One end of the sixth metal connection bar 28 is connected to the gate drive circuit connection segment 29, and the other end of the sixth metal connection bar 28 is connected to the third ohmic metal 20. Such an arrangement enables one end of each field plate drive resistor 15 to be electrically connected to the gate structure 12, and the other end of each field plate drive resistor 15 to be electrically connected to the gate electrode 11 through the second extension segment 38.

[0059] Figure 1Schematic top view structure of the depletion-mode GaN device of this embodiment. Let Figure 1 the field plate driving resistor 15 near the gate driving resistor 14 in Figure 1 be the first field plate driving resistor 15, and the field plate driving resistor 15 far from the gate driving resistor 14 in Figure 1 be the second field plate driving resistor 15. Then, in this embodiment, the gate driving resistor 14 is less than or equal to the first field plate driving resistor 15, and the first field plate driving resistor 15 is less than or equal to the second field plate driving resistor 15. Among them, the gate driving resistor 14 is greater than or equal to 0.1 Ω, preferably 0.1 - 5 Ω, and the second field plate driving resistor 15 is less than or equal to 1000 Ω, preferably 10 - 40 Ω.

[0060] As Figure 1 and Figure 10 shown, through the structural design of the depletion-mode GaN device in this embodiment, the gate structure 12 and the two field plate units respectively have their own different driving circuits, which is convenient for voltage division adjustment, can realize the voltage division control of the low-voltage MOS device to the safe range, and at the same time extend the turn-on time of the device and shorten the turn-off time; it is especially suitable for flyback circuits, etc., which is beneficial to improving EMI and will not cause high turn-off losses at the same time.

[0061] Perform double-pulse measurement simulation calculations on each structure in the depletion-mode GaN device of this embodiment, and analyze the voltage division of each structure. As Figure 13 shown, it is a graph of the voltage division corresponding to each field plate 13 in the gate structure 12 and the two field plate units versus the driving resistor. It can be seen from Figure 13 that in this embodiment, even if the gate structure 12 and the corresponding field plates 13 in the two field plate units adopt the same driving resistor, the variation rules of the voltage division of each structure and the driving resistor all show a more consistent corresponding relationship (linear relationship), rather than being irregular, which is beneficial to the voltage division adjustment of each structure in the depletion-mode GaN device.

[0062] In some other embodiments of the present invention, conventionally, the number of field plate units can also be set to one, three, or four. The numbers of the second dielectric layer 9, the field plate driving resistor 15, the field plate connection component, and the field plate driving loop connection segment 30 are all the same as the number of field plate units. In addition, the resistance value of the gate driving resistor 14 is less than or equal to the resistance value of the field plate driving resistor 15 corresponding to the field plate unit in the layer of the second dielectric layer 9 closest to the first dielectric layer 8. And, the resistance values of the field plate driving resistors 15 corresponding to the respective field plate units in each layer of the second dielectric layer 9 gradually increase from the layer of the second dielectric layer 9 closest to the first dielectric layer 8 to the layer of the second dielectric layer 9 far from the first dielectric layer 8. And compared with two field plate units, the introduction of four field plate units is more beneficial to the voltage division optimization of the device and improves the breakdown voltage capability.

[0063] Embodiment 2 Device Structure

[0064] As Figure 6 and Figure 7 shown, the depletion-mode GaN device in this embodiment includes a source electrode 10, a drain electrode 42, a gate electrode 11, a gate structure 12, a field plate unit, a gate connection component, a field plate connection component, a gate driving resistor 14, a field plate driving resistor 15, a source electrode ohmic metal 16, a drain electrode ohmic metal 17, a first ohmic metal 18, a second ohmic metal 19, a third ohmic metal 20, a fourth ohmic metal 21, a fifth ohmic metal 22, a Schottky metal 23, a gate driving loop connection segment 29, a field plate driving loop connection segment 30, a first metal connection bar 24, a second metal connection bar 41, a third metal connection bar 25, a fourth metal connection bar 26, a fifth metal connection bar 27, a sixth metal connection bar 28, and a substrate 1, a stacked structure 2, a first dielectric layer 8, and a second dielectric layer 9 arranged in sequence from bottom to top. Among them, a plurality of gate structures 12 are provided, and the plurality of gate structures 12 are all located in the first dielectric layer 8; two field plate units are provided in this embodiment, and the second dielectric layer 9 is provided with two layers, and the two field plate units are respectively located in the two second dielectric layers 9; each field plate unit includes a plurality of field plates 13, and the number of field plates 13 in each field plate unit is equal to the number of gate structures 12. Correspondingly, the field plate driving resistor 15, the field plate connection component, and the field plate driving loop connection segment 30 are all arranged in one-to-one correspondence with the field plate unit.

[0065] Furthermore, the stacked structure 2 includes a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6, and a cap layer 7 arranged in sequence from bottom to top; the source electrode 10, the drain electrode 42, the gate driving loop connection segment 29, and the field plate driving loop connection segment 30 are all located above the second dielectric layer 9. The source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20, the fourth ohmic metal 21, the fifth ohmic metal 22, and the Schottky metal 23 are all located in the barrier layer 6 and the cap layer 7, and the first ohmic metal 18 and the second ohmic metal 19 are respectively located on both sides of the gate driving resistor 14, and one third ohmic metal 20 and one fourth ohmic metal 21 are respectively arranged on both sides of each field plate driving resistor 15. Each field plate driving resistor 15 in this embodiment includes a first resistor portion R1 and a second resistor portion R2 connected to each other, the fourth ohmic metal 21 is located on the side of the first resistor portion R1 away from the second resistor portion R2, the third ohmic metal 20 is electrically connected to the fifth ohmic metal 22, and the second resistor portion R2 is connected in parallel with the Schottky metal 23.

[0066] Further, the gate connection component includes a gate connection end 31, a gate connection segment 32, and a plurality of first connection segments 33. The gate connection end 31 is located in the first dielectric layer 8. One end of the gate connection segment 32 is connected to the gate connection end 31. The plurality of first connection segments 33 are respectively arranged in one-to-one correspondence with the plurality of gate structures 12, so that one end of each first connection segment 33 is connected to a corresponding gate structure 12, and the other end of each first connection segment 33 is connected to the gate connection segment 32. The gate connection segment 32 and the plurality of first connection segments 33 are used to connect the plurality of gate structures 12 in parallel. Each field plate connection component includes a field plate connection end 34, a field plate connection segment 35, and a plurality of second connection segments 36. A field plate connection end 34 is located in a corresponding layer of the second dielectric layer 9. One end of the field plate connection segment 35 is connected to the field plate connection end 34. The plurality of second connection segments 36 are respectively arranged in one-to-one correspondence with the plurality of field plates 13 in each field plate unit, so that one end of each second connection segment 36 is connected to a corresponding field plate 13, and the other end of each second connection segment 36 is connected to a corresponding field plate connection segment 35 in a field plate unit. The field plate connection segment 35 and the plurality of second connection segments 36 are used to connect the plurality of field plates 13 in the field plate unit in parallel.

[0067] The first ohmic metal 18 is located on a side of the gate driving resistor 14 close to the gate connection end 31. The third ohmic metal 20 is located on a side of the field plate driving resistor 15 close to the field plate connection end 34. One end of the second ohmic metal 19 far from the gate driving resistor 14 is provided with a first extension segment 37. One end of the fourth ohmic metal 21 far from the field plate driving resistor 15 is provided with a second extension segment 38. In this embodiment, two second extension segments 38 are provided in total. One ends of the first extension segment 37 and the second extension segment 38 are both connected to the gate electrode 11. In addition, the first metal connection strip 24 and the second metal connection strip 41 in this embodiment both penetrate through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The first metal connection strip 24 is located between the source electrode 10 and the source electrode ohmic metal 16, and one end of the first metal connection strip 24 is connected to the source electrode 10, and the other end of the first metal connection strip 24 is connected to the source electrode ohmic metal 16; the second metal connection strip 41 is located between the drain electrode 42 and the drain electrode ohmic metal 17, and one end of the second metal connection strip 41 is connected to the drain electrode 42, and the other end of the second metal connection strip 41 is connected to the drain electrode ohmic metal 17.

[0068] In this embodiment, both the third metal connecting bar 25 and the fourth metal connecting bar 26 penetrate through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The third metal connecting bar 25 is located between the gate driving circuit connection segment 29 and the gate connection end 31. One end of the third metal connecting bar 25 is connected to the gate driving circuit connection segment 29, and the other end of the third metal connecting bar 25 is connected to the gate connection end 31. The fourth metal connecting bar 26 is located between the gate driving circuit connection segment 29 and the first ohmic metal 18. One end of the fourth metal connecting bar 26 is connected to the gate driving circuit connection segment 29, and the other end of the fourth metal connecting bar 26 is connected to the first ohmic metal 18. Such an arrangement enables one end of the gate driving resistor 14 to be electrically connected to the gate structure 12, and the other end of the gate driving resistor 14 to be electrically connected to the gate electrode 11 through the first extension segment 37.

[0069] In this embodiment, the arrangement of other structures corresponding to a field plate unit in a layer of the second dielectric layer 9 close to the first dielectric layer 8 is as follows: The fifth metal connecting bar 27 penetrates through the thickness direction of the two layers of the second dielectric layer 9. The fifth metal connecting bar 27 is located between a field plate driving circuit connection segment 30 and a corresponding field plate connection end 34. One end of the fifth metal connecting bar 27 is connected to the field plate driving circuit connection segment 30, and the other end of the fifth metal connecting bar 27 is connected to the field plate connection end 34. The sixth metal connecting bar 28 penetrates through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The sixth metal connecting bar 28 is located between the same field plate driving circuit connection segment 30 and the third ohmic metal 20. One end of the sixth metal connecting bar 28 is connected to the gate driving circuit connection segment 29, and the other end of the sixth metal connecting bar 28 is connected to the third ohmic metal 20.

[0070] The arrangement of other structures corresponding to a field plate unit in a layer of the second dielectric layer 9 far from the first dielectric layer 8 is as follows: The fifth metal connecting bar 27 penetrates through the thickness direction of the layer of the second dielectric layer 9 far from the first dielectric layer 8. The fifth metal connecting bar 27 is located between another field plate driving circuit connection segment 30 and a corresponding another field plate connection end 34. One end of the fifth metal connecting bar 27 is connected to the field plate driving circuit connection segment 30, and the other end of the fifth metal connecting bar 27 is connected to the field plate connection end 34. The sixth metal connecting bar 28 penetrates through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The sixth metal connecting bar 28 is located between the same field plate driving circuit connection segment 30 and the third ohmic metal 20. One end of the sixth metal connecting bar 28 is connected to the gate driving circuit connection segment 29, and the other end of the sixth metal connecting bar 28 is connected to the third ohmic metal 20. Such an arrangement enables one end of each field plate driving resistor 15 to be electrically connected to the gate structure 12, and the other end of each field plate driving resistor 15 to be electrically connected to the gate electrode 11 through the second extension segment 38.

[0071] Figure 6Schematic top view structure of the depletion-mode GaN device of this embodiment. Let Figure 6 the field plate driving resistor 15 close to the gate driving resistor 14 in Figure 6 be the first field plate driving resistor 15, and the field plate driving resistor 15 far from the gate driving resistor 14 in

[0072] be the second field plate driving resistor 15. Then, in this embodiment, the gate driving resistor 14 is less than or equal to the first field plate driving resistor 15, and the first field plate driving resistor 15 is less than or equal to the second field plate driving resistor 15. Figure 6 and Figure 11 As shown in

[0073] Example 3 Device Structure

[0074] As shown in Figure 8 and Figure 9As shown, the depletion-mode GaN device in this embodiment is different from that in Embodiment 2 in that: the direction of the diode in this embodiment is opposite to that of the diode in Embodiment 2. Specifically, in this embodiment, the depletion-mode GaN device includes a source electrode 10, a drain electrode 42, a gate electrode 11, a gate structure 12, a field plate unit, a gate connection component, a field plate connection component, a gate driving resistor 14, a field plate driving resistor 15, a source electrode ohmic metal 16, a drain electrode ohmic metal 17, a first ohmic metal 18, a second ohmic metal 19, a third ohmic metal 20, a fourth ohmic metal 21, a fifth ohmic metal 22, a Schottky metal 23, a gate driving loop connection segment 29, a field plate driving loop connection segment 30, a first metal connection strip 24, a second metal connection strip 41, a third metal connection strip 25, a fourth metal connection strip 26, a fifth metal connection strip 27, a sixth metal connection strip 28, and a substrate 1, a stack structure 2, a first dielectric layer 8, and a second dielectric layer 9 arranged in sequence from bottom to top. Among them, a plurality of gate structures 12 are provided, and the plurality of gate structures 12 are all located in the first dielectric layer 8; two field plate units are provided in this embodiment, and the second dielectric layer 9 is provided with two layers, and the two field plate units are respectively located in the two second dielectric layers 9; each field plate unit includes a plurality of field plates 13, and the number of field plates 13 in each field plate unit is equal to the number of gate structures 12. Correspondingly, the field plate driving resistor 15, the field plate connection component, and the field plate driving loop connection segment 30 are all arranged in one-to-one correspondence with the field plate unit.

[0075] Furthermore, the stack structure 2 includes a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6, and a cap layer 7 arranged in sequence from bottom to top; the source electrode 10, the drain electrode 42, the gate driving loop connection segment 29, and the field plate driving loop connection segment 30 are all located above the second dielectric layer 9. The source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20, the fourth ohmic metal 21, the fifth ohmic metal 22, and the Schottky metal 23 are all located in the barrier layer 6 and the cap layer 7, and the first ohmic metal 18 and the second ohmic metal 19 are respectively located on both sides of the gate driving resistor 14, and a third ohmic metal 20 and a fourth ohmic metal 21 are respectively arranged on both sides of each field plate driving resistor 15. Each field plate driving resistor 15 in this embodiment includes a first resistor portion R1 and a second resistor portion R2 connected to each other, the fourth ohmic metal 21 is located on the side of the first resistor portion R1 away from the second resistor portion R2, the third ohmic metal 20 is electrically connected to the Schottky metal 23, and the second resistor portion R2 is connected in parallel with the Schottky metal 23. The positions of the fifth ohmic metal 22 and the Schottky metal 23 in this embodiment are opposite to the positions of the fifth ohmic metal 22 and the Schottky metal 23 in Embodiment 2.

[0076] Further, the gate connection component includes a gate connection end 31, a gate connection segment 32, and a plurality of first connection segments 33. The gate connection end 31 is located in the first dielectric layer 8. One end of the gate connection segment 32 is connected to the gate connection end 31. The plurality of first connection segments 33 are respectively arranged in one-to-one correspondence with the plurality of gate structures 12, such that one end of each first connection segment 33 is connected to a corresponding gate structure 12, and the other end of each first connection segment 33 is connected to the gate connection segment 32. The gate connection segment 32 and the plurality of first connection segments 33 are used to connect the plurality of gate structures 12 in parallel. Each field plate connection component includes a field plate connection end 34, a field plate connection segment 35, and a plurality of second connection segments 36. A field plate connection end 34 is located in a corresponding layer of the second dielectric layer 9. One end of the field plate connection segment 35 is connected to the field plate connection end 34. The plurality of second connection segments 36 are respectively arranged in one-to-one correspondence with the plurality of field plates 13 in each field plate unit, such that one end of each second connection segment 36 is connected to a corresponding field plate 13, and the other end of each second connection segment 36 is connected to a corresponding field plate connection segment 35 in a field plate unit. The field plate connection segment 35 and the plurality of second connection segments 36 are used to connect the plurality of field plates 13 in the field plate unit in parallel.

[0077] The first ohmic metal 18 is located on the side of the gate driving resistor 14 close to the gate connection end 31. The third ohmic metal 20 is located on the side of the field plate driving resistor 15 close to the field plate connection end 34. One end of the second ohmic metal 19 far from the gate driving resistor 14 is provided with a first extension segment 37. One end of the fourth ohmic metal 21 far from the field plate driving resistor 15 is provided with a second extension segment 38. In this embodiment, two second extension segments 38 are provided in total. One ends of the first extension segment 37 and the second extension segment 38 are both connected to the gate electrode 11. In addition, the first metal connection bar 24 and the second metal connection bar 41 in this embodiment both penetrate through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The first metal connection bar 24 is located between the source electrode 10 and the source electrode ohmic metal 16, and one end of the first metal connection bar 24 is connected to the source electrode 10, and the other end of the first metal connection bar 24 is connected to the source electrode ohmic metal 16; the second metal connection bar 41 is located between the drain electrode 42 and the drain electrode ohmic metal 17, and one end of the second metal connection bar 41 is connected to the drain electrode 42, and the other end of the second metal connection bar 41 is connected to the drain electrode ohmic metal 17.

[0078] In this embodiment, both the third metal connection bar 25 and the fourth metal connection bar 26 penetrate through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The third metal connection bar 25 is located between the gate driving circuit connection section 29 and the gate connection end 31. One end of the third metal connection bar 25 is connected to the gate driving circuit connection section 29, and the other end of the third metal connection bar 25 is connected to the gate connection end 31. The fourth metal connection bar 26 is located between the gate driving circuit connection section 29 and the first ohmic metal 18. One end of the fourth metal connection bar 26 is connected to the gate driving circuit connection section 29, and the other end of the fourth metal connection bar 26 is connected to the first ohmic metal 18. Such an arrangement enables one end of the gate driving resistor 14 to be electrically connected to the gate structure 12, and the other end of the gate driving resistor 14 to be electrically connected to the gate electrode 11 through the first extension section 37.

[0079] In this embodiment, the arrangement of other structures corresponding to a field plate unit in the second dielectric layer 9 adjacent to the first dielectric layer 8 is as follows: The fifth metal connection bar 27 penetrates through the thickness direction of the two second dielectric layers 9. The fifth metal connection bar 27 is located between a field plate driving circuit connection section 30 and a corresponding field plate connection end 34. One end of the fifth metal connection bar 27 is connected to the field plate driving circuit connection section 30, and the other end of the fifth metal connection bar 27 is connected to the field plate connection end 34. The sixth metal connection bar 28 penetrates through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The sixth metal connection bar 28 is located between the same field plate driving circuit connection section 30 and the third ohmic metal 20. One end of the sixth metal connection bar 28 is connected to the gate driving circuit connection section 29, and the other end of the sixth metal connection bar 28 is connected to the third ohmic metal 20.

[0080] The arrangement of other structures corresponding to a field plate unit in the second dielectric layer 9 far from the first dielectric layer 8 is as follows: The fifth metal connection bar 27 penetrates through the thickness direction of the second dielectric layer 9 far from the first dielectric layer 8. The fifth metal connection bar 27 is located between another field plate driving circuit connection section 30 and a corresponding another field plate connection end 34. One end of the fifth metal connection bar 27 is connected to the field plate driving circuit connection section 30, and the other end of the fifth metal connection bar 27 is connected to the field plate connection end 34. The sixth metal connection bar 28 penetrates through the thickness directions of the first dielectric layer 8 and the second dielectric layer 9. The sixth metal connection bar 28 is located between the same field plate driving circuit connection section 30 and the third ohmic metal 20. One end of the sixth metal connection bar 28 is connected to the gate driving circuit connection section 29, and the other end of the sixth metal connection bar 28 is connected to the third ohmic metal 20. Such an arrangement enables one end of each field plate driving resistor 15 to be electrically connected to the gate structure 12, and the other end of each field plate driving resistor 15 to be electrically connected to the gate electrode 11 through the second extension section 38.

[0081] Figure 8The top view structural schematic diagram of the depletion-mode GaN device in this embodiment is shown. Let Figure 8 the field plate driving resistor 15 near the gate driving resistor 14 in Figure 8 be the first field plate driving resistor 15, and the field plate driving resistor 15 far from the gate driving resistor 14 in Figure 8 be the second field plate driving resistor 15. Then, in this embodiment, the gate driving resistor 14 is less than or equal to the first field plate driving resistor 15, and the first field plate driving resistor 15 is less than or equal to the second field plate driving resistor 15.

[0082] As Figure 8 and Figure 12 shown, the first resistor portion R1 and the second resistor portion R2 of each field plate driving resistor 15 in this embodiment are connected in series. The setting of the Schottky metal 23 is equivalent to introducing a diode, and the diode is connected in parallel with the second resistor portion R2. Through the structural design of the depletion-mode GaN device in this embodiment, the gate structure 12 and the two field plate units respectively have their own different driving circuits, which is convenient for voltage division adjustment, can realize the voltage division control of the low-voltage MOS device to the safe range, and at the same time extend the turn-on time of the device and shorten the turn-off time; since the direction of the diode in this embodiment is opposite to that in Embodiment 2, when the GaN device is turned on, the driving current of the corresponding field plate 13 in each field plate unit flows through the diode, and when it is turned off, the driving current flows through the second resistor portion R2, which is beneficial to making the turn-on speed faster and is more suitable for high-power half-bridge circuits.

[0083] Embodiment 4 Preparation Method

[0084] This embodiment provides a preparation method for preparing the depletion-mode GaN device in the above Embodiment 1, which specifically includes the following steps:

[0085] Step 1: Perform nitride epitaxial growth on the substrate 1 to sequentially form a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6, and a cap layer 7. The materials include group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, and SiN. The nucleation layer 3, the buffer layer 4, the channel layer 5, the barrier layer 6, and the cap layer 7 constitute a stacked structure 2, thereby forming a complete semiconductor epitaxial layer structure and being able to form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 5 and the barrier layer 6 to generate a conductive channel.

[0086] The substrate 1 is one or a combination of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium, or any other material capable of growing group III nitride materials.

[0087] Step 2: Through photoresist protection, perform patterning on the top of the capping layer 7 and implant ionic materials to disrupt the two-dimensional electron gas to form isolation regions, and protect the non-implanted regions as the continuous region chip active region 40 with the source electrode 10, drain electrode 42, and gate structure 12, and form the gate drive resistor 14 and two field plate drive resistors 15.

[0088] Step 3: On the top of the capping layer 7, perform patterning etching to form the first ohmic hole and the second ohmic hole. At the same time, perform patterning etching on both sides of the gate drive resistor 14 to form the third ohmic hole and the fourth ohmic hole, and perform patterning etching on both sides of each field plate drive resistor 15 to form the fifth ohmic hole and the sixth ohmic hole.

[0089] Step 4: Fill the first ohmic hole, the second ohmic hole, the third ohmic hole, the fourth ohmic hole, the fifth ohmic hole, and the sixth ohmic hole with metal to respectively form the source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18 and the second ohmic metal 19 on both sides of the gate drive resistor 14 (a first extension section 37 is simultaneously formed on the side of the second ohmic metal 19 away from the first ohmic metal 18), the third ohmic metal 20 and the fourth ohmic metal 21 on both sides of each field plate drive resistor 15 (a second extension section 38 is simultaneously formed on the side of the fourth ohmic metal 21 away from the third ohmic metal 20), and perform annealing treatment. At this time, the source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20, and the fourth ohmic metal 21 respectively form ohmic contacts with the epitaxial materials below them. Among them, the second ohmic metal 19 and the two fourth ohmic metals 21 are connected in parallel through the first extension section 37 and the second extension section 38 to form the gate electrode 11. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu.

[0090] Step 5: Fill the top of the capping layer 7 with metal and etch to form the gate structure 12. Among them, multiple gate structures 12 are connected in parallel. Then deposit on the top of the gate structure 12 a combination including one or more of SiN, SiO 2 、SiON、Al 2 O 3 to form the first dielectric layer 8.

[0091] Step 6: Fill the top of the first dielectric layer 8 with metal and etch to form the first field plate unit and the field plate connection component. At the same time, multiple field plates 13 of this field plate unit are connected in parallel; then deposit on the top of the first field plate unit a combination including one or more of SiN, SiO 2 、SiON、Al 2 O 3 to form the first layer of the second dielectric layer 9.

[0092] Step 7: Fill the metal above the second dielectric layer 9 of the first layer, and etch to form the second field plate unit and the field plate connection component. At the same time, a plurality of field plates 13 of this field plate unit are connected in parallel; then deposit on the top of the second field plate unit a material including one or more combinations of SiN, SiO 2 , SiON, Al 2 O 3 to form the second dielectric layer 9 of the second layer.

[0093] Step 8: Etch downward from the second dielectric layer 9 of the second layer to above the source electrode ohmic metal 16 to form the first via hole and the second via hole. The first via hole and the second via hole penetrate the first dielectric layer 8 and the two second dielectric layers 9; etch downward from the second dielectric layer 9 of the second layer to the gate connection end 31 to form the third via hole, and etch downward from the second dielectric layer 9 of the second layer to the first ohmic metal 18 to form the fourth via hole. The third via hole and the fourth via hole penetrate the first dielectric layer 8 and the two second dielectric layers 9; etch downward from the second dielectric layer 9 of the second layer to the field plate connection end 34 in the field plate connection component connected to the first field plate unit to form a fifth via hole, and etch downward from the second dielectric layer 9 of the second layer to the third ohmic metal 20 to form a sixth via hole. Among them, the fifth via hole penetrates the two second dielectric layers 9, and the sixth via hole penetrates the first dielectric layer 8 and the two second dielectric layers 9; etch downward from the second dielectric layer 9 of the second layer to the field plate connection end 34 in the field plate connection component connected to the second field plate unit to form another fifth via hole, and etch downward from the second dielectric layer 9 of the second layer to the third ohmic metal 20 to form another sixth via hole. Among them, the fifth via hole here penetrates one second dielectric layer 9 away from the first dielectric layer 8, and the sixth via hole penetrates the first dielectric layer 8 and the two second dielectric layers 9.

[0094] Step 9: Fill the metal in the first via hole, the second via hole, the third via hole, the fourth via hole, the fifth via hole and the sixth via hole to form the first metal connection bar 24, the second metal connection bar 41, the third metal connection bar 25, the fourth metal connection bar 26, the fifth metal connection bar 27 and the sixth metal connection bar 28 respectively.

[0095] Step 10: Fill the metal above the second dielectric layer 9 of the second layer and etch to form the source electrode 10, the drain electrode 42, the gate drive circuit connection segment 29 and two field plate drive circuit connection segments 30. Among them, the source electrode 10 is electrically connected to the first metal connection bar 24, the drain electrode 42 is electrically connected to the second metal connection bar 41, the gate drive circuit connection segment 29 is electrically connected to the third metal connection bar 25 and the fourth metal connection bar 26 to form the gate drive circuit. Each field plate drive circuit connection segment 30 is respectively electrically connected to the corresponding fifth metal connection bar 27 and the sixth metal connection bar 28 to form the field plate drive circuit of each field plate unit, and finally a depletion-mode GaN device is obtained.

[0096] Example 5 Preparation Method

[0097] This example provides a preparation method for preparing the depletion-type GaN device in Example 2 above, specifically including the following steps:

[0098] Step 1: Perform nitride epitaxial growth on the substrate 1 to sequentially form a nucleation layer 3, a buffer layer 4, a channel layer 5, a barrier layer 6, and a cap layer 7. The materials include group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, SiN, etc. The nucleation layer 3, the buffer layer 4, the channel layer 5, the barrier layer 6, and the cap layer 7 constitute a stacked structure 2, thereby forming a complete semiconductor epitaxial layer structure, and a high-concentration two-dimensional electron gas can be formed at the heterojunction interface between the channel layer 5 and the barrier layer 6 to generate a conductive channel.

[0099] The substrate 1 is one or a combination of silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium, or any other material capable of growing group III nitride materials.

[0100] Step 2: Through photoresist protection, perform patterning and ion material injection above the cap layer 7 to destroy the two-dimensional electron gas to form an isolation region, and protect the non-injected region as the continuous region chip active region 40 with a source electrode 10, a drain electrode 42, and a gate structure 12, and form a gate drive resistor 14, two field plate drive resistors 15, and a diode injection protection region 39 (to facilitate the subsequent formation of a diode).

[0101] Step 3: Above the cap layer 7, perform patterned etching to form a first ohmic hole and a second ohmic hole. At the same time, perform patterned etching on both sides of the gate drive resistor 14 to form a third ohmic hole and a fourth ohmic hole, perform patterned etching on both sides of each field plate drive resistor 15 to form a fifth ohmic hole and a sixth ohmic hole, and perform patterned etching on both sides of the diode injection protection region 39 to form a seventh ohmic hole and a filling hole.

[0102] Step 4: Fill the first ohmic hole, the second ohmic hole, the third ohmic hole, the fourth ohmic hole, the fifth ohmic hole, the sixth ohmic hole, and the seventh ohmic hole with metal to form the source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18 and the second ohmic metal 19 on both sides of the gate driving resistor 14 (a first extension section 37 is formed simultaneously on the side of the second ohmic metal 19 away from the first ohmic metal 18), the third ohmic metal 20 and the fourth ohmic metal 21 on both sides of each field plate driving resistor 15 (a second extension section 38 is formed simultaneously on the side of the fourth ohmic metal 21 away from the third ohmic metal 20), and the fifth ohmic metal 22 on one side of the diode implantation protection area 39, and then perform annealing treatment. At this time, the source electrode ohmic metal 16, the drain electrode ohmic metal 17, the first ohmic metal 18, the second ohmic metal 19, the third ohmic metal 20, the fourth ohmic metal 21, and the fifth ohmic metal 22 respectively form ohmic contacts with the epitaxial material below them. Further fill the filling holes with metal to form the Schottky metal 23 without annealing to form Schottky contacts. Among them, the second ohmic metal 19 and the two fourth ohmic metals 21 are connected in parallel through the first extension section 37 and the second extension section 38 to form the gate electrode 11. The metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu.

[0103] Step 5: Fill the metal above the capping layer 7 and etch to form the gate structure 12. Among them, multiple gate structures 12 are connected in parallel. Then deposit a material including one or more combinations of SiN, SiO 2 , SiON, Al 2 O 3 above the gate structure 12 to form the first dielectric layer 8.

[0104] Step 6: Fill the metal above the first dielectric layer 8 and etch to form the first field plate unit and the field plate connection component. At the same time, multiple field plates 13 of this field plate unit are connected in parallel; then deposit a material including one or more combinations of SiN, SiO 2 , SiON, Al 2 O 3 above the first field plate unit to form the first layer of the second dielectric layer 9.

[0105] Step 7: Fill the metal above the first layer of the second dielectric layer 9 and etch to form the second field plate unit and the field plate connection component. At the same time, multiple field plates 13 of this field plate unit are connected in parallel; then deposit a material including one or more combinations of SiN, SiO 2 , SiON, Al 2 O 3 above the second field plate unit to form the second layer of the second dielectric layer 9.

[0106] Step 8: Etch downward from the second second dielectric layer 9 to above the source electrode ohmic metal 16 to form a first through-hole and a second through-hole, and the first through-hole and the second through-hole penetrate through the first dielectric layer 8 and the two second dielectric layers 9; etch downward from the second second dielectric layer 9 to the gate connection end 31 to form a third through-hole, and etch downward from the second second dielectric layer 9 to the first ohmic metal 18 to form a fourth through-hole, and the third through-hole and the fourth through-hole penetrate through the first dielectric layer 8 and the two second dielectric layers 9; etch downward from the second second dielectric layer 9 to the field plate connection end 34 in the field plate connection assembly connected to the first field plate unit to form a fifth through-hole, and etch downward from the second second dielectric layer 9 to the third ohmic metal 20 to form a sixth through-hole, wherein the fifth through-hole penetrates through the two second dielectric layers 9, and the sixth through-hole penetrates through the first dielectric layer 8 and the two second dielectric layers 9; etch downward from the second second dielectric layer 9 to the field plate connection end 34 in the field plate connection assembly connected to the second field plate unit to form another fifth through-hole, and etch downward from the second second dielectric layer 9 to the third ohmic metal 20 to form another sixth through-hole, wherein the fifth through-hole here penetrates through one second dielectric layer 9 away from the first dielectric layer 8, and the sixth through-hole penetrates through the first dielectric layer 8 and the two second dielectric layers 9.

[0107] Step 9: Fill the first through-hole, the second through-hole, the third through-hole, the fourth through-hole, the fifth through-hole and the sixth through-hole with metal to respectively form a first metal connection bar 24, a second metal connection bar 41, a third metal connection bar 25, a fourth metal connection bar 26, a fifth metal connection bar 27 and a sixth metal connection bar 28.

[0108] Step 10: Fill the metal above the second second dielectric layer 9 and etch to form a source electrode 10, a drain electrode 42, a gate drive circuit connection segment 29 and two field plate drive circuit connection segments 30, wherein the source electrode 10 is electrically connected to the first metal connection bar 24, the drain electrode 42 is electrically connected to the second metal connection bar 41, the gate drive circuit connection segment 29 is electrically connected to the third metal connection bar 25 and the fourth metal connection bar 26 to form a gate drive circuit, and each field plate drive circuit connection segment 30 is respectively electrically connected to the corresponding fifth metal connection bar 27 and the sixth metal connection bar 28 to form a field plate drive circuit of each field plate unit, and finally a depletion-mode GaN device is obtained.

[0109] For the depletion-mode GaN device of the present invention, by respectively designing different drive circuits for the gate structure 12 and the field plate unit, it is convenient for voltage division adjustment, which is beneficial to realizing the voltage division control of the low-voltage MOS device to the safe range, while prolonging the turn-on time, shortening the turn-off time, and at the same time not causing high turn-off loss, and can improve a series of problems caused by too fast switching in practical applications, and effectively improve the reliability of the device.

[0110] The above embodiments of the present invention are only for illustrating the technical concept and features of the present invention, and the purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. It is not intended to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims

1. A depletion-mode GaN device, characterized in that: The invention comprises a source electrode, a drain electrode, a gate electrode, a gate structure, a field plate unit, a gate connection component, a field plate connection component, a gate driving resistor, a field plate driving resistor, and a substrate, a stacked structure, a first dielectric layer, and a second dielectric layer arranged in sequence from bottom to top, wherein the gate structure is located in the first dielectric layer, the field plate unit is located in the second dielectric layer, a plurality of gate structures are provided, the field plate unit includes a plurality of field plates, and the number of field plates in the field plate unit is equal to the number of gate structures; One end of each of the gate structures is electrically connected to one end of the gate connection component, and the other end of the gate connection component is electrically connected to one end of the gate driving resistor; One end of each of the field plates in the field plate unit is connected to one end of the field plate connecting component, and the other end of the field plate connecting component is electrically connected to one end of the field plate driving resistor; the gate driving resistor and the field plate driving resistor are both connected in parallel to the gate electrode.

2. A depletion-mode GaN device according to claim 1, characterized in that: The resistance of the gate driving resistor is less than or equal to the resistance of the field plate driving resistor.

3. A depletion-mode GaN device according to claim 2, characterized in that: The stacked structure includes a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer from bottom to top, wherein the barrier layer and the cap layer are provided with a source electrode ohmic metal, a drain electrode ohmic metal, a first ohmic metal, a second ohmic metal, a third ohmic metal and a fourth ohmic metal, wherein the first ohmic metal and the second ohmic metal are respectively located on both sides of the gate drive resistor, and the third ohmic metal and the fourth ohmic metal are respectively located on both sides of the field plate drive resistor.

4. A depletion-mode GaN device according to claim 3, characterized in that: It also includes a fifth ohmic metal and a Schottky metal, the field plate drive resistor includes a first resistor part and a second resistor part connected to each other, the fifth ohmic metal and the Schottky metal are both located in the barrier layer and the cap layer, the fourth ohmic metal is located on the side of the first resistor part away from the second resistor part, the third ohmic metal is electrically connected to the fifth ohmic metal or the Schottky metal, the Schottky metal is used to form a diode, and the diode is connected in parallel with the second resistor part.

5. A depletion-mode GaN device according to claim 3 or 4, characterized in that: It also includes a gate drive loop connection section and a field plate drive loop connection section. The source electrode, the drain electrode, the gate drive loop connection section and the field plate drive loop connection section are all located above the second dielectric layer.

6. A depletion-mode GaN device according to claim 5, characterized in that: A first metal connecting strip and a second metal connecting strip are provided in the first dielectric layer and the second dielectric layer, one end of the first metal connecting strip is connected to the source electrode, the other end of the first metal connecting strip is connected to the ohmic metal of the source electrode, one end of the second metal connecting strip is connected to the drain electrode, the other end of the second metal connecting strip is connected to the ohmic metal of the drain electrode.

7. A depletion-mode GaN device according to claim 6, characterized in that: The grid connection assembly comprises a grid connection terminal, a grid connection segment and a plurality of first connection segments, one end of the grid connection segment is connected to the grid connection terminal, the plurality of first connection segments are respectively arranged in one-to-one correspondence with the plurality of grid structures, one end of each of the first connection segments is connected to a corresponding grid structure, the other end of each of the first connection segments is connected to the grid connection segment, and the grid connection segment and the plurality of first connection segments are used to connect the plurality of grid structures in parallel; The field plate connection assembly includes a field plate connection terminal, a field plate connection segment, and a plurality of second connection segments, one end of the field plate connection segment is connected to the field plate connection terminal, the plurality of second connection segments are respectively arranged in one-to-one correspondence with the plurality of field plates in the field plate unit, one end of each of the second connection segments is connected to a corresponding field plate, the other end of each of the second connection segments is connected to the field plate connection segment, and the field plate connection segment and the plurality of second connection segments are used to connect the plurality of field plates in the field plate unit in parallel.

8. A depletion-mode GaN device according to claim 7, characterized in that: The gate connection terminal is located in the first dielectric layer, and a third metal connection bar and a fourth metal connection bar are arranged in the first dielectric layer and the second dielectric layer, one end of the third metal connection bar and the fourth metal connection bar are both connected to the gate drive circuit connection section, the other end of the third metal connection bar is connected to the gate connection terminal, and the other end of the fourth metal connection bar is connected to the first ohmic metal.

9. A depletion-mode GaN device according to claim 8, characterized in that: The field plate connection terminal is located in the second dielectric layer, and a fifth metal connection strip and a sixth metal connection strip are provided in the first dielectric layer and the second dielectric layer, one end of the fifth metal connection strip and the sixth metal connection strip are both connected to the field plate drive circuit connection section, the other end of the fifth metal connection strip is connected to the field plate connection terminal, and the other end of the sixth metal connection strip is connected to the third ohmic metal.

10. A depletion-mode GaN device according to claim 9, characterized in that: The first ohmic metal is located on a side of the gate driving resistor close to the gate connection terminal, the third ohmic metal is located on a side of the field plate driving resistor close to the field plate connection terminal, a first extension section is provided at one end of the second ohmic metal away from the gate driving resistor, a second extension section is provided at one end of the fourth ohmic metal away from the field plate driving resistor, and one end of each of the first extension section and the second extension section is connected to the gate electrode.

11. The depletion-mode GaN device according to claim 5, characterized in that: There are multiple field plate units, multiple layers of the second dielectric layer, and one field plate unit is disposed in each of the second dielectric layers; the field plate driving resistor, the field plate connecting component and the field plate driving loop connecting section are all disposed in one-to-one correspondence with the field plate units.

12. A depletion-mode GaN device according to claim 11, characterized in that: The resistance of the gate drive resistor is less than or equal to the resistance of the field plate drive resistor corresponding to the field plate unit located in a second dielectric layer close to the first dielectric layer, and the resistance of the field plate drive resistor corresponding to each field plate unit located in each layer of the second dielectric layer gradually increases from a second dielectric layer close to the first dielectric layer to a second dielectric layer far away from the first dielectric layer.

13. A method for preparing a depletion-mode GaN device according to any one of claims 1 to 12, characterized in that: The steps include: An active area, a gate drive resistor, and a field plate drive resistor are formed on the stacked structure by photoresist protection; or, an active area, a gate drive resistor, a field plate drive resistor, and a diode injection protection area are formed; Forming a source electrode ohmic metal, a drain electrode ohmic metal, a first ohmic metal, a second ohmic metal, a third ohmic metal, and a fourth ohmic metal over the stacked structure; or forming a source electrode ohmic metal, a drain electrode ohmic metal, a first ohmic metal, a second ohmic metal, a third ohmic metal, a fourth ohmic metal, a fifth ohmic metal, and a Schottky metal; Filling metal on the stacked structure and etching to form a gate structure and a gate connection component; depositing a first dielectric layer over the gate structure, and forming a field plate and a field plate connection assembly over the first dielectric layer; Depositing a second dielectric layer above the field plate, etching through holes downward from the second dielectric layer and filling them with metal to form a first metal connecting bar, a second metal connecting bar, a third metal connecting bar, a fourth metal connecting bar, a fifth metal connecting bar and a sixth metal connecting bar; A source electrode, a drain electrode, a gate drive loop connection section and a field plate drive loop connection section are formed on the second dielectric layer to obtain the depletion-mode GaN device.

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