Semiconductor wafer with GAN intermediate layer for constructing

Abstract

The invention relates to a semiconductor wafer for producing a GaN semiconductor component, having a diameter of at least 100 mm, comprising a substrate having an upper side and an underside, the substrate being made of silicon on the upper side, a transition layer being integrally bonded to the upper side of the substrate, and an insulating layer being bonded to the underside of the substrate. A transition layer is arranged on the substrate, a first GaN layer is arranged on the transition layer in a material locking manner, the first GaN layer comprises a first GaN sub-layer and a second GaN sub-layer, the second GaN sub-layer is arranged on the first GaN sub-layer, the second GaN sub-layer has a lower number of linear dislocations than the first GaN sub-layer, and the second GaN sub-layer has a lower number of linear dislocations than the first GaN sub-layer. The first GaN sub-layer has a first layer thickness, the second GaN sub-layer has a second layer thickness, and the second layer thickness is greater than or equal to the first layer thickness.

Description

Technical Field

[0001] The invention relates to a semiconductor wafer for forming GaN semiconductor components. Background Art

[0002] Semiconductor wafers of this type mainly have a silicon substrate with a buffer layer system located thereon, wherein the uppermost layer of the buffer layer system comprises a GaN layer. GaN semiconductor components, in particular power transistors or LEDs, are produced on the GaN layer by means of growth and structuring of further layers.

[0003] The goal is to structure the epitaxial growth, in particular of GaN layers or GaN sublayers, as dislocation-free and monocrystalline as possible. In other words, the number of defects, such as linear dislocations, is reduced as much as possible and a defect-free, monocrystalline GaN layer is deposited in order to achieve the highest possible yield when producing semiconductor components comprising or consisting of GaN.

[0004] The production of the layers of the buffer layer system, including the GaN layer, is usually carried out using a vapor phase epitaxy process, known as MOVPE, in which the corresponding semiconductor layers are produced by deposition from the gas phase.

[0005] To produce GaN layers from the gas phase, organic carrier gases, such as trimethylgallium ((CH 3 ) 3 Ga) and ammonia (NH 3 ) with addition of hydrogen, are used as carrier gases during the growth of gallium nitride, wherein the reaction can be described by means of the following reaction formula:

[0006] (CH3)3Ga+NH3→GaN (fest) +3CH 4(gas)

[0007] Due to the presence of a large amount of carbon and hydrogen, a small amount of hydrogen and carbon is also unintentionally and inevitably incorporated into the semiconductor crystal, ie, into the GaN layer.

[0008] Although hydrogen can be removed by annealing in an inert gas atmosphere or in vacuum, for example in order not to passivate acceptors required for p-type conduction, the unavoidable and unintentional incorporation of carbon caused by this process leads to p-doping or to an increase in the residual conductivity.

[0009] Despite the existence of elaborate methods for avoiding all impurities resulting from the use of the equipment and starting materials (eg metal organics) required for producing GaN layers, unintentional and unavoidable impurities such as oxygen are still found in GaN layers.

[0010] Methods for producing GaN layers are known from DE 10 2006 008 929 A1, EP 2 767 620 A1, DE 102 56911 A1, US 2006 / 0281284 A1 and US 2013 / 0087762 A1. Summary of the invention

[0011] Against this background, the object of the present invention is to provide a device which expands the prior art.

[0012] This object is achieved by a semiconductor wafer for forming GaN semiconductor components having the features of claim 1. Advantageous embodiments of the invention are the subject matter of the dependent claims.

[0013] According to the subject matter of the present invention, a semiconductor wafer for forming a GaN semiconductor component is provided, wherein the semiconductor wafer has a diameter of at least 100 mm. It should be understood that the semiconductor wafer can also have a diameter of 150 mm or 200 mm or 300 mm or 450 mm.

[0014] Furthermore, the semiconductor wafer has a substrate having a top side and an underside, wherein the substrate consists of silicon on the top side.

[0015] Furthermore, the transition layer is connected to the top side of the substrate in a material-bonded manner. The structured first GaN layer is arranged in a material-bonded manner on the transition layer.

[0016] The first GaN layer includes a first GaN sublayer and a second GaN sublayer, wherein the second GaN sublayer is formed on the first GaN sublayer.

[0017] On average, the second GaN sub-layer has a lower number of linear dislocations than the first GaN sub-layer.

[0018] Furthermore, the first GaN sublayer has a first layer thickness, and the second GaN sublayer has a second layer thickness, wherein the second layer thickness is greater than or equal to the first layer thickness.

[0019] It is to be understood that the semiconductor wafer comprises a substrate, wherein the substrate comprises or consists of a single layer, or in another embodiment, the substrate comprises or consists of a plurality of layers arranged in a stack.

[0020] It should be noted that a monocrystalline silicon layer is formed on the substrate on the upper side. In one embodiment, only the upper side consists of a monocrystalline layer. In an extension, the thickness of the uppermost monocrystalline layer includes a thickness in the range of 10 nm to 100 μm. Preferably, the entire surface includes or consists of a monocrystalline layer.

[0021] In one embodiment, the entire substrate consists of silicon, ie, consists of a single monocrystalline silicon layer.

[0022] Preferably, the crystal orientation of the layers of the single crystal is either <100> , or <111> However, it should be understood that the layers of the single crystal may also have other crystal directions, in particular <110> or <011> Or <001> direction.

[0023] It should be noted that the term "on average" is understood to mean the total number of linear dislocations relative to the entire area of ​​the first GaN sublayer or relative to the entire area of ​​the second GaN sublayer. With the above definition, it applies that the area density of linear dislocations in the second GaN sublayer determined in this way is lower than the area density of linear dislocations in the first GaN sublayer.

[0024] In other words, if the number of linear dislocations over a small selected area of ​​the second GaN sublayer is compared to a small selected area of ​​the first GaN sublayer, it is possible that the number of linear dislocations on the second GaN sublayer is equal to or even greater than the number of linear dislocations on the first GaN sublayer.

[0025] It should also be noted that the expression GaN layer or GaN sublayer is understood to mean a layer which comprises at least the elements Ga and N. It should also be noted that both unintentional and unavoidable impurities and intentionally introduced dopants are always included in all layers.

[0026] In one configuration, the GaN layer or the GaN sublayer comprises, in addition to the elements Ga and N, further elements, for example In and / or Al and / or further elements of the III or V main group.

[0027] In another embodiment, the proportion of further elements of main group III and / or the amount of elements associated with main group V is less than 10%, preferably less than 5%, most preferably less than 1%.

[0028] In another configuration, the GaN layer or the corresponding GaN sublayer consists exclusively of the elements Ga and N, but nevertheless simultaneously contains unintentional and unavoidable impurities and intentionally introduced dopants.

[0029] It should be noted that the above-mentioned layers including at least the transition layer and the first GaN layer are part of a semiconductor buffer layer sequence. As already mentioned at the outset, the purpose of the semiconductor buffer layer sequence is to provide GaN layers that are as defect-free as possible so that GaN semiconductor components can be produced.

[0030] One advantage of forming a GaN layer consisting of a plurality, ie at least two, GaN sublayers is that the quality of the uppermost GaN sublayer is improved compared to a GaN layer comprising or consisting of a single GaN sublayer.

[0031] The reason for improving the layer quality of the GaN layer is mainly the reduction in the number of linear dislocations.

[0032] Another advantage is that in the second GaN sublayer, the area of ​​the majority of the grains is increased compared to the first GaN sublayer. This reduces the number of linear dislocations in particular. The observed area of ​​the grains is each constructed parallel to the corresponding layer area and is also referred to as the lateral area below.

[0033] In other words, the average size of the grains in the second GaN sublayer is increased compared to the average size of the grains of the first GaN sublayer. Here, "average size of the grains" is understood as the arithmetic mean, ie the sum of the lateral areas divided by the number of grains.

[0034] Studies have shown that the difference between the two GaN sublayers can be produced by changes in the growth conditions. At least one deposition parameter is changed between the two GaN sublayers, i.e., at the location where the interface between the two GaN sublayers is formed, in the MOVPE facility. It should be understood that the change in the changed deposition parameter is greater than the inaccuracy of the corresponding deposition parameter caused by the facility conditions.

[0035] In an extended embodiment, the magnitude of the parameter change or the lower limit for the parameter change is at least 2 times or at least 10 times or at least 50 times the inaccuracy of the parameter predefined by the control system on the MOVPE. It should be understood that in the case of a plurality of changed deposition parameters, the above description applies to each of the changed deposition parameters.

[0036] In one configuration, the first GaN sublayer and the second GaN sublayer have the same stoichiometry.

[0037] In another configuration, the difference in stoichiometry between the two GaN sublayers with respect to the elements of the III main group is less than 2%, and the difference in stoichiometry with respect to the elements of the V main group is less than 2%.

[0038] In one embodiment, the difference in curvature of the semiconductor wafer when depositing the first GaN sublayer and the second GaN sublayer is less than 5 km -1 In other words, the two layers, ie, the first GaN sublayer and the second GaN sublayer, apply the same or nearly the same stress to the substrate.

[0039] In one configuration, the first GaN sublayer is virtually or completely stress-free during and / or directly after deposition, ie, is neither compressively nor tensilely stressed.

[0040] In one configuration, the second GaN sublayer is virtually or completely stress-free during and / or directly after deposition, ie, is neither compressively nor tensilely stressed.

[0041] In one embodiment, the magnitude of the wafer curvature is, in a first approximation, independent of the diameter of the semiconductor wafer.

[0042] In one embodiment, the first GaN sublayer has a first lattice constant and the second GaN sublayer has a second lattice constant. Preferably, the first lattice constant is the same as the second lattice constant. In another extended solution, the difference between the two lattice constants is less than 1% or less than 0.5% or less than 0.3%.

[0043] In another embodiment, the second GaN sublayer is formed in a material-bonded manner on the first GaN sublayer.

[0044] In an extended solution, a connection layer is formed between the first GaN sublayer and the second GaN sublayer. Preferably, the lattice constant of the connection layer is the same as the lattice constant of the first GaN sublayer and / or the same as the lattice constant of the second GaN sublayer, or in another alternative solution, the lattice constant of the connection layer is different from the lattice constant of the first GaN sublayer and / or the lattice constant of the second GaN sublayer.

[0045] In one embodiment, the thickness of the connecting layer lies in a range between 0.5 nm and 100 nm, preferably between 0.5 nm and 30 nm.

[0046] In a further configuration, the difference in the lattice constant between the connecting layer and the first and / or second GaN sublayer is either overall less than 1% or less than 0.5% or less than 0.3%.

[0047] In one embodiment, the ratio of the sum of the linear dislocations of the second GaN sublayer to the sum of the linear dislocations of the first GaN sublayer is between 2 and 1000 or between 5 and 40. The sum is determined by the total number of linear dislocations of the entire layer. Preferably, the sum of the linear dislocations on the surface of the respective GaN sublayer is determined.

[0048] In another embodiment, the difference in the sum of linear dislocations at the interface between the second GaN sublayer and the first GaN sublayer is between 2 and 1000 or between 5 and 40. In this case, the interface includes the bottom side of the second GaN sublayer and the top side of the first GaN sublayer.

[0049] In one embodiment, the surface density of linear dislocations in the first GaN sublayer is between 2*10 9 cm -2 With 1*10 10 cm -2 In the range between 1 and 10 7 cm -2 With 1*10 9 cm -2 In the range between.

[0050] In one embodiment, the surface density of linear dislocations on the bottom side in the first GaN sublayer is greater than 5*10 10 cm -2 In addition, the surface density of linear dislocations on the upper side in the first GaN sublayer is located at 2*10 9 cm -2 With 1*10 10 cm -2 In the range between 10 and 10 7 cm -2 With 1*10 9 cm -2 In the range between.

[0051] In another embodiment, the first GaN sublayer has a greater total number of linear dislocations with an inclined orientation than the second GaN sublayer. It should be noted that the term "inclined orientation" refers to the orientation of the linear dislocations in the corresponding GaN sublayer that deviates from the vertical direction, i.e., deviates from the direction of the normal on the upper side of the corresponding GaN sublayer.

[0052] Here, it should be understood that the course of the linear dislocations in the corresponding GaN sublayers not only has a vertical section or a section extending vertically in a first approximation, but that the course only takes on an inclined course as the length of the course of the linear dislocations increases. It is desirable that the inclined course of the linear dislocations extends as horizontally as possible, i.e. parallel to the upper side of the corresponding GaN sublayer.

[0053] In one embodiment, at least 50% or at least 80% of the linear dislocations in the first GaN sublayer have an inclined course. In one embodiment, the dislocation angle is greater than 10° or 30° or 50°.

[0054] In one configuration, in the first GaN sublayer, in the case of obliquely extending linear dislocations, the step angle is greater than 50° or greater than 30°.

[0055] In another embodiment, the ratio of the thickness of the second GaN sublayer to the thickness of the first GaN sublayer lies in the range between 1 and 100 or in the range between 1 and 10 or in the range between 1 and 3.

[0056] In a further configuration, the thickness of the first GaN sublayer lies in the range between 5 nm and 300 nm and / or the thickness of the second GaN sublayer lies in the range between 300 nm and 5000 nm.

[0057] In a further embodiment, the first GaN layer has a total layer thickness of at least 0.35 μm and a thickness of at most 5 μm.

[0058] As mentioned at the beginning, in the vapor deposition for producing GaN layers, carbon and oxygen are inevitably incorporated during the growth of the GaN layer due to the equipment and starting materials required for producing the GaN layer by MOVPE. This incorporation is also referred to as unintentional incorporation. It should be noted here that MOVPE is a feasible and common method for producing GaN layers. In particular, GaN layers can also be produced by methods such as MBE or LPE or HVPE.

[0059] The study showed that by changing the growth conditions from depositing the first GaN sublayer to depositing the second GaN sublayer, the amount of unintentional incorporation of carbon and oxygen ( ) changes.

[0060] In one embodiment, both the first GaN sublayer and the second GaN sublayer have a carbon concentration that is unintentionally and inevitably generated, ie, as described above, by the deposition process. The carbon concentration is greater in the first GaN sublayer than in the second GaN sublayer.

[0061] In other words, at least one deposition process parameter when manufacturing the first GaN sublayer is different from one of the deposition process parameters used to manufacture the second GaN sublayer, wherein the second GaN sublayer therefore has an unintentional and unavoidable carbon concentration that is higher than the unintentional and unavoidable carbon concentration of the first GaN sublayer.

[0062] In one embodiment, at the interface, a ratio of an unintentional and unavoidable carbon concentration of the second GaN sublayer to an unintentional and unavoidable carbon concentration of the first GaN sublayer is in a range between 2 and 1000 or in a range between 4 and 200 or in a range between 10 and 100.

[0063] In a further configuration, the unintentional and unavoidable carbon concentration in the first GaN sublayer is constant or decreases in the direction of the second GaN sublayer.

[0064] In one embodiment, the unintentional and unavoidable carbon concentration in the first GaN sublayer is constant or decreases along a path from the interface between the transition layer and the first GaN sublayer to the interface between the first GaN sublayer and the second GaN sublayer.

[0065] In one embodiment, the unintentional and unavoidable carbon concentration in the first GaN sublayer is between 1*10 17 cm -3 With 5*10 18 cm -3 In the range between 5*10 15 cm -3 With 5*10 16 cm -3 In the range between.

[0066] In one embodiment, both the first GaN sublayer and the second GaN sublayer have an oxygen concentration that is unintentionally and inevitably generated, ie, as described above, by the deposition process. The oxygen concentration is greater in the first GaN sublayer than in the second GaN sublayer.

[0067] In other words, at least one deposition process parameter when manufacturing the first GaN sublayer is different from one of the deposition process parameters used to manufacture the second GaN sublayer, wherein the second GaN sublayer therefore has an unintentional and unavoidable oxygen concentration that is higher than the unintentional and unavoidable oxygen concentration of the first GaN sublayer.

[0068] In one embodiment, at the boundary layer, a ratio of an unintentional and unavoidable oxygen concentration of the second GaN sublayer to an unintentional and unavoidable oxygen concentration of the first GaN sublayer is in a range between 2 and 5000 or in a range between 4 and 200 or in a range between 10 and 100.

[0069] In a further configuration, the unintentional and unavoidable oxygen concentration in the first GaN sublayer is constant or decreases in the direction of the second GaN sublayer.

[0070] In one embodiment, in the first GaN sublayer, the unintentional and unavoidable oxygen concentration is constant or decreases along a section from the interface between the transition layer and the first GaN sublayer to the interface between the first GaN sublayer and the second GaN sublayer.

[0071] In one embodiment, the unintentional and unavoidable oxygen concentration in the first GaN sublayer is between 2*10 17 cm -3With 5*10 18 cm -3 In the range between 1*10 15 cm -3 With 1*10 17 cm -3 In the range between.

[0072] In one embodiment, the density of linear dislocations in the first GaN sublayer is at least 2 times and at most 1000 times the density of linear dislocations in the second GaN sublayer.

[0073] In another embodiment, a plurality of spots are formed on the upper side of the silicon layer of the substrate, which spots are formed in a materially bonded manner with the upper side and contain oxygen. Thus, the oxide spots are formed on the upper side of the silicon layer and below the transition layer.

[0074] In one embodiment, the spots containing oxygen cover at least 0.005% and at most 35% of the upper side of the substrate. Alternatively, the spots containing oxygen cover at least 5% and at most 50% of the upper side of the substrate.

[0075] It should be understood that the layers are each formed over the entire surface. Here, the term "full surface" refers in the present case to the entire area of ​​the semiconductor wafer. It should also be noted that the spots are mainly composed of silicon oxide, i.e., are composed of oxide or at least include oxide. In other words, the oxide spots remain and are covered by subsequent layers. However, in no case do the oxide spots form a coherent layer on the upper side of the silicon layer.

[0076] One advantage is that, surprisingly, the quality of the semiconductor buffer layer sequence, ie, the GaN layer on the respective top side, can be improved by means of the spots. In particular, the cohesion during the growth of the semiconductor buffer layer sequence can be improved.

[0077] In one configuration, the spots containing oxygen preferably cover min. 0.2% to max. 20% or min. 0.01% to max. 30% or min. 0.1% to max. 25% of the top side of the substrate and are integrally connected to the top side of the substrate.

[0078] In another embodiment, the spots containing oxygen each have an extent of at least 10 nm or at least 50 nm or at least 100 nm. In this case, the spots can have a variety of shapes.

[0079] In one embodiment, the spots containing oxygen each have an extent of at most 5 μm or at most 1 μm or at most 0.5 μm.

[0080] In one configuration, the spots containing oxygen have a thickness in the range between a monolayer and 4 nm, wherein the thickness of a monolayer is approximately 0.4 nm.

[0081] In one embodiment, the spots with oxygen include or consist of silicon dioxide and / or silicon monoxide, which are collectively referred to as silicon oxide hereinafter.

[0082] In another embodiment, the silicon oxide is configured as a naturally grown oxide.Native oxide, ie, silicon oxide, grows in an environment having oxygen.

[0083] However, it should be noted that the formation of native oxide is accelerated in a humid environment. The density of the native oxide is less than that of the thermally grown oxide. In the present case, the natively grown oxide is understood to be a silicon oxide that is preferably formed at room temperature, but most preferably at a temperature of less than 100° C. or less than 200° C. The thickness of the native oxide is between a monolayer, i.e., approximately 0.4 nm and 4 nm. In an extension, the thickness of the native oxide is between 1 nm and 2 nm.

[0084] In the present case, a thermally grown oxide is understood to be a silicon oxide which is preferably grown at a temperature of more than 500° C. Preferably, the density of the thermal oxide is more than 30% higher than the density of the native oxide.

[0085] In another embodiment, the spots containing oxygen include or consist of silicon oxide or oxynitride.

[0086] In one embodiment, the spots containing oxygen are distributed almost uniformly on the top side. The term "uniformly distributed" is understood in the present case to mean that the spots are located uniformly distributed over the entire surface of the semiconductor wafer. In one embodiment, the number of spots on a region of the wafer comprising at least 20% of the total area differs from the number of spots in a second region of the semiconductor wafer of the same size by no more than 50%.

[0087] In one configuration, the semiconductor buffer layer sequence has a thickness of at least 1 μm or at least 4 μm and at most 30 μm. In one embodiment, the semiconductor buffer layer sequence has a thickness on the top side of between 0.5 μm and 10 μm or between 1.0 μm and 5 μm.

[0088] In a further embodiment, the transition layer comprises a layer sequence of at least two different layers or consists of a layer sequence of at least two different layers.

[0089] In one embodiment, the transition layer has a nucleation layer composed of AlN and completely or partially covering the upper side of the substrate. The nucleation layer has a thickness of at least 5 nm and at most 50 nm. It is understood that if oxide spots are present on the upper side of the substrate, the nucleation layer at least partially covers the oxide spots.

[0090] In another embodiment, the nucleation layer has a plurality of holes. Preferably, the proportion of the area of ​​the holes on the upper side of the nucleation layer, ie the total hole area, is between 1% and 30% of the total area of ​​the nucleation layer.

[0091] The proportion of the total pore area is calculated here by dividing the total area of ​​the pores over the total layer area by the total area of ​​the nucleation layer. If the transition layer on the upper side consists only of the upper side of the nucleation layer, it is understood that the transition layer has the distribution and number of pores of the nucleation layer.

[0092] In one embodiment, the holes are distributed uniformly in a first approximation over the entire surface of the nucleation layer.

[0093] In another embodiment, the pore area is in the range between 5% and 20% relative to the entire surface of the nucleation layer.

[0094] In one embodiment, a masking layer is formed on the nucleation layer and comprises (Al)GaN or consists of (Al)GaN and at least partially covers the nucleation layer.

[0095] In one embodiment, the masking layer has a surface and aluminum content of between 0% and 10% relative to all elements of the main group III contained in the periodic table. The thickness of the masking layer has a layer thickness of at least 100 nm or at least 300 nm and a maximum of 900 nm. In another embodiment, the masking layer has a thickness of between 400 nm and 600 nm.

[0096] In one configuration, a first GaN layer is formed on the masking layer. Preferably, the first GaN layer is formed directly on the surface of the masking layer.

[0097] In one embodiment, a sequence of an intermediate layer and a layer comprising a second GaN is constructed on the first GaN layer. It should be understood that the second GaN layer includes or consists of the first GaN sublayer.

[0098] In one configuration, the second GaN layer includes the first GaN sublayer and the second GaN sublayer, or the second GaN layer consists of the first GaN sublayer and the second GaN sublayer.

[0099] In one embodiment, a plurality of sequences are formed on the first GaN layer. In this case, at least one sequence and a maximum of 10 sequences are formed on the first GaN layer.

[0100] In one embodiment, the sequence has a thickness of between 0.5 μm and 10 μm or between 1.0 μm and 5 μm. In one embodiment, the sequence has a thickness of at least 1 μm or at least 4 μm and a thickness of at most 30 μm.

[0101] In one configuration, the intermediate layer comprises Al. In another configuration, the intermediate layer comprises AlGaN or consists of AlGaN. BRIEF DESCRIPTION OF THE DRAWINGS

[0102] In the following, the invention is explained in more detail with reference to the accompanying drawings. Here, the same parts are marked with the same names. The embodiments shown are highly schematic, i.e. the spacings and the lateral and vertical extensions are not to scale and, unless otherwise stated, do not have any geometrical relationships that can be derived from one another. It is shown:

[0103] Figure 1 shows a cross section of a semiconductor wafer having a GaN layer, wherein the GaN layer is divided into a first GaN sublayer and a second GaN sublayer,

[0104] Figure 2 Shown in Figure 1 The background of the diagram shows the trend of the lattice constant of the semiconductor wafer.

[0105] Figure 3 shows a cross section of a semiconductor wafer having a further embodiment of a layer arrangement,

[0106] Figure 4 A cross section of a semiconductor wafer is shown, which shows in detail the difference in linear dislocations between a first GaN sublayer and a second GaN sublayer. DETAILED DESCRIPTION

[0107] The layer arrangement shown below above the substrate is part of a semiconductor buffer layer sequence, wherein a so-called active layer for producing GaN semiconductor components is formed above the semiconductor buffer layer sequence, which active layer is generally not to be regarded as part of the semiconductor buffer layer sequence.

[0108] Figure 1 The illustration of shows a cross-sectional view of a semiconductor wafer consisting of a substrate 10, preferably a silicon substrate, having a top side OS and an underside US. The substrate 10 consists of monocrystalline silicon at least on the top side and has a diameter of at least 100 mm.

[0109] A transition layer UES having a top side OF is formed on the top side OS of the substrate 10, wherein the transition layer UES is connected in a materially bonded manner to the substrate 10. A first GaN layer GS is arranged in a materially bonded manner on the top side OF of the transition layer UES.

[0110] The first GaN layer GS includes or is composed of a first GaN sublayer GN1 having a thickness D1 and a second GaN sublayer GN2 having a thickness D2, wherein the thickness of the first GaN sublayer GN1 is configured to be less than or equal to the thickness D2 of the second GaN sublayer. An interface GRZ is configured between the first GaN sublayer GN1 and the second GaN sublayer GN2.

[0111] An intermediate layer ZW is formed above the first GaN layer. In the present case, the intermediate layer ZW is connected to the top side of the first GaN layer GS in a material-bonded manner.

[0112] A further GaN layer GAU is formed on the upper side of the intermediate layer ZW. The intermediate layer ZW and the further GaN layer together form a sequence AF.

[0113] In an embodiment not shown, a plurality of sequences AF are arranged consecutively. It should be understood that in each of the sequences AF, the additional GaN layer GAU includes or consists of a first GaN sublayer and / or a second GaN sublayer.

[0114] Figure 2 The diagram shows Figure 1 The trend of the lattice constant of a semiconductor wafer is shown in the context of a diagram of FIG. Figure 1 The difference between the icons.

[0115] The first GaN sublayer GN1 has a first lattice constant G1. The second GaN sublayer GN2 has a second lattice constant G2. In the present case, the first lattice constant GN1 and the second lattice constant GN2 are almost the same size or exactly the same size.

[0116] An alternative sequence of intermediate layers ZW and further GaN layers is shown by dashed lines, wherein in the present case the lattice constant remains unchanged.

[0117] Figure 3 The figure shows a cross section of a semiconductor wafer having a further embodiment of a layer arrangement. In the following, only the differences from one of the previous figures are explained.

[0118] On the upper side OS of the silicon substrate 10, spots OXF with oxygen are shown in dashed lines, i.e. optionally. It should be noted that the spots OXF, hereinafter referred to as oxide spots, are distributed as evenly as possible on the upper side OS, but the spots OXF have irregular contours and sizes not shown and cover at least 0.005% and a maximum of 50% of the upper side OS of the substrate 10.

[0119] An optional spot OXF is shown as part of the transition layer UES. The transition layer UES comprises a nucleation layer NUS and a masking layer MASK constructed on the nucleation layer NUS. The masking layer MASK structures the upper side OF of the transition layer UES.

[0120] On the interface GRZ between the first GaN sublayer GN1 and the second GaN sublayer GN2 , a thin connection layer VS is optionally arranged.

[0121] The connection layer VS has the same lattice constant as that of the first GaN sublayer GN1 located therebelow.

[0122] Figure 4 The illustration of shows a cross section of a semiconductor wafer showing in detail the first GaN layer GS which differs in a linear dislocation FV between the first GaN sublayer GN1 and the second GaN sublayer GN2 .

[0123] On average, the number of linear dislocations FV in the second GaN sublayer GN2 is lower than the number of linear dislocations FV in the first GaN sublayer GN1. The linear dislocations FV in the first GaN sublayer GN1 also generally have a more inclined orientation than the linear dislocations FV in the second GaN sublayer GN2. In other words, the first GaN sublayer has a lower quality than the second GaN sublayer GN2.

[0124] The number of linear dislocations FV in the second GaN sublayer GN2 is also lower than that in the first GaN sublayer GN1. Therefore, the size of the grains in the second GaN sublayer GN2 is also significantly larger than that in the first GaN sublayer GN1.

Claims

1. A semiconductor wafer for forming a GaN semiconductor component, the semiconductor wafer having a diameter of at least 100 mm, the semiconductor wafer having - a substrate (10) having an upper side (OS) and an underside (US), wherein: The substrate (10) consists of silicon on the upper side (OS), a transition layer (UES) connected in a materially bonded manner to the upper side (OS) of the substrate, a first GaN layer (GS) formed in a material-bonded manner on the transition layer (UES), It is characterized in that The first GaN layer (GS) includes a first GaN sublayer (GN1) and a second GaN sublayer (GN2), The second GaN sublayer (GN2) is constructed on the first GaN sublayer (GN1), wherein, on average, the number of linear dislocations (FV) in the second GaN sublayer (GN2) is lower than the number of linear dislocations in the first GaN sublayer (GN1), The first GaN sublayer (GN1) has a first layer thickness (D1), and the second GaN sublayer (GN2) has a second layer thickness (D2), wherein the second layer thickness (D2) is greater than or equal to the first layer thickness (D1).

2. The semiconductor wafer according to claim 1, characterized in that When depositing the first GaN sublayer (GN1) and the second GaN sublayer (GN2), the difference in curvature of the semiconductor wafer is less than 5 km -1 .

3. The semiconductor wafer according to claim 1 or claim 2, characterized in that: The first GaN sublayer (GN1) has a first lattice constant (G1), and the second GaN sublayer (GN2) has a second lattice constant (G2), wherein the first lattice constant (G1) and the second lattice constant (G2) are the same size or the difference between the two lattice constants (G1, G2) is less than 1%.

4. The semiconductor wafer according to claim 1, characterized in that The second GaN sublayer (GN2) is material-lockedly constructed on the first GaN sublayer (GN1), or a connecting layer (VS) is constructed between the first GaN sublayer (GN1) and the second GaN sublayer (GN2), wherein the lattice constant of the connecting layer (VS) is the same as the lattice constant of the first sublayer (GN1), or the lattice constant of the connecting layer (VS) is different from the lattice constant of the first GaN sublayer (GN1) or the second GaN sublayer (GN2).

5. The semiconductor wafer according to claim 1, characterized in that A ratio of the sum of the linear dislocations (FV) of the second GaN sublayer (GN2) to the sum of the linear dislocations (FV) of the first GaN sublayer (GN1) is between 2 and 1000 or between 5 and 40.

6. The semiconductor wafer according to claim 1, characterized in that The surface density of linear dislocations in the first GaN sublayer (GN1) is between 2*10 9 cm -2 With 1*10 10 cm -2 In the range between 1*10 7 cm -2 With 1*10 9 cm -2 In the range between.

7. The semiconductor wafer according to claim 1, characterized in that Unlike the second GaN sub-layer (GN2), the first GaN sub-layer (GN1) has a greater total number of linear dislocations (FV) having an inclined orientation.

8. The semiconductor wafer according to claim 1, characterized in that At least 50% or at least 80% of the linear dislocations (FV) in the first GaN sublayer (GN1) have an inclined course.

9. The semiconductor wafer according to claim 1, characterized in that The ratio of the thickness (D2) of the second GaN sublayer (GN2) to the thickness (D1) of the first GaN sublayer (GN1) is in the range between 1 and 100 or in the range between 1 and 10 or in the range between 1 and 3.

10. The semiconductor wafer according to claim 1, characterized in that The first GaN sublayer (GN1) and the second GaN sublayer (GN2) respectively have unintentionally incorporated oxygen and / or unintentionally incorporated carbon, wherein the concentration of oxygen and / or carbon in the first GaN sublayer (GN1) is greater than the concentration of oxygen and / or carbon in the second GaN sublayer (GN2).

11. The semiconductor wafer according to claim 1, characterized in that On the boundary layer (GRZ), the ratio of the concentration of unintentionally incorporated carbon in the second GaN sublayer (GN2) to the concentration of unintentionally incorporated carbon in the first GaN sublayer (GN1) is in the range between 2 and 1000 or in the range between 4 and 200 or in the range between 10 and 100.

12. The semiconductor wafer according to claim 1, characterized in that On the boundary layer (GRZ), the ratio of the concentration of unintentionally incorporated oxygen in the second GaN sublayer (GN2) to the concentration of unintentionally incorporated oxygen in the first GaN sublayer (GN1) is in the range between 2 and 5000 or in the range between 4 and 200 or in the range between 10 and 100.

13. The semiconductor wafer according to claim 1, characterized in that In the first GaN sublayer (GN1), the unintentional oxygen concentration is between 2*10 17 cm -3 With 5*10 18 cm -3 In the range between 1*10 15 cm -3 With 1*10 17 cm -3 In the range between.

14. The semiconductor wafer according to claim 1, characterized in that In the first GaN sublayer (GN1), the unintentional carbon concentration is between 1*10 17 cm -3 With 5*10 18 cm -3 In the range between 5*10 15 cm -3 With 5*10 16 cm -3 In the range between.

15. The semiconductor wafer according to claim 1, characterized in that The first GaN layer (GS) has a total layer thickness of at least 0.35 μm and at most 5 μm.

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