Package comprising core particle between two metallization portions

Abstract

A package includes: a first metallization portion; a first integrated device coupled to the first metallization portion; a second integrated device coupled to the first metallization portion; interconnecting a second metallization portion coupled to the first metallization portion through a first plurality of solder posts; the first core particle is arranged between the first metallization part and the second metallization part, the second core particle is arranged between the first metallization part and the second metallization part, the first core particle is configured to be electrically coupled to the first integrated device through the first metallization part, and the second core particle is configured to be electrically coupled to the second integrated device through the second metallization part. Wherein the second core particle is configured to be electrically coupled to the second integrated device through the first metallization portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of non-provisional application S / N. 17 / 894,057 filed in the U.S. Patent Office on August 23, 2022, the entire contents of which are incorporated herein by reference as if fully set forth in its entirety below and for all applicable purposes. Technical Field

[0003] Various features are directed to packages including integrated devices. Background Art

[0004] A package may include a substrate, integrated devices, and passive components. These components are coupled together to provide a package that can perform various electrical functions. How the integrated devices, substrate, and passive components are coupled together affects the overall performance of the package. There is a constant need to provide a package with better performance. Summary of the invention

[0005] Various features are directed to packages including integrated devices.

[0006] One example provides a package comprising a first metallization portion, a first integrated device coupled to the first metallization portion via a first plurality of solder column interconnects, and a first core particle located between the first integrated device and the first metallization portion, wherein the first core particle is coupled to the first integrated device via a first plurality of solder column interconnects.

[0007] Another example provides a device including a package. The package includes a first metallization portion, a first integrated device coupled to the first metallization portion through a first plurality of solder pillar interconnects, and a first die located between the first integrated device and the first metallization portion, wherein the first die is coupled to the first integrated device through a first plurality of solder pillar interconnects.

[0008] Another example provides a method for manufacturing a package. The method provides a first integrated device and a first plurality of solder column interconnects. The method forms an encapsulation layer encapsulating the first integrated device and the first plurality of solder column interconnects. The method forms a first plurality of solder column interconnects configured to be coupled to the first integrated device. The method couples a first core particle to the first integrated device through the first plurality of solder column interconnects. The method forms a first metallization portion such that the first metallization portion is coupled to the first core particle and the first encapsulation layer.

[0009] Another example provides a package comprising a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion via a first plurality of solder pillar interconnects, a first core particle located between the first metallization portion and the second metallization portion, and a second core particle located between the first metallization portion and the second metallization portion, wherein the first core particle is configured to be electrically coupled to the first integrated device via the first metallization portion, and wherein the second core particle is configured to be electrically coupled to the second integrated device via the first metallization portion.

[0010] Another example provides a device including a package. The package includes a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, the second metallization portion coupled to the first metallization portion through a first plurality of solder pillar interconnects, a first core particle located between the first metallization portion and the second metallization portion, and a second core particle located between the first metallization portion and the second metallization portion, wherein the first core particle is configured to be electrically coupled to the first integrated device through the first metallization portion, and wherein the second core particle is configured to be electrically coupled to the second integrated device through the first metallization portion.

[0011] Another example provides a method for manufacturing a package. The method provides a first integrated device and a second integrated device. The method forms an encapsulation layer that encapsulates the first integrated device and the second integrated device. The method forms a first metallization portion so that the first metallization portion is coupled to the first integrated device and the second integrated device. The method forms a first plurality of solder pillar interconnects and a second plurality of solder pillar interconnects so that the first plurality of solder pillar interconnects and the second plurality of solder pillar interconnects are coupled to the first metallization portion. The method couples a first core particle and a second core particle to the first metallization portion. The method forms another encapsulation layer that encapsulates the first plurality of solder pillar interconnects, the second plurality of solder pillar interconnects, the first core particle, and the second core particle. The method forms a second metallization portion so that the second metallization portion is coupled to the first core particle and the second core particle.

[0012] Another example provides a method for manufacturing a package. The method forms a second metallization portion. The method forms a first plurality of solder pillar interconnects and a second plurality of solder pillar interconnects, so that the first plurality of solder pillar interconnects and the second plurality of solder pillar interconnects are coupled to the second metallization portion. The method couples a first core particle and a second core particle to the second metallization portion. The method forms an encapsulation layer that encapsulates the first plurality of solder pillar interconnects, the second plurality of solder pillar interconnects, the first core particle, and the second core particle. The method forms a first metallization portion, so that the first metallization portion is coupled to the first core particle and the second core particle. The method couples a first integrated device and a second integrated device to the first metallization portion. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various features, characteristics and advantages will become apparent when the detailed description set forth below is read in conjunction with the accompanying drawings in which like reference numerals designate corresponding features throughout.

[0014] Figure 1 A plan view of a package including an integrated device, metallization, and a deep trench capacitor between the integrated device and the metallization is illustrated.

[0015] Figure 2 A plan view of a package including an integrated device, metallization, and a deep trench capacitor between the integrated device and the metallization is illustrated.

[0016] Figure 3 A plan view of a package including an integrated device, metallization, and a die between the integrated device and the metallization is illustrated.

[0017] Figure 4 A plan view of a package including multiple integrated devices, metallization, and multiple deep trench capacitors is illustrated.

[0018] Figure 5 A plan view of a package including multiple integrated devices, metallization, a bridge, and multiple deep trench capacitors is illustrated.

[0019] Figure 6 A plan view of a package including multiple integrated devices, metallization, a bridge, and multiple die is illustrated.

[0020] Figure 7 A plan view of a package including multiple integrated devices, metallization, and multiple deep trench capacitors is illustrated.

[0021] Figure 8 A plan view of a package including multiple integrated devices, metallization, a bridge, and multiple deep trench capacitors is illustrated.

[0022] Fig. 9 A plan view of a package including multiple integrated devices, metallization, a bridge, and multiple die is illustrated.

[0023] Fig.10 A plan view of a package including multiple integrated devices, metallization, a bridge, and multiple deep trench capacitors is illustrated.

[0024] Fig.11 A cutaway cross-sectional view of a deep trench capacitor is illustrated.

[0025] Fig. 12A -12D illustrates an exemplary process for fabricating a deep trench capacitor.

[0026] Fig.13 An exemplary flow chart illustrating a method for fabricating a deep trench capacitor is illustrated.

[0027] Fig.14A -14D illustrates an exemplary process for fabricating a package including multiple integrated devices, metallization, a bridge, and multiple deep trench capacitors.

[0028] Fig.15A -15C illustrates an exemplary process for fabricating a package including multiple integrated devices, metallization, a bridge, and multiple deep trench capacitors.

[0029] Fig.16A -16C illustrates an exemplary process for fabricating a package including multiple integrated devices, metallization, a bridge, and multiple deep trench capacitors.

[0030] Figures 17A-17B An exemplary process for manufacturing a substrate is illustrated.

[0031] Fig.18 An exemplary flow chart of a method for manufacturing a substrate is illustrated.

[0032] Fig.19 Various electronic devices are illustrated that may integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. DETAILED DESCRIPTION

[0033] In the following description, specific details are given to provide a thorough understanding of various aspects of the present disclosure. However, it will be understood by those of ordinary skill in the art that these aspects can be practiced without these specific details. For example, circuits may be shown with block diagrams to avoid burying these aspects in unnecessary details. In other examples, well-known circuits, structures, and techniques may not be shown in detail to avoid burying these aspects of the present disclosure.

[0034] The present disclosure describes a package, which includes a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion through a first plurality of solder pillar interconnects, a first core particle located between the first metallization portion and the second metallization portion, and a second core particle located between the first metallization portion and the second metallization portion, wherein the first core particle is configured to be electrically coupled to the first integrated device through the first metallization portion, wherein the second core particle is configured to be electrically coupled to the second integrated device through the first metallization portion. The first core particle may include a first active core particle or a first passive core particle. The second core particle may include a second active core particle or a second passive core particle. Positioning the first core particle close to the first integrated device and positioning the second core particle close to the second integrated device helps to improve the performance of the package. Reducing the electrical path between the first integrated device and the first core particle and / or the electrical path between the second integrated device and the second core particle helps to reduce the waiting time of the signal and / or current, which can help to improve the performance of the package. As will be further described below, instead of one integrated device performing all functions of a package, the various functions of the package are performed by different integrated devices and / or different cores. By redistributing the functions of the package to different integrated devices and / or different cores, cost savings in manufacturing the package can be achieved while still providing a package with high performance capabilities.

[0035] Example Package Including Integrated Device and Chip

[0036] Figure 1 A cross-sectional cutaway view of a package 100 including an integrated device and a die is illustrated. The package 100 includes a metallization portion 102, an integrated device 104, a die 106, a plurality of solder pillar interconnects 107, and an encapsulation layer 108. The plurality of solder pillar interconnects 107 include a plurality of solder pillar interconnects 107a and a plurality of solder pillar interconnects 107b. The package 100 is coupled to a substrate 109 via a plurality of solder interconnects 196. In some implementations, the substrate 109 may be considered a part of the package 100. A plurality of solder interconnects 198 are coupled to the bottom of the substrate 109. The substrate 109 may be configured to be coupled to a board (not shown) (such as a printed circuit board (PCB)) via a plurality of solder interconnects 198. The substrate 109 includes at least one dielectric layer 190 (e.g., at least one substrate dielectric layer) and a plurality of interconnects 192 (e.g., a plurality of substrate interconnects).

[0037] The integrated device 104 is coupled to the metallization portion 102 via a plurality of solder pillar interconnects 107a. The integrated device 104 is coupled to the core 106 via a plurality of solder pillar interconnects 107b and a plurality of solder interconnects 140. The plurality of solder pillar interconnects 107b may be located between the integrated device 104 and the core 106. The plurality of solder pillar interconnects 107b may include a plurality of solder pillar interconnects. The plurality of solder pillar interconnects may be similar to the plurality of solder pillar interconnects 107a. However, the plurality of solder pillar interconnects may be shorter than the plurality of solder pillar interconnects 107a. The plurality of solder pillar interconnects may be located between the integrated device 104 and the core 106. The core 106 is coupled to the metallization portion 102. The core 106 may be configured as a passive core. The core 106 may be configured as a trench capacitor device (e.g., a deep trench capacitor (DTC) device). The core 106 is located between the metallization portion 102 and the integrated device 104. The core 106 includes a front side and a back side. The front side of the die 106 faces the integrated device 104. For example, the front side of a deep trench capacitor faces the integrated device 104.

[0038] The core particle 106 includes a die substrate 160, a plurality of through-substrate vias 162, a plurality of trench interconnects 164, a plurality of trench interconnects 166, and a plurality of trench capacitors 167. The plurality of trench interconnects 164 are located on the front side (e.g., top side) of the core particle 106. The plurality of trench interconnects 166 are located on the back side (e.g., bottom side) of the core particle 106. One or more through-substrate vias from the plurality of through-substrate vias 162 can be coupled to one or more trench capacitors from the plurality of trench capacitors 167. The plurality of through-substrate vias 162 can be coupled to the plurality of trench interconnects 164 and the plurality of trench interconnects 166. The plurality of trench interconnects 164 are coupled to the plurality of solder pillar interconnects 107b through the plurality of solder interconnects 140. Thus, for example, the plurality of solder interconnects 140 are coupled to the plurality of trench interconnects 164 and the plurality of solder pillar interconnects 107b. The plurality of trench interconnects 166 can be coupled (e.g., directly coupled) to the metallization portion 102. For example, the plurality of trench interconnects 166 may be configured to be directly coupled to the metallization interconnects 121 from the metallization portion 102, such that the plurality of trench interconnects 166 contact the plurality of metallization interconnects 121 from the metallization portion 102. The plurality of trench interconnects 166 may be optional. In some implementations, the plurality of through-substrate vias 162 may be configured to be coupled (e.g., directly coupled) to the metallization portion 102. For example, the plurality of through-substrate vias 162 may be configured to be directly coupled to the metallization interconnects 121 from the metallization portion 102, such that the plurality of through-substrate vias 162 contact the plurality of metallization interconnects 121 from the metallization portion 102. More detailed examples of trench capacitors are described below in at least some embodiments of the present disclosure. Fig.11 The front side of the die faces the integrated device 104 .

[0039] The metallization portion 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 121. The metallization portion 102 may include a redistribution portion. The plurality of metallization interconnects 121 may include a plurality of redistribution interconnects. The metallization portion 102 may be a device for metallization interconnects. The plurality of metallization interconnects 121 may be coupled to the back side of the core particle 106. For example, the plurality of metallization interconnects 121 may be coupled to a plurality of trench interconnects 166 or a plurality of through-substrate vias 162. The plurality of metallization interconnects 121 may be coupled to a plurality of solder pillar interconnects 107a.

[0040] As mentioned above, the metallization portion (e.g., 102, 702) may include a redistribution portion that includes a redistribution interconnect (e.g., a redistribution layer (RDL) interconnect). The redistribution interconnect may include a portion having a U-shape or a V-shape. The terms "U-shape" and "V-shape" should be interchangeable. The terms "U-shape" and "V-shape" may refer to the side profile shape of an interconnect and / or a redistribution interconnect. A U-shaped interconnect (e.g., a U-shaped side profile interconnect) and a V-shaped interconnect (e.g., a V-shaped side profile interconnect) may have a top and a bottom. The bottom of a U-shaped interconnect (or a V-shaped interconnect) may be coupled to the top of another U-shaped interconnect (or a V-shaped interconnect).

[0041] One or more electrical paths (eg, first electrical path, second electrical path, third electrical path) between metallization portion 102 and integrated device 104 may include at least one metallization interconnect from plurality of metallization interconnects 121 and at least one solder pillar interconnect from plurality of solder pillar interconnects 107a.

[0042] One or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the metallization portion 102 and the integrated device 104 may include at least one metallization interconnect from the plurality of metallization interconnects 121, at least one trench interconnect from the plurality of trench interconnects 166, at least one through-substrate through-via from the plurality of through-substrate vias 162, at least one trench interconnect from the plurality of trench interconnects 164, at least one solder interconnect from the plurality of solder interconnects 140, and / or at least one solder pillar interconnect from the plurality of solder pillar interconnects 107b.

[0043] The integrated device 104 may be configured to be electrically coupled to the core 106 via a plurality of solder pillar interconnects 107 b and a plurality of solder interconnects 140. Thus, one or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the integrated device 104 and the core 106 may include at least one solder pillar interconnect from the plurality of solder pillar interconnects 107 b and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0044] The encapsulation layer 108 may be coupled to the metallization 102, the integrated device 104, and the die 106. The encapsulation layer 108 may be coupled to the plurality of pillar interconnects 107. The encapsulation layer 108 may be coupled to a first surface (e.g., a top surface) of the metallization 102. The encapsulation layer 108 may (e.g., partially or completely) encapsulate the integrated device 104 and the die 106. Figure 1 The back side of the integrated device 104 is illustrated as being exposed and not covered by an encapsulation layer. However, in some implementations, the back side of the integrated device 104 may be coupled to an encapsulation layer 108. The encapsulation layer 108 may include a molding, a resin, and / or an epoxy. The encapsulation layer 108 may be a means for encapsulation. The encapsulation layer 108 may be provided using a compression and transfer molding process, a sheet molding process, or a liquid molding process.

[0045] The metallization 102 is coupled to the substrate 109 through the plurality of solder interconnects 196. For example, a metallization interconnect from the plurality of metallization interconnects 121 can be coupled to an interconnect from the plurality of interconnects 192 through the plurality of solder interconnects 196. The underfill 105 is coupled to the substrate 109, the metallization 102, and the encapsulation layer 108. The underfill 105 can be considered as part of the package 100.

[0046] The location and / or placement of the core particle 106 near the integrated device 104 helps reduce signal and / or current delays between the integrated device 104 and the core particle 106, which helps improve the performance of the integrated device 104 and / or the package 100. The core particle 106 is described as being configured as a deep trench capacitor. However, as will be further described below, different implementations may use core particles configured to perform other operations and / or functionalities.

[0047] exist Figure 1 in the package and at least Figure 2-10 The use of integrated devices, die, and metallization in a package as described herein provides several advantages. One advantage is that redistributing various functions of a package across at least one integrated device and at least one die may result in cost savings for the package. The integrated device and die may be manufactured using different technology nodes that may have different costs.

[0048] A technology node may refer to a specific manufacturing process and / or technology for manufacturing an integrated device and / or a core particle. A technology node may specify the minimum possible size (e.g., minimum size) that can be manufactured (e.g., the size of a transistor, the width of a trace, the gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Compared with technology nodes that produce components with less fine details (e.g., traces, transistors), technology nodes that produce components with fine details (e.g., traces, transistors) are more expensive and may have higher yield losses. Therefore, more advanced technology nodes may be more expensive and may have higher yield losses compared to less advanced technology nodes. When all functions of a package are implemented in a single integrated device, even if some of the functions of the integrated device do not need to be manufactured using the specific technology node, the same technology node is used to manufacture the entire integrated device. Thus, the integrated device is locked into one technology node. In order to optimize the cost of the package, some functions may be implemented in different integrated devices and / or core particles, where different integrated devices and / or core particles may be manufactured using different technology nodes to reduce the total cost. For example, functions that require the use of the most advanced technology node may be implemented in an integrated device, and functions that can be implemented using a less advanced technology node may be implemented in another integrated device and / or one or more core particles. An example would be an integrated device configured to provide a computing application manufactured using a first technology node (e.g., the most advanced technology node), and at least one core particle configured to provide other functionality manufactured using a second technology node, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node manufactures components with a minimum size that is greater than the minimum size of components manufactured using the first technology node. Examples of computing applications may include high performance computing and / or high performance processing, which may be achieved by manufacturing and packaging as many transistors as possible in an integrated device, which is why an integrated device configured for a computing application may be manufactured using the most advanced technology node available, while other core particles may be manufactured using less advanced technology nodes, as those core particles may not require as many transistors to be manufactured in the core particles. Therefore, the combination of using different technology nodes (which may have different associated yield losses) for different integrated devices and / or core particles may reduce the overall cost of the package compared to using a single integrated device to perform all functions of the package.

[0049] Another advantage of splitting the functionality into several integrated devices and / or core particles is that it allows the performance of the package to be improved without having to redesign each individual integrated device and / or core particle. For example, if the configuration of the package uses a first integrated device and a first core particle, the performance of the package can be improved by changing the design of the first integrated device while keeping the design of the first core particle the same. Thus, the first core particle can be reused with an improved and / or differently configured first integrated device. This saves costs by not having to redesign the first core particle when manufacturing a package with an improved integrated device.

[0050] In addition, the core particle can be coupled to the integrated device by copper-to-copper hybrid bonding or by solder interconnection, so that the core particle is very close to the integrated device. For example, the core particle and the integrated device can be implemented with a metallization portion (e.g., a redistribution portion) to position the core particle as close to the integrated device as possible, which reduces the electrical path between the core particle and the integrated device. This helps to improve the performance of the integrated device and the power provided to the integrated device. In some implementations, the minimum spacing of the interconnects coupled to the core particle can be as small as about 20 microns.

[0051] In addition, core particles including trench capacitors provide several technical benefits. Trench capacitors and / or trench capacitor devices provide capacitors with high capacitance and / or high capacitance density. Capacitors with higher capacitance density allow for a more compact form factor for the package because these capacitors take up less space but are able to provide the same and / or comparable capacitance as larger sized capacitors. The compact form factor of the trench capacitors allows them to be located very close to the integrated device, which can help improve the power delivery performance to the integrated device. In addition, because these trench capacitors have a small form factor, they can be implemented with metallization portions rather than in the package substrate. Thus, high capacitance capacitors can be implemented during the manufacture of the package rather than when the package is coupled to the substrate.

[0052] High capacitance capacitors are particularly important in certain types of processing operations, such as computing applications (e.g., high performance processing). The use of die, integrated devices, and metallization portions as described in the present disclosure helps improve die-to-die communications, which helps improve the overall performance of the integrated devices and packages.

[0053] Figure 2 A cross-sectional view of a package 200 including an integrated device and a die is illustrated. The package 200 includes a metallization portion 102, an integrated device 104, a die 106, a plurality of solder pillar interconnects 107, an encapsulation layer 108, an encapsulation layer 208, and a dielectric layer 281. The package 200 and Figure 1The die 106 is similar to the package 100 of FIG. 1 and thus includes the same or similar components arranged and / or configured in the same and / or similar manner as the package 100. For example, the die 106 may be configured to operate as a deep trench capacitor, such as at least Fig.11 The deep trench capacitor described in .

[0054] The package 200 includes two encapsulation layers separated by a dielectric layer. Encapsulation layer 108 can be a first encapsulation layer and encapsulation layer 208 can be a second encapsulation layer. Dielectric layer 281 is located between encapsulation layer 108 and encapsulation layer 208. Dielectric layer 281 is coupled to the inner surface of encapsulation layer 108 and the inner surface of encapsulation layer 208. Dielectric layer 281 can include polyimide (PI). In some implementations, encapsulation layer 208 can be the same as encapsulation layer 108. In some implementations, encapsulation layer 208 can have one or more properties that are different from encapsulation layer 108. For example, encapsulation layer 108 can include a higher concentration of filler than encapsulation layer 208. As will be described below at least in Fig.14A As further described in , the plurality of solder pillar interconnects 107 may include a seed layer (e.g., a metal seed layer, a copper seed layer) that is planar with the dielectric layer 281. The encapsulation layer 108 is coupled to the integrated device 104, at least a portion of the plurality of solder pillar interconnects 107a, and at least a portion of the plurality of solder pillar interconnects 107b. The encapsulation layer 208 is coupled to the metallization portion 102, the core particle 106, the plurality of solder interconnects 140, and at least a portion of the plurality of solder pillar interconnects 107a.

[0055] Figure 3 A cross-sectional view of a package 300 including an integrated device and a die is illustrated. The package 300 includes a metallization portion 102, an integrated device 104, a die 306, a plurality of solder pillar interconnects 107, an encapsulation layer 108, an encapsulation layer 208, and a dielectric layer 281. The package 300 and Figure 1 Package 100 and / or Figure 2 Package 200 is similar to package 100 and / or package 200 , and thus includes the same or similar components arranged and / or configured in the same and / or similar manner as package 100 and / or package 200 .

[0056] Core particle 306 may be configured to provide functionality different from core particle 106. Core particle 306 may be configured as an active core particle or a passive core particle. Core particle 306 may be configured to operate as a memory (e.g., a first memory, a second memory), a power management integrated circuit (PMIC) (e.g., a first power management integrated circuit, a second power management integrated circuit), and / or a voltage regulator (e.g., a first voltage regulator, a second voltage regulator). Core particle 306 may include an integrated device that is smaller in size than integrated device 104. Chip 306 may include a die substrate, a plurality of die transistors, and a plurality of die interconnects (all not shown). In some implementations, core particle 306 may include a plurality of through-substrate vias (not shown).

[0057] The die 306 is coupled to the integrated device 104 through the plurality of solder pillar interconnects 104 and the plurality of solder interconnects 107b. The front side of the die 306 faces the integrated device 104. Figure 3 The back side of the die 306 is illustrated as not contacting the metallization 102. However, in some implementations, the die 306 may contact the metallization 102. In some implementations, the back side of the die 306 may contact the metallization 102. For example, the back side of the die 306 may contact the metallization 102. Figure 1 and Figure 2 The die 106 may contact and / or be coupled to the metallization interconnect 121 of the metallization portion 102 in a manner similar to that described above. The front side of the die 306 may face the integrated device 104.

[0058] Figure 4 A package 400 including at least two integrated devices and at least two die is illustrated. The package 400 includes an integrated device 104, a die 106, an integrated device 404, a die 406, a metallization 102, and an encapsulation layer 108. The die 106 is located between the integrated device 104 and the metallization 102. The die 406 is located between the integrated device 404 and the metallization 102. The encapsulation layer 108 encapsulates the integrated device 104, the integrated device 404, the die 106, and the die 406. The encapsulation layer 108 may be coupled to the metallization 102.

[0059] The package 400 is coupled to the substrate 109 through a plurality of solder interconnects 196. A plurality of solder interconnects 198 may be coupled to the substrate 109. The underfill 105 is coupled to the substrate 109, the metallization 102, and the encapsulation layer 108.

[0060] The integrated device 104 is coupled to the metallization portion 102 through a plurality of solder pillar interconnects 107a. The integrated device 104 is coupled to the core 106 through a plurality of solder pillar interconnects 107b and a plurality of solder interconnects 140. The plurality of solder pillar interconnects 107b may be located between the integrated device 104 and the core 106. The core 106 is coupled to the metallization portion 102. The core 106 may be configured as a passive core. The core 106 may be configured as a deep trench capacitor (DTC). The core 106 is located between the metallization portion 102 and the integrated device 104. The core 106 includes a front side and a back side. The front side of the core 106 faces the integrated device 104. For example, the front side of the deep trench capacitor faces the integrated device 104.

[0061] Integrated device 404 is coupled to metallization portion 102 via multiple solder pillar interconnects 407a. Integrated device 404 is coupled to core 406 via multiple solder pillar interconnects 407b and multiple solder interconnects 440. Multiple solder pillar interconnects 407b may be located between integrated device 404 and core 406. Multiple solder pillar interconnects 407b may include multiple solder pillar interconnects. Multiple solder pillar interconnects may be similar to multiple solder pillar interconnects 407a. However, multiple solder pillar interconnects may be shorter than multiple solder pillar interconnects 407a. Multiple solder pillar interconnects may be located between integrated device 404 and core 406. Core 406 is coupled to metallization portion 102. Core 406 may be configured as a passive core. Core 406 may be configured as a deep trench capacitor (DTC). Core 406 is located between metallization portion 102 and integrated device 404. Core 406 includes a front side and a back side. The front side of the die 406 faces the integrated device 404. For example, the front side of a deep trench capacitor faces the integrated device 404.

[0062] Integrated device 104 may be configured to be electrically coupled to integrated device 404 through metallization portion 102. For example, integrated device 104 may be configured to be electrically coupled to integrated device 404 through an electrical path including (i) at least one solder pillar interconnect from the plurality of solder pillar interconnects 107a, (ii) at least one metallization interconnect from the plurality of metallization interconnects 121, and (iii) at least one solder pillar interconnect from the plurality of solder pillar interconnects 407a.

[0063] One or more electrical paths (eg, first electrical path, second electrical path, third electrical path) between metallization portion 102 and integrated device 104 may include at least one metallization interconnect from plurality of metallization interconnects 121 and at least one solder pillar interconnect from plurality of solder pillar interconnects 107a.

[0064] One or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the metallization portion 102 and the integrated device 104 may include at least one metallization interconnect from the plurality of metallization interconnects 121, at least one trench interconnect from the plurality of trench interconnects 166, at least one through-substrate through-via from the plurality of through-substrate vias 162, at least one trench interconnect from the plurality of trench interconnects 164, at least one solder interconnect from the plurality of solder interconnects 140, and / or at least one solder pillar interconnect from the plurality of solder pillar interconnects 107b.

[0065] The integrated device 104 may be configured to be electrically coupled to the core 106 via a plurality of solder pillar interconnects 107 b and a plurality of solder interconnects 140. Thus, one or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the integrated device 104 and the core 106 may include at least one solder pillar interconnect from the plurality of solder pillar interconnects 107 b and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0066] One or more electrical paths (eg, first electrical path, second electrical path, third electrical path) between metallization portion 102 and integrated device 404 may include at least one metallization interconnect from plurality of metallization interconnects 121 and at least one solder pillar interconnect from plurality of solder pillar interconnects 407a.

[0067] One or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the metallization portion 102 and the integrated device 404 may include at least one metallization interconnect from the plurality of metallization interconnects 121, at least one trench interconnect from the plurality of trench interconnects 466, at least one through-substrate through-via from the plurality of through-substrate vias 462, at least one trench interconnect from the plurality of trench interconnects 464, at least one solder interconnect from the plurality of solder interconnects 440, and / or at least one solder pillar interconnect from the plurality of solder pillar interconnects 407b.

[0068] The integrated device 404 may be configured to be electrically coupled to the core 406 via a plurality of solder pillar interconnects 407b and a plurality of solder interconnects 440. Thus, one or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the integrated device 404 and the core 406 may include at least one solder pillar interconnect from the plurality of solder pillar interconnects 407b and / or at least one solder interconnect from the plurality of solder interconnects 440.

[0069] Figure 5A package 500 including a bridge, at least two integrated devices, and at least two cores is illustrated. The package 500 includes the integrated device 104, the core 106, the integrated device 404, the core 406, the metallization 102, the bridge 505, and the encapsulation layer 108. The package 500 is similar to the package 400 and can be configured in a manner similar to that described for the package 400. The core 106 is located between the integrated device 104 and the metallization 102. The core 406 is located between the integrated device 404 and the metallization 102. The encapsulation layer 108 encapsulates the integrated device 104, the integrated device 404, the core 106, the core 406, and the bridge 505. The encapsulation layer 108 can be coupled to the metallization 102.

[0070] The bridge 505 may include a die substrate and a plurality of bridge interconnects. The bridge 505 may include a dielectric layer. The bridge 505 is coupled to the metallization 102. The front side of the bridge 505 may be coupled to the metallization 102.

[0071] Integrated device 104 may be configured to be electrically coupled to integrated device 404 through metallization 102 and bridge 505. For example, integrated device 104 may be configured to be electrically coupled to integrated device 404 through an electrical path that includes: (i) at least one solder pillar interconnect from the plurality of solder pillar interconnects 107a, (ii) at least one metallization interconnect from the plurality of metallization interconnects 121, (iii) at least one die interconnect from bridge 505, (iv) at least one metallization interconnect from the plurality of metallization interconnects 121, and (v) at least one solder pillar interconnect from the plurality of solder pillar interconnects 407a.

[0072] In some implementations, package 400 and / or package 500 may include dielectric layer 281 in encapsulation layer 108 in a manner similar to that described with respect to package 200 and / or package 300 .

[0073] Figure 6 A package 600 including a bridge, at least two integrated devices, and at least two die is illustrated. The package 600 includes the integrated device 104, the die 306, the integrated device 404, the die 606, the metallization 102, the bridge 505, and the encapsulation layer 108. The package 600 is similar to the package 400 and the package 500, and can be configured in a manner similar to that described for the package 400 and the package 500. The die 306 is located between the integrated device 104 and the metallization 102. The die 606 is located between the integrated device 404 and the metallization 102. The encapsulation layer 108 encapsulates the integrated device 104, the integrated device 404, the die 306, the die 606, and the bridge 505. The encapsulation layer 108 can be coupled to the metallization 102.

[0074] The bridge 505 may include a die substrate and a plurality of bridge interconnects. The bridge 505 may include a dielectric layer. The bridge 505 is coupled to the metallization 102. The front side of the bridge 505 may be coupled to the metallization 102.

[0075] Integrated device 104 may be configured to be electrically coupled to integrated device 404 through metallization 102 and bridge 505. For example, integrated device 104 may be configured to be electrically coupled to integrated device 404 through an electrical path that includes: (i) at least one solder pillar interconnect from the plurality of solder pillar interconnects 107a, (ii) at least one metallization interconnect from the plurality of metallization interconnects 121, (iii) at least one die interconnect from bridge 505, (iv) at least one metallization interconnect from the plurality of metallization interconnects 121, and (v) at least one solder pillar interconnect from the plurality of solder pillar interconnects 407a.

[0076] The integrated device 104 may be configured to be electrically coupled to the core 306 via the plurality of solder pillar interconnects 107 b and the plurality of solder interconnects 140. Thus, one or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the integrated device 104 and the core 306 may include at least one solder pillar interconnect from the plurality of solder pillar interconnects 107 b and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0077] The integrated device 404 may be configured to be electrically coupled to the core 606 via the plurality of solder pillar interconnects 207 b and the plurality of solder interconnects 240. Thus, one or more electrical paths (e.g., a first electrical path, a second electrical path, a third electrical path) between the integrated device 404 and the core 606 may include at least one solder pillar interconnect from the plurality of solder pillar interconnects 207 b and / or at least one solder interconnect from the plurality of solder interconnects 240.

[0078] Figure 7 A package 700 including at least two integrated devices and at least two cores is illustrated. The package 700 includes an integrated device 104, a core 106, an integrated device 404, a core 406, a metallization 102, a metallization 702, an encapsulation layer 108, and an encapsulation layer 708. The metallization 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 121. The metallization 702 includes at least one dielectric layer 720 and a plurality of metallization interconnects 721. The encapsulation layer 108 encapsulates the integrated device 104, the integrated device 404. The encapsulation layer 108 may be coupled to the metallization 102.

[0079] The core 106 is located between the metallization 102 and the metallization 702. The core 106 can be coupled to the metallization 102 through a plurality of solder interconnects 710. The plurality of solder interconnects 710 can be coupled to at least one interconnect from the core 106 and at least one of the plurality of metallization interconnects 121 from the metallization 102. The core 106 can contact the metallization 702. For example, an interconnect from the core 106 can contact at least one of the plurality of metallization interconnects 721 from the metallization 702. The core 406 is located between the metallization 102 and the metallization 702. The core 406 can be coupled to the metallization 102 through a plurality of solder interconnects 740. The core 406 can contact the metallization 702. For example, an interconnect from the core 406 can contact at least one of the plurality of metallization interconnects 721 from the metallization 702.

[0080] The encapsulation layer 708 may encapsulate the die 106 and the die 406. The encapsulation layer 708 may be coupled to the metallization 102 and the metallization 702. A plurality of through-mold vias 780 may be located in the encapsulation layer 708. The plurality of through-mold vias 780 are located between the metallization 102 and the metallization 702. The plurality of through-mold vias 780 may be configured to be coupled to the metallization 102 and the metallization 702. For example, the plurality of through-mold vias 780 may be configured to be coupled to (i) the plurality of metallization interconnects 121 of the metallization 102 and (ii) the plurality of metallization interconnects 721 of the metallization 702.

[0081] The integrated device 104 is configured to be electrically coupled to the integrated device 404 through the metallization portion 102. For example, the electrical path between the integrated device 104 and the integrated device 404 may include at least one metallization interconnect from the plurality of metallization interconnects 121 of the metallization portion 102. The electrical path between the integrated device 104 and the integrated device 404 may be configured for signals (e.g., input / output signals) between the integrated device 104 and the integrated device 404.

[0082] In some implementations, an electrical path between the substrate 709 and the integrated device 104 (e.g., configured to provide power) may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) the core particle 106, (iv) at least one solder interconnect from the plurality of solder interconnects 710, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0083] In some implementations, the electrical path between substrate 709 and integrated device 104 may include (i) at least one solder interconnect from multiple solder interconnects 196, (ii) at least one metallization interconnect from multiple metallization interconnects 721, (iii) at least one through-mold via from multiple through-mold vias 780, and (iv) at least one metallization interconnect from multiple metallization interconnects 121.

[0084] In some implementations, an electrical path between the substrate 709 and the integrated device 404 (e.g., configured to provide power) may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) the core particle 406, (iv) at least one solder interconnect from the plurality of solder interconnects 740, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0085] In some implementations, the electrical path between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, and (iv) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0086] Integrated device 104 is configured to be electrically coupled to die 106. For example, integrated device 104 may be configured to be electrically coupled to die 106 through an electrical path including at least one metallization interconnect from plurality of metallization interconnects 121 and at least one solder interconnect from plurality of solder interconnects 710.

[0087] Integrated device 404 is configured to be electrically coupled to die 406. For example, integrated device 404 may be configured to be electrically coupled to die 406 through an electrical path including at least one metallization interconnect from plurality of metallization interconnects 121 and at least one solder interconnect from plurality of solder interconnects 740.

[0088] Figure 8A package 800 including at least two integrated devices and at least two die is illustrated. The package 800 is similar to the package 700, and thus the package 800 can be configured in a manner similar to that described for the package 700. The package 800 includes the integrated device 104, the die 106, the integrated device 404, the die 406, the metallization 102, the metallization 702, the bridge 505, the encapsulation layer 108, and the encapsulation layer 708. The metallization 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 121. The metallization 702 includes at least one dielectric layer 720 and a plurality of metallization interconnects 721. The encapsulation layer 108 encapsulates the integrated device 104, the integrated device 404. The encapsulation layer 108 can be coupled to the metallization 102.

[0089] The core 106 is located between the metallization 102 and the metallization 702. The core 106 can be coupled to the metallization 102 through a plurality of solder interconnects 710. The plurality of solder interconnects 710 can be coupled to at least one interconnect from the core 106 and at least one of the plurality of metallization interconnects 121 from the metallization 102. The core 106 can contact the metallization 702. For example, an interconnect from the core 106 can contact at least one of the plurality of metallization interconnects 721 from the metallization 702. The core 406 is located between the metallization 102 and the metallization 702. The core 406 can be coupled to the metallization 102 through a plurality of solder interconnects 740. The core 406 can contact the metallization 702. For example, an interconnect from the core 406 can contact at least one of the plurality of metallization interconnects 721 from the metallization 702.

[0090] The bridge 505 is located between the metallization 102 and the metallization 702. The bridge 505 is coupled to the metallization 102 through a plurality of solder interconnects 850. The bridge 505 may include a die substrate and a plurality of bridge interconnects. The bridge 505 may include a dielectric layer. The front side of the bridge 505 may be coupled to the metallization 102.

[0091] The encapsulation layer 708 may encapsulate the die 106, the die 406, and the bridge 505. The encapsulation layer 708 may be coupled to the metallization 102 and the metallization 702. A plurality of through-mold vias 780 may be located in the encapsulation layer 708. The plurality of through-mold vias 780 are located between the metallization 102 and the metallization 702. The plurality of through-mold vias 780 may be configured to be coupled to the metallization 102 and the metallization 702. For example, the plurality of through-mold vias 780 may be configured to be coupled to (i) the plurality of metallization interconnects 121 of the metallization 102 and (ii) the plurality of metallization interconnects 721 of the metallization 702.

[0092] The integrated device 104 is configured to be electrically coupled to the integrated device 404 through the metallization portion 102 and the bridge 505. For example, the electrical path between the integrated device 104 and the integrated device 404 may include (i) at least one metallization interconnect from the plurality of metallization interconnects 121 of the metallization portion 102, (ii) at least one solder interconnect from the plurality of solder interconnects 850, (iii) the bridge 505, (iv) at least one solder interconnect from the plurality of solder interconnects 850, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121 from the metallization portion 102. The electrical path between the integrated device 104 and the integrated device 404 may be configured for signals (e.g., input / output signals) between the integrated device 104 and the integrated device 404.

[0093] In some implementations, an electrical path between the substrate 709 and the integrated device 104 (e.g., configured to provide power) may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) the core particle 106, (iv) at least one solder interconnect from the plurality of solder interconnects 710, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0094] In some implementations, the electrical path between substrate 709 and integrated device 104 may include (i) at least one solder interconnect from multiple solder interconnects 196, (ii) at least one metallization interconnect from multiple metallization interconnects 721, (iii) at least one through-mold via from multiple through-mold vias 780, and (iv) at least one metallization interconnect from multiple metallization interconnects 121.

[0095] In some implementations, an electrical path between the substrate 709 and the integrated device 404 (e.g., configured to provide power) may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) the core particle 406, (iv) at least one solder interconnect from the plurality of solder interconnects 740, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0096] In some implementations, the electrical path between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, and (iv) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0097] Integrated device 104 is configured to be electrically coupled to die 106. For example, integrated device 104 may be configured to be electrically coupled to die 106 through an electrical path including at least one metallization interconnect from plurality of metallization interconnects 121 and at least one solder interconnect from plurality of solder interconnects 710.

[0098] Integrated device 404 is configured to be electrically coupled to die 406. For example, integrated device 404 may be configured to be electrically coupled to die 406 through an electrical path including at least one metallization interconnect from plurality of metallization interconnects 121 and at least one solder interconnect from plurality of solder interconnects 740.

[0099] Fig. 9 A package 900 including at least two integrated devices and at least two die is illustrated. The package 900 is similar to the package 800, and thus the package 900 can be configured in a manner similar to that described for the package 800. The package 900 includes the integrated device 104, the die 306, the integrated device 404, the die 606, the metallization 102, the metallization 702, the bridge 505, the encapsulation layer 108, and the encapsulation layer 708. The metallization 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 121. The metallization 702 includes at least one dielectric layer 720 and a plurality of metallization interconnects 721. The encapsulation layer 108 encapsulates the integrated device 104, the integrated device 404. The encapsulation layer 108 can be coupled to the metallization 102.

[0100] The core 306 is located between the metallization 102 and the metallization 702. The core 306 can be coupled to the metallization 102 through a plurality of solder interconnects 710. The plurality of solder interconnects 710 can be coupled to at least one interconnect from the core 306 and at least one of the plurality of metallization interconnects 121 from the metallization 102. The core 306 can contact the metallization 702. For example, an interconnect from the core 306 can contact at least one of the plurality of metallization interconnects 721 from the metallization 702. The core 606 is located between the metallization 102 and the metallization 702. The core 606 can be coupled to the metallization 102 through a plurality of solder interconnects 740. The core 606 can contact the metallization 702. For example, an interconnect from the core 606 can contact at least one of the plurality of metallization interconnects 721 from the metallization 702.

[0101] The bridge 505 is located between the metallization 102 and the metallization 702. The bridge 505 is coupled to the metallization 102 through a plurality of solder interconnects 850. The bridge 505 may include a die substrate and a plurality of bridge interconnects. The bridge 505 may include a dielectric layer. The front side of the bridge 505 may be coupled to the metallization 102.

[0102] The encapsulation layer 708 may encapsulate the die 306, the die 606, and the bridge 505. The encapsulation layer 708 may be coupled to the metallization 102 and the metallization 702. A plurality of through-mold vias 780 may be located in the encapsulation layer 708. The plurality of through-mold vias 780 are located between the metallization 102 and the metallization 702. The plurality of through-mold vias 780 may be configured to be coupled to the metallization 102 and the metallization 702. For example, the plurality of through-mold vias 780 may be configured to be coupled to (i) the plurality of metallization interconnects 121 of the metallization 102 and (ii) the plurality of metallization interconnects 721 of the metallization 702.

[0103] The front side of bridge 505 faces metallization 102. The front side of die 306 faces metallization 102. The front side of die 606 faces metallization 102.

[0104] The integrated device 104 is configured to be electrically coupled to the integrated device 404 through the metallization portion 102 and the bridge 505. For example, the electrical path between the integrated device 104 and the integrated device 404 may include (i) at least one metallization interconnect from the plurality of metallization interconnects 121 of the metallization portion 102, (ii) at least one solder interconnect from the plurality of solder interconnects 850, (iii) the bridge 505, (iv) at least one solder interconnect from the plurality of solder interconnects 850, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121 from the metallization portion 102. The electrical path between the integrated device 104 and the integrated device 404 may be configured for signals (e.g., input / output signals) between the integrated device 104 and the integrated device 404.

[0105] In some implementations, an electrical path between substrate 709 and integrated device 104 (e.g., configured to provide power) may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) core particle 306, (iv) at least one solder interconnect from the plurality of solder interconnects 710, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0106] In some implementations, the electrical path between substrate 709 and integrated device 104 may include (i) at least one solder interconnect from multiple solder interconnects 196, (ii) at least one metallization interconnect from multiple metallization interconnects 721, (iii) at least one through-mold via from multiple through-mold vias 780, and (iv) at least one metallization interconnect from multiple metallization interconnects 121.

[0107] In some implementations, an electrical path between the substrate 709 and the integrated device 404 (e.g., configured to provide power) may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) the core particle 606, (iv) at least one solder interconnect from the plurality of solder interconnects 740, and (v) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0108] In some implementations, the electrical path between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, and (iv) at least one metallization interconnect from the plurality of metallization interconnects 121.

[0109] Integrated device 104 is configured to be electrically coupled to die 306. For example, integrated device 104 may be configured to be electrically coupled to die 306 through an electrical path including at least one metallization interconnect from plurality of metallization interconnects 121 and at least one solder interconnect from plurality of solder interconnects 710.

[0110] Integrated device 404 is configured to be electrically coupled to die 606. For example, integrated device 404 may be configured to be electrically coupled to die 606 through an electrical path including at least one metallization interconnect from plurality of metallization interconnects 121 and at least one solder interconnect from plurality of solder interconnects 740.

[0111] Fig.10 A package 1000 including at least two integrated devices and at least two die is illustrated. The package 1000 is similar to the package 900, and thus the package 1000 can be configured in a manner similar to that described for the package 1000. The package 1000 includes an integrated device 104, a die 106, an integrated device 404, a die 406, a metallization 102, a metallization 702, a bridge 505, an encapsulation layer 108, and an encapsulation layer 708. The metallization 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 121. The metallization 702 includes at least one dielectric layer 720 and a plurality of metallization interconnects 721. The encapsulation layer 108 encapsulates the integrated device 104, the integrated device 404. The encapsulation layer 108 can be coupled to the metallization 102.

[0112] The core 106 is located between the metallization 102 and the metallization 702. The core 106 can be coupled to the metallization 702 through a plurality of solder interconnects 710. The plurality of solder interconnects 710 can be coupled to at least one interconnect from the core 106 and at least one of the plurality of metallization interconnects 721 from the metallization 702. The core 106 can contact the metallization 102. For example, an interconnect from the core 106 can contact at least one of the plurality of metallization interconnects 121 from the metallization 102. The core 406 is located between the metallization 102 and the metallization 702. The core 406 can be coupled to the metallization 702 through a plurality of solder interconnects 740. The core 406 can contact the metallization 102. For example, an interconnect from the core 406 can contact at least one of the plurality of metallization interconnects 121 from the metallization 102.

[0113] The bridge 505 is located between the metallization 102 and the metallization 702. The bridge 505 is coupled to the metallization 102. The bridge 505 may include a die substrate and a plurality of die interconnects. The bridge 505 may include a dielectric layer. The front side of the bridge 505 may be coupled to the metallization 102. The back side of the bridge 505 may be coupled to the metallization 702 by an adhesive 1005. For example, the back side of the die substrate of the bridge 505 may be coupled to the metallization 702 by an adhesive 1005. The front side of the bridge 505 faces the metallization 102. The front side of the core 406 faces the metallization 102. The front side of the core 406 faces the metallization 102.

[0114] The encapsulation layer 708 may encapsulate the die 106, the die 406, and the bridge 505. The encapsulation layer 708 may be coupled to the metallization 102 and the metallization 702. A plurality of through-mold vias 780 may be located in the encapsulation layer 708. The plurality of through-mold vias 780 are located between the metallization 102 and the metallization 702. The plurality of through-mold vias 780 may be configured to be coupled to the metallization 102 and the metallization 702. For example, the plurality of through-mold vias 780 may be configured to be coupled to (i) the plurality of metallization interconnects 121 of the metallization 102 and (ii) the plurality of metallization interconnects 721 of the metallization 702.

[0115] The integrated device 104 is coupled to the metallization 102 through a plurality of solder interconnects 1010. The integrated device 404 is coupled to the metallization 102 through a plurality of solder interconnects 1030. The integrated device 104 is configured to be electrically coupled to the integrated device 404 through the metallization 102 and the bridge 505. For example, the electrical path between the integrated device 104 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 1010, (ii) at least one metallization interconnect from the plurality of metallization interconnects 121 from the metallization 102, (iii) the bridge 505, (iv) at least one metallization interconnect from the plurality of metallization interconnects 121 from the metallization 102, and (v) at least one solder interconnect from the plurality of solder interconnects 830. The electrical path between the integrated device 104 and the integrated device 404 may be configured for signals (e.g., input / output signals) between the integrated device 104 and the integrated device 404.

[0116] In some implementations, an electrical path between the substrate 709 and the integrated device 104 (e.g., configured to provide power) may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one solder interconnect from the plurality of solder interconnects 1060, (iv) the core particle 106, (v) at least one metallization interconnect from the plurality of metallization interconnects 121, and (vi) at least one solder interconnect from the plurality of solder interconnects 1010.

[0117] In some implementations, the electrical path between the substrate 709 and the integrated device 104 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, (iv) at least one metallization interconnect from the plurality of metallization interconnects 121, and (v) at least one solder interconnect from the plurality of solder interconnects 1010.

[0118] In some implementations, an electrical path between the substrate 709 and the integrated device 404 (e.g., configured to provide power) may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one solder interconnect from the plurality of solder interconnects 1040, (iv) the core particle 406, (v) at least one metallization interconnect from the plurality of metallization interconnects 121, and (vi) at least one solder interconnect from the plurality of solder interconnects 1030.

[0119] In some implementations, the electrical path between the substrate 709 and the integrated device 404 may include (i) at least one solder interconnect from the plurality of solder interconnects 196, (ii) at least one metallization interconnect from the plurality of metallization interconnects 721, (iii) at least one through-mold via from the plurality of through-mold vias 780, (iv) at least one metallization interconnect from the plurality of metallization interconnects 121, and (v) at least one solder interconnect from the plurality of solder interconnects 1030.

[0120] Integrated device 104 is configured to be electrically coupled to die 106. For example, integrated device 104 may be configured to be electrically coupled to die 106 through an electrical path including at least one solder interconnect from plurality of solder interconnects 1010 and at least one metallization interconnect from plurality of metallization interconnects 121.

[0121] Integrated device 404 is configured to be electrically coupled to die 406. For example, integrated device 404 may be configured to be electrically coupled to die 406 through an electrical path including at least one solder interconnect from plurality of solder interconnects 1030 and at least one metallization interconnect from plurality of metallization interconnects 121.

[0122] The package 1000 is coupled to a substrate 709 via a plurality of solder interconnects 196. The substrate 709 may be a board (eg, a printed circuit board).

[0123] Figure 1-10 Various packages including at least one core particle located near an integrated device are explained. The use of core particles and integrated devices in conjunction with metallizations provides several advantages. One advantage is that the core particles can be manufactured using a different manufacturing process (e.g., technology node) than the integrated device. This helps save costs because the core particles may not need to be manufactured using the most expensive manufacturing process. In addition, the use of core particles in conjunction with metallizations helps improve the electrical performance between integrated devices and / or core particles because the core particles and / or integrated devices can be located near each other.

[0124] As mentioned above, the package may include several metallizations. Any metallization may be a first metallization, and / or any metallization may be a second metallization. For example, in some implementations, the metallization 102 may be considered a first metallization, and the metallization 702 may be considered a second metallization. In some implementations, the metallization 702 may be considered a first metallization, and the metallization 102 may be considered a second metallization.

[0125] As mentioned above, the core particles can include trench capacitors and / or be configured to operate as trench capacitor devices. Trench capacitors and / or trench capacitor devices provide capacitors with high capacitance and / or high capacitance density. Capacitors with higher capacitance density allow for a more compact form factor for packaging because these capacitors take up less space but are able to provide the same and / or comparable capacitance as larger sized capacitors. The compact form factor of trench capacitors allows them to be located very close to integrated devices, which can help improve the power delivery performance to the integrated devices. In addition, because these trench capacitors have a small form factor, they can be implemented with metallization portions rather than in the package substrate.

[0126] Exemplary die with trench capacitors

[0127] Fig.11 A cross-sectional view of a core 1100 configured as a trench capacitor device is illustrated. Core 1100 can be an integrated passive device including a plurality of trench capacitors (e.g., deep trench capacitors). Core 1100 can be a device for trench capacitance. Core 1100 can represent core 106 and / or core 406. Core 1100 includes a front side and a back side. The front side of core 1100 can include a plurality of trench capacitors.

[0128] The chip 1100 includes a chip substrate 1102 and a plurality of trench capacitors 1105. A plurality of solder interconnects (not shown) may be coupled to the chip 1100. The chip substrate 1102 may include silicon (Si). The chip substrate 1102 may include a plurality of trenches and / or cavities on which capacitors may be formed. Examples of trenches and / or cavities are described in at least Figures 12A-12C Further described in .

[0129] The plurality of trench capacitors 1105 include trench capacitors 1105a and trench capacitors 1105b. The trench capacitors 1105a and 1105b may be configured to be part of the same capacitor (e.g., a first capacitor, a first trench capacitor). The trench capacitors 1105a and 1105b may be configured to be coupled to a first power distribution network (PDN) and / or configured to be part of a first power distribution network (PDN). The trench capacitors 1105a and 1105b may be configured to be part of a first electrical path for a first power of a package. The trench capacitors 1105a and 1105b may be configured to be coupled to an integrated device.

[0130] like Fig.11As shown in , the core 1100 includes a core substrate 1102, an oxide layer 1104, a first conductive layer 1106, a dielectric layer 1108, and a second conductive layer 1110. The first conductive layer 1106 and / or the second conductive layer 1110 may include polysilicon. The oxide layer 1104 and / or the dielectric layer 1108 may include SiO2 (e.g., low pressure chemical vapor deposition (LPCVD) SiO2) or Si3N4 (e.g., LPCVD Si3N4). Portions of the oxide layer 1104, the first conductive layer 1106, the dielectric layer 1108, and the second conductive layer 1110 may be located in grooves and / or cavities of the core substrate 1102. Note that the core substrate 1102 may be considered to have a groove or cavity even if the groove or cavity is filled with one or more materials.

[0131] The trench capacitor 1105a (e.g., a first trench capacitor, a first capacitor, a device for a first trench capacitor) can be defined by (i) a first portion of an oxide layer 1104, (ii) a first portion of a first conductive layer 1106, (iii) a first portion of a dielectric layer 1108, and (iv) a first portion of a second conductive layer 1110 located in a trench (e.g., a first trench) of the core substrate 102.

[0132] Trench capacitor 1105b (e.g., second trench capacitor, second capacitor, means for second trench capacitance) may be defined by (i) a second portion of oxide layer 1104, (ii) a second portion of first conductive layer 1106, (iii) a second portion of dielectric layer 1108, and (iv) a second portion of second conductive layer 1110 located in a trench (e.g., second trench) of core substrate 102. Note that trench capacitor 1105b may be part of the same capacitor as trench capacitor 1105a. That is, trench capacitor 1105a and trench capacitor 1105b may be configured to be electrically coupled together to form a capacitor (e.g., first capacitor) having a larger capacitance.

[0133] Core 1100 also includes interconnect 1109, interconnect 1192, and interconnect 1194. Interconnect 1109 is coupled to interconnect 1192 and interconnect 1194. Interconnect 1109 can be a through-substrate via extending through core substrate 1102. Interconnect 1192 can be a pad interconnect. Interconnect 1194 can be a pad interconnect. Interconnect 1192 can be located on the front side of core 1100. Interconnect 1192 can be located on the back side of core 1100. Interconnect 1109 can be a through-core substrate interconnect. The core can include at least one through-core substrate interconnect.

[0134] The integrated device (e.g., 104, 404) may include a die (e.g., a bare semiconductor die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs)-based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si)-based integrated device, a silicon carbide (SiC)-based integrated device, a memory, a power management processor, and / or a combination thereof. The integrated device (e.g., 104, 404) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may include a transistor. The integrated device may be an example of an electrical component and / or an electrical device. In some implementations, the integrated device may be a core particle. The core particles may be manufactured using a process that provides a better yield than other processes used to manufacture other types of integrated devices, which may reduce the overall cost of manufacturing the core particles. Different core particles may have different sizes and / or shapes. Different core particles may be configured to provide different functions. Different core particles may have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several core particles may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As mentioned, using several core particles that perform several functions can reduce the overall cost of the package relative to using a single chip to perform all functions of the package. In some implementations, the same technology node or two or more different technology nodes may be used to manufacture one or more core particles (e.g., 106, 306, 406, 606, 1100) and / or one or more integrated devices (e.g., 104, 404) described in the present disclosure. For example, an integrated device (e.g., 104) may be manufactured using a first technology node, and a core particle (e.g., 106) may be manufactured using a second technology node that is not as advanced as the first technology node. In such examples, the integrated device (e.g., 104) may include components (e.g., interconnects, transistors) having a first minimum size, and the die (e.g., 106) may include components (e.g., interconnects, transistors) having a second minimum size, where the second minimum size is greater than the first minimum size. In some implementations, the packaged integrated device 104 and the integrated device 404 may be manufactured using the same technology node or different technology nodes. In some implementations, the packaged die (e.g., 106) and the other die (e.g., 406) may be manufactured using the same technology node or different technology nodes.

[0135] As an example, in some implementations, a first integrated device (e.g., 104) may include a first plurality of die interconnects including a first minimum spacing, and a second integrated device (e.g., 404) may include a second plurality of die interconnects including a second minimum spacing. A core particle (e.g., 106, 306, 406) may include a plurality of interconnects including a third minimum spacing. In some implementations, the third minimum spacing may be different from the first minimum spacing and / or the second minimum spacing. In another example, in some implementations, an integrated device (e.g., 104, 404) may include a plurality of die interconnects including a first minimum spacing, and a core particle (e.g., 106, 306, 406) may include a plurality of interconnects including a second minimum spacing. In yet another example, an integrated device (e.g., 104, 404) may include a first plurality of transistors including a first minimum spacing, and a core particle (e.g., 106, 306, 606) may include a second plurality of transistors including a second minimum spacing. In some implementations, the first minimum spacing may be less than the second minimum spacing. In some implementations, the first minimum spacing may be the same as the second minimum spacing.

[0136] Exemplary Process for Making a Die with a Trench Capacitor

[0137] In some implementations, fabricating a die having a trench capacitor includes several processes. Fig. 12A -12D illustrates an exemplary process for providing or manufacturing a core particle having a trench capacitor. In some implementations, Figures 12A-12D The process can be used to provide or manufacture Fig.11 The core particle is 1100. However, Figures 12A-12D The process may be used to manufacture any of the core particles (eg, 106, 406) described in the present disclosure.

[0138] It should be noted that Figures 12A-12D The process of the present invention may combine one or more stages to simplify and / or clarify the process for providing or manufacturing a core particle having a trench capacitor. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure.

[0139] like Fig. 12A As shown in FIG. 1 , stage 1 illustrates a state after providing a substrate 1102. The substrate 1102 may be a core particle substrate. The substrate 1102 may include silicon (Si).

[0140] Stage 2 illustrates a state after a plurality of grooves 1200 are formed in substrate 1102. A plurality of grooves 1200 may include a plurality of cavities. A plurality of grooves 1200 may include a first groove, a second groove, a third groove, and a fourth groove. These grooves may have different shapes and / or different depths. An etching process may be used to form a plurality of grooves. A plurality of grooves 1200 may be evenly spaced or have different spacings.

[0141] like Fig. 12B , stage 3 illustrates a state after an oxide layer 1104 is formed over the surface of the substrate 1102. The oxide layer 1104 may be formed over the surface of the substrate 1102 (including over and in the plurality of trenches 1200) using a deposition process. For example, the oxide layer 1104 may be formed using a chemical vapor deposition (CVD) process. The oxide layer 1104 may be formed using a low pressure chemical vapor deposition (LPCVD) process. The oxide layer 1104 may take up the shape and / or contour of the plurality of trenches 1200.

[0142] Stage 4 illustrates a state after forming a first conductive layer 1106 on the oxide layer 1104. The first conductive layer 1106 may include polysilicon. The first conductive layer 1106 may be formed on the oxide layer 1104 (including on and in the plurality of trenches 1200) using a deposition process. For example, the first conductive layer 1106 may be formed using a chemical vapor deposition (CVD) process. The first conductive layer 1106 may be formed using a low pressure chemical vapor deposition (LPCVD) process. The first conductive layer 1106 may occupy the shape and / or contour of the oxide layer 1104 and / or the plurality of trenches 1200. The first conductive layer 1106 may include polysilicon. The first conductive layer 1106 may be doped. An example of a dopant includes boron. Thus, for example, the first conductive layer 1106 may include LPCVD polysilicon doped with boron.

[0143] like Fig. 12C As shown in FIG. 1 , stage 5 illustrates a state after a dielectric layer 1108 is formed over the first conductive layer 1106. The dielectric layer 1108 may be formed over the first conductive layer 1106 (including over and in the plurality of trenches 1200) using a deposition process and / or a lamination process.

[0144] Stage 6 illustrates a state after forming a second conductive layer 1110 on the dielectric layer 1108. The second conductive layer 1110 may include polysilicon. The second conductive layer 1110 may be formed on the dielectric layer 1108 (including on and in the plurality of trenches 1200) using a deposition process. For example, the second conductive layer 1110 may be formed using a chemical vapor deposition (CVD) process. The second conductive layer 1110 may be formed using a low pressure chemical vapor deposition (LPCVD) process. Portions of the second conductive layer 1110 may be formed using an etching process. The second conductive layer 1110 may fill the plurality of trenches 1200. The second conductive layer 1110 may be doped. An example of a dopant includes boron. Thus, for example, the second conductive layer 1110 may include LPCVD polysilicon doped with boron. Stage 6 may also illustrate where additional portions of the first conductive layer 1106 may be formed. Additional portions of the first conductive layer 1106 may be formed through openings of the dielectric layer 1108. Additional portions of the first conductive layer 1106 not covered by the dielectric layer 1108 may be used as pads coupled to solder interconnects. Additional portions of the first conductive layer 1106 may be formed using a deposition process. The first conductive layer 1106 and / or the second conductive layer 1110 may include polysilicon.

[0145] like Fig.12D As shown in FIG. 1 , stage 7 illustrates a state after at least one cavity 1210 is formed in the substrate 1102. The at least one cavity 1210 extending through the entire thickness of the substrate 1102 may be formed using an etching process and / or a laser process (eg, laser ablation).

[0146] Stage 8 illustrates a state after forming interconnect 1109, interconnect 1192, and interconnect 1194. Interconnect 1109, interconnect 1192, and interconnect 1194 may be formed using an electroplating process. Stage 8 illustrates an example of a die 1100 including a plurality of trench capacitors 1105.

[0147] Exemplary Flowchart of a Method for Fabricating a Core Die Having a Trench Capacitor

[0148] In some implementations, fabricating a die having a trench capacitor includes several processes. Fig.13 An exemplary flow chart of a method 1300 for providing or manufacturing a die having a trench capacitor is illustrated. In some implementations, Fig.13 The method 1300 may be used to provide or manufacture Fig.11 However, the method 1300 can be used to fabricate any core having a trench capacitor. Fig.13 The method 1300 will be used to describe manufacturing the core particle 302 .

[0149] It should be noted that Fig.13The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a core die having a trench capacitor. In some implementations, the order of the processes may be changed or modified.

[0150] The method provides (at 1305) a substrate (eg, 1102). The substrate 1102 may be a core particle substrate. The substrate 1102 may include silicon (Si). Fig. 12A Stage 1 of the present invention illustrates and describes an example of providing a core particle substrate.

[0151] The method forms (at 1310) a plurality of grooves (e.g., 1200) in a substrate (e.g., 1102). The plurality of grooves 1200 may include a plurality of cavities. The plurality of grooves 1200 may include a first groove, a second groove, a third groove, and a fourth groove. The grooves may have different shapes and / or different depths. An etching process may be used to form the plurality of grooves 1200. The plurality of grooves 1200 may be evenly spaced or have different spacings. Fig. 12A Stage 2 of the present invention illustrates and describes an example of forming a groove.

[0152] The method forms (at 1315) an oxide layer (e.g., 1104) over the plurality of trenches. The oxide layer 1104 may be formed over a surface of the substrate 1102. The oxide layer 1104 may be formed over the surface of the substrate 1102 (including over and in the plurality of trenches 1200) using a deposition process. The oxide layer 1104 may be formed using a low pressure chemical vapor deposition (LPCVD) process. The oxide layer 1104 may take up the shape and / or contour of the plurality of trenches 1200. Fig. 12B Stage 3 of the present invention illustrates and describes an example of forming an oxide layer.

[0153] The method forms (at 1320) a first conductive layer (e.g., 1106) over the oxide layer (e.g., 1104). The first conductive layer 1106 may be formed over the oxide layer 1104. The first conductive layer 1106 may include polysilicon. The first conductive layer 1106 may be formed over the oxide layer 1104 (including over and in the plurality of trenches 1200) using a deposition process. For example, the first conductive layer 1106 may be formed using a low pressure chemical vapor deposition (LPCVD) process. The first conductive layer 1106 may take up the shape and / or contour of the oxide layer 1104 and / or the plurality of trenches 1200. Forming the first conductive layer 1106 may include doping the first conductive layer 1106 with a dopant. Fig. 12B Stage 4 of the present invention illustrates and describes an example of forming a first conductive layer.

[0154] The method forms (at 1325) a dielectric layer (eg, 1108) over the first conductive layer (eg, 1106). The dielectric layer 1108 may be formed over the first conductive layer 1106 (including over and in the plurality of trenches 1200) using a deposition process. Fig. 12C Stage 5 of the present invention illustrates and describes an example of forming a dielectric layer.

[0155] The method forms (at 1330) a second conductive layer (e.g., 1110) over the dielectric layer (e.g., 1108). The second conductive layer 1110 may include polysilicon. The second conductive layer 1110 may be formed over the dielectric layer 1108 (including over and in the plurality of trenches 1200) using a deposition process. The second conductive layer 1110 may be formed using a low pressure chemical vapor deposition (LPCVD) process. The second conductive layer 1110 may fill the plurality of trenches 1200. In some implementations, additional portions of the first conductive layer 1106 may also be formed (at 1330). The additional portions of the first conductive layer 1106 may be formed through the openings of the dielectric layer 1108. The additional portions of the first conductive layer 1106 may be used as pads configured to be coupled to solder interconnects. Fig.12D Stage 6 of the present invention illustrates and describes an example of forming a second conductive layer.

[0156] The method forms (at 1335) at least one cavity (eg, 1210) in the substrate 1102. The at least one cavity 1210 extending through the entire thickness of the substrate 1102 may be formed using an etching process and / or a laser process (eg, laser ablation). Fig.12D Stage 7 of the present invention illustrates and describes an example of forming at least one cavity in a substrate.

[0157] The method forms (at 1340) at least one interconnect (e.g., 1109) in a cavity (e.g., 1210) of a substrate (e.g., 1102). In some implementations, a first interconnect (e.g., 1192) may be formed over a first surface of the substrate, and a second interconnect (e.g., 1194) may be formed over a second surface of the substrate. The first interconnect and the second interconnect may be coupled to an interconnect located in the cavity of the substrate. These interconnects (e.g., 1109, 1192, 1194) may be formed using a plating process. Fig.12D Stage 8 of the present invention illustrates and describes an example of forming at least one interconnect in a cavity of a substrate.

[0158] Exemplary process for making a package including an integrated device and a die

[0159] Fig.14A -14D illustrates an exemplary process for providing or manufacturing a package including an integrated device and a die. In some implementations, Fig.14A –14D processes can be used to provide or manufacture Figure 5 Package 500, or any package described in this disclosure.

[0160] It should be noted that Fig.14A The process of -14D may combine one or more stages to simplify and / or clarify the process for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure. Fig.14A The 14D process can be used to manufacture one package or several packages at a time (as part of a wafer).

[0161] like Fig.14A As shown, stage 1 illustrates a state after providing integrated device 104 and integrated device 404 on carrier 1400. A pick-and-place process may be used to place the back side of integrated device 104 and the back side of integrated device 404 on carrier 1400. Carrier 1400 may include a tape. Integrated device 104 may include a plurality of solder pillar interconnects 1407. The plurality of solder pillar interconnects 1407 may include a plurality of solder pillar inter-interconnects. Integrated device 404 may include a plurality of solder pillar interconnects 1447. The plurality of solder pillar interconnects 1447 may include a plurality of solder pillar inter-interconnects. Some of the plurality of solder pillar interconnects 1407 may represent a plurality of solder pillar interconnects 107 b. Some of the plurality of solder pillar interconnects 1447 may represent a plurality of solder pillar interconnects 407 b.

[0162] Stage 2 illustrates a state after encapsulation layer 108 is formed over carrier 1400, integrated device 104, and integrated device 404. Encapsulation layer 108 is coupled to carrier 1400, integrated device 104, and integrated device 404. Encapsulation layer 108 may encapsulate multiple solder pillar interconnects 1407 and multiple solder pillar interconnects 1447. Encapsulation layer 108 may include a molding, a resin, and / or an epoxy resin. Encapsulation layer 108 may be a device for encapsulation. Encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, encapsulation layer 108 is provided, and a polishing and / or grinding process is subsequently performed to remove portions of encapsulation layer 108 and / or portions of solder pillar interconnects 1407 of integrated device 104 and / or portions of solder pillar interconnects 1447 of integrated device 404 to produce a planar surface.

[0163] Stage 3 illustrates a state after dielectric layer 281 is optionally formed over the surface of encapsulation layer 108. There may be openings in dielectric layer 281 that expose the solder pillar interconnects of integrated device 104 and the solder pillar interconnects of integrated device 404. Dielectric layer 281 may include polyimide (PI). Dielectric layer 281 can help create a flatter surface. In some implementations, seed layer 1401 can be optionally formed over the plurality of solder pillar interconnects. Seed layer 1401 can be located in the openings of dielectric layer 281. Seed layer 1401 can help form interconnects over solder pillar interconnects.

[0164] Stage 4 illustrates a state after (i) a plurality of solder pillar interconnects 1404 are formed and coupled to solder pillar interconnects of integrated device 104, and (ii) a plurality of solder pillar interconnects 1414 are formed and coupled to solder pillar interconnects of integrated device 404. A plating process may be used to form the plurality of pillar interconnects 1404 and / or 1414. The plurality of solder pillar interconnects 1404 may represent a plurality of solder pillar interconnects 107a. The plurality of solder pillar interconnects 1414 may represent a plurality of solder pillar interconnects 407a. In some implementations, the plurality of solder pillar interconnects 1404 may include a seed layer 1401 and / or a plurality of solder pillar interconnects 1407. In some implementations, the plurality of solder pillar interconnects 1414 may include a seed layer 1401 and / or a plurality of solder pillar interconnects 1447. For the purpose of simplifying the drawings, Figures 14A-14D Stage 4 and subsequent stages of FIG. 4 do not illustrate dielectric layer 281 and seed layer 1401. Note, however, that dielectric layer 281 and seed layer 1401 may be located in the package in a manner consistent with that described in the present disclosure.

[0165] Stage 5 illustrates a state after the core particle 106 is coupled to the plurality of solder pillar interconnects 1407 of the integrated device 104 through the plurality of solder interconnects 140. Stage 5 also illustrates a state after the core particle 406 is coupled to the plurality of solder pillar interconnects 1447 of the integrated device 404 through the plurality of solder interconnects 440. The core particles 106 and 406 may be coupled to their respective solder pillar interconnects using a solder reflow process. Stage 5 also illustrates a state after the bridge 505 is placed on the encapsulation layer 108. The back side of the bridge 505 may be placed and / or coupled to the encapsulation layer 108. When the dielectric layer 281 is present, the back side of the bridge 505 may be placed and / or coupled to the dielectric layer 281.

[0166] Stage 6 illustrates a state after encapsulation layer 1408 is formed on encapsulation layer 108, dielectric layer 281, core particle 106, core particle 406, multiple solder pillar interconnects 1404, and / or multiple solder pillar interconnects 1414. Encapsulation layer 1408 is coupled to encapsulation layer 108, dielectric layer 281, core particle 106, core particle 406, multiple solder pillar interconnects 1404, and / or multiple solder pillar interconnects 1414. Encapsulation layer 1408 may include a molding, a resin, and / or an epoxy resin. Encapsulation layer 1408 may be a device for encapsulation. Encapsulation layer 1408 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, encapsulation layer 1408 is provided and a polishing and / or grinding process is subsequently performed to remove portions of encapsulation layer 1408 and / or portions of pillar interconnects 1404 and / or portions of pillar interconnects 1414 to produce a planar surface.

[0167] like Fig. 14B As shown in FIG. 1 , stage 7 illustrates a state after dielectric layer 1420 is formed over encapsulation layer 108. Note that encapsulation layer 108 may represent encapsulation layer 108 and encapsulation layer 1408. In some implementations, encapsulation layer 108 shown at stage 7 may include the encapsulation layer 108 as described above in Fig.14A The dielectric layer 281 described in . The dielectric layer 1420 can be formed using a lamination process.

[0168] Stage 8 illustrates a state after a plurality of cavities 1421 are formed in the dielectric layer 1420. The plurality of cavities 1421 may be openings in the dielectric layer 1420 that expose interconnects. The plurality of cavities 1421 may be formed using an exposure and development process.

[0169] Stage 9 illustrates a state after forming a plurality of metallization interconnects 1420 in and over the dielectric layer 1422. The plurality of metallization interconnects 1422 may be formed using a plating process.

[0170] Stage 10 illustrates a state after a dielectric layer 1430 is formed over the dielectric layer 1420. The dielectric layer 1430 may be formed using a lamination process.

[0171] like Fig. 14C As shown in FIG. 1 , stage 11 illustrates a state after a plurality of cavities 1431 are formed in the dielectric layer 1430. The plurality of cavities 1431 may be openings in the dielectric layer 1430 that expose interconnects. The plurality of cavities 1431 may be formed using an exposure and development process.

[0172] Stage 12 illustrates a state after a plurality of metallization interconnects 1430 are formed in and on a dielectric layer 1432. The plurality of metallization interconnects 1432 may be coupled to the plurality of metallization interconnects 1422. The plurality of metallization interconnects 1432 may be formed using a plating process. The dielectric layer 1420, the dielectric layer 1430, the plurality of metallization interconnects 1422, and the plurality of metallization interconnects 1432 may form a metallization portion 102. The plurality of metallization interconnects 1422 and the plurality of metallization interconnects 1432 may be represented by a plurality of metallization interconnects 122. The dielectric layer 1420 and the dielectric layer 1430 may be represented by at least one dielectric layer 120.

[0173] Stage 13 illustrates a state after the plurality of solder interconnects 196 are coupled to the metallization 102. The plurality of solder interconnects 196 may be coupled to the plurality of metallization interconnects 122 of the metallization 102. The plurality of solder interconnects 196 may be coupled to the metallization 102 using a solder reflow process.

[0174] Stage 14 illustrates a state after the carrier 1400 is decoupled from the encapsulation layer 108 , leaving the package 500 including the integrated device 104 , the integrated device 404 , the die 106 , the die 406 , the bridge 505 , the metallization 102 , and the encapsulation layer 108 .

[0175] like Fig.14D As shown in FIG. 1 , stage 15 illustrates a state after package 500 is coupled to substrate 109 via a plurality of solder interconnects 196. Package 500 may be coupled to substrate 109 using a solder reflow process.

[0176] Stage 16 illustrates a state after forming underfill 105 between package 500 and substrate 109. Underfill 105 may be coupled to substrate 109 and to sides of package 500.

[0177] Figures 14A-14DAn example of a method for manufacturing a package is explained. The method may provide a first integrated device and a first plurality of solder pillar interconnects. The method may form an encapsulation layer encapsulating the first integrated device and the first plurality of solder pillar interconnects. The method may form a first plurality of solder pillar interconnects configured to be coupled to the first integrated device. The method may couple a first core particle to the first integrated device through a first plurality of solder pillar interconnects. The method may form a first metallization portion such that the first metallization portion is coupled to the first core particle and the first encapsulation layer. In some implementations, the method may form a second encapsulation layer encapsulating the first core particle. The second encapsulation layer and the encapsulation layer may be part of the same encapsulation layer. The method may provide a second integrated device and a second plurality of solder pillar interconnects, wherein forming the encapsulation layer includes forming an encapsulation layer further encapsulating the second integrated device and the second plurality of solder pillar interconnects. The method may couple a second core particle to the second integrated device through a second plurality of solder pillar interconnects. The method may provide a bridge configured to provide at least one electrical path between the first integrated device and the second integrated device.

[0178] Exemplary process for making a package including an integrated device and a die

[0179] Fig.15A -15C illustrates an exemplary process for providing or manufacturing a package including an integrated device and a die. In some implementations, Figures 15A-15C The process can be used to provide or manufacture Figure 8 Package 800, or any package described in this disclosure.

[0180] It should be noted that Fig.15A The process of -15C may combine one or more stages to simplify and / or clarify the process for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure. Fig.15A The –15C process can be used to manufacture one package or several packages at a time (as part of a wafer).

[0181] like Fig.15A As shown, stage 1 illustrates a state after providing integrated device 104 and integrated device 404 on carrier 1500. A pick-and-place process may be used to place the back side of integrated device 104 and the back side of integrated device 404 on carrier 1500. Carrier 1500 may include a tape.

[0182] Stage 2 illustrates a state after encapsulation layer 108 is formed over carrier 1500, integrated device 104, and integrated device 404. Encapsulation layer 108 is coupled to carrier 1500, integrated device 104, and integrated device 404. Encapsulation layer 108 may include a molding, a resin, and / or an epoxy resin. Encapsulation layer 108 may be a device for encapsulation. Encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, encapsulation layer 108 is provided, and a polishing and / or grinding process is subsequently performed to remove portions of encapsulation layer 108 so as to produce a planar surface.

[0183] Stage 3 illustrates a state after forming the metallization 102. The metallization 102 may be formed over the integrated device 104, the integrated device 404, and the encapsulation layer 108. The metallization 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. The metallization 102 may be connected to the integrated device 104, the integrated device 404, and the encapsulation layer 108. Figures 14A-14D The metallization portion 102 shown in FIG. 1 is formed in a manner similar to that described above.

[0184] like Fig. 15B As shown, stage 4 illustrates a state after the formation of a plurality of solder pillar interconnects 1580. A plating process may be used to form the plurality of solder pillar interconnects 1580. The plurality of solder pillar interconnects may be coupled to the plurality of metallization interconnects 122.

[0185] Stage 5 illustrates a state after the core 106 is coupled to the plurality of metallization interconnects 122 through the plurality of solder interconnects 740. Stage 5 also illustrates a state after the core 406 is coupled to the plurality of metallization interconnects 122 through the plurality of solder interconnects 740. The core 106 and the core 406 may be coupled to the plurality of metallization interconnects 122 using a solder reflow process. Stage 5 also illustrates a state after the bridge 505 is coupled to the plurality of metallization interconnects 122 through the plurality of solder interconnects 850. The front side of the bridge 505 may face the metallization portion 102.

[0186] Stage 6 illustrates a state after encapsulation layer 708 is formed over encapsulation layer 108, core particle 106, core particle 406, bridge 505, and multiple solder pillar interconnects 1580. Encapsulation layer 708 is coupled to encapsulation layer 108, core particle 106, core particle 406, bridge 505, and multiple solder pillar interconnects 1580. Multiple solder pillar interconnects 1580 can be represented as multiple through-mold vias 780 in encapsulation layer 708. Encapsulation layer 708 can include a molding, a resin, and / or an epoxy resin. Encapsulation layer 708 can be a device for encapsulation. Encapsulation layer 708 can be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, encapsulation layer 708 is provided, and a polishing and / or grinding process is subsequently performed to remove portions of encapsulation layer 708 and / or portions of through-mold vias 780 to produce a planar surface.

[0187] like Fig. 15C As shown in FIG. 1 , stage 7 illustrates a state after forming a metallization portion 702. The metallization portion 702 may be formed over the encapsulation layer 708, the core 106, and the core 406. The metallization portion 702 includes at least one dielectric layer 720 and a plurality of metallization interconnects 722. The metallization portion 702 may be connected to a substrate 720 for a substrate 720. Figures 14A-14D The metallization portion 102 shown in FIG. 1 is formed in a manner similar to that described above.

[0188] Stage 8 illustrates a state after the plurality of solder interconnects 196 are coupled to the metallization 702. The plurality of solder interconnects 196 may be coupled to the plurality of metallization interconnects 722 of the metallization 702. A solder reflow process may be used to couple the plurality of solder interconnects 196 to the metallization 702. Stage 8 also illustrates a state after the carrier 1500 is decoupled from the encapsulation layer 108, leaving a package 800 including the integrated device 104, the integrated device 404, the die 106, the die 406, the bridge 505, the metallization 102, the metallization 702, the encapsulation layer 108, and the encapsulation layer 708.

[0189] Figures 15A-15CAn example of a method for manufacturing a package is explained. The method may provide a first integrated device and a second integrated device. The method may form an encapsulation layer encapsulating the first integrated device and the second integrated device. The method may form a first metallization portion such that the first metallization portion is coupled to the first integrated device and the second integrated device. The method may form a first plurality of solder pillar interconnects and a second plurality of solder pillar interconnects such that the first plurality of solder pillar interconnects and the second plurality of solder pillar interconnects are coupled to the first metallization portion. The method may couple a first core and a second core to the first metallization portion. The method may form another encapsulation layer encapsulating the first plurality of solder pillar interconnects, the second plurality of solder pillar interconnects, the first core, and the second core. The method may form a second metallization portion such that the second metallization portion is coupled to the first core and the second core. In some implementations, coupling the first core and the second core to the first metallization portion includes coupling the first core to the first metallization portion such that the front side of the first core faces the first metallization portion, and coupling the second core to the first metallization portion such that the front side of the second core faces the first metallization portion. The first core particle may be coupled to the first metallization portion via a first plurality of solder interconnects. The second core particle may be coupled to the first metallization portion via a second plurality of solder interconnects. The method may couple the bridge to the first metallization portion such that a front side of the bridge faces the first metallization portion. The bridge may be coupled to the first metallization portion via a plurality of solder interconnects.

[0190] Any metallization portion may be a first metallization portion, and / or any metallization portion may be a second metallization portion. For example, in some implementations, the metallization portion 102 may be considered a first metallization portion, and the metallization portion 702 may be considered a second metallization portion. In some implementations, the metallization portion 702 may be considered a first metallization portion, and the metallization portion 102 may be considered a second metallization portion.

[0191] Exemplary process for making a package including an integrated device and a die

[0192] Fig.16A -16C illustrates an exemplary process for providing or manufacturing a package including an integrated device and a die. In some implementations, Fig.16A –16C processes can be used to provide or manufacture Fig.10 Package 1000, or any package described in this disclosure.

[0193] It should be noted that Fig.16A The process of -16C may combine one or more stages to simplify and / or clarify the process for providing or manufacturing a package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be replaced or substituted without departing from the scope of the present disclosure. Fig.16A– The 16C process can be used to manufacture one package or several packages at a time (as part of a wafer).

[0194] like Fig.16A As shown in FIG. 1 , stage 1 illustrates a state after a metallization portion 702 is formed on the carrier 1600. The metallization portion 702 includes at least one dielectric layer 720 and a plurality of metallization interconnects 722. The metallization portion 702 may be connected to a substrate 1600. Figures 14A-14D The metallization portion 102 shown in FIG. 1 is formed in a manner similar to that described above.

[0195] Stage 2 illustrates a state after forming a plurality of solder pillar interconnects 1680. A plating process may be used to form the plurality of solder pillar interconnects 1680. The plurality of solder pillar interconnects may be coupled to the plurality of metallization interconnects 722.

[0196] Stage 3 illustrates a state after die 106 is coupled to plurality of metallization interconnects 722 via plurality of solder interconnects 1060. Stage 3 also illustrates a state after die 406 is coupled to plurality of metallization interconnects 722 via plurality of solder interconnects 1040. Die 106 and die 406 may be coupled to plurality of metallization interconnects 722 using a solder reflow process.

[0197] like Fig. 16B , stage 4 illustrates a state after the bridge 505 is coupled to the plurality of metallization interconnects 722 via the adhesive 1005. The back side of the bridge 505 may be coupled to the metallization 702 via the adhesive 1005. For example, the back side of the die substrate of the bridge 505 may be coupled to the metallization 702 via the adhesive 1005.

[0198] Stage 5 illustrates a state after forming an encapsulation layer 708 over the metallization 702, the core 106, the core 406, the bridge 505, and the plurality of solder pillar interconnects 1680. The encapsulation layer 708 is coupled to the metallization 702, the core 106, the core 406, the bridge 505, and the plurality of solder pillar interconnects 1680. The plurality of solder pillar interconnects 1680 may be represented as a plurality of through-mold vias 780 in the encapsulation layer 708. The encapsulation layer 708 may include a molding, a resin, and / or an epoxy. The encapsulation layer 708 may be a device for encapsulation. The encapsulation layer 708 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, the encapsulation layer 708 is provided, and a polishing and / or grinding process is subsequently performed to remove portions of the encapsulation layer 708 and / or portions of the through-mold vias 780 so as to produce a planar surface.

[0199] Stage 6 illustrates a state after forming metallization 102. Metallization 102 may be formed over encapsulation layer 708, bridge 505, core 106, and core 406. Metallization 102 includes at least one dielectric layer 120 and a plurality of metallization interconnects 122. Metallization 102 may be formed with respect to Figures 14A-14D The metallization portion 102 shown in FIG. 1 is formed in a manner similar to that described above.

[0200] like Fig. 16C As shown in FIG. 1 , stage 7 illustrates a state after the integrated device 104 is coupled to the metallization portion 102 through the plurality of solder interconnects 1010. The integrated device 104 is coupled to the plurality of metallization interconnects 122 through the plurality of solder interconnects 1010. Stage 7 also illustrates a state after the integrated device 404 is coupled to the metallization portion 102 through the plurality of solder interconnects 1030. The integrated device 404 is coupled to the plurality of metallization interconnects 122 through the plurality of solder interconnects 1030. A solder reflow process may be used to couple the integrated device 104 and the integrated device 404 to the metallization portion 102.

[0201] Stage 8 illustrates a state after encapsulation layer 108 is formed over integrated device 104, integrated device 404, and metallization 102. Encapsulation layer 108 is coupled to metallization 102, integrated device 104, and integrated device 404. Encapsulation layer 108 may include a molding, a resin, and / or an epoxy resin. Encapsulation layer 108 may be a device for encapsulation. Encapsulation layer 108 may be provided by using a compression and transfer molding process, a sheet molding process, or a liquid molding process. In some implementations, encapsulation layer 108 is provided, and a polishing and / or grinding process is subsequently performed to remove portions of encapsulation layer 108.

[0202] Stage 9 illustrates a state after carrier 1600 is decoupled from encapsulation layer 702 , leaving package 1000 including integrated device 104 , integrated device 404 , die 106 , die 406 , bridge 505 , metallization 702 , metallization 102 , encapsulation layer 108 , and encapsulation layer 708 .

[0203] Stage 9 also illustrates a state after the plurality of solder interconnects 196 are coupled to the metallization 702. The plurality of solder interconnects 196 may be coupled to the plurality of metallization interconnects 722 of the metallization 702. The plurality of solder interconnects 196 may be coupled to the metallization 702 using a solder reflow process.

[0204] Figures 16A-16CAn example of a method for manufacturing a package is explained. The method may form a second metallization. The method may form a first plurality of solder pillar interconnects and a second plurality of solder pillar interconnects, such that the first plurality of solder pillar interconnects and the second plurality of solder pillar interconnects are coupled to the second metallization. The method may couple a first core and a second core to the second metallization. The method may form another encapsulation layer encapsulating the first plurality of solder pillar interconnects, the second plurality of solder pillar interconnects, the first core, and the second core. The method may form a first metallization such that the first metallization is coupled to the first core and the second core. The method may couple a first integrated device and a second integrated device to the first metallization. In some implementations, coupling the first core and the second core to the second metallization includes coupling the first core to the second metallization such that the back side of the first core faces the second metallization, and coupling the second core to the second metallization such that the back side of the second core faces the second metallization. The first core may be coupled to the second metallization via a first plurality of solder interconnects. The second core may be coupled to the second metallization via a second plurality of solder interconnects. The method may couple the bridge to the second metallization such that a back side of the bridge faces the second metallization. The method may form another encapsulation layer encapsulating the first integrated device and the second integrated device.

[0205] Any metallization portion may be a first metallization portion, and / or any metallization portion may be a second metallization portion. For example, in some implementations, the metallization portion 102 may be considered a first metallization portion, and the metallization portion 702 may be considered a second metallization portion. In some implementations, the metallization portion 702 may be considered a first metallization portion, and the metallization portion 102 may be considered a second metallization portion.

[0206] Exemplary Process for Making a Substrate

[0207] In some implementations, manufacturing the substrate includes several processes. Figures 17A-17B Exemplary processes for providing or manufacturing a substrate are described. In some implementations, Figures 17A-17B The process may be used to provide or manufacture the substrate 109. However, Figures 17A-17B The process may be used to manufacture any substrate described in this disclosure.

[0208] It should be noted that Figures 17A-17B The process of one or more stages can be combined to simplify and / or illustrate the process for providing or manufacturing a substrate. In some implementations, the order of each process can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the scope of the present disclosure.

[0209] like Fig.17AAs shown in , stage 1 illustrates a state after providing a carrier 1700. A seed layer 1701 and an interconnect 1702 may be located on the carrier 1700. The interconnect 1702 may be located on the seed layer 1701. The interconnect 1702 may be formed using a plating process and an etching process. In some implementations, the carrier 1700 may be provided with a seed layer 1701 and a metal layer that is patterned to form the interconnect 1702. The interconnect 1702 may represent at least some of the interconnects from the plurality of interconnects 192.

[0210] Stage 2 illustrates a state after dielectric layer 1720 is formed over carrier 1700, seed layer 1701, and interconnect 1702. Dielectric layer 1720 may be formed using a deposition and / or lamination process. Dielectric layer 1720 may include prepreg and / or polyimide. Dielectric layer 1720 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0211] Stage 3 illustrates a state after a plurality of cavities 1710 are formed in the dielectric layer 1720. The plurality of cavities 1710 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0212] Stage 4 illustrates a state after interconnects 1712 are formed in and over dielectric layer 1720, including in and over plurality of cavities 1710. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0213] Stage 5 illustrates a state after dielectric layer 1722 is formed over dielectric layer 1720 and interconnect 1712. Dielectric layer 1722 may be formed using a deposition and / or lamination process. Dielectric layer 1722 may include prepreg and / or polyimide. Dielectric layer 1722 may include a photoimageable dielectric. However, different implementations may use different materials for the dielectric layer.

[0214] like Fig. 17B , stage 6 illustrates a state after a plurality of cavities 1730 are formed in the dielectric layer 1722. The plurality of cavities 1730 may be formed using an etching process (eg, a photolithography process) or a laser process.

[0215] Stage 7 illustrates a state after interconnects 1714 are formed in and over dielectric layer 1722, including in and over plurality of cavities 1730. For example, vias, pads, and / or traces may be formed. A plating process may be used to form the interconnects.

[0216] Stage 8 illustrates a state after decoupling (e.g., separating, removing, grinding away) the carrier 1700 from the at least one dielectric layer 190 and the seed layer 1701, removing (e.g., etching away) portions of the seed layer 1701, thereby leaving the metallization portion 102 including the at least one dielectric layer 190 and the plurality of interconnects 192. The at least one dielectric layer 190 may represent the dielectric layer 1720 and / or the dielectric layer 1722. The plurality of interconnects 192 may represent the interconnects 1702, 1712, and / or 1714.

[0217] Different implementations may use different processes to form the metal layer(s) and / or interconnects. In some implementations, the metal layer(s) may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process.

[0218] Exemplary Flowchart of a Method for Manufacturing a Substrate

[0219] In some implementations, manufacturing the substrate includes several processes. Fig.18 An exemplary flow chart of a method 1800 for providing or manufacturing a substrate is illustrated. In some implementations, Fig.18 The method 1800 can be used to provide or manufacture the substrate(s) of the present disclosure. For example, Fig.18 The method 1800 may be used to manufacture the metallization portion 102 .

[0220] It should be noted that Fig.18 The method 1800 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes may be changed or modified.

[0221] The method provides (at 1805) a carrier (e.g., 1700). Different implementations may use different materials for the carrier 1700. The carrier 1700 may include a seed layer (e.g., 1701). The seed layer 1701 may include a metal (e.g., copper). The carrier may include a substrate, glass, quartz, and / or a carrier tape. Fig.17A Stage 1 of the present invention illustrates and describes an example of a carrier provided with a seed layer.

[0222] The method forms (at 1810) interconnects over the carrier 1700 and the seed layer 1701 and patterns them. The metal layer may be patterned to form the interconnects. A plating process may be used to form the metal layer and the interconnects. In some implementations, the carrier and the seed layer may include a metal layer. The metal layer is located over the seed layer, and the metal layer may be patterned to form the interconnects (e.g., 192). Fig.17A Stage 1 of the present invention illustrates and describes an example of forming and patterning interconnects over a seed layer and a carrier.

[0223] The method forms / provides (at 1815) a dielectric layer 1720 over the seed layer 1701, the carrier 1700, and the interconnect 1702. The dielectric layer 1720 may be formed using a deposition and / or lamination process. The dielectric layer 1720 may include prepreg and / or polyimide. The dielectric layer 1720 may include a photoimageable dielectric. Forming the dielectric layer 1720 may also include forming a plurality of cavities (e.g., 1710) in the dielectric layer 1720. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Fig.17A Stages 2-3 of FIG. 1 illustrate and describe an example of forming a dielectric layer and forming a cavity in the dielectric layer.

[0224] The method forms (at 1820) interconnects in and on the dielectric layer. For example, interconnects 1712 may be formed in and on dielectric layer 1720. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnects may also include forming the interconnects in a cavity of the dielectric layer. Fig.17A Stage 4 of the present invention illustrates and describes an example of forming interconnects in and above a dielectric layer.

[0225] The method forms / provides (at 1825) a dielectric layer 1720 over the dielectric layer 1722 and the interconnect 1712. The dielectric layer 1722 may be formed using a deposition and / or lamination process. The dielectric layer 1722 may include prepreg and / or polyimide. The dielectric layer 1722 may include a photoimageable dielectric. Forming the dielectric layer 1722 may also include forming a plurality of cavities (e.g., 1730) in the dielectric layer 1722. The plurality of cavities may be formed using an etching process (e.g., photolithography) or a laser process. Figures 17A-17B Stages 5-6 of FIG. 1 illustrate and describe an example of forming a dielectric layer and forming a cavity in the dielectric layer.

[0226] The method forms (at 1830) interconnects in and on the dielectric layer. For example, interconnect 1714 may be formed in and on dielectric layer 1722. A plating process may be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnects may also include forming the interconnects in a cavity of the dielectric layer. Fig. 17B Stage 7 of 1825 illustrates and describes an example of forming interconnects in and on the dielectric layer. The method can form additional dielectric layers and additional interconnects, as described at 1825 and 1830.

[0227] In some implementations, once all dielectric layers and additional interconnects are formed, the method can decouple the carrier (e.g., 1700) from the seed layer (e.g., 1701) (at 1835). The carrier 1700 can be separated and / or ground away. The method can also remove portions of the seed layer (e.g., 1701) (at 1835). An etching process can be used to remove portions of the seed layer 1701. Fig. 17B Stage 8 illustrates and describes an example of decoupling the carrier and seed layer removal.

[0228] Different implementations may use different processes to form the metal layer(s). In some implementations, the metal layer(s) may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spraying process, and / or a plating process.

[0229] Exemplary Electronic Devices

[0230] Fig.19 Various electronic devices that may be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system-in-package (SiP), or systems on a chip (SoC) are illustrated. For example, a mobile phone device 1902, a laptop computer device 1904, a fixed location terminal device 1906, a wearable device 1908, or a motor vehicle 1910 may include a device 1900 as described herein. The device 1900 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Fig.19 The devices 1902, 1904, 1906, and 1908, and the vehicle 1910 illustrated in the figure are merely exemplary. Other electronic devices can also feature the device 1900, including, but not limited to, a group of devices (e.g., electronic devices) including: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), devices enabled with a global positioning system (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading equipment), communication devices, smart phones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0231] Figure 1-11, 12A-12D, 13, 14A-14D, 15A-15C, 16A-16C, 17A-17B and / or 18-19, one or more of the components, processes, features, and / or functions illustrated in the embodiments of the present invention may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that Figure 1-11 , 12A-12-D, 13, 14A-14D, 15A-15C, 16A-16C, 17A-17B and / or 18-19 and their corresponding descriptions in this disclosure are not limited to die and / or IC. In some implementations, Figure 1-11 , 12A-12D, 13, 14A-14D, 15A–15C, 16A–16C, 17A–17B, and / or 18-19 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat sink, and / or an interposer.

[0232] Note that the drawings in this disclosure may represent actual representations and / or conceptual representations of various components, assemblies, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, for clarity, not all components and / or parts are shown. In some instances, the positioning, location, size, and / or shape of the various components and / or assemblies in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0233] The wording "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any implementation or aspect described herein as "exemplary" is not necessarily to be interpreted as superior or superior to other aspects of the present disclosure. Likewise, the term "aspect" does not require that all aspects of the present disclosure include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered to be coupled to each other - even if they are not in direct physical contact with each other. An object coupled to another object may be coupled to at least a portion of the other object. The term "electrically coupled" may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can be transferred between the two objects. Two electrically coupled objects may or may not have an electric current transfer between the two objects. The use of the terms "first", "second", "third", and "fourth" (and / or anything higher than the fourth) is arbitrary. Any component described may be a first component, a second component, a third component, or a fourth component. For example, the component referred to as the second component may be the first component, the second component, the third component, or the fourth component. The term "encapsulation" means that an object may partially encapsulate or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. The component located at the top may be located above the component located at the bottom. The top component may be considered as the bottom component, and vice versa. As described in the present disclosure, the first component located "above" the second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, the first component may be located above (e.g., above) the first surface of the second component, and the third component may be located above (e.g., below) the second surface of the second component, wherein the second surface is opposite to the first surface. Further note that the term "above" as used in the context of a component being located above another component in the present application may be used to indicate that the component is on and / or in another component (e.g., on the surface of the component or embedded in the component). Thus, for example, a first component is above a second component may mean: (1) the first component is above the second component, but not directly contacting the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component that is "in" a second component may be partially in the second component or completely in the second component. As used in this disclosure, the term "about 'value X'" or "approximately value X" means within ten percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0234] In some implementations, interconnection is an element or component that allows or facilitates electrical connection between two points, elements and / or components in a device or package. In some implementations, interconnection may include traces, through-holes, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnections. In some implementations, interconnection may include a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal), grounding, and / or power. Interconnection may include more than one element or component. Interconnection may be defined by one or more interconnections. Interconnection may include one or more metal layers. Interconnection may be a part of a circuit. Different implementations may use different processes and / or procedures to form interconnection. In some implementations, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spraying, and / or electroplating processes may be used to form interconnection.

[0235] It should also be noted that the various disclosures contained herein may be described as processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although a flow chart may describe an operation as a sequential process, many operations may be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. A process terminates when its operations are completed.

[0236] Further examples are described below to facilitate understanding of the present invention.

[0237] Aspect 1: A package comprises a first metallization portion, a first integrated device coupled to the first metallization portion via a first plurality of solder pillar interconnects, and a first core particle located between the first integrated device and the first metallization portion, wherein the first core particle is coupled to the first integrated device via a first plurality of solder pillar interconnects.

[0238] Aspect 2: The package of aspect 1, wherein the first die comprises a trench capacitor.

[0239] Aspect 3: The package of aspect 2, wherein the first die comprises a die substrate; a plurality of trench capacitors; and at least one through-die substrate interconnect.

[0240] Aspect 4: The package of aspect 1, wherein the first chip comprises a memory, a power management integrated circuit, or a voltage regulator.

[0241] Aspect 5: The package of aspects 1 to 4, further comprising an encapsulation layer coupled to the first metallization portion and the first integrated device.

[0242] Aspect 6: The package of aspect 5, wherein the encapsulation layer comprises a first encapsulation layer coupled to the first integrated device; and a second encapsulation layer coupled to the first metallization portion.

[0243] Aspect 7: The package of aspect 6, further comprising a dielectric layer located between the first encapsulation layer and the second encapsulation layer, wherein the dielectric layer is coupled to the first encapsulation layer and the second encapsulation layer.

[0244] Aspect 8: A package as in Aspects 1 to 7, further comprising a second integrated device coupled to the first metallization portion via a second plurality of solder pillar interconnects; and a second core particle located between the second integrated device and the first metallization portion, wherein the second core particle is coupled to the second integrated device via a second plurality of solder pillar interconnects.

[0245] Aspect 9: The package of aspect 8, further comprising a bridge coupled to the first metallization, wherein the bridge is configured to provide at least one electrical path between the first integrated device and the second integrated device.

[0246] Aspect 10: The package of aspects 8 to 9, wherein the first die is laterally surrounded by a first plurality of solder pillar interconnects; and wherein the second die is laterally surrounded by a second plurality of solder pillar interconnects.

[0247] Aspect 11: The package of aspects 8 to 10, wherein the first integrated device comprises a first plurality of die interconnects comprising a first minimum spacing, and wherein the second integrated device comprises a second plurality of die interconnects comprising a second minimum spacing.

[0248] Aspect 12: The package of aspect 11, wherein the first die comprises a plurality of interconnects comprising a third minimum spacing.

[0249] Aspect 13: The package of aspects 1 to 10, wherein the first integrated device comprises a plurality of die interconnects comprising a first minimum spacing, and wherein the first die comprises a plurality of interconnects comprising a second minimum spacing.

[0250] Aspect 14: The package of aspect 13, wherein the first minimum interval is smaller than the second minimum interval.

[0251] Aspect 15: The package of aspects 1 to 10, wherein the first integrated device comprises a first plurality of transistors having a first minimum spacing, and wherein the first die comprises a second plurality of transistors having a second minimum spacing.

[0252] Aspect 16: An apparatus, comprising a package, the package comprising a first metallization portion, a first integrated device coupled to the first metallization portion via a first plurality of solder pillar interconnects, and a first die located between the first integrated device and the first metallization portion, wherein the first die is coupled to the first integrated device via a first plurality of solder pillar interconnects.

[0253] Aspect 17: The apparatus of aspect 16, wherein the first die comprises a trench capacitor.

[0254] Aspect 18: The apparatus of aspect 17, wherein the first chip comprises a chip substrate; a plurality of trench capacitors; and at least one through-chip substrate interconnect.

[0255] Aspect 19: The apparatus of aspect 16, wherein the first chip comprises a memory, a power management integrated circuit, or a voltage regulator.

[0256] Aspect 20: A device as in Aspects 16 to 19, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0257] Aspect 21: A method for manufacturing a package. The method provides a first integrated device and a first plurality of solder pillar interconnects. The method forms an encapsulation layer encapsulating the first integrated device and the first plurality of solder pillar interconnects. The method forms a first plurality of solder pillar interconnects configured to be coupled to the first integrated device. The method couples a first core particle to the first integrated device through the first plurality of solder pillar interconnects. The method forms a first metallization portion such that the first metallization portion is coupled to the first core particle and the first encapsulation layer.

[0258] Aspect 22: The method of aspect 21, wherein the first die comprises a trench capacitor.

[0259] Aspect 23: The method of aspect 22, wherein the first chip comprises a chip substrate; a plurality of trench capacitors; and at least one through-chip substrate interconnect.

[0260] Aspect 24: The method of aspect 21, wherein the first chip comprises a memory, a power management integrated circuit, or a voltage regulator.

[0261] Aspect 25: The method according to aspects 21 to 24, further comprising forming a second encapsulating layer encapsulating the first core particle.

[0262] Aspect 26: The method of aspect 25, wherein the second encapsulating layer and the encapsulating layer are part of the same encapsulating layer.

[0263] Aspect 27: The method of aspects 21 to 26 further includes providing a second integrated device and a second plurality of interconnections between solder pillars, wherein forming an encapsulation layer includes forming an encapsulation layer that further encapsulates the second integrated device and the second plurality of interconnections between solder pillars; and coupling a second core particle to the second integrated device through the second plurality of interconnections between solder pillars.

[0264] Aspect 28: The method of aspect 27, further comprising providing a bridge configured to provide at least one electrical path between the first integrated device and the second integrated device.

[0265] Aspect 29: The method of aspects 21 to 28, wherein the first integrated device comprises a plurality of die interconnects comprising a first minimum spacing, and wherein the first die comprises a plurality of interconnects comprising a second minimum spacing.

[0266] Aspect 30: The method of any of aspects 21 to 29, wherein the first integrated device comprises a first plurality of transistors having a first minimum spacing, and wherein the first die comprises a second plurality of transistors having a second minimum spacing.

[0267] Aspect 31: A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion through a first plurality of solder pillar interconnects, a first core particle located between the first metallization portion and the second metallization portion, and a second core particle located between the first metallization portion and the second metallization portion, wherein the first core particle is configured to be electrically coupled to the first integrated device through the first metallization portion, and wherein the second core particle is configured to be electrically coupled to the second integrated device through the first metallization portion.

[0268] Aspect 32: The package of Aspect 31, further comprising a bridge between the first metallization portion and the second metallization portion.

[0269] Aspect 33: The package of aspects 31 to 32, further comprising a first encapsulation layer coupled to the first metallization portion, the first integrated device, and the second integrated device.

[0270] Aspect 34: The package of aspect 33, further comprising a second encapsulation layer coupled to the first metallization, the second metallization, the first core die, and the second core die, wherein the second encapsulation layer is located between the first metallization and the second metallization.

[0271] Aspect 35: A package as in Aspects 31 to 34, wherein the first chip comprises a first trench capacitor, a first memory, a first power management integrated circuit, or a first voltage regulator, and wherein the second chip comprises a second trench capacitor, a second memory, a second power management integrated circuit, or a second voltage regulator.

[0272] Aspect 36: The package of aspects 31 to 35, wherein the first integrated device is coupled to the first metallization via a first plurality of solder interconnects, and wherein the second integrated device is coupled to the first metallization via a second plurality of solder interconnects.

[0273] Aspect 37: The package of aspects 31 to 36, wherein the first die is coupled to the first metallization via a first plurality of solder interconnects, and wherein the second die is coupled to the first metallization via a second plurality of solder interconnects.

[0274] Aspect 38: The package of aspect 37, further comprising a bridge between the first metallization and the second metallization, wherein the bridge is coupled to the first metallization via a third plurality of solder interconnects.

[0275] Aspect 39: The package of aspect 38, wherein the front side of the bridge faces the first metallization, wherein the front side of the first die faces the first metallization, and wherein the front side of the second die faces the first metallization.

[0276] Aspect 40: The package of aspects 31 to 36, wherein the first die is coupled to the second metallization via a first plurality of solder interconnects, and wherein the second die is coupled to the second metallization via a second plurality of solder interconnects.

[0277] Aspect 41: The package of aspect 40, further comprising a bridge between the first metallization and the second metallization, wherein the bridge is coupled to the first metallization via a third plurality of solder interconnects.

[0278] Aspect 42: The package of aspect 41, wherein the front side of the bridge faces the first metallization, wherein the front side of the first die faces the first metallization, and wherein the front side of the second die faces the first metallization.

[0279] Aspect 43: The package of aspects 31 to 42, wherein the first integrated device comprises a first plurality of die interconnects comprising a first minimum spacing, and wherein the second integrated device comprises a second plurality of die interconnects comprising a second minimum spacing.

[0280] Aspect 44: The package of aspects 31 to 34, wherein the first die comprises a plurality of interconnects comprising a third minimum spacing.

[0281] Aspect 45: The package of aspects 31 to 42, wherein the first integrated device comprises a plurality of die interconnects comprising a first minimum spacing, and wherein the first die comprises a plurality of interconnects comprising a second minimum spacing.

[0282] Aspect 46: The package of aspects 31 to 45, wherein the first integrated device comprises a first plurality of transistors having a first minimum spacing, and wherein the first die comprises a second plurality of transistors having a second minimum spacing.

[0283] Aspect 47: An apparatus, comprising a package. The package comprises a first metallization, a first integrated device coupled to the first metallization, a second integrated device coupled to the first metallization, the second metallization coupled to the first metallization via a first plurality of solder pillar interconnects, a first core particle located between the first metallization and the second metallization, and a second core particle located between the first metallization and the second metallization, wherein the first core particle is configured to be electrically coupled to the first integrated device via the first metallization, and wherein the second core particle is configured to be electrically coupled to the second integrated device via the first metallization.

[0284] Aspect 48: The apparatus of aspect 47, wherein the first chip comprises a first trench capacitor, a first memory, a first power management integrated circuit, or a first voltage regulator, and wherein the second chip comprises a second trench capacitor, a second memory, a second power management integrated circuit, or a second voltage regulator.

[0285] Aspect 49: The apparatus of aspects 47 to 48, wherein the first integrated device comprises a plurality of die interconnects comprising a first minimum spacing, and wherein the first die comprises a plurality of interconnects comprising a second minimum spacing.

[0286] Aspect 50: A device as in Aspects 47 to 49, wherein the device is selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

[0287] Aspect 51: A method for manufacturing a package. The method provides a first integrated device and a second integrated device. The method forms an encapsulation layer encapsulating the first integrated device and the second integrated device. The method forms a first metallization portion such that the first metallization portion is coupled to the first integrated device and the second integrated device. The method forms a first plurality of solder pillar interconnects and a second plurality of solder pillar interconnects such that the first plurality of solder pillar interconnects and the second plurality of solder pillar interconnects are coupled to the first metallization portion. The method couples a first core particle and a second core particle to the first metallization portion. The method forms another encapsulation layer encapsulating the first plurality of solder pillar interconnects, the second plurality of solder pillar interconnects, the first core particle, and the second core particle. The method forms a second metallization portion such that the second metallization portion is coupled to the first core particle and the second core particle.

[0288] Aspect 52: A method as in Aspect 51, wherein coupling the first core and the second core to the first metallization portion includes coupling the first core to a first plurality of metallization portions such that the front side of the first core faces the first metallization portion; and coupling the second core to the first metallization portion such that the front side of the second core faces the first metallization portion.

[0289] Aspect 53: The method of aspect 52, wherein the first die is coupled to the first metallization via a first plurality of solder interconnects, and wherein the second die is coupled to the first metallization via a second plurality of solder interconnects.

[0290] Aspect 54: The method of aspects 51 to 53, further comprising coupling the bridge to the first metallization portion such that a front side of the bridge faces the first metallization portion.

[0291] Aspect 55: The method of aspect 54, wherein the bridge is coupled to the first metallization via a plurality of solder interconnects.

[0292] Aspect 56: A method for manufacturing a package. The method forms a second metallization portion. The method forms a first plurality of solder pillar interconnects and a second plurality of solder pillar interconnects, such that the first plurality of solder pillar interconnects and the second plurality of solder pillar interconnects are coupled to the second metallization portion. The method couples a first core particle and a second core particle to the second metallization portion. The method forms an encapsulation layer encapsulating the first plurality of solder pillar interconnects, the second plurality of solder pillar interconnects, the first core particle, and the second core particle. The method forms a first metallization portion such that the first metallization portion is coupled to the first core particle and the second core particle. The method couples a first integrated device and a second integrated device to the first metallization portion.

[0293] Aspect 57: A method as in Aspect 56, wherein coupling the first core particle and the second core particle to the second metallization portion includes coupling the first core particle to the second metallization portion so that the back side of the first core particle faces the second metallization portion; and coupling the second core particle to the second metallization portion so that the back side of the second core particle faces the second metal portion.

[0294] Aspect 58: The method of aspect 57, wherein the first die is coupled to the second metallization via a first plurality of solder interconnects, and wherein the second die is coupled to the second metallization via a second plurality of solder interconnects.

[0295] Aspect 59: The method of aspects 56 to 57, further comprising coupling the bridge to the second metallization portion such that a back side of the bridge faces the second metallization portion.

[0296] Aspect 60: The method of aspects 56 to 59, further comprising forming another encapsulation layer encapsulating the first integrated device and the second integrated device.

[0297] The various features of the present disclosure described herein may be implemented in different systems without departing from the present disclosure. It should be noted that the above aspects of the present disclosure are merely examples and should not be construed as limiting the present disclosure. The description of the various aspects of the present disclosure is intended to be illustrative rather than limiting the scope of the appended claims. Thus, the teachings of the present disclosure may be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: a first metallized portion; a first integrated device coupled to the first metallization; a second integrated device coupled to the first metallization; a second metallization coupled to the first metallization via a first plurality of solder pillar interconnects; a first core-die located between the first metallization portion and the second metallization portion, wherein the first core-die is configured to be electrically coupled to the first integrated device through the first metallization portion; as well as A second core-die is located between the first metallization and the second metallization, wherein the second core-die is configured to be electrically coupled to the second integrated device through the first metallization.

2. The package of claim 1, further comprising: A bridge is located between the first metallization and the second metallization.

3. The package of claim 1, further comprising: A first encapsulation layer is coupled to the first metallization, the first integrated device, and the second integrated device.

4. The package of claim 3, further comprising: A second encapsulation layer is coupled to the first metallization, the second metallization, the first core die, and the second core die, wherein the second encapsulation layer is located between the first metallization and the second metallization.

5. The package according to claim 1, The first chip comprises a first trench capacitor, a first memory, a first power management integrated circuit or a first voltage regulator, and The second chip includes a second trench capacitor, a second memory, a second power management integrated circuit or a second voltage regulator.

6. The package according to claim 1, wherein the first integrated device is coupled to the first metallization portion via a first plurality of solder interconnects, and The second integrated device is coupled to the first metallization portion via a second plurality of solder interconnects.

7. The package according to claim 1, wherein the first die is coupled to the first metallization portion via a first plurality of solder interconnects, and The second die is coupled to the first metallization portion via a second plurality of solder interconnects.

8. The package of claim 7, further comprising: A bridge is located between the first metallization and the second metallization, wherein the bridge is coupled to the first metallization through a third plurality of solder interconnects.

9. The package according to claim 8, wherein the front side of the bridge faces the first metallization portion, wherein the front side of the first core particle faces the first metallization portion, and The front side of the second core particle faces the first metallization portion.

10. The package according to claim 1, wherein the first die is coupled to the second metallization portion via a first plurality of solder interconnects, and The second die is coupled to the second metallization portion via a second plurality of solder interconnects.

11. The package of claim 10, further comprising: A bridge is located between the first metallization and the second metallization, wherein the bridge is coupled to the first metallization through a third plurality of solder interconnects.

12. The package according to claim 11, wherein the front side of the bridge faces the first metallization portion, wherein the front side of the first core particle faces the first metallization portion, and The front side of the second core particle faces the first metallization portion.

13. The package according to claim 1, wherein the first integrated device comprises a first plurality of die interconnects comprising a first minimum spacing, and The second integrated device includes a second plurality of die interconnects comprising a second minimum spacing.

14. The package of claim 1, wherein the first die comprises a plurality of interconnects comprising a third minimum spacing.

15. The package according to claim 1, wherein the first integrated device comprises a plurality of die interconnects including a first minimum spacing, and The first core particle includes a plurality of interconnections having a second minimum spacing.

16. The package according to claim 1, wherein the first integrated device includes a first plurality of transistors having a first minimum spacing, and The first core comprises a second plurality of transistors having a second minimum spacing.

17. A device comprising: A package, the package comprising: a first metallization portion; a first integrated device coupled to the first metallization; a second integrated device coupled to the first metallization; a second metallization coupled to the first metallization via a first plurality of solder pillar interconnects; a first core-die located between the first metallization and the second metallization, wherein the first core-die is configured to be electrically coupled to the first integrated device through the first metallization; and A second core-die is located between the first metallization and the second metallization, wherein the second core-die is configured to be electrically coupled to the second integrated device through the first metallization.

18. The device according to claim 17, The first chip comprises a first trench capacitor, a first memory, a first power management integrated circuit or a first voltage regulator, and The second chip includes a second trench capacitor, a second memory, a second power management integrated circuit or a second voltage regulator.

19. The device according to claim 17, wherein the first integrated device comprises a plurality of die interconnects including a first minimum spacing, and The first core particle includes a plurality of interconnections having a second minimum spacing.

20. The device of claim 17, wherein the device is selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smart phone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

21. A method for manufacturing a package, comprising: Providing a first integrated device and a second integrated device; forming an encapsulation layer encapsulating the first integrated device and the second integrated device; forming a first metallization portion such that the first metallization portion is coupled to the first integrated device and the second integrated device; forming a first plurality of solder pillar interconnects and a second plurality of solder pillar interconnects such that the first plurality of solder pillar interconnects and the second plurality of solder pillar interconnects are coupled to the first metallization; coupling a first core particle and a second core particle to the first metallization portion; forming another encapsulation layer encapsulating the first plurality of solder pillar interconnects, the second plurality of solder pillar interconnects, the first core particle, and the second core particle; as well as A second metallization is formed such that the second metallization is coupled to the first core die and the second core die.

22. The method of claim 21, wherein coupling the first die and the second die to the first metallization comprises: coupling the first core to the first metallization such that a front side of the first core faces the first metallization; as well as The second core-die is coupled to the first metallization such that a front side of the second core-die faces the first metallization.

23. The method of claim 22, wherein the first die is coupled to the first metallization portion via a first plurality of solder interconnects, and The second die is coupled to the first metallization portion via a second plurality of solder interconnects.

24. The method of claim 21, further comprising: A bridge is coupled to the first metallization such that a front side of the bridge faces the first metallization.

25. The method of claim 24, wherein the bridge is coupled to the first metallization via a plurality of solder interconnects.

26. A method for manufacturing a package, comprising: forming a second metallization portion; forming a first plurality of solder pillar interconnects and a second plurality of solder pillar interconnects such that the first plurality of solder pillar interconnects and the second plurality of solder pillar interconnects are coupled to the second metallization; coupling the first core particle and the second core particle to the second metallization portion; forming an encapsulation layer encapsulating the first plurality of solder pillar interconnects, the second plurality of solder pillar interconnects, the first core particle, and the second core particle; forming a first metallization portion such that the first metallization portion is coupled to the first core particle and the second core particle; as well as A first integrated device and a second integrated device are coupled to the first metallization.

27. The method of claim 26, wherein coupling the first die and the second die to the second metallization comprises: coupling the first core to the second metallization so that a back side of the first core faces the second metallization; as well as The second core-die is coupled to the second metallization such that a back side of the second core-die faces the second metallization.

28. The method of claim 27, wherein the first die is coupled to the second metallization portion via a first plurality of solder interconnects, and The second die is coupled to the second metallization portion via a second plurality of solder interconnects.

29. The method of claim 26, further comprising: A bridge is coupled to the second metallization such that a back side of the bridge faces the second metallization.

30. The method of claim 26, further comprising: Another encapsulation layer is formed encapsulating the first integrated device and the second integrated device.

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