Power supply for computing core

Abstract

This document describes a power supply for a computing core. In one aspect, a power supply system for a computing core includes a main power converter configured to provide and regulate direct current (DC) power to the computing core through a power rail electrically coupling an output of the main power converter to the computing core. The power supply system also includes a transient suppressor circuit coupled to the power rail and configured to suppress a transient voltage difference between a target supply voltage for the computing core and an actual supply voltage to the computing core.

Description

Technical Field

[0001] This specification relates to power supplies for computing cores. Background Art

[0002] A power management integrated circuit (PMIC) is an integrated circuit (IC) that provides power management for other circuits such as a computing core. A PMIC can provide various power management functions such as power conversion, voltage regulation, and directionality of power flow. Summary of the invention

[0003] This document describes a power supply topology for a computing core. When a high-performance computing core is supplied with an onboard PMIC, the loop bandwidth is limited due to the RLC filter formed by the package and parasitic inductance, parasitic resistance, and decoupling capacitors. To compensate for the voltage drop due to these parasitics, the power converter of the PMIC that supplies power to the computing core is typically set to output a higher output voltage than required, resulting in additional power losses. For example, these losses can amount to 5% to 15% of the total system power losses. Higher output voltages also result in higher temperatures.

[0004] Some cores include an on-chip droop mitigation feature that is used to compensate for voltage drops that occur when the core's load increases. This droop mitigation can include reducing the core's clock cycle and / or delaying instructions until the voltage supplied to the core returns to an acceptable level or target level. If droop mitigation is applied, the voltage error seen by the PMIC decreases and the system tends to stay in the mitigation state longer than optimal, which negatively affects the core's performance.

[0005] The power supply topology described in this document includes a main power converter that can be implemented as a PMIC, and a transient suppressor circuit. The main power converter is configured to provide supply power to the core. For example, the main power converter can provide all the direct current (DC) power consumed by the core during any normal load condition of the core. The transient suppressor circuit is configured to suppress transient deviations between the target supply voltage to the core and the actual input voltage to the core. These deviations typically occur when the core transitions between different load levels (e.g., from a low load level to a high load level, and vice versa) and when the core transitions between different target supply voltages for the core. For example, when transitioning from a lower target supply voltage to a higher target supply voltage, the PMIC typically overshoots the target supply voltage.

[0006] The transient suppressor circuit is configured to provide additional current to and / or remove charge from a power rail that supplies power to the core to quickly mitigate the difference between a target supply voltage and an actual input voltage to the core. The transient suppressor circuit may include a power converter that operates at a higher frequency than the main power converter, so that the transient suppressor circuit can act quickly to reduce the voltage difference until the main converter can compensate for the voltage difference. To reduce the voltage difference, the transient suppressor circuit may be configured to selectively supply charge to or remove charge from the power rail when the rate of change of the actual input voltage to the core is high (e.g., greater than a threshold). This also enables the transient suppressor circuit to adjust the rate of change of the input voltage, which results in less overshoot and undershoot, faster transitions between target supply voltage levels, and a reduced time in a state where the voltage difference is higher than desired.

[0007] The transient suppressor circuit can be configured to signal the main converter when the circuit is actively injecting charge into or removing charge from the power rail. This informs the main power converter that it needs to compensate for the voltage difference so that the main power converter can adjust its output voltage. In this way, the amount of time that the transient suppressor circuit injects charge into or removes charge from the power rail is reduced. For example, without such a signal, it would take the main power converter longer to detect that the main power converter is not providing the appropriate voltage level to the core. Similarly, when on-chip droop mitigation is active, the transient suppressor circuit can signal the main power converter so that the main power converter can increase its output voltage so that droop mitigation is no longer needed. This reduces the amount of time that droop mitigation is active compared to a power supply that does not include a transient suppressor circuit, thereby improving the performance of the core.

[0008] Generally speaking, one innovative aspect of the subject matter described in this specification can be embodied in a power supply system comprising: a main power converter configured to provide and regulate direct current (DC) power to a computing core by electrically coupling an output of the main power converter to a power rail of the computing core; and a transient suppressor circuit coupled to the power rail and configured to suppress transient voltage differences between a target supply voltage for the computing core and an actual supply voltage to the computing core. Other embodiments of this aspect include corresponding apparatus, methods, and computer programs configured to perform the actions of the methods, encoded on a computer storage device.

[0009] These and other implementations may each optionally include one or more of the following features. In some aspects, the transient suppressor circuit includes an additional power converter configured to selectively inject charge onto one or more capacitors coupled to the power rail based on a transient voltage difference. The transient suppressor circuit may include a hysteresis control loop including a rate of change controller that regulates a rate of change of an actual supply voltage to the computing core. The rate of change controller may include multiple modes, including a disabled mode in which the rate of change controller is disabled when the main power converter is actively increasing or decreasing the actual supply voltage based on the workload of the computing core. The power converter may include a buck converter.

[0010] In some aspects, the transient suppressor circuit includes a signal conditioning circuit configured to condition a voltage signal representing an actual supply voltage and provide the conditioned voltage signal to a main power converter. The main power converter can be configured to condition the DC power to the computing core based on an error representing a difference between a target supply voltage and the conditioned voltage signal.

[0011] In some aspects, the transient suppressor circuit includes a combiner circuit configured to generate an adjusted voltage signal based on an output current of the transient suppressor circuit injected into or removed from the power rail by the transient suppressor circuit. The transient suppressor circuit may include a combiner circuit configured to generate the adjusted voltage signal based on an error signal received from the computing core. The error signal may indicate whether a sag mitigator of the computing core is mitigating a voltage sag of the computing core.

[0012] In some aspects, the transient suppressor circuit is physically located closer to the computing core than the main power converter. In some aspects, the control loop of the transient suppressor circuit is faster than the control loop of the main power converter and has a higher bandwidth than the control loop of the main power converter.

[0013] In general, another innovative aspect of the subject matter described in this specification can be embodied in a method, the method comprising the following operations: providing direct current (DC) power to a power core by a main converter by electrically coupling an output of the main power converter to a power rail of a computing core; regulating a voltage level of the power rail by the main power converter; detecting a transient voltage difference between a target supply voltage for the computing core and the voltage level of the power rail by a transient suppressor circuit electrically coupled to the power rail; and selectively adjusting the voltage level of the power rail by the transient suppressor circuit by injecting charge into or removing charge from one or more capacitors electrically coupled to the power rail. Other embodiments of this aspect include corresponding systems, apparatus, and computer programs encoded on computer storage devices configured to perform the actions of the method.

[0014] These and other implementations can each optionally include one or more of the following features. In some aspects, detecting the transient voltage difference includes detecting, by a rate of change controller of the transient suppressor circuit, a rate of change of a voltage level of the power rail and determining that the rate of change satisfies a threshold rate of change.

[0015] Some aspects include receiving a mode signal indicating that a main power converter is actively increasing or decreasing an actual supply voltage based on a workload of a computing core, and disabling a rate of change controller in response to receiving the mode signal.

[0016] Some aspects include conditioning, by a signal conditioning circuit of the transient suppressor circuit, a voltage signal representative of an actual supply voltage, and providing, by the signal conditioning circuit, the conditioned voltage signal to a main power converter.

[0017] Some aspects include regulating, by the main power converter, DC power to the computing core based on an error representing a difference between a target supply voltage and the regulated voltage signal.

[0018] Some aspects include generating, by a combiner circuit of a transient suppressor circuit, an adjusted voltage signal based on an output current of the transient suppressor circuit injected onto or removed from the power rail by the transient suppressor circuit.

[0019] Some aspects include generating, by a combiner circuit of a transient suppressor circuit, an adjusted voltage signal based on an error signal received from a computing core. The error signal may indicate whether a sag mitigator of the computing core is mitigating a voltage sag of the computing core.

[0020] Specific embodiments of the subject matter described in this specification can be implemented to achieve one or more of the following advantages. A power supply topology including a main power converter and a transient suppressor circuit that both regulate the voltage of the power rails for the core provides faster digital voltage scaling (DVS) transitions (e.g., transitions between different target supply voltage levels) while also reducing overshoots (e.g., exceeding an increased target supply voltage level) and undershoots (e.g., exceeding a decreased target supply voltage level) that occur during these voltage level transitions and also during load level transitions. This results in improved energy efficiency due to shorter transition times and less time above or below the target supply voltage, and also results in improved core performance due to faster transitions to higher voltages enabling the core to respond faster to higher load levels. The increased transition speed also reduces the amount of time the core spends at a higher operating point, which reduces overall power consumption and, thus, further improves energy efficiency.

[0021] The transient suppressor circuit also enables the main power converter to operate at a lower output voltage without negatively affecting the core performance. PMICs typically operate at a higher voltage, for example, at a voltage that is approximately 15% higher, to prevent the actual supply voltage from excessively sagging when the core's load increases, which results in an increase in the core's current draw and voltage sag. Since the transient suppressor circuit can respond to such sag faster than the main power converter, the main power converter can operate at a lower voltage than normal operation (e.g., output a lower voltage) to provide the same target supply voltage to the core, because the main power converter can rely on the transient power suppressor to alleviate the sag until the main power converter can provide a higher voltage to the core. This lower operating voltage improves the energy efficiency and thermal output of the power supply system (e.g., less heat is dissipated). The tighter margin between the output voltage of the main power converter and the target supply voltage can also enable the core to operate at a higher clock speed without increasing the thermal output of the system. For example, if the main power converter outputs an output voltage that is 15% higher than required by the core, the core can use this higher voltage to operate at a higher clock speed, rather than using the 15% higher voltage as an allowance for voltage droop, if a transient suppressor circuit is included. This improves the performance of the core by enabling the core to execute more instructions per unit time.

[0022] The transient suppressor circuit can be a modular addition to the same package as the core, so that the physical space occupied by the core's power supply is not increased or only slightly increased. The combination of space savings, energy efficiency, and improved thermal characteristics is important for mobile device implementations with limited energy resources, sensitive to high heat output, and with limited physical space. Since the transient suppressor circuit allows the reduction of bulk capacitance on the power rails to the core, the physical space occupied by the power supply can be further reduced.

[0023] The details of one or more embodiments of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A and Figure 1B Depicted is an example power supply system for a computing core.

[0025] Figure 2 An example layout of an integrated circuit on a circuit board is depicted.

[0026] Figure 3 A diagram depicting the voltage and current measurements used to calculate the core power system.

[0027] Figure 4 is a flow chart of an example process for suppressing supply voltage differences.

[0028] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0029] In general, this document describes a power supply topology for a computing core. The power supply includes a main power converter configured to provide main DC power to the core via a power rail. The power supply also includes a transient suppressor circuit electrically coupled to the same power rail and configured to assist the main power converter in regulating the power rail by suppressing transient voltage differences between a target supply voltage for the core and an actual input voltage to the core and regulating a rate of change of voltage on the power rail. Although the example power supply topology is described with respect to regulating power to a computing core, the power supply topology may be used in other applications where fast transient response is advantageous.

[0030] Figure 1A and Figure 1B An example power supply system 100 for a computing core 132 is depicted. Specifically, Figure 1BComponents of an example implementation of transient suppressor circuit 140 of power supply system 100 are depicted in greater detail. Components of power supply system 100 may be implemented using hardware and / or software. Hardware connections between components may be implemented using conductors such as wires, traces, and the like.

[0031] refer to Figure 1A , the computing core 132 may include a processor core, such as a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), another type of machine learning accelerator, a digital signal processing (DSP) unit, or a core of other suitable types of processing units. The computing core 132 may be implemented in an integrated circuit (IC) of an IC package 130. Although only one core 132 is shown in FIG. 1 , the IC package 130 may include multiple cores, for example, in the form of a multi-core processor. For simplicity, the computing core is also referred to as a core. The core 132 and its power supply system 100 may be part of a computing device, such as a notebook computer, a desktop computer, a tablet computer, a smart phone, or other suitable mobile or non-mobile computing device.

[0032] The core 132 includes a droop mitigator 134 configured to provide on-chip droop mitigation by detecting when there is a voltage droop in the supply voltage of the core 132 and mitigating the effects of any detected voltage droop. For example, the core 132 may request the main power converter 110 to provide a target supply voltage to the core 132 based on the workload that the core 132 is processing or about to process. If the actual supply voltage level drops below the target, for example, due to the sudden additional current drawn by the load of the core 132, the droop mitigator 134 may detect the voltage droop (e.g., by comparing the difference between the target voltage and the actual voltage to a threshold) and mitigate the effects of the voltage droop. For example, the core 132 may mitigate the effects by reducing its clock frequency or the number of instructions processed by the core 132 per unit time.

[0033] The power supply system 100 includes a main power converter 110, a transient suppressor circuit 140, a power rail 115, and associated components, such as capacitors and inductors electrically coupled to the power rail 115. The main power converter 110 is configured to provide main DC power to power the core 132 through the power rail 115. For example, the main power converter 110 is configured to power the core 132 under all normal operating conditions of the core 132. In normal steady state operation, the main power converter 110 provides all DC power used by the core 132.

[0034] The main power converter 110 may be implemented in the form of a PMIC that may be mounted on or otherwise supported by the same printed circuit board at the IC package 130. The main power converter 110 may include a DC to DC converter that converts an input DC supply (e.g., Vsys) to a voltage level suitable for the core 132, for example, by raising and / or lowering the voltage level. The supply voltage used by the core 132 may vary based on the load level of the core 132 (e.g., the number of instructions processed per unit time and / or the operating frequency). For example, when the core 132 needs to process a large workload (e.g., a large number of instructions), the core 132 may request the main power converter 110 to increase the supply voltage provided to the core 132 via the power rail 115. A higher voltage level enables the core 132 to operate at a higher clock frequency and therefore execute more instructions per unit time. When the core 132 is processing a smaller workload, the core 132 may request the main power converter 110 to reduce the voltage level to reduce wasted energy and unnecessary heat output. Thus, main power converter 132 may be configured to output a DC supply voltage to core 132 at different voltage levels.

[0035] The example main power converter 110 includes a buck converter 112 configured to reduce the voltage level for the core 132 and a controller 111 configured to control the buck converter 112. The main supply voltage of the computing device is typically 12 VDC, while the core typically operates at a voltage level of 5 VDC or lower. The buck converter is a switching converter that includes one or more switches (e.g., semiconductor switches) that operate (e.g., turn on and off) at a specific frequency to provide a desired DC voltage level at the output of the converter. In the case where it is necessary to increase rather than decrease the voltage, based on the power requirements of the core 132 and the available power source, the buck converter 112 can be replaced with a boost converter or another appropriate type of converter.

[0036] The controller 111 may operate the switches of the buck converter 112 by sending control signals to the switches. The controller may adjust the switch signals (e.g., pulse width modulation (PWM) signals) based on the error between the target output voltage of the main power converter 132 (which may be received from the core 132) and the voltage signal (Vsns). In general, the voltage signal Vsns represents the actual supply voltage at the core 132, but may be modified by the transient suppressor circuit 140, as described in more detail below. The buck converter 112 may include a gate driver that operates the switches based on the switch signals received from the controller 111.

[0037] In some implementations, the buck converter 112 is a multiphase converter. For example, the buck converter 112 is shown in FIG. 1 as a two-phase converter that outputs DC power at two different phases. The buck converter 112 may include a power stage for each phase, and the power stage for each phase may include a corresponding capacitor and / or inductor electrically coupled at the output of the power stage.

[0038] The transient suppressor circuit 140 assists the main power converter 110 in regulating the power rail 115 for the core 132. The transient suppressor circuit 140 is configured to suppress transient voltage differences between a target supply voltage for the core 132 and an actual supply voltage to the core 132. The transient suppressor circuit 140 also regulates the rate of change of the supply voltage to the core 132, for example, to reduce overshoot and undershoot, and to allow for tighter margins between the target supply voltage and the output voltage of the main power converter 110. As described above, this also increases the speed at which the transition occurs.

[0039] Transient suppressor circuit 140 includes power converter 149 and signal conditioning circuit 141. In some cases, power converter 149 is configured to regulate the voltage of power rail 115, for example, to compensate for transient voltage differences between a target supply voltage for core 132 and an actual supply voltage to core 132. Figure 1B Described in more detail, power converter 149 may include a hysteretic converter that operates in current mode to inject charge into or remove charge from power rail 115 .

[0040] Power converter 149 may be configured to increase or decrease the voltage of power rail 115 based on the rate of change of the actual supply voltage to core 132. The voltage change may be caused by main converter 110 transitioning between target supply voltage levels or a change in the load level of core 132. For example, if the actual supply voltage increases at a rate exceeding a threshold, power converter 149 may remove current from power rail 115 to adjust the rate of change of voltage and prevent or reduce overshoot.

[0041] The power converter 149 is electrically coupled to the power rail 115 using one or more inductors 151. Each inductor 151 serves as an energy storage element for the power conversion performed by the power converter 149. The power rail 115 also includes a decoupling capacitor 152 that serves as an energy storage element for the power conversion performed by the power converter 149 and decouples the power converter 149 from the power rail 115. Although two decoupling capacitors 152 are shown in this example, any number of decoupling capacitors 152 may be used based on the application of the power system 100 and the target decoupling capacitance.

[0042] To adjust the voltage of the power rail 115, the power converter 115 may inject charge into the decoupling capacitor 152 or remove charge from the decoupling capacitor 152. For example, the power converter 115 may inject charge into the decoupling capacitor 152 to increase the voltage of the power rail 115 or remove charge from the decoupling capacitor 152 to decrease the voltage of the power rail 115.

[0043] Similar to the main power converter 110, the power converter 149 may include a buck converter 128 and a corresponding controller 129, such as Figure 1B The controller 129 can operate the switches of the buck converter 128 to convert the input DC power (e.g., Vsys) to a voltage level for injecting charge into or removing charge from the decoupling capacitor 152. When the transient suppressor circuit 140 removes charge from the power rail 115, the transient suppressor circuit 140 can route current to a battery of the computing device to charge the battery.

[0044] The buck converter 112 of the main power converter 149 can have a higher efficiency than the buck converter 129 of the power converter 149. The buck converter 112 can also have a lower bandwidth than the buck converter 129. This configuration enables the main power converter 110 to operate at high efficiency under steady-state core conditions and enables the transient suppressor circuit 140 to quickly respond to the transient voltage difference between the target supply voltage and the actual supply voltage. For example, the buck converter 112 can have an efficiency of about 90% (e.g., between 85% and 95%) and a bandwidth of about 1 megahertz (MHz). In contrast, the buck converter 129 can have an efficiency of about 70% (e.g., between 65% and 75%) and a bandwidth between 10 and 50 MHz. Since the transient suppressor circuit 140 is configured to quickly respond to the transient voltage difference and hand over the voltage regulation to the main power converter 110 when the main power converter 110 is able to respond to the voltage difference, the efficiency of the power converter 149 can be lower. In other words, power converter 149 should only be active for short periods of time during transient excursions in the voltage level of power rail 115 , and the impact of the lower efficiency may be negligible.

[0045] The signal adjustment circuit 141 is configured to selectively adjust the voltage signal Vsns representing the actual supply voltage at the core 132. As described above, the main power converter 110 can control its output voltage based on an error representing the difference between the target supply voltage for the core and the actual supply voltage at the core 132 represented by the voltage signal Vsns. When the transient suppressor circuit 140 or the droop mitigator 134 performs a mitigation operation based on the actual supply voltage to the core 132, the signal adjustment circuit 141 can adjust the voltage signal Vsns to signal the power converter 110.

[0046] For example, when the mitigation operation is being performed, the signal adjustment circuit 141 can reduce the voltage signal Vsns to cause the main power converter 110 to increase its output voltage. In this example, the main power converter 110 will calculate a larger error between the target supply voltage and the actual supply voltage based on the reduction made by the signal adjustment circuit 141. In response, the main power converter 110 will compensate for the higher error by increasing its output voltage.

[0047] In another example, when the power converter 149 removes charge from the decoupling capacitor 115 based on the actual supply voltage being higher than the target supply voltage, the signal conditioning circuit 141 can reduce the voltage signal Vsns. In this example, the main power converter 110 will calculate a larger error between the target supply voltage and the actual supply voltage based on the increase made by the signal conditioning circuit 141. In response, the main power converter 110 will compensate for the higher error by reducing its output voltage.

[0048] The signal conditioning circuit 141 includes a combiner 144, which may be implemented as a summing circuit, and a buffer 146. Figure 1B As shown and described below, implementations of the signal conditioning circuit 141 may include additional components. A buffer 146 isolates the output of the combiner 144 from the input of the main converter 110 .

[0049] Combiner 144 adjusts voltage signal Vsns based on a current signal representing current supplied to or removed from power rail 115 by transient suppressor circuit 140 (e.g., output current of power converter 149) and / or an error signal output by droop mitigator 134. Transient suppressor circuit current is denoted “Isuppressor” and may be multiplied by a constant K1 before reaching the input of combiner 144.

[0050] The error signal is represented as "Error" and can be multiplied by the constant K2 before reaching the input of the combiner 144. When the droop mitigator 134 is not mitigating the droop, the error signal can have a value of zero, and when the droop mitigator 134 is mitigating the droop, the error signal can have a positive value. The error signal can represent the difference between the target clock frequency of the core 132 and the actual clock frequency of the core 132. Typically, the two clock frequencies are the same, but when the droop mitigator 134 is in active droop mitigation, the droop mitigator 134 can reduce the clock frequency, which increases the error signal. In other examples, the error signal can represent the magnitude of the voltage droop, the difference between the target number of instructions executed per unit time by the core 132 and the number of instructions actually executed per unit time by the core 132, or an error signal generated by the droop mitigator 134 based on the mitigation level being executed by the droop mitigator 134. Constants K1 and K2 can be used to standardize the current and can be tuned for various implementations of the power supply system 100. For example, the constants K1 and K2 may be programmable such that a user may set the values ​​of the constants K1 and K2.

[0051] like Figure 1A As shown, the polarity of the input to the combiner 144 of the current signal and the error signal is negative. The polarity of the input to the combiner of the voltage signal Vsns to the core is positive. This indicates that the current signal and the error signal are subtracted from the actual supply voltage. Therefore, when the power converter 149 is injecting current into the power rail 115, the combiner 144 subtracts the positive error signal from the voltage signal Vsns, thereby generating an adjusted voltage signal Vsns' lower than the voltage signal Vsns. This signal causes the main power converter 110 to calculate an error signal indicating that the actual supply voltage is less than the voltage actually present on the power rail 115, thereby causing the main power converter 110 to calculate a higher positive error and increase its output voltage. By increasing the output voltage based on this signal, the main power converter 110 can adapt more quickly to the low rail voltage being mitigated by the transient suppressor circuit 140. When the output voltage of the main power converter is high enough, the transient suppressor circuit 140 can stop injecting current onto the power rail 115, which reduces or eliminates the difference between Vsns' and Vsns and the calculated error. When the error signal is positive, indicating that the droop mitigator 140 is actively mitigating, the combiner 144 and the main power converter 110 operate in a similar manner.

[0052] When the power converter 149 is removing charge from the decoupling capacitor 152, the combiner 144 subtracts the negative error signal from the voltage signal Vsns, thereby generating an adjusted voltage signal Vsns' that is higher than the voltage signal Vsns. This signal causes the main power converter 110 to calculate an error signal indicating that the actual supply voltage is greater than the voltage actually present on the power rail 115, thereby causing the main power converter 110 to calculate a higher negative error and reduce its output voltage. By reducing the output voltage based on this signal, the main power converter 110 can adapt more quickly to the high rail voltage being mitigated by the transient suppressor circuit 140. When the output voltage of the main power converter is low enough, the transient suppressor circuit 140 can stop removing current on the power rail 115, which reduces or eliminates the difference between Vsns' and Vsns and the calculated error.

[0053] The magnitude of the current signal and the error signal may affect the error that controls the magnitude of the adjustment made by the main power converter 110 to its output voltage. For example, a higher current signal indicates that the transient suppressor circuit 140 is injecting more current onto the power rail 115 than would be indicated by a lower current signal. Thus, the transient suppressor circuit 140 is compensating for a larger voltage difference, and the main power converter 110 should increase its voltage to a higher level to compensate.

[0054] See also Figure 1B , the signal adjustment circuit 141 may include a combiner 141, a buffer 146, a first gain circuit 147, and a second gain circuit 148. The first gain circuit 147 may apply a gain to the current signal Isuppressor and output the adjusted current signal to the combiner 144. For example, the first gain circuit 147 may multiply the current signal Isuppressor by a constant K1. The second gain circuit 148 may apply a gain to the error signal Error and output the adjusted error signal to the combiner 144. For example, the second gain circuit 148 may multiply the error signal Error by a constant K2.

[0055] A voltage sensor may be electrically coupled to the input of core 132 to detect the actual supply voltage (denoted as Vcore) and provide a voltage signal Vsns to combiner 144. Similarly, a current sensor may be electrically coupled to the output of buck converter 129 to detect the current Isuppressor.

[0056] In this example, the power converter 149 is configured as a hysteretic converter, and a rate controller 122 is added, which adjusts the rate of change of the voltage on the power rail 115 to power the core 132. Other suitable types of converters can also be used to adjust the voltage of the power rail 115 when the voltage difference between the target supply voltage and the actual supply voltage exceeds a threshold, for example, by injecting charge into and removing charge from the decoupling capacitor 152.

[0057] The power converter 149 includes a reference generator 120 and an error amplifier 121. The reference generator 120 generates an initial reference signal based on a target supply voltage of the core 132. The reference generator 120 can generate a reference signal by selectively adjusting or not adjusting the target supply voltage based on an operating mode of the power converter 149. As described in more detail below, a rate of change controller 122 can select a mode of the transient suppressor circuit 140 based on a difference between the target supply voltage and an actual supply voltage to the core 132 and / or a rate of change of the actual supply voltage to the core 132. The modes may include an undershoot mode, an overshoot mode, and a disable mode.

[0058] In the undershoot mode, the transient suppressor circuit 140 injects charge into the decoupling capacitor 152 to reduce or prevent undershoot of the target supply voltage (e.g., reduce the amount that the actual supply voltage drops below the target) and increase the speed at which droop is corrected. In the overshoot mode, the transient suppressor circuit 140 removes charge from the decoupling capacitor 152 to reduce or prevent overshoot of the target supply voltage (e.g., reduce the amount that the actual supply voltage rises above the target) and increase the speed at which droop is corrected. In the disabled mode, the transient suppressor circuit 140 inactively injects charge onto or removes charge from the decoupling capacitor 152.

[0059] In the disabled mode, the reference generator 120 does not modify the target supply voltage. Therefore, in the disabled mode, the initial reference signal output by the reference generator 120 can be equal to the target supply voltage. In the overshoot mode, the reference generator 120 can generate a reference signal by applying a negative gain to the target supply voltage so that the reference signal is less than the target supply voltage. In the undershoot mode, the reference generator 120 can generate a reference signal by applying a positive gain so that the reference signal is greater than the target supply voltage. These adjustments can be step-by-step adjustments using a step value to adjust the target supply voltage based on the mode.

[0060] The power converter 121 includes an error amplifier 121, which receives an initial reference signal from a reference generator 120 and a voltage signal Vsns representing an actual supply voltage from a voltage sensor. The error amplifier 121 is configured to generate an intermediate reference signal based on the initial reference signal and the voltage signal Vsns. The error amplifier can perform a control loop to generate an intermediate reference signal to compensate for any residual regulation error imposed by the hysteresis control described below. In general, hysteresis control can use current feedback to adjust the output voltage to the computing core 135. This can create a load line, and the error amplifier 121 compensates for the load line. The control loop of the error amplifier 121 can be slower than the hysteresis control loop. The rate of change controller 122 can use the voltage signal Vsns to calculate the rate of change of the actual supply voltage to the core 132. The rate of change controller 122 can select a mode for the transient suppressor circuit 140 based on the calculated rate of change. The rate of change controller 122 can compare the rate of change with one or more thresholds to select a mode. For example, if the rate of change satisfies a first threshold having a positive value, e.g., by reaching or exceeding the first threshold, the rate of change controller 122 may select the overshoot mode because a rapid increase in the actual supply voltage indicates that an overshoot is possible or likely. If the rate of change satisfies a second threshold having a negative value, e.g., by reaching the second threshold or having a more negative value than the second threshold, the rate of change controller 122 may select the undershoot mode because a rapid decrease in the actual supply voltage indicates that an undershoot is possible or likely. If the rate of change is between the first threshold and the second threshold, the rate of change controller 122 may select the disable mode. In a specific example, the rate of change controller 122 selects the overshoot mode more when the rate of change is greater than X millivolts (mV) / microseconds (µs), selects the undershoot mode more when the rate of change is less than -X mV / µs (i.e., when the rate has a negative value greater than X), and selects the disable mode more when the rate of change is between X mV / µs and -X mV / µs, where X is an arbitrary number.

[0061] The rate range for the disable mode acts as a deadband that prevents the transient suppressor circuit 140 from injecting or removing charge when there are small changes in the actual supply voltage. Since these small changes may not affect the core 132, the main power converter 110 can adjust its output voltage at a slower rate to correct the deviation. In addition, this prevents the transient suppressor circuit 140 from responding to normal ripples in the voltage.

[0062] The rate controller 122 provides a mode signal indicating the mode to the reference generator 120 and to the controller 128 of the buck converter 129. The controller 128 may use the mode to generate switching signals for switches of the buck converter 129, as described in more detail below.

[0063] The rate of change controller 122 also provides a dynamic reference signal to the hysteresis generator 123. The rate of change controller 122 can generate the dynamic reference signal by adjusting the intermediate reference signal received from the error amplifier 121 based on the rate of change of the actual supply voltage. For example, when the transient suppressor circuit 140 is in the undershoot mode, the rate of change controller 122 can generate the dynamic reference signal by reducing the reference. When the transient suppressor circuit 140 is in the overshoot mode, the rate of change controller 122 can also generate the dynamic reference signal by increasing the reference signal. This adjustment of the reference signal effectively moves the hysteresis window that the hysteresis comparator 124 uses to determine when to cause the controller 128 to operate the switch of the buck converter 129 to inject charge on the decoupling capacitor 152 or remove charge from the decoupling capacitor 152.

[0064] In some implementations, the rate of change controller 122 is disabled when the main power converter 110 is transitioning between voltage levels, for example, during a DVS transition. The power manager may output a DC_mode signal that is routed to the transient suppressor circuit 140, which in turn provides the DC_mode signal to the rate of change controller 122. The DC_mode signal may indicate when a transition is in progress, which instructs the transient suppressor circuit 140 to operate in a DC mode, causing the control of the power converter 149 to operate as a buck converter rather than a hysteretic converter. In this DC mode, the rate of change controller 122 may pass the intermediate reference signal as a dynamic reference signal without making any adjustments to the intermediate reference signal. This may prevent the rate of change controller 122 from slowing down the transition.

[0065] In general, hysteresis generator 123, window generator 125, and hysteresis comparator 124 are configured to use hysteresis to inject or remove charge when there is a sufficiently large deviation between the target supply voltage and the actual supply voltage. When the target output moves at a given rate, the hysteresis window moves at the same rate. In this way, the hysteresis window can limit the rate of change of the actual supply voltage to the core 132.

[0066] The hysteresis generator 123 generates a hysteresis reference for the hysteresis comparator 124 based on the target reference received from the rate of change controller 122 and the hysteresis window generated by the hysteresis window generator 125. The hysteresis window generator 125 generates the hysteresis window based on the reference clock signal "Ref_osc" and the output frequency of the hysteresis comparator 124, which can be implemented using a frequency locked loop (FLL). The window generator 125 can try to adjust the comparator frequency to match the reference clock by moving the hysteresis window. In some implementations, the window generator 125 uses a static value to generate the hysteresis window by adding the static value to the dynamic reference signal output by the rate of change controller 122 to obtain a high value of the window, and subtracting the static value from the dynamic reference signal output by the rate of change controller 122 to obtain a low value of the window. The hysteresis window represents the operating frequency of the buck converter 129. A larger hysteresis window provides a lower operating frequency.

[0067] The hysteresis generator 123 outputs a high value of the hysteresis window or a low value of the hysteresis window as a hysteresis reference signal, depending on the input value "Hi / Lo" received from the output of the hysteresis comparator 124. The hysteresis comparator 124 compares the sum of the current Isuppressor output by the converter 129 and the voltage signal Vsns (output by the combiner 126) with the hysteresis reference. In some implementations, the current Isuppressor can be scaled using a gain before being added to the voltage signal Vsns.

[0068] If the sum is greater than the hysteresis reference, the hysteresis comparator generates a comparator output "Comp_out" representing a high signal. If the sum is less than the hysteresis reference, the hysteresis comparator generates a comparator output representing a low signal.

[0069] When the comparator output is high, the hysteresis generator 123 can be configured to output a low value of the hysteresis window as a hysteresis reference to make the output of the converter 129 lower. Similarly, when the comparator output is low, the hysteresis generator 123 can be configured to output a high value of the hysteresis window as a hysteresis reference to make the output of the converter 129 higher.

[0070] The comparator output is also routed to the input of the controller 128. The controller 128 uses the comparator output from the hysteresis comparator 124 and the mode of the transient suppressor circuit 140 to generate a switching signal (e.g., a PWM signal) for the switch of the buck converter 129. In general, the duty cycle of the hysteresis comparator 124 is the duty cycle of the switch of the buck converter 129. When the comparator output is high, the controller 128 can close the high-side switch of the buck converter 129 and open the low-side switch of the buck converter 129. When the comparator output 124 is low, the controller 128 can open the high-side switch of the buck converter 129 and close the low-side switch of the buck converter 129.

[0071] The mode signal drives the controller 128 how to operate the switches of the buck converter 128. For example, when the mode is overshoot or undershoot, the controller 128 can operate the switches according to the duty cycle of the comparator output. If the mode is disable, there will be no hysteresis window, and the controller 128 can control the switches like a normal buck converter by adjusting the duty cycle of the switches to increase or decrease the output voltage to meet the target supply voltage.

[0072] Figure 2 An example layout of an integrated circuit on a circuit board 200 is depicted. The circuit board 200 includes a main power converter 210, an IC package 230, and an additional component 290 disposed between the main power converter 210 and the IC package. The main power converter 210 may be used Figure 1A and Figure 1B The additional components 290 may include other ICs, resistors, capacitors, inductors, etc.

[0073] IC package 230 includes processing units 231 (i.e., 231-1 to 231-4) and transient suppressor circuits 240. Processing units 231 may be CPUs, GPUs, TPUs, DSPs, and / or other suitable types of processing units. In this example, each processing unit 231 includes four cores (not shown), and IC package 230 includes transient suppressor circuits 240 for each core. Other numbers of processing units and other numbers of cores per processing unit may also be used. Each transient suppressor circuit 240 may be implemented using transient suppressor circuit 140 of FIG. 1.

[0074] In general, transient suppressor circuits 240 for the cores can be positioned close to the cores to reduce parasitic effects of electrical coupling between the transient suppressor circuits and the power rails for the cores. For example, transient suppressor circuits 240 for the cores can be positioned within 10 millimeters (mm) of the actual circuitry of the cores. In contrast, main power converters 310 can be located farther from the cores, for example, one inch or more from each core. In addition to reducing parasitics, this close location enables faster response to transients and rapid changes in the supply voltage to the cores.

[0075] Due to the close location and high frequency operation of transient suppressor circuit 240, a very small amount of inductance can be used between transient suppressor circuit 240 and the power rail. For example, the inductance can be about 10 to 20 nanohenries (nHs) or even less, which can be achieved using an air core coil instead of a typical inductor.

[0076] Transient suppressor circuit 240 for core may be located adjacent to core, above core, below core, or in other ways near core. For example, transient suppressor circuit 240 for core may be embedded in substrate below core. Transient suppressor circuit 240 may be included in IC package 230 or separate from IC package 230.

[0077] Each transient suppressor circuit 240 can be electrically coupled to a corresponding power rail that electrically couples the main power converter 210 to one or more cores of the IC package 230. For example, the main power converter 210 can be configured to provide power to multiple rails between the main power converter and the IC package 230, such as one rail per core or one rail per group of cores. This electrical coupling enables the transient suppressor circuit 240 to inject charge onto the decoupling capacitor 152 and / or remove charge from the decoupling capacitor 152.

[0078] Figure 3 A graph 300 of voltage and current measurements for an example computing core power system is depicted. The graph shows changes in a target supply voltage for core 132, an output voltage of main power converter 110, an actual supply voltage to core 132, a current of main power converter 110, a current output by transient suppressor circuit 140, and a current draw of core 132.

[0079] In phase A, the target supply voltage is transitioned from a low voltage state to a high voltage state for core 132. The transition may be a DVS transition in anticipation of the workload being processed in phase B. As the target supply voltage increases as shown at reference numeral 310, the output voltage of the main power converter increases at a rate similar to the rate at which the target supply voltage increases. However, the output voltage of the main power converter 110 overshoots the target supply voltage by a small amount before settling at or near the target supply voltage, as shown at reference numeral 311.

[0080] During the transition, the transient suppressor circuit 140 injects current onto the power rail 115 to regulate the rate at which the actual supply voltage to the core 132 increases until an overshoot occurs as shown at reference numeral 313. To reduce or prevent the overshoot from causing a similar overshoot at the core 132, the transient suppressor circuit 140 removes charge from the power rail 115 as shown at reference numeral 314. As shown at reference numeral 312, the difference between the target supply voltage and the actual supply voltage is less than the difference between the output voltage of the main power converter 110 and the target supply voltage. Without the transient suppressor circuit 140, the difference could be approximately 50 mV or even higher due to the overshoot of the main power converter 110.

[0081] As shown at reference numeral 315, transient suppressor circuit 140 injects current for a short period of time until main power converter 110 reaches an output voltage level that provides an actual supply voltage level that matches or is within a tolerance range of the target supply voltage level at core 132. When the change in actual supply voltage is small, e.g., less than a threshold value, transient suppressor circuit 140 may stop injecting or removing charge.

[0082] In phase B, the core 132 increases its current draw from the power rail 132, as shown at reference numeral 316. This will generally result in a droop in the actual supply voltage at the core 132 while waiting for the main power converter 110 to increase its voltage to compensate for the additional current draw. To reduce such droop, the transient suppressor circuit 140 injects current onto the power rail 115, as shown at reference numeral 317, thereby providing undershoot mitigation. A short time after the increased current draw begins and the transient suppressor circuit 140 injects current, the output voltage of the main power converter 110 increases, as shown between reference numerals 318 and 319. As the output voltage of the main power converter increases, the transient suppressor circuit 140 can reduce the amount of current it injects onto the power rail 115. As shown in phase B, the actual supply voltage closely tracks the target supply voltage due to the undershoot mitigation provided by the transient suppressor circuit 140.

[0083] In phase C, core 132 reduces its current draw from power rail 132, as shown at reference numeral 330. This generally results in an increased voltage at core 132. To reduce or prevent such an increase, transient suppressor circuit 140 removes charge from power rail 115, as shown at reference numeral 331.

[0084] In phase D, the target supply voltage is transitioned from a high voltage state to a low voltage state for core 132. This transition may be a DVS transition after processing the workload in phase B. When the target supply voltage is reduced as shown at reference numeral 340, the output voltage of the main power converter is reduced at a rate similar to the rate at which the target supply voltage is reduced.

[0085] During the transition, the transient suppressor circuit 140 removes charge from the power rail 115 to regulate the rate at which the actual supply voltage to the core 132 decreases, as shown at reference numeral 341. To reduce or prevent the undershoot of the main power converter 110 from causing a similar undershoot at the core 132, the transient suppressor circuit 140 injects current into the power rail 115, as shown at reference numeral 342. As shown at reference numeral 343, the actual supply voltage closely tracks the target supply voltage without any significant undershoot. Without the transient suppressor circuit 140, the actual supply voltage would drop below the target supply voltage until the main power converter 110 is able to compensate.

[0086] Graph 300 illustrates how the fast reaction of transient suppressor circuit 140 may act within a short period of time to prevent significant deviations from a target supply voltage while allowing main power converter 110 to provide the main voltage to core 132 .

[0087] Figure 4 4 is a flow chart of an example process 400 for suppressing supply voltage differences. Process 400 may be performed by, for example Figure 1A and Figure 1B The power supply system 100 is implemented by the power supply system.

[0088] Main power converter 110 of power supply system 100 provides DC power to a computer core 410. Main power converter 110 may provide DC power to a computing core by electrically coupling the main power converter to a power rail of the computing core.

[0089] Main power converter 110 regulates the DC power provided to the computing core (420). For example, main power converter 110 may regulate the DC voltage and / or current level of the power rail. As described above, main power converter 110 may use closed-loop control and a buck converter to regulate the DC power. For example, main power converter 110 may receive a target voltage level for powering the computing core and regulate the power rail to maintain that voltage level on the power rail.

[0090] The transient suppressor circuit 140 of the power supply system 100 is configured to detect a transient difference between a target voltage level for a computing core and an actual voltage level of a power rail. For example, the transient suppressor circuit 140 can be configured to detect a voltage difference and / or a rate of change of the actual voltage level of the power rail. The transient suppressor circuit 140 can determine whether a transient is present based on the voltage difference and / or the rate of change (430). For example, when the voltage difference and / or the rate of change meet corresponding thresholds, the transient suppressor circuit can determine that a transient is present.

[0091] If a transient voltage difference is detected, transient suppressor circuit 140 may mitigate the voltage difference (440). As described above, transient suppressor circuit 140 includes a control loop and a power converter that selectively injects charge into or removes charge from one or more capacitors coupled to a power rail whenever a transient is detected.

[0092] The subject matter and the embodiments of the operation described in this specification may be implemented in a digital electronic circuit system or in computer software, firmware or hardware (including the structures disclosed in this specification and their structural equivalents), or in a combination of one or more of them. The embodiments of the subject matter described in this specification may be implemented as one or more computer programs, that is, one or more modules of computer program instructions, which are encoded on multiple computer storage media (or one computer storage medium) for data processing equipment to execute or control the operation of data processing equipment. Alternatively or additionally, the program instructions may be encoded on an artificially generated propagation signal (e.g., a machine-generated electrical, optical or electromagnetic signal), which is generated to encode information for transmission to a suitable receiver device for data processing equipment to execute. The computer storage medium may be the following or included in the following: a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them. In addition, although the computer storage medium is not a propagation signal, the computer storage medium may be the source or destination of the computer program instructions encoded in the artificially generated propagation signal. The computer storage medium can also be, or be included in, one or more separate physical components or media (eg, multiple CDs, disks, or other storage devices).

[0093] The operations described in this specification can be implemented as operations performed by a data processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

[0094] The term "data processing equipment" encompasses all types of equipment, devices and machines for processing data, including, for example, a programmable processor, a computer, a system on a chip, or a plurality of the foregoing or a combination of the foregoing. The equipment may include a dedicated logic circuit system, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, the equipment may also include code for creating an execution environment for the computer program involved, for example, code constituting a processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination of one or more of them. The equipment and execution environment may implement a variety of different computing model infrastructures, such as web services, distributed computing, and grid computing infrastructures.

[0095] A computer program (also referred to as a program, software, software application, script, or code) may be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages; and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program may be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or portions of code). A computer program may be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communications network.

[0096] The processes and logic flows described in this specification may be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input data and generating output. The processes and logic flows may also be performed by, and the apparatus may be implemented as, a special purpose logic circuit system, such as an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0097] Processors suitable for executing computer programs include, for example, both general-purpose microprocessors and special-purpose microprocessors. In general, the processor will receive instructions and data from a read-only memory or a random access memory or both. The basic elements of a computer are a processor for performing actions according to instructions and one or more memory devices for storing instructions and data. Typically, the computer will also include one or more mass storage devices for storing data, such as a magnetic disk, a magneto-optical disk, or an optical disk, or will be operatively coupled to receive data from the one or more mass storage devices or transfer data to the one or more mass storage devices, or both. However, the computer does not have to have such devices. In addition, the computer may be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device (e.g., a universal serial bus (USB) flash drive), to name a few. Devices suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices); magnetic disks (e.g., internal hard disks or removable disks); magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0098] To provide interaction with a user, embodiments of the subject matter described in this specification may be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user, and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other kinds of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback; and input from the user may be received in any form, including sound, voice, or tactile input. In addition, the computer may interact with the user by sending documents to and receiving documents from a device used by the user; for example, by sending a web page to a web browser on a user's client device in response to a request received from the web browser.

[0099] Embodiments of the subject matter described in this specification may be implemented in a computing system that includes a back-end component, such as a data server, or includes a middleware component, such as an application server, or includes a front-end component, such as a client computer with a graphical user interface or a web browser through which a user can interact with an implementation of the subject matter described in this specification, or any combination of one or more such back-end, middleware, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include local area networks ("LANs") and wide area networks ("WANs"), interconnected networks (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks).

[0100] A computing system may include a client and a server. The client and server are usually remote from each other and typically interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. In some embodiments, the server transmits data (e.g., an HTML web page) to a client device (e.g., for the purpose of displaying data to a user interacting with the client device and receiving user input from the user). Data generated at the client device (e.g., the result of the user interaction) can be received from the client device at the server.

[0101] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of any invention or the scope that may be claimed, but should be interpreted as descriptions of features that are peculiar to a particular embodiment of a particular invention. Certain features described in the context of a separate embodiment in this specification may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. In addition, although features may be described above as acting in certain combinations and even initially claimed as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claimed combination may involve a sub-combination or a variation of the sub-combination.

[0102] Similarly, although operations are depicted in a particular order in the accompanying drawings, this should not be understood as requiring that such operations be performed in the particular order shown or in a continuous order, or that all of the operations shown be performed, to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. In addition, the separation of various system components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0103] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions set forth in the claims can be performed in different orders and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some implementations, multitasking and parallel processing may be advantageous.

Claims

1. A power supply system for a computing core, comprising: a main power converter configured to provide and regulate direct current (DC) power to the computing core by electrically coupling an output of the main power converter to a power rail of the computing core; as well as A transient suppressor circuit is coupled to the power rail and is configured to suppress transient voltage differences between a target supply voltage for the computing core and an actual supply voltage to the computing core.

2. The power supply system of claim 1 , wherein the transient suppressor circuit comprises an additional power converter configured to selectively inject charge onto one or more capacitors coupled to the power rail based on the transient voltage difference.

3. The power supply system of claim 2, wherein the transient suppressor circuit includes a hysteretic control loop, the hysteretic control loop including a rate of change controller, the rate of change controller regulating the rate of change of the actual supply voltage to the computing core.

4. The power supply system of claim 3 , wherein the rate of change controller comprises multiple modes, the multiple modes comprising a disable mode in which the rate of change controller is disabled when the main power converter is actively increasing or decreasing the actual supply voltage based on a workload of the computing core.

5. The power system of claim 2, wherein the power converter comprises a buck converter.

6. A power supply system according to any preceding claim, wherein the transient suppressor circuit comprises a signal conditioning circuit configured to condition a voltage signal representative of the actual supply voltage and to provide the conditioned voltage signal to the main power converter. 7 . The power supply system of claim 6 , wherein the main power converter is configured to adjust the DC power to the computing core based on an error representing a difference between the target supply voltage and the adjusted voltage signal.

8. The power supply system of claim 6 or 7, wherein the transient suppressor circuit comprises a combiner circuit configured to generate the regulated voltage signal based on an output current of the transient suppressor circuit injected into or removed from the power rail by the transient suppressor circuit.

9. The power supply system of any one of claims 6 to 8, wherein the transient suppressor circuit comprises a combiner circuit configured to generate the adjusted voltage signal based on an error signal received from the computing core. 10 . The power supply system of claim 9 , wherein the error signal indicates whether the droop mitigator of the computing core is mitigating voltage droop of the computing core.

11. A power supply system according to any preceding claim, wherein the transient suppressor circuit is physically located closer to the computing core than the main power converter.

12. A power supply system according to any preceding claim, wherein a control loop of the transient suppressor circuit is faster than a control loop of the main power converter and has a higher bandwidth than the control loop of the main power converter.

13. A method for regulating power to a computing core, the method comprising: providing direct current (DC) power to the power core by a main converter by electrically coupling an output of the main power converter to a power rail of the computing core; regulating, by the main power converter, a voltage level of the power rail; detecting, by a transient suppressor circuit electrically coupled to the power rail, a transient voltage difference between a target supply voltage for the computing core and the voltage level of the power rail; as well as The voltage level of the power rail is selectively adjusted by the transient suppressor circuit by injecting charge into or removing charge from one or more capacitors electrically coupled to the power rail.

14. The method of claim 13, wherein detecting the transient voltage difference comprises: detecting, by a rate of change controller of the transient suppressor circuit, a rate of change of the voltage level of the power rail; as well as It is determined that the rate of change satisfies a threshold rate of change.

15. The method according to claim 14, further comprising: receiving a mode signal indicating that the main power converter is actively increasing or decreasing the actual supply voltage based on a workload of the computing core; as well as The rate of change controller is disabled in response to receiving the mode signal.

16. The method according to any one of claims 13 to 15, further comprising: conditioning a voltage signal representative of the actual supply voltage by a signal conditioning circuit of the transient suppressor circuit; as well as The regulated voltage signal is provided by the signal conditioning circuit to the main power converter. 17 . The method of claim 16 , further comprising adjusting, by the main power converter, the DC power to the computing core based on an error representing a difference between the target supply voltage and the adjusted voltage signal.

18. The method of claim 16 or 17, further comprising generating, by a combiner circuit of the transient suppressor circuit, the adjusted voltage signal based on an output current of the transient suppressor circuit injected onto or removed from the power rail by the transient suppressor circuit.

19. The method of any one of claims 16 to 18, further comprising generating, by a combiner circuit of the transient suppressor circuit, the adjusted voltage signal based on an error signal received from the computing core.

20. The method of claim 19, wherein the error signal indicates whether a droop mitigator of the computing core is mitigating voltage droop of the computing core.

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