A multi-layer silicon electrical interconnection structure and preparation method thereof

Abstract

The present invention discloses a multi-layer silicon electrical interconnection structure and a preparation method thereof, the structure comprising a top silicon wiring layer, an insulating layer, and a bottom silicon wiring layer arranged in sequence from top to bottom, the bottom silicon wiring layer having a bottom silicon wiring structure, the top silicon wiring layer having a top silicon wiring structure, the top silicon wiring layer having a top deep hole, the top deep hole penetrating the insulating layer, the top deep hole having a metal connection layer, the metal connection layer connecting the bottom silicon wiring layer and the top silicon wiring layer. In the present invention, the proposed multi-layer silicon electrical interconnection structure and preparation method thereof; having a multi-layer silicon wiring structure, a deep hole, and a connecting metal layer, can realize electrical interconnection between multi-layer silicon wirings and interconnection between MEMS internal structures and multi-port electrode lead-out, solve the technical problem of electrode lead-out of complex structures and array MEMS device structures, and has high practical value in product applications.

Description

Technical Field

[0001] The present invention relates to the field of MEMS (micro-electromechanical system) technology, and in particular to a multi-layer silicon electrical interconnection structure and a preparation method thereof. Background Art

[0002] MEMS devices are developed on the basis of semiconductor manufacturing technology. They are micro-mechanical electronic devices made by integrating bulk silicon processing technology and are widely used in consumer electronics, industry, communications and other fields. With the development of MEMS manufacturing technology, more and more complex microstructures and large-scale array devices have begun to be commercially applied, and the number of device wiring and electrodes has also increased. Therefore, the electrode lead-out technology problem of complex structures and array MEMS device structures has been introduced. Summary of the invention

[0003] In order to solve the technical problems existing in the background technology, the present invention provides a multi-layer silicon electrical interconnect structure and a preparation method thereof.

[0004] A multi-layer silicon electrical interconnect structure proposed in the present invention comprises a top silicon wiring layer, an insulating layer, and a bottom silicon wiring layer arranged in sequence from top to bottom, wherein the bottom silicon wiring layer has a bottom silicon wiring structure, the top silicon wiring layer has a top silicon wiring structure, a top deep hole is opened on the top silicon wiring layer, the top deep hole penetrates the insulating layer, a metal connection layer is arranged in the top deep hole, and the metal connection layer conductively connects the bottom silicon wiring layer and the top silicon wiring layer.

[0005] As a further optimized solution of the present invention, the top silicon wiring layer and the bottom silicon wiring layer are connected via silicon-oxygen-silicon bonding to form a silicon oxide layer, which is an insulating layer.

[0006] As a further optimized solution of the present invention, there is a substrate layer below the bottom silicon wiring layer.

[0007] As a further optimized solution of the present invention, it also includes a middle silicon wiring layer, on which there is a middle silicon wiring structure, the middle silicon wiring layer is located between the bottom silicon wiring layer and the bottom silicon wiring layer, an insulating layer is provided between the middle silicon wiring layer and the bottom silicon wiring layer and the top silicon wiring layer, and the middle silicon wiring layer, the bottom silicon wiring layer and the top silicon wiring layer are all conductively connected through the metal connection layer.

[0008] As a further optimized solution of the present invention, a middle deep hole is opened on the middle silicon wiring layer and penetrates the insulating layer located on the bottom silicon wiring layer, the top deep hole includes a first top deep hole and a second top deep hole, the first top deep hole is opposite to and connected to the middle deep hole, the second top deep hole penetrates the insulating layer located between the top silicon wiring layer and the middle silicon wiring layer, the metal connection layer includes a first metal connection layer arranged in the first top deep hole and a second metal connection layer arranged in the second top deep hole, the first metal connection layer conductively connects the bottom silicon wiring layer, the middle silicon wiring layer and the top silicon wiring layer, and the second metal connection layer conductively connects the middle silicon wiring layer and the top silicon wiring layer.

[0009] Preferably, the middle silicon wiring layer is provided with at least two layers, an insulating layer is provided between any two adjacent groups of the middle silicon wiring layers, and the middle silicon wiring layer, the bottom silicon wiring layer and the top silicon wiring layer, as well as the adjacent middle silicon wiring layers are all conductively connected through the metal connection layer.

[0010] A method for preparing a multi-layer silicon electrical interconnect structure comprises the following steps:

[0011] S1. Make the bottom silicon wiring layer:

[0012] Selecting a bottom silicon SOI silicon wafer as a bottom silicon wiring layer wafer, performing photolithography and etching to form a bottom silicon wiring structure to form a bottom silicon wiring layer;

[0013] S2. Wiring layer bonding:

[0014] The top silicon SOI wafer is selected as the top silicon wiring layer wafer, and after oxidation, silicon-oxygen-silicon bonding is performed with the bottom silicon wiring layer;

[0015] S3. Preparation of top deep hole:

[0016] The substrate silicon and buried oxide layer of the SOI silicon wafer of the top silicon are removed by mechanical thinning and corrosion, and the silicon at the deep hole and the bottom silicon oxide layer are removed by photolithography and etching to form a top deep hole, and the top deep hole extends to the upper surface of the bottom silicon wiring layer;

[0017] S4. Preparation of metal connection layer:

[0018] A metal connection layer is prepared by sputtering or evaporation, and photolithography and etching are performed to form a connection metal connection layer, and the metal connection layer in the top deep hole realizes the connection between the top silicon wiring layer and the bottom silicon wiring layer;

[0019] S5. Preparing a top silicon wiring structure of a top silicon wiring layer

[0020] Photolithography and etching are performed to form a top silicon wiring structure, thereby forming a top silicon wiring layer.

[0021] For a structure having a middle silicon wiring layer, a method for preparing a multi-layer silicon electrical interconnect structure comprises the following steps:

[0022] S1. Make the bottom silicon wiring layer:

[0023] Selecting a bottom silicon SOI silicon wafer as a bottom silicon wiring layer wafer, performing photolithography and etching to form a bottom silicon wiring structure to form a bottom silicon wiring layer;

[0024] S2, bonding between the middle silicon wiring layer and the bottom silicon wiring layer:

[0025] The SOI silicon wafer with the lower silicon layer is selected as the middle silicon wiring layer wafer, and after oxidation, silicon-oxygen-silicon bonding is performed with the bottom silicon wiring layer;

[0026] The substrate silicon and buried oxide layer of the SOI silicon wafer of the middle silicon wiring layer are removed by mechanical thinning and corrosion, and the silicon and the bottom silicon oxide layer at the deep hole are removed by photolithography and etching to form a middle deep hole, and the middle deep hole extends to the upper surface of the bottom silicon wiring layer;

[0027] Performing photolithography and etching on the middle silicon wiring layer to form a middle silicon wiring structure, thereby forming a middle silicon wiring layer;

[0028] S3, bonding of the middle silicon wiring layer and the top silicon wiring layer:

[0029] Select the top silicon SOI silicon wafer as the top silicon wiring layer wafer, oxidize it and perform silicon-oxygen-silicon bonding with the bottom silicon wiring layer;

[0030] S4. Preparation of top deep hole:

[0031] The substrate silicon and buried oxide layer of the SOI silicon wafer of the top silicon are removed by mechanical thinning and corrosion, and the silicon at the deep hole and the bottom silicon oxide layer are removed by photolithography and etching to form a top deep hole, and the top deep hole extends to the upper surface of the middle silicon wiring layer;

[0032] S5. Preparing a metal connection layer:

[0033] Prepare a metal connection layer by sputtering or evaporation, perform photolithography and etching to form a connection metal connection layer, and the metal connection layer in the top deep hole realizes the conductive connection between the middle silicon wiring layer, the bottom silicon wiring layer and the top silicon wiring layer;

[0034] S6, preparing a top silicon wiring structure of a top silicon wiring layer:

[0035] Photolithography and etching are performed to form a top silicon wiring structure to form a top silicon wiring layer.

[0036] Specifically, in step S4, the top deep hole includes a first top deep hole and a second top deep hole, the first top deep hole is opposite to and connected to the middle deep hole, and the second top deep hole penetrates the insulating layer between the top silicon wiring layer and the middle silicon wiring layer;

[0037] In step S5, the metal connection layer includes a first metal connection layer and a second metal connection layer, wherein the first metal connection layer conductively connects the bottom silicon wiring layer, the middle silicon wiring layer and the top silicon wiring layer, and the second metal connection layer conductively connects the middle silicon wiring layer and the top silicon wiring layer.

[0038] In some embodiments, step S2 and step S3 further include S20:

[0039] Selecting a middle silicon SOI wafer as a middle silicon wiring layer wafer, performing silicon-oxygen-silicon bonding with the middle silicon wiring layer after oxidation;

[0040] The substrate silicon and buried oxide layer of the SOI silicon wafer of the upper middle silicon wiring layer are removed by mechanical thinning and corrosion, and the silicon and the bottom silicon oxide layer at the deep hole are removed by photolithography and etching to form a middle deep hole, and the middle deep hole extends to the upper surface of the middle silicon wiring layer of the upper layer;

[0041] The uppermost middle silicon wiring layer is subjected to photolithography and etching to form a middle silicon wiring structure and then form an upper middle silicon wiring layer.

[0042] In the present invention, the proposed multi-layer silicon electrical interconnection structure and preparation method have a multi-layer silicon wiring structure, deep holes and connecting metal layers, which can realize electrical interconnection between multi-layer silicon wirings and interconnection between MEMS internal structures and multi-port electrode lead-out, solve the technical problem of electrode lead-out of complex structures and array MEMS device structures, and have high practical value in product applications.

[0043] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 This is a structural diagram of Embodiment 1 of the present invention;

[0045] Figure 2 This is a schematic diagram of the structure after the bottom silicon wiring layer is processed and manufactured by the present invention;

[0046] Figure 3 This is a structural schematic diagram of step S2 of processing a multi-layer silicon electrical interconnect structure in accordance with an embodiment of the present invention;

[0047] Figure 4 This is a structural schematic diagram of step S3 of processing a multi-layer silicon electrical interconnect structure in Example 1 of the present invention;

[0048] Figure 5 This is a structural schematic diagram of step S4 of processing a multi-layer silicon electrical interconnect structure in accordance with an embodiment of the present invention;

[0049] Figure 6 This is a structural diagram of Embodiment 2 of the present invention;

[0050] Figure 7 This is a structural schematic diagram of step S2 of processing a multi-layer silicon electrical interconnect structure in Example 2 of the present invention;

[0051] Figure 8 This is a structural schematic diagram of step S3 of processing a multi-layer silicon electrical interconnect structure in Example 2 of the present invention;

[0052] Fig. 9 This is a structural schematic diagram of step S4 of processing a multi-layer silicon electrical interconnect structure in Example 2 of the present invention;

[0053] Fig.10 This is a structural diagram of step S5 of processing a multi-layer silicon electrical interconnect structure in Example 2 of the present invention;

[0054] Fig.11 This is a structural diagram of Embodiment 3 of the present invention;

[0055] Fig.12 This is a structural schematic diagram of step S20 of processing a multi-layer silicon electrical interconnect structure in Example 3 of the present invention.

[0056] In the figure: 1. Top silicon wiring layer; 10. Top deep hole; 2. Insulation layer; 3. Bottom silicon wiring layer; 4. Substrate layer; 5. Metal connection layer; 6. Middle silicon wiring layer; 60. Middle deep hole. DETAILED DESCRIPTION

[0057] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar symbols throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0058] like Figure 1 A multi-layer silicon electrical interconnect structure is shown, comprising a top silicon wiring layer 1, an insulating layer 2, and a bottom silicon wiring layer 3 arranged in sequence from top to bottom, a bottom silicon wiring structure on the bottom silicon wiring layer 3, a substrate layer 4 below the bottom silicon wiring layer 3, the bottom silicon wiring layer 3 is grown on the substrate layer 4, a top silicon wiring structure on the top silicon wiring layer 1, a top deep hole 10 is opened on the top silicon wiring layer 1, the top deep hole 10 penetrates the insulating layer 2, a metal connection layer 5 is arranged in the top deep hole 10, and the metal connection layer 5 connects the bottom silicon wiring layer 3 and the top silicon wiring layer 1.

[0059] Specifically, the top silicon wiring layer 1 and the bottom silicon wiring layer 3 are connected by silicon-oxygen-silicon bonding to form a silicon oxide layer, which is the insulating layer 2 .

[0060] A method for preparing a multi-layer silicon electrical interconnect structure comprises the following steps:

[0061] S1. Fabrication of bottom silicon wiring layer 3:

[0062] Selecting a SOI silicon wafer with low resistivity bottom silicon as the bottom silicon wiring layer 3 wafer, performing photolithography and etching to form a bottom silicon wiring structure to form a bottom silicon wiring layer 3; Figure 2 As shown;

[0063] S2. Wiring layer bonding:

[0064] Select a low resistivity top silicon SOI silicon wafer as the top silicon wiring layer 1 wafer, oxidize it and bond it with the bottom silicon wiring layer 3 to form a silicon-oxygen-silicon bond. Figure 3 The structure shown;

[0065] S3, preparation of top deep hole 10:

[0066] The substrate silicon and buried oxide layer of the SOI silicon wafer of the top silicon are removed by mechanical thinning and etching, and the silicon at the deep hole and the bottom silicon oxide layer are removed by photolithography and etching to form a top deep hole 10, which extends to the upper surface of the bottom silicon wiring layer 3 to form a top deep hole 10. Figure 4 The structure shown;

[0067] S4, preparing metal connection layer 5:

[0068] The metal connection layer 5 is prepared by sputtering or evaporation, and photolithography and etching are performed to form the connection metal connection layer 5. The metal connection layer 5 in the top deep hole 10 realizes the connection between the top silicon wiring layer 1 and the bottom silicon wiring layer 3, forming a Figure 5 The structure shown;

[0069] S5, preparing a top silicon wiring structure of the top silicon wiring layer 1:

[0070] Photolithography and etching are performed to form a top silicon wiring structure, thereby forming a top silicon wiring layer 1, forming a Figure 1 The structure shown.

[0071] Embodiment 2

[0072] like Figure 6A multi-layer silicon electrical interconnect structure is shown, and the difference between this embodiment and the first embodiment is that: it also includes a middle silicon wiring layer 6, and the middle silicon wiring layer 6 has a middle silicon wiring structure, the middle silicon wiring layer 6 is located between the bottom silicon wiring layer 3 and the bottom silicon wiring layer 3, and an insulating layer 2 is provided between the middle silicon wiring layer 6 and the bottom silicon wiring layer 3 and the top silicon wiring layer 1, and the middle silicon wiring layer 6, the bottom silicon wiring layer 3 and the top silicon wiring layer 1 are all conductively connected through a metal connection layer 5;

[0073] A middle deep hole 60 is opened on the middle silicon wiring layer 6 and penetrates the insulating layer 2 located on the bottom silicon wiring layer 3. The top deep hole 10 includes a first top deep hole 100 and a second top deep hole 101. The first top deep hole 100 is opposite to and connected to the middle deep hole 60. The second top deep hole 101 penetrates the insulating layer 2 located between the top silicon wiring layer 1 and the middle silicon wiring layer 6 and the second top deep hole 101 is not connected to the middle deep hole 60. The metal connection layer 5 includes a first metal connection layer 50 arranged in the first top deep hole 100 and a second metal connection layer 51 arranged in the second top deep hole 101. The first metal connection layer 50 conductively connects the bottom silicon wiring layer 3, the middle silicon wiring layer 6 and the top silicon wiring layer 1, and the second metal connection layer 51 conductively connects the middle silicon wiring layer 6 and the top silicon wiring layer 1.

[0074] A method for preparing a multi-layer silicon electrical interconnect structure comprises the following steps:

[0075] S1. Fabrication of bottom silicon wiring layer 3:

[0076] Select a SOI silicon wafer with low resistivity bottom silicon as the bottom silicon wiring layer 3 wafer, perform photolithography and etching to form a bottom silicon wiring structure to form a bottom silicon wiring layer 3; form as shown in Figure 2 The structure shown

[0077] S2, the middle silicon wiring layer 6 is bonded to the bottom silicon wiring layer 3:

[0078] Select a low resistivity middle layer silicon SOI silicon wafer as the middle silicon wiring layer 6 wafer, and perform silicon-oxygen-silicon bonding with the bottom silicon wiring layer 3 after oxidation;

[0079] The substrate silicon and buried oxide layer of the SOI silicon wafer of the middle silicon wiring layer 6 are removed by mechanical thinning and corrosion, and the silicon and the bottom silicon oxide layer at the deep hole are removed by photolithography and etching to form a middle deep hole 60, which extends to the upper surface of the bottom silicon wiring layer 3;

[0080] The middle silicon wiring layer 6 is photolithographically and etched to form a middle silicon wiring structure, thereby forming the middle silicon wiring layer 6. Figure 7 The structure shown;

[0081] S3, the middle silicon wiring layer 6 is bonded to the top silicon wiring layer 1:

[0082] Select a low resistivity top silicon SOI silicon wafer as the top silicon wiring layer 1 wafer, oxidize it and perform silicon-oxygen-silicon bonding with the middle silicon wiring layer 6 to form a Figure 8 The structure shown;

[0083] S4, preparation of top deep hole 10:

[0084] The substrate silicon and buried oxide layer of the SOI silicon wafer of the top silicon are removed by mechanical thinning and corrosion, and photolithography and etching are performed to remove the silicon at the deep hole and the bottom silicon oxide layer to form a top deep hole 10. The top deep hole 10 extends to the upper surface of the middle silicon wiring layer 6. The top deep hole 10 includes a first top deep hole 100 and a second top deep hole 101. The first top deep hole 100 is opposite to and connected to the middle deep hole 60. The second top deep hole 101 penetrates the insulating layer 2 between the top silicon wiring layer 1 and the middle silicon wiring layer 6, and the second top deep hole 101 is not connected to the middle deep hole 60, so as to form a top deep hole 100. Fig. 9 The structure shown;

[0085] S5, preparing metal connection layer 5:

[0086] The metal connection layer 5 is prepared by sputtering or evaporation, and photolithography and etching are performed to form the connection metal connection layer 5. The metal connection layer 5 includes a first metal connection layer 50 arranged in the first top deep hole 100 and a second metal connection layer 51 arranged in the second top deep hole 101. The first metal connection layer 50 electrically connects the bottom silicon wiring layer 3, the middle silicon wiring layer 6 and the top silicon wiring layer 1, and the second metal connection layer 51 electrically connects the middle silicon wiring layer 6 and the top silicon wiring layer 1; forming as shown in FIG. Fig.10 The structure shown,

[0087] S6, preparing a top silicon wiring structure of the top silicon wiring layer 1:

[0088] Perform photolithography and etching to form a top silicon wiring structure to form a top silicon wiring layer 1, forming a Figure 6 The structure shown.

[0089] Embodiment 3

[0090] like Fig.11As shown, the difference between this embodiment and the second embodiment is that the middle silicon wiring layer 6 is provided with at least two layers, an insulating layer 2 is provided between any two adjacent groups of middle silicon wiring layers 6, and any two adjacent groups of middle silicon wiring layers 6 are connected through the metal connection layer 5 in the middle deep hole 60 on the middle silicon wiring layer 6 on the upper layer, the middle silicon wiring layer 6 on the uppermost layer is connected through the metal connection layer 5 in the top deep hole 10, and the middle silicon wiring layer 6 on the lowermost layer is connected through the metal connection layer 5 in the middle deep hole 60 of the middle silicon wiring layer 6.

[0091] Specifically, the middle deep hole 60 of the middle silicon wiring layer 6 located in the upper layer includes a first middle deep hole 600 and a second middle deep hole 601. The first middle deep hole 600 is connected to the middle deep hole 60 of the middle silicon wiring layer 6 located in the lower layer. The second middle deep hole 601 penetrates the insulating layer 2 between the two middle silicon wiring layers 6 and extends to the upper surface of the middle silicon wiring layer 6 located below. The second middle deep hole 601 is not connected to the middle deep hole 60 of the hungry middle silicon wiring layer 6 in the lower layer. The top deep hole 10 includes a first top deep hole 100 and a second top deep hole 101. The first top deep hole 100 is opposite to and connected to the middle deep hole 60 of the middle silicon wiring layer 6 located in the upper layer. The second top deep hole 101 penetrates the insulating layer 2 between the top silicon wiring layer 1 and the middle silicon wiring layer 6 of the uppermost layer and The second top deep hole 101 is not connected to the middle deep hole 60. The metal connection layer 5 includes a first metal connection layer 50, a second metal connection layer 51 and a third metal connection layer 52. The second metal layer is located in the second top deep hole 101 and conductively connects the top middle silicon wiring layer 6 and the top silicon wiring layer 1. The first metal connection layer 50 and the third metal connection layer 52 are both arranged in the first top deep hole 100, and the third metal connection layer 52 is located in the first middle deep hole 600 and extends to the lower middle deep hole 60. The third metal connection layer 52 conductively connects the bottom silicon wiring layer 3, the two middle silicon wiring layers 6 and the top silicon wiring layer 1. The first metal connection layer 50 is located in the second middle deep hole 601, and the second metal connection layer 50 conductively connects the top silicon wiring layer 1 and the two middle silicon wiring layers 6.

[0092] The difference between this embodiment and the second embodiment is that step S2 and step S3 further include step S20 between step S2 and step S3:

[0093] Selecting a low resistivity middle layer silicon SOI silicon wafer as the middle silicon wiring layer 6 wafer, and performing silicon-oxygen-silicon bonding with the middle silicon wiring layer 6 after oxidation;

[0094] The substrate silicon and buried oxide layer of the SOI silicon wafer of the upper middle silicon wiring layer 6 are removed by mechanical thinning and corrosion, and photolithography and etching are performed to remove the silicon at the deep hole and the bottom silicon oxide layer to form a middle deep hole 60, wherein the middle deep hole 60 includes a first middle deep hole 600 and a second middle deep hole 601, wherein the first middle deep hole 600 is connected to the middle deep hole 60 of the middle silicon wiring layer 6 located at the lower layer, and the second middle deep hole 601 penetrates the insulating layer 2 between the two middle silicon wiring layers 6 and extends to the upper surface of the middle silicon wiring layer 6 located below, and the second middle deep hole 601 is not connected to the middle deep hole 60 of the hungry middle silicon wiring layer 6 at the lower layer;

[0095] The uppermost middle silicon wiring layer 6 is photolithographically and etched to form a middle silicon wiring structure and then form the upper middle silicon wiring layer 6, forming a Fig.12 The structure shown.

[0096] It should be understood that the terms "upper", "lower", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0097] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0098] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0099] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0100] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A multi-layer silicon electrical interconnect structure, characterized in that: The invention comprises a top silicon wiring layer (1), an insulating layer (2), and a bottom silicon wiring layer (3) which are arranged in sequence from top to bottom. The bottom silicon wiring layer (3) has a bottom silicon wiring structure, and the top silicon wiring layer (1) has a top silicon wiring structure. The top silicon wiring layer (1) has a top deep hole (10), and the top deep hole (10) penetrates the insulating layer (2). A metal connection layer (5) is arranged in the top deep hole (10), and the metal connection layer (5) electrically connects the bottom silicon wiring layer (3) and the top silicon wiring layer (1).

2. The multi-layer silicon electrical interconnect structure and preparation method according to claim 1, characterized in that: The top silicon wiring layer (1) is connected to the bottom silicon wiring layer (3) via silicon-oxygen-silicon bonding.

3. The multi-layer silicon electrical interconnect structure according to claim 1, characterized in that: There is a substrate layer (4) below the bottom silicon wiring layer (3).

4. The multi-layer silicon electrical interconnect structure according to claim 1, characterized in that: The invention also comprises a middle silicon wiring layer (6), on which a middle silicon wiring structure is provided, the middle silicon wiring layer (6) is located between the bottom silicon wiring layer (3) and the bottom silicon wiring layer (3), an insulating layer (2) is provided between the middle silicon wiring layer (6), the bottom silicon wiring layer (3) and the top silicon wiring layer (1), and the middle silicon wiring layer (6), the bottom silicon wiring layer (3) and the top silicon wiring layer (1) are all conductively connected via the metal connection layer (5).

5. The multi-layer silicon electrical interconnect structure according to claim 4, characterized in that: The middle silicon wiring layer (6) is provided with a middle deep hole (60) penetrating the insulating layer (2) located on the bottom silicon wiring layer (3); the top deep hole (10) comprises a first top deep hole (100) and a second top deep hole (101); the first top deep hole (100) is opposite to and connected to the middle deep hole (60); the second top deep hole (101) penetrates the insulating layer (2) located between the top silicon wiring layer (1) and the middle silicon wiring layer (6); the metal connection layer (5) comprises a first metal connection layer (50) arranged in the first top deep hole (100) and a second metal connection layer (51) arranged in the second top deep hole (101); the first metal connection layer (50) electrically connects the bottom silicon wiring layer (3), the middle silicon wiring layer (6) and the top silicon wiring layer (1); the second metal connection layer (51) electrically connects the middle silicon wiring layer (6) and the top silicon wiring layer (1).

6. The multi-layer silicon electrical interconnect structure according to claim 4, characterized in that: The middle silicon wiring layer (6) is provided with at least two layers, an insulating layer (2) is provided between any two adjacent groups of the middle silicon wiring layers (6), and the middle silicon wiring layer (6), the bottom silicon wiring layer (3) and the top silicon wiring layer (1), as well as adjacent middle silicon wiring layers (6) are all conductively connected via the metal connection layer (5).

7. A method for preparing a multi-layer silicon electrical interconnect structure, characterized in that: The steps include: S1. Fabrication of bottom silicon wiring layer (3): Selecting a bottom silicon SOI silicon wafer as a bottom silicon wiring layer (3) wafer, performing photolithography and etching to form a bottom silicon wiring structure to form a bottom silicon wiring layer (3); S2. Wiring layer bonding: A top silicon SOI silicon wafer is selected as a top silicon wiring layer (1) wafer, and after oxidation, silicon-oxygen-silicon bonding is performed with a bottom silicon wiring layer (3); S3. Preparation of top deep hole (10): The substrate silicon and buried oxide layer of the SOI silicon wafer of the top silicon are removed by mechanical thinning and corrosion, and the silicon at the deep hole and the bottom silicon oxide layer are removed by photolithography and etching to form a top deep hole (10), wherein the top deep hole (10) extends to the upper surface of the bottom silicon wiring layer (3); S4. Preparing a metal connection layer (5): A metal connection layer (5) is prepared by sputtering or evaporation, and photolithography and etching are performed to form a connection metal connection layer (5), wherein the metal connection layer (5) in the top deep hole (10) realizes the connection between the top silicon wiring layer (1) and the bottom silicon wiring layer (3); S5, preparing a top silicon wiring structure of the top silicon wiring layer (1): Photolithography and etching are performed to form a top silicon wiring structure, thereby forming a top silicon wiring layer (1).

8. A method for preparing a multi-layer silicon electrical interconnect structure, characterized in that: The steps include: S1. Fabrication of bottom silicon wiring layer (3): Selecting a bottom silicon SOI silicon wafer as a bottom silicon wiring layer (3) wafer, performing photolithography and etching to form a bottom silicon wiring structure to form a bottom silicon wiring layer (3); S2, the middle silicon wiring layer (6) is bonded to the bottom silicon wiring layer (3): The SOI silicon wafer of the middle silicon is selected as the middle silicon wiring layer (6) wafer, and after oxidation, silicon-oxygen-silicon bonding is performed with the bottom silicon wiring layer (3); The substrate silicon and buried oxide layer of the SOI silicon wafer of the middle silicon wiring layer (6) are removed by mechanical thinning and corrosion, and the silicon at the deep hole and the bottom silicon oxide layer are removed by photolithography and etching to form a middle deep hole (60), wherein the middle deep hole (60) extends to the upper surface of the bottom silicon wiring layer (3); Performing photolithography and etching on the middle silicon wiring layer (6) to form a middle silicon wiring structure, thereby forming a middle silicon wiring layer (6); S3, the middle silicon wiring layer (6) is bonded to the top silicon wiring layer (1): A top silicon SOI silicon wafer is selected as a top silicon wiring layer (1) wafer, and after oxidation, silicon-oxygen-silicon bonding is performed with a middle silicon wiring layer (6); S4. Preparation of top deep hole (10): The substrate silicon and buried oxide layer of the SOI silicon wafer of the top silicon are removed by mechanical thinning and corrosion, and the silicon at the deep hole and the bottom silicon oxide layer are removed by photolithography and etching to form a top deep hole (10), and the top deep hole (10) extends to the upper surface of the middle silicon wiring layer (6); S5. Preparing a metal connection layer (5): A metal connection layer (5) is prepared by sputtering or evaporation, and photolithography and etching are performed to form a connection metal connection layer (5), wherein the metal connection layer (5) in the top deep hole (10) realizes conductive connection between the middle silicon wiring layer (6), the bottom silicon wiring layer (3) and the top silicon wiring layer (1); S6, preparing a top silicon wiring structure of the top silicon wiring layer (1): Photolithography and etching are performed to form a top silicon wiring structure to form a top silicon wiring layer (1).

9. The method for preparing a multi-layer silicon electrical interconnect structure according to claim 8, characterized in that: In step S4, the top deep hole (10) comprises a first top deep hole (100) and a second top deep hole (101), wherein the first top deep hole (100) is opposite to and connected to the middle deep hole (60), and the second top deep hole (101) penetrates the insulating layer (2) located between the top silicon wiring layer (1) and the middle silicon wiring layer (6); In step S5, the metal connection layer (5) includes a first metal connection layer (50) and a second metal connection layer (51), wherein the first metal connection layer (50) conductively connects the bottom silicon wiring layer (3), the middle silicon wiring layer (6) and the top silicon wiring layer (1), and the second metal connection layer (51) conductively connects the middle silicon wiring layer (6) and the top silicon wiring layer (1).

10. The method for preparing a multi-layer silicon electrical interconnect structure according to claim 8, characterized in that: Step S20 is also included between step S2 and step S3: Selecting a middle silicon SOI silicon wafer as a middle silicon wiring layer (6) wafer, performing silicon-oxygen-silicon bonding with the middle silicon wiring layer (6) after oxidation; The substrate silicon and buried oxide layer of the SOI silicon wafer of the upper middle silicon wiring layer (6) are removed by mechanical thinning and corrosion, and the silicon at the deep hole and the bottom silicon oxide layer are removed by photolithography and etching to form a middle deep hole (60), wherein the middle deep hole (60) extends to the upper surface of the middle silicon wiring layer (6) of the lower layer; The uppermost middle silicon wiring layer (6) is subjected to photolithography and etching to form a middle silicon wiring structure and then to form an upper middle silicon wiring layer (6).

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