A multi-channel test circuit suitable for measuring chip leakage characteristic curve
By improving the connection method and control logic of matrix switches, a multi-channel test circuit suitable for chip leakage characteristic curve measurement was designed, which solved the problems of limited testing accuracy, complex control logic and reliability in the prior art, and achieved high-precision detection and system simplification.
Patent Information
- Application Number
- CN202510019937.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-04-08
Smart Images
Figure CN119780680A_ABST
Abstract
Description
Technical Field
[0001] The present invention is applied to the technical field of leakage testing, and in particular relates to a multi-channel testing circuit suitable for measuring a chip leakage characteristic curve. Background Art
[0002] For single chips or SIP chips, the leakage characteristic curve of the chip pins is an important electrical characteristic parameter that reflects the semiconductor characteristics and power consumption of the chip. Through voltage scanning, the voltage and current data of each point in the circuit can be obtained, and then the leakage curve can be drawn to help engineers determine whether the working status of the circuit is normal. As an important electronic component, the matrix switch plays a key role in the voltage scanning process. The matrix switch is composed of multiple switching elements, each of which can be connected to two or more contacts. By controlling the conduction state of the switching element, switching between different signals can be achieved. During the voltage scanning process, the matrix switch can be used to select different signal paths, thereby realizing the switching and selection of multi-channel networks.
[0003] Currently, existing open-short circuit detection schemes mainly adopt series or parallel connection methods.
[0004] Series connection: In this method, multiple networks are connected in series according to certain rules, and open and short circuit tests of multiple networks can be realized. However, as the number of signals increases, the complexity of the series connection will also increase, which limits its application in the case of a large number of signals, and there will be many limitations, and it may not be possible to accurately measure every loop.
[0005] Parallel connection: In this method, multiple networks are connected in parallel according to certain rules, so that multiple signals can enter a specific output terminal at the same time, thereby realizing multi-channel open and short circuit testing. Although the parallel connection method is suitable for situations with a large number of signals, it is impossible to accurately determine the abnormality of a certain circuit in actual applications.
[0006] The prior art has the following disadvantages: 1. Limited test accuracy: Regardless of the series or parallel connection method, as the number of signals increases, the number of series and parallel loops increases, and it is impossible to accurately determine the abnormality of a certain loop in the loop.
[0007] 2. Complex control logic: In existing implementations, achieving both open circuit and short circuit requires complex control logic to ensure accurate signal switching and selection, which increases the complexity of the system and the difficulty of debugging.
[0008] 3. Reliability issues: Due to the numerous connections and complex control logic, failures are prone to occur, thus affecting the reliability of the system.
[0009] Therefore, it is necessary to provide a multi-channel test circuit suitable for measuring the chip leakage characteristic curve, simplifying the system complexity, improving control efficiency, having high-precision detection capability, enhancing system reliability, being easy to integrate and expand, and meeting the needs of circuit open and short circuit conditions and chip and substrate connectivity analysis by improving the connection method and control logic of the matrix switch. Summary of the invention
[0010] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art and provide a multi-channel test circuit suitable for measuring the leakage characteristic curve of a chip, which simplifies the system complexity, improves the control efficiency, has high-precision detection capability, enhances the system reliability, is easy to integrate and expand, and meets the needs of circuit open and short circuit conditions and chip and substrate connectivity analysis by improving the connection mode and control logic of the matrix switch.
[0011] The technical solution adopted by the present invention is: the present invention includes an MCU module, a digital-to-analog converter, an analog-to-digital converter, an amplifier circuit, a feedback circuit, an electronic switch, an analog switch, a reverse circuit, a calibration loop, a digital multimeter, a range switching circuit, a matrix switch, a differential sampling circuit, and a circuit under test. The MCU module is connected to the amplifier circuit via the digital-to-analog converter, the output end of the amplifier circuit is divided into three paths, one path is connected to the analog switch via the reverse circuit, two paths are connected to the range switching circuit, and three paths are connected to the electronic switch via the feedback circuit. The analog switch is divided into two paths, one path is connected to the range switching circuit, and two paths are connected to the digital multimeter via the calibration loop. The range switching circuit is divided into two paths, one path is connected to the circuit under test via the matrix switch, and two paths are connected to the analog-to-digital converter via the differential sampling circuit. The electronic switch is connected to the MCU module via the analog-to-digital converter.
[0012] As can be seen from the above scheme, the multi-channel test circuit provides an improved method of switching a multi-channel network using a matrix switch to perform an open-short circuit test, which can improve the accuracy and efficiency of the measurement, expand the scope of application, and simplify the operation process. In addition, the hardware of this method is small in size and low in cost, and it is easy to implement high-precision and accurate testing of such SIP packaged chips during quantitative production, and is also suitable for verification testing in the product development stage; this application has the following advantages: 1. Simplify system complexity: Reduce system complexity and cost by optimizing the connection mode and control logic of the matrix switch. Improve control efficiency: Design a simpler and more efficient control logic to ensure accurate switching and selection of signals and improve system control efficiency.
[0013] 2. High-precision detection capability: The VI curve can be measured by voltage point scanning, accurately capturing the tiny voltage and current changes at the chip and substrate pad points, thereby achieving accurate analysis of welding problems. Whether it is welding fracture, dirt or missing parts, it can be clearly reflected on the voltage and current curve, improving the accuracy and reliability of detection.
[0014] 3. Enhance system reliability: By optimizing the connection and control methods of the matrix switch, the possibility of failure is reduced and the reliability of the system is improved.
[0015] 4. Easy to integrate and expand: The test system of the present application is easy to integrate with other test equipment and software, making it convenient for users to incorporate it into the existing test process. In addition, the system has good scalability and can easily cope with more test requirements that may arise in the future. Whether it is increasing the number of test points, improving test accuracy or introducing new test functions, the present invention can provide flexible support and solutions.
[0016] In summary, the present application aims to provide a simpler, more efficient and more reliable voltage scanning method by improving the connection mode and control logic of the matrix switch, so as to meet the needs of modern electronic testing and analysis for circuit open and short circuit conditions and chip and substrate connectivity analysis.
[0017] A preferred solution is that the multi-channel test circuit suitable for measuring the chip leakage characteristic curve also includes a filtering circuit, the filtering circuit includes a first resistor and a capacitor, the OUT0 terminal of the digital-to-analog converter is connected to the positive input terminal of the amplifier circuit via the first resistor, and the first resistor is grounded via the capacitor.
[0018] A preferred solution is that the digital-to-analog converter uses a 16-bit high-precision DAC with an internal reference voltage as a voltage output source, with a minimum resolution of This determines the system accuracy A preferred solution is that the filter circuit is used to filter out high-frequency clutter, and the cut-off low-pass frequency is designed according to actual needs. , here we choose R:3Kohm / C:560pf, Cutoff frequency The calculation formula is: A preferred solution is that the amplification circuit includes an operational amplifier, the inverting circuit includes an inverting proportional amplifier, the amplification factor of the inverting proportional amplifier is: B=-1, the output end of the operational amplifier is connected to the inverting input end of the inverting proportional amplifier, the positive input end of the inverting proportional amplifier is connected to the second resistor, the amplification factor of the operational amplifier is related to the sampling interval and the sampling accuracy, and the minimum resolution is The maximum drive is 30mA; The simplified formula of the amplification factor of the amplifier circuit is: At this time, the power output range is adjusted to: A preferred solution is that the output end of the inverting proportional amplifier is connected to the SB end of the analog switch, and the analog switch is used to switch the positive and negative power supply output modes to expand the scanning interval. A preferred solution is that the calibration loop includes a relay, and the relay performs linear fitting calibration on the output voltage and the voltage range of the digital multimeter in parallel, or performs linear fitting calibration on the current loop in series on the current range of the DMM, wherein KB is introduced into the setting and measurement loop as a linear calibration coefficient and stored in the memory preset of the MCU module, and the linear fitting calculates K&B by the least square method from the two sets of series of expected data and original data, A preferred solution is that the range switching circuit includes a multi-channel electronic switch, and the multi-channel electronic switch switches different sampling resistors and gain resistors of the differential sampling circuit to achieve different current measurement ranges. Taking 3.3V as an example, in order to measure negative current, the reference voltage is set to 1.8V, the sampling resistors are divided into: 2R / 100R / 1K / 10K, and the differential sampling gain ratio is divided into: 20.8 / 100, Rs=2ohm Gain=20.8 range: [-36mA~36mA] Gain=100 range: [-7.5mA~7.5mA] Rs=100ohm Gain=20.8 range: [-0.75mA~0.75mA] Gain=100 range: [-0.15mA~0.15mA] Rs=1Kohm Gain=20.8 range: [-75uA~75uA]Gain=100 range: [-15uA~15uA] Rs=10Kohm Gain=20.8 range: [-7.5uA~7.5uA] Gain=100 range: [-1.5uA~1.5uA] The voltage of the differential sampling circuit is switched to the digital-to-analog converter through the analog switch to measure the voltage value, and the voltage acquisition formula is: Current measurement formula: Current sampling is brought into the calibration coefficient formula: A preferred solution is that the matrix switch is used to cut through the circuit under test, use the IIC bus of the MCU module to communicate and switch each circuit, and cut through any X pin to any Y pin to cope with the various requirements of short circuit and functional testing of a large number of PAD points under test in chip pin BGA / SIP and other packages. The leakage current of the matrix switch is as small as 1nA. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 is a system topology block diagram of the present invention; Figure 2 It is a circuit schematic diagram of the present invention; Figure 3 is a matrix switch circuit diagram of the present invention; Figure 4 It is a matrix switch leakage current test curve diagram of the present invention; Figure 5 is the multi-channel scanning curve of the present invention; Figure 6 is a single channel scanning curve of the present invention; Figure 7 is the short-circuit scanning curve of the present invention; Figure 8 is the open circuit scanning curve of the present invention; Fig. 9 It is the first part of the original data table of the curve drawing of the present invention; Fig.10 It is the second part of the original data table for curve drawing of the present invention. DETAILED DESCRIPTION
[0020] like Figures 1 to 3As shown, in this embodiment, the present invention includes an MCU module 1, a digital-to-analog converter 2, an analog-to-digital converter 3, an amplifier circuit 4, a feedback circuit 5, an electronic switch 6, an analog switch 7, a reverse circuit 8, a calibration loop 9, a digital multimeter 10, a range switching circuit 11, a matrix switch 12, a differential sampling circuit 13, and a circuit under test 14. The MCU module 1 is connected to the amplifier circuit 4 via the digital-to-analog converter 2. The output end of the amplifier circuit 4 is divided into three paths, one of which is connected to the analog switch 7 via the reverse circuit 8, two of which are connected to the range switching circuit 11, and three of which are connected to the electronic switch 6 via the feedback circuit 5. The analog switch 7 is divided into two paths, one of which is connected to the range switching circuit 11, and two of which are connected to the digital multimeter 10 via the calibration loop 9. The range switching circuit 11 is divided into two paths, one of which is connected to the circuit under test 14 via the matrix switch 12, and two of which are connected to the analog-to-digital converter 3 via the differential sampling circuit 13. The electronic switch 6 is connected to the MCU module 1 via the analog-to-digital converter 3.
[0021] The MCU module 1 can store presets, communicate with the host computer in real time, and interact with the digital-to-analog converter 2 and the analog-to-digital converter 3 via the SPI bus.
[0022] The digital-to-analog converter 2 configures the internal registers of the MCU module 1 to output high-precision voltage values via the SPI bus.
[0023] The analog-to-digital converter 3 is configured for voltage measurement through the built-in pins of the MCU module 1 .
[0024] The amplifier circuit 4 is used for signal amplification to increase current output capability.
[0025] The calibration loop 9 can be used for loop voltage measurement and regulation.
[0026] The electronic switch 6 is used for switching the voltage measurement network.
[0027] The analog switch 7 is used for switching between positive and negative voltage gears.
[0028] The reverse circuit 8 is used to adjust the positive and negative values of the output voltage.
[0029] The calibration loop 9 is used to calibrate the output voltage and the measured current value.
[0030] The range switching circuit 11 is used to switch the current measurement range.
[0031] The differential sampling circuit 13 is used to sample the current value in the series loop.
[0032] The matrix switch 12 is used to switch the measurement loop.
[0033] The circuit under test 14 is a circuit to be measured by voltage scanning.
[0034] like Figure 1 and Figure 2 As shown, in this embodiment, the multi-channel test circuit suitable for measuring the chip leakage characteristic curve further includes a filter circuit 15, the filter circuit 15 includes a first resistor R2 and a capacitor C4, the OUT0 end of the digital-to-analog converter 2 is connected to the positive input end of the amplifier circuit 4 via the first resistor R2, and the first resistor R2 is grounded via the capacitor C4. The filter circuit 15 can be configured as a low-pass filter to filter out high-frequency noise.
[0035] like Figure 1 and Figure 2 As shown, in this embodiment, the digital-to-analog converter 2 uses a 16-bit high-precision DAC with an internal reference voltage as a voltage output source, and the minimum resolution is This determines the system accuracy like Figure 1 and Figure 2 As shown, in this embodiment, the filter circuit 15 is used to filter out high-frequency noise, and the cut-off low-pass frequency is designed according to actual needs. , here we choose R:3Kohm / C:560pf, Cutoff frequency The calculation formula is: like Figure 1 and Figure 2 As shown, in this embodiment, the amplification circuit 4 includes an operational amplifier U3, the inverting circuit 8 includes an inverting proportional amplifier U1, the amplification factor of the inverting proportional amplifier U1 is: B=-1, the output end of the operational amplifier U3 is connected to the inverting input end of the inverting proportional amplifier U1, the positive input end of the inverting proportional amplifier U1 is connected to the second resistor R1, the amplification factor of the operational amplifier U3 is related to the sampling interval and the sampling accuracy, and the minimum resolution is The maximum drive is 30mA; if you need to increase the output current capability, you need to add a drive level circuit. The simplified formula of the amplification factor of the amplifier circuit 4 is: At this time, the power output range is adjusted to: like Figure 1 and Figure 2 As shown, in this embodiment, the output end of the inverting proportional amplifier U1 is connected to the SB end of the analog switch 7, and the analog switch 7 is used to switch the positive and negative power supply output modes to expand the scanning interval. like Figure 1 and Figure 2 As shown, in this embodiment, the calibration loop 9 includes a relay K1, and the relay K1 performs linear fitting calibration on the output voltage and the voltage range of the digital multimeter 10 in parallel, or performs linear fitting calibration on the current loop in series on the DMM current range, wherein K gain B bias is introduced into the setting and measurement loop as a linear calibration coefficient and stored in the memory preset of the MCU module 1. The linear fitting calculates K&B by the least square method from the two sets of series of expected data and original data. like Figure 1 and Figure 2 As shown, in this embodiment, the range switching circuit 11 includes a multi-channel electronic switch U6, and the multi-channel electronic switch U6 switches different sampling resistors and gain resistors of the differential sampling circuit 13 to achieve different current measurement ranges. Taking 3.3V as an example, in order to measure the negative current, the reference voltage 1.8V is set, the sampling resistors are divided into: 2R / 100R / 1K / 10K, and the differential sampling gain ratio is divided into: 20.8 / 100, Rs=2ohm Gain=20.8 range: [-36mA~36mA] Gain=100 range: [-7.5mA~7.5mA] Rs=100ohm Gain=20.8 range: [-0.75mA~0.75mA] Gain=100 range: [-0.15mA~0.15mA] Rs=1Kohm Gain=20.8 range: [-75uA~75uA]Gain=100 range: [-15uA~15uA] Rs=10Kohm Gain=20.8 range: [-7.5uA~7.5uA] Gain=100 range: [-1.5uA~1.5uA] The voltage of the differential sampling circuit 13 is switched to the digital analog converter 2 through the analog switch 7 to obtain the measured voltage value. The voltage acquisition formula is 2R / 20.8 as an example: The current measurement formula takes 2R / 20.8 as an example: Current sampling is brought into the calibration coefficient formula: like Figure 1 and Figure 2 As shown, in this embodiment, the matrix switch 12 is used to cut through the circuit under test, use the IIC bus of the MCU module 1 to communicate and switch each circuit, and cut through any X pin to any Y pin to cope with the chip pin BGA / SIP and other packages with a large number of PAD points under test to open short circuit and functional test various requirements, the leakage current of the matrix switch 12 is extremely small, 1nA.
[0036] In this embodiment, the digital-to-analog converter 2 is of the model DAC80508ZRTET, and the internal DAC of the MCU module 1 can also be used to save costs. The model of the analog switch 7 is ADG1419BRMZ, the model of the operational amplifier U3 is OPA2991SIRUGR, the model of the relay K1 is AGQ200A4H. The model of the multi-channel electronic switch U6 is ADG1604BRUZ.
[0037] like Figure 3 As shown, in this embodiment, the model of the matrix switch 12 is ADG2128BCPZ-REEL7. The matrix switch 12 is used to switch through the circuit under test. The IIC bus of the MCU module 1 can be used to communicate and switch various circuits, and any X pin can be switched to any Y pin to cope with the needs of short circuit and function test of a large number of PAD points under test in BGA / SIP and other chip pin packages. At the same time, the leakage current of the matrix switch 12 is extremely small, about 1nA, which has little effect on high-precision current measurement.
[0038] like Figures 4 to 10 As shown, this application performs an open-short circuit test on the pins of the SIP packaged chip, with a scanning voltage range of -760mV~1000mV. 40mV step, current measurement at the same time A VI curve can be drawn. For logic chip pins, there is a reverse diode connected in parallel to the interface, so the normal graph is similar to the diode VI curve.
[0039] like Figure 7As shown, X1 is scanned during the short circuit test. Then other X2~Xx are connected to Y-GND. If X1 and X2 are short-circuited, the X1 pin will also be short-circuited to GND by X2. For the entire model, it is similar to a voltage source connected in series with a resistor connected to GND (matrix switches, lines, range switching circuits, etc. can be equivalent to series resistors), so a graph similar to the VI curve of a resistor is drawn.
[0040] like Figure 8 As shown in the figure, X1 is scanned during the open circuit test. For the entire model, it is similar to the voltage source being suspended, and almost no current flows through the sampling resistor.
[0041] Draw a certain analysis of the curve of the graph, set the upper and lower limits of the current at different voltage points, and filter out chips with abnormal package interfaces. For example, when the voltage is set to -760mV, the current PASS interval [-5mA, -0.01mA] can filter out open circuits, and when the voltage is set to 800mV, the current PASS interval [0mA, 0.3mA] can filter out short circuits. The analysis method can be customized according to the actual needs of the project.
[0042] Although the embodiments of the present invention are described with practical solutions, they do not constitute limitations on the meaning of the present invention. For those skilled in the art, it is obvious to modify the implementation scheme and combine it with other solutions based on this description.
Claims
1. A multi-channel test circuit suitable for measuring chip leakage characteristic curve, characterized in that: It comprises an MCU module (1), a digital-to-analog converter (2), an analog-to-digital converter (3), an amplifier circuit (4), a feedback circuit (5), an electronic switch (6), an analog switch (7), a reverse circuit (8), a calibration loop (9), a digital multimeter (10), a range switching circuit (11), a matrix switch (12), a differential sampling circuit (13), and a circuit to be tested (14). The MCU module (1) is connected to the amplifier circuit (4) via the digital-to-analog converter (2). The output end of the amplifier circuit (4) is divided into three paths, one of which is connected to the analog switch (7) via the reverse circuit (8), and the other is connected to the analog switch (7) via the reverse circuit (8). The analog switch (7) is divided into two paths, one of which is connected to the range switching circuit (11), and the other is connected to the digital multimeter (10) via the calibration loop (9). The range switching circuit (11) is divided into two paths, one of which is connected to the measured circuit (14) via the matrix switch (12), and the other is connected to the analog-to-digital converter (3) via the differential sampling circuit (13). The electronic switch (6) is connected to the MCU module (1) via the analog-to-digital converter (3).
2. A detection method according to claim 1, characterized in that: The multi-channel test circuit suitable for measuring chip leakage characteristic curves further comprises a filter circuit (15), the filter circuit (15) comprising a first resistor (R2) and a capacitor (C4), an OUT0 terminal of the digital-to-analog converter (2) is connected to a positive input terminal of the amplifier circuit (4) via the first resistor (R2), and the first resistor (R2) is grounded via the capacitor (C4).
3. A multi-channel test circuit suitable for measuring chip leakage characteristic curve according to claim 2, characterized in that: The digital-to-analog converter (2) uses a 16-bit high-precision DAC with an internal reference voltage as a voltage output source, with a minimum resolution of This determines the system accuracy 4. A multi-channel test circuit suitable for measuring chip leakage characteristic curve according to claim 3, characterized in that: The filter circuit (15) is used to filter out high-frequency noise, and the cut-off low-pass frequency is designed according to actual needs. , here we choose R:3Kohm / C:560pf, Cutoff frequency The calculation formula is:
5. A multi-channel test circuit suitable for measuring chip leakage characteristic curve according to claim 4, characterized in that: The amplification circuit (4) includes an operational amplifier (U3), the inverting circuit (8) includes an inverting proportional amplifier (U1), the amplification factor of the inverting proportional amplifier (U1) is: B=-1, the output end of the operational amplifier (U3) is connected to the inverting input end of the inverting proportional amplifier (U1), the positive input end of the inverting proportional amplifier (U1) is connected to the second resistor (R1), the amplification factor of the operational amplifier (U3) is related to the sampling interval and the sampling accuracy, and the minimum resolution is The maximum drive is 30mA; The simplified formula of the amplification factor of the amplifier circuit (4) is: At this time, the power output range is adjusted to:
6. A multi-channel test circuit suitable for measuring chip leakage characteristic curve according to claim 5, characterized in that: The output end of the inverting proportional amplifier (U1) is connected to the SB end of the analog switch (7), and the analog switch (7) is used to switch the positive and negative power supply output modes and expand the scanning interval.
7. A multi-channel test circuit suitable for measuring chip leakage characteristic curve according to claim 6, characterized in that: The calibration loop (9) comprises a relay (K1), wherein the relay (K1) performs linear fitting calibration on the output voltage and the voltage range of the digital multimeter (10) in parallel, or performs linear fitting calibration on the current loop connected in series to the current range of the DMM, wherein K (gain) and B (bias) are introduced into the setting and measurement loop as linear calibration coefficients and stored in the memory preset of the MCU module (1). The linear fitting calculates K&B by using the least square method from the two sets of series of expected data and original data.
8. A multi-channel test circuit suitable for measuring chip leakage characteristic curve according to claim 7, characterized in that: The range switching circuit (11) comprises a multi-channel electronic switch (U6), wherein the multi-channel electronic switch (U6) switches different sampling resistors and gain resistors of the differential sampling circuit (13) to achieve different current measurement ranges. Taking 3.3V as an example, in order to measure negative current, a reference voltage of 1.8V is set, and the sampling resistors are divided into: 2R / 100R / 1K / 10K, and the differential sampling gain ratio is divided into: 20.8 / 100. Rs=2ohm Gain=20.8 range: [-36mA~36mA] Gain=100 range: [-7.5mA~7.5mA] Rs=100ohm Gain=20.8 range: [-0.75mA~0.75mA] Gain=100 range: [-0.15mA~0.15mA] Rs=1Kohm Gain=20.8 range: [-75uA~75uA] Gain=100 range: [-15uA~15uA] Rs=10Kohm Gain=20.8 range: [-7.5uA~7.5uA] Gain=100 range: [-1.5uA~1.5uA] The voltage of the differential sampling circuit (13) is switched to the digital-to-analog converter (2) through the analog switch (7) to measure the voltage value, and the voltage acquisition formula (taking 2R / 20.8 as an example) can be obtained: Current measurement formula (taking 2R / 20.8 as an example): Current sampling is brought into the calibration coefficient formula:
9. A multi-channel test circuit suitable for measuring chip leakage characteristic curve according to claim 8, characterized in that: The matrix switch (12) is used to switch through the circuit under test, using the IIC bus communication of the MCU module (1) to switch each circuit, switching any X pin to any Y pin, so as to cope with various requirements of short circuit and function test of a large number of PAD points under test in chip pin BGA / SIP and other packages, and the leakage current of the matrix switch (12) is extremely small, at 1 nA.