Time-to-digital converter of successive approximation structure

Abstract

The invention provides a time-to-digital converter of a successive approximation structure, and relates to the technical field of converters, and the time-to-digital converter comprises a digital conversion module which is configured to receive a first time signal group; according to the first time signal group, outputting a first discrimination signal group to an output logic circuit, and executing a selection delay processing operation on the first time signal group to obtain a second time signal group; the second time signal group is used for being input into the digital conversion module at the rear end of the digital conversion module and is used for being input into the tail end discriminator; the end discriminator is configured to receive a second time signal group sent by a digital conversion module electrically connected with the end discriminator; outputting a second discrimination signal group to the output logic circuit according to the second time signal group; and the output logic circuit is configured to output digital code signals according to all the first discrimination signal groups and the second discrimination signal groups so as to solve the problem that the power consumption and the area of the circuit are relatively large due to the fact that the number of required devices is relatively large when an existing time-to-digital converter operates.

Description

Technical Field

[0001] The present application relates to the technical field of converters, and in particular to a time-to-digital converter with a successive approximation structure. Background Art

[0002] Analog-to-digital converters (A / D converters, or ADCs for short) are usually electronic components that convert an input voltage signal into an output digital signal. Nowadays, due to the rapid development of high-speed communications, cloud computing, and the Internet of Things, there is an increasing demand for analog-to-digital converters with medium accuracy (6-10 bits), gigahertz (GHz) sampling rates, and low power consumption.

[0003] Time domain analog-to-digital converter (TD ADC) has become a research hotspot due to its high speed, large bandwidth, small area and low power consumption. TD ADC consists of a voltage-to-time converter (VTC) and a time-to-digital converter (TDC) to complete the conversion from voltage to digital code.

[0004] The TDC structure commonly used in time domain analog-to-digital converters is a flash structure. This structure is fast, but requires a large number of devices. Every time its resolution is increased by 1 bit, the number of required devices will double, causing the circuit power consumption and area to double. Summary of the invention

[0005] The present application provides a time-to-digital converter with a successive approximation structure to solve the technical problem that when the existing time-to-digital converter is in operation, a large number of components are required, resulting in large power consumption and area of ​​the circuit.

[0006] In a first aspect, the present application provides a time-to-digital converter of a successive approximation structure, comprising: at least one digital conversion module electrically connected in sequence and an end discriminator electrically connected to the digital conversion module at the end; and also including an output logic circuit electrically connected to each of the digital conversion modules and the end discriminator respectively; The digital conversion module is configured as follows: Receive a first time signal group; the first time signal group is an initial time signal group or a time signal group output by a digital conversion module located at the front end of the digital conversion module; According to the first time signal group, a first discrimination signal group is output to the output logic circuit, and a selection delay processing operation is performed on the first time signal group to obtain a second time signal group; the second time signal group is used to input a digital conversion module located at the rear end of the digital conversion module, or to input the end discriminator; the end discriminator is configured as: Receiving the second time signal group sent by the digital conversion module electrically connected to the end discriminator; outputting a second discrimination signal group to the output logic circuit according to the second time signal group; The output logic circuit is configured as follows: A digital code signal is outputted based on all of the first discrimination signal group and the second discrimination signal group.

[0007] In some embodiments, the first time signal group includes: a first time signal and a second time signal; the first discrimination signal group includes: a first discrimination sub-signal and a second discrimination sub-signal; The digital conversion module includes: a discriminator, wherein the discriminator is configured to: receiving the first time signal and the second time signal; The first and second determination sub-signals are output to the output logic circuit according to the first and second time signals.

[0008] In some embodiments, the time when the first time signal is input to the digital conversion module is earlier than the time when the second time signal is input to the digital conversion module; The second time signal group includes: a delay signal and a slow signal; the second discrimination signal group includes: a third discrimination sub-signal and a fourth discrimination sub-signal; the selection delay processing operation includes: a fast and slow selection processing operation and a delay processing operation; The digital conversion module further includes: a fast-slow selector and a delay unit, wherein the fast-slow selector is electrically connected to the discriminator and the delay unit; The fast and slow selectors are configured: receiving the first time signal and the second time signal; Performing a fast / slow selection processing operation on the first time signal and the second time signal, obtaining a fast signal based on the first time signal; obtaining a slow signal based on the second time signal; the fast signal is used to input the delay unit; The delay unit is configured: receiving the fast signal; Performing a delay processing operation on the fast signal to obtain a delayed signal; The end discriminator is further configured as follows: Receiving the delayed signal and the slow signal sent by the digital conversion module electrically connected to the end discriminator; The third and fourth determination sub-signals are output to the output logic circuit according to the delay signal and the slow signal.

[0009] In some embodiments, the discriminator and the end discriminator include: A first transistor module, a second transistor module, a third transistor module, and a fourth transistor module that are electrically connected; The first transistor module is configured with four transistors; the second transistor module and the third transistor module are configured with three transistors; the fourth transistor module is configured with two transistors; The first transistor module, the second transistor module, and the third transistor module are configured as follows: According to the level value of the input signal, the transistors in the first transistor module, the second transistor module and the third transistor module are turned on or off to determine the level value of the output signal.

[0010] In some embodiments, the delay unit comprises: Two first inverters are electrically connected; the first inverter is configured with two transistors.

[0011] In some embodiments, the fast / slow selector includes: An electrically connected first signal generator, a second signal generator, a custom AND gate, and a custom OR gate; The first signal generator is configured to: output a first rising edge signal and a first falling edge signal according to a first input signal; the first falling edge signal is an inverse signal of the first rising edge signal, and the first falling edge signal and the first rising edge signal are output simultaneously; The second signal generator is configured to: output a second rising edge signal and a second falling edge signal according to a second input signal; the second falling edge signal is an inverse signal of the second rising edge signal, and the second falling edge signal and the second rising edge signal are output simultaneously; The custom AND gate is configured to: output a slow signal according to the first rising edge signal and the second rising edge signal; The custom OR gate is configured to: output a fast signal according to the first rising edge signal, the first falling edge signal, the second rising edge signal, and the second falling edge signal; If the time when the first input signal is input to the first signal generator is earlier than the time when the second input signal is input to the second signal generator, the first input signal has the same waveform as the fast signal, and the second input signal has the same waveform as the slow signal.

[0012] In some embodiments, the first signal generator and the second signal generator include: A fifth transistor module and a sixth transistor module electrically connected; the fifth transistor module is configured with four transistors, and the sixth transistor module is configured with six transistors; The fifth transistor module is configured to: output the first rising edge signal or the second rising edge signal according to the first input signal or the second input signal; The sixth transistor module is configured to: output the first falling edge signal or the second falling edge signal according to the first input signal or the second input signal; The transistor size ratio in the fifth transistor module is 2:2:3:8; The transistor size ratio in the sixth transistor module is 3:3:4:4:4:8.

[0013] In some embodiments, the custom AND gate includes: A seventh transistor module and an eighth transistor module electrically connected; the seventh transistor module is configured with eight transistors, and the eighth transistor module is configured with two transistors; The custom AND gate is further configured as: According to the first rising edge signal and the second rising edge signal, the transistors in the seventh transistor module are turned on or off to output a slow signal.

[0014] In some embodiments, the custom OR gate includes: A ninth transistor module and a tenth transistor module electrically connected; the ninth transistor module is configured with twelve transistors, and the tenth transistor module is configured with two transistors; The custom OR gate is further configured as: According to the first rising edge signal, the first falling edge signal, the second rising edge signal, and the second falling edge signal, the transistors in the ninth transistor module are turned on or off to output a fast signal.

[0015] In some embodiments, the output logic circuit includes: A second inverter electrically connected to at least one multiplexer; The second inverter is configured to: output a first high-bit digital code signal according to the first discrimination sub-signal and the second discrimination sub-signal; The multiplexer is configured to: output a second high-order digital code signal according to the third discrimination sub-signal and the fourth discrimination sub-signal; The output logic circuit is further configured to: A quantization result is output according to the first high-bit digital code signal and the second high-bit digital code signal.

[0016] The present application provides a time-to-digital converter of a successive approximation structure, comprising: at least one digital conversion module electrically connected in sequence and an end discriminator electrically connected to the digital conversion module located at the end; and also comprising an output logic circuit electrically connected to each of the digital conversion modules and the end discriminator respectively; the digital conversion module is configured to: receive a first time signal group; the first time signal group is an initial time signal group or a time signal group output by a digital conversion module located at the front end of the digital conversion module; output a first discrimination signal group to the output logic circuit according to the first time signal group, and perform a selection delay on the first time signal group. The second time signal group is obtained by performing a late processing operation; the second time signal group is used to input the digital conversion module located at the rear end of the digital conversion module, or is used to input the terminal discriminator; the terminal discriminator is configured to: receive the second time signal group sent by the digital conversion module electrically connected to the terminal discriminator; output a second discrimination signal group to the output logic circuit according to the second time signal group; the output logic circuit is configured to: output a digital code signal according to all the first discrimination signal groups and the second discrimination signal groups, so as to reduce the number of devices required for the operation of the time-to-digital converter, thereby reducing the power consumption and area of ​​the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0018] Figure 1 This is a schematic diagram of the structure of the time-to-digital converter in this application; Figure 2 A circuit diagram of a time-to-digital converter in this application; Figure 3 This is a flowchart of the operation of the time-to-digital converter in this application; Figure 4 is a circuit diagram of the discriminator in this application; Figure 5 It is a schematic diagram of the structure of the delay unit in this application; Figure 6 This is a waveform diagram of the delay unit in the present application when it is running; Figure 7 A circuit diagram of a delay unit in this application; Figure 8 This is a schematic diagram of the structure of the fast and slow selector in this application; Fig. 9 This is a waveform diagram of the fast and slow selector in this application when it is running; Fig.10is a circuit diagram of a signal generator in this application; Fig.11 This is a waveform diagram of the signal generator in this application when it is running; Fig.12 The circuit diagram of the custom AND gate in this application; Fig.13 The circuit diagram of the custom OR gate in this application; Fig.14 is a schematic structural diagram of the second inverter in this application; Fig.15 This is a schematic diagram of the structure of a multiplexer in one embodiment of the present application; Fig.16 is a schematic structural diagram of a multiplexer in another embodiment of the present application; Fig.17 This is a spectrum analysis diagram of the quantification results in this application.

[0019] Description of reference numerals: 1-digital conversion module; 11-discriminator; 111-first transistor module; 112-second transistor module; 113-third transistor module; 114-fourth transistor module; 12-fast and slow selector; 121-first signal generator; 1211-fifth transistor module; 1212-sixth transistor module; 122-second signal generator; 123-custom AND gate; 1231-seventh transistor module; 1232-eighth transistor module; 124-custom OR gate; 1241-ninth transistor module; 1242-tenth transistor module; 13-delay unit; 131-first inverter; 2-end discriminator; 3-output logic circuit; 31-second inverter; 32-multiplexer. DETAILED DESCRIPTION

[0020] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application.

[0021] Since in some technologies, when a time-to-digital converter is running, a large number of devices are required, resulting in large power consumption and area of ​​the circuit, in order to solve this technical problem, the present application provides a time-to-digital converter with a successive approximation structure. The structures of the various parts of the time-to-digital converter are described below: For example, there are many structures of time-to-digital converters (TDCs), and currently common structures include flash type, vernier type, ring oscillator type, and traditional successive approximation circuit structures.

[0022] Exemplarily, the flash TDC circuit is mainly composed of a delay unit, a discriminator and a logic circuit. Its working principle is: the circuit receives two rising edge signals, of which the earliest signal is called the start signal (STA) and the latest signal is called the end signal (STP). The STA signal passes through a series of delay units with a delay time of Td1 to generate a series of signals STA with different delays. <1> , STA <2> , STA <3> Etc., and then compare them with STP. When the signal arrives before STP, the corresponding i-th discriminator will output the result 1; otherwise, when the i-th delayed signal STA When STP arrives later, the corresponding i-th discriminator will output the result 0. The output results of these discriminators can be used through the logic circuit to obtain the output binary code, completing the conversion of the time signal to the digital code signal. There are many flash TDC devices. Every time the resolution is increased by 1 bit, the number of delay units and discriminators required will double, and the power consumption and area of ​​the circuit will also double.

[0023] For example, the vernier type TDC circuit is mainly composed of a delay unit, a discriminator and a logic circuit, and its structure is similar to that of the flash type TDC circuit, except that the STP signal passes through a series of delay units with a delay time of Td2 to generate a series of signals STP with different delays. <1> 、STP <2> 、STP <3> The signal judged by the discriminator is no longer STA Unlike STP, it is STA With STP The accuracy of the vernier TDC is higher than that of the flash TDC, but the number of components becomes larger, and the power consumption and area of ​​the circuit are still high.

[0024] Exemplarily, the traditional successive approximation TDC circuit is mainly composed of a delay unit, a discriminator, an auxiliary delay circuit, a multiplexer (MUX) and a logic circuit, wherein the delay unit, the discriminator, the auxiliary delay circuit and the multiplexer constitute a unit module. The working process of each unit module is as follows: the unit module receives two rising edge signals, which are respectively called the P-end signal and the N-end signal. The discriminator outputs a logical result of 0 or 1 according to the speed of the arrival of the P-end signal and the N-end signal. At the same time, the P-end signal and the N-end signal pass through the auxiliary delay circuit to generate the P0 signal and the N0 signal, and the P0 signal and the N0 signal pass through the delay unit to generate the P1 signal and the N1 signal. The multiplexer selects different signals to be passed to the next-level unit module based on the output result of the discriminator. If the P-terminal signal arrives before the N1 signal, the discriminator outputs a logic result of 1, and the multiplexer passes the P1 signal and the N0 signal to the next level; conversely, if the P-terminal signal arrives after the N1 signal, the discriminator outputs a logic result of 0, and the multiplexer passes the P0 signal and the N1 signal to the next level. Finally, the output results of these discriminators can be passed through the logic circuit to obtain the output binary code, completing the conversion of the time signal to the digital code signal. Compared with the flash TDC and the vernier TDC, the traditional successive approximation TDC circuit reduces the number of discriminators, and reduces the power consumption and area of ​​the circuit. However, since the multiplexer needs to wait for the output result of the discriminator, an additional auxiliary delay circuit is introduced, which reduces the speed of the overall circuit and also increases the power consumption and area of ​​the circuit to a certain extent.

[0025] Based on the above TDC circuit structure, the present application provides a successive approximation TDC circuit structure, which, while retaining the advantages of the traditional successive approximation TDC circuit structure, eliminates the auxiliary delay circuit, improves the speed of the overall circuit, and further reduces the power consumption and area of ​​the circuit.

[0026] like Figure 1 The figure shows a schematic diagram of the structure of the time-to-digital converter in the present application.

[0027] The present application provides a time-to-digital converter with a successive approximation structure, comprising: At least one digital conversion module 1 electrically connected in sequence and an end discriminator 2 electrically connected to the digital conversion module 1 at the end; and also includes an output logic circuit 3 electrically connected to each of the digital conversion modules 1 and the end discriminator 2 respectively.

[0028] The digital conversion module 1 is configured to: receive a first time signal group; the first time signal group is an initial time signal group or a time signal group output by the digital conversion module 1 located at the front end of the digital conversion module 1; output a first discrimination signal group to the output logic circuit 3 according to the first time signal group, and perform a selection delay processing operation on the first time signal group to obtain a second time signal group; the second time signal group is used to input the digital conversion module 1 located at the back end of the digital conversion module 1, or, is used to input the end discriminator 2.

[0029] The end discriminator 2 is configured to: receive the second time signal group sent by the digital conversion module 1 electrically connected to the end discriminator 2; and output a second discrimination signal group to the output logic circuit 3 according to the second time signal group.

[0030] The output logic circuit 3 is configured to output a digital code signal according to all of the first discrimination signal groups and the second discrimination signal groups.

[0031] Exemplarily, the working process of each digital conversion module 1 is as follows: the digital conversion module 1 receives two rising edge signals, which are respectively called the P-end signal and the N-end signal. The discriminator 11 outputs a logic result of 0 or 1 according to the speed of the arrival time of the P-end signal and the N-end signal. At the same time, the speed selector 12 generates two rising edge signals according to the speed of the arrival time of the P-end signal and the N-end signal, wherein the earliest generated signal is called the fast signal (Early), and the latest generated signal is called the slow signal (Late), and the time difference between the Early signal and the Late signal is substantially the same as the time difference between the P-end signal and the N-end signal, and then the Early signal is delayed by the binary weight to generate a corresponding delay signal (Delay). The Delay signal and the Late signal become the P-end signal and the N-end signal of the next-level unit module and are passed on. Finally, the output results of these discriminators can be obtained through the output logic circuit 3 to obtain the output binary code, completing the conversion of the time signal to the digital code. The entire TDC circuit forms a successive approximation structure, which reduces the number of discriminators 11 and reduces the circuit power consumption and area. At the same time, the introduction of the fast / slow selector 12 eliminates the auxiliary delay circuit of the traditional successive approximation TDC, thereby increasing the speed of the overall circuit and further reducing the power consumption and area of ​​the circuit.

[0032] like Figure 3 The figure shows the working flow chart of the time-to-digital converter in the present application during operation.

[0033] For example, assuming that the TDC is 3b, that is, a circuit structure with three discriminators is provided; the delay time Td of the delay unit 13 is 20 picoseconds (ps), then the quantization range of the TDC is . Define that when the rising edge of the Tp signal arrives before the rising edge of the Tn signal, it is a positive input, and when the rising edge of the Tp signal arrives after the rising edge of the Tn signal, it is a negative input. The quantization range of the TDC is corrected to -80ps~80ps. Figure 3 It can be seen that if the input time difference tin is 25ps, since the rising edge of the Tp signal arrives before the rising edge of the Tn signal, the first discriminator outputs the logic result OUTP0 of 1, and the fast and slow selector outputs the fast signal Early1 and the slow signal Late1. After Early1 passes through two delay units, it generates the delayed signal Delay1 (delayed 40ps). Therefore, for the subsequent circuit, the P-end signal becomes Delay1, the N-end signal becomes Late1, and the time difference becomes 15ps. Since the Delay1 signal arrives after the Late1 signal, the second discriminator outputs the logic result OUTP1 of 0, and the fast and slow selector outputs the fast signal Early2 and the slow signal Late2. After Early2 passes through a delay unit, it generates the delayed signal Delay2 (delayed 20ps). Therefore, for the subsequent circuit, the P-end signal becomes Delay2, the N-end signal becomes Late2, and the time difference becomes 5ps. Since the Delay2 signal arrives after the Late2 signal, the third discriminator, the end discriminator 2, outputs the logic result OUTP2 of 0. Finally, the output logic circuit outputs a digital code signal, such as 001, based on the output results of all discriminators.

[0034] like Figure 2 Shown is a circuit diagram of the time-to-digital converter in this application.

[0035] In this embodiment, the first time signal group includes: a first time signal INp and a second time signal INn; the first discrimination signal group includes: a first discrimination sub-signal OUTN0 and a second discrimination sub-signal OUTP0; and the digital conversion module 1 includes: a discriminator 11.

[0036] The discriminator 11 is configured as follows: The first time signal INp and the second time signal INn are received; and the first determination sub-signal OUTN0 and the second determination sub-signal OUTP0 are output to the output logic circuit 3 according to the first time signal INp and the second time signal INn.

[0037] In this embodiment, the time when the first time signal INp is input to the digital conversion module 1 is earlier than the time when the second time signal INn is input to the digital conversion module 1; the second time signal INn group includes: a delay signal Delay and a slow signal Late; the second discrimination signal group includes: a third discrimination sub-signal OUTN2 and a fourth discrimination sub-signal OUTN2; the selection delay processing operation includes: a fast or slow selection processing operation and a delay processing operation; the digital conversion module 1 also includes: a fast or slow selector 12 and a delay unit 13, and the fast or slow selector 12 is electrically connected to the discriminator 11 and the delay unit 13.

[0038] The fast / slow selector 12 is configured to: receive the first time signal INp and the second time signal INn; perform a fast / slow selection processing operation on the first time signal INp and the second time signal INn, and obtain a fast signal Early based on the first time signal INp; and obtain a slow signal Late based on the second time signal INn; and the fast signal Early is used to input the delay unit 13.

[0039] The delay unit 13 is configured to: receive the fast signal Early; and perform a delay processing operation on the fast signal Early to obtain a delayed signal Delay.

[0040] The end discriminator 2 is further configured to: receive the delay signal Delay and the slow signal Late sent by the digital conversion module 1 electrically connected to the end discriminator 2; and output the third discrimination sub-signal OUTN2 and the fourth discrimination sub-signal OUTN2 to the output logic circuit 3 according to the delay signal Delay and the slow signal Late.

[0041] It is worth noting that the number of the digital conversion modules 1 is one or more. When the number of the digital conversion modules 1 is more than one, the digital conversion module 1 located between the digital conversion module 1 at the head end and the terminal discriminator 2 is used to receive the delay signal Delay and the slow signal Late output by the digital conversion module 1 electrically connected to the front end; wherein, the discriminator 11 of the digital conversion module 1 arranged between the digital conversion module 1 at the head end and the terminal discriminator 2 is used to output the first discrimination sub-signal and the second discrimination sub-signal according to the delay signal Delay and the slow signal Late; the fast-slow selector 12 of the digital conversion module 1 arranged between the digital conversion module 1 at the head end and the terminal discriminator 2 is used to output the fast signal Early and the slow signal Late according to the delay signal Delay and the slow signal Late, and the delay unit 13 arranged between the digital conversion module 1 at the head end and the terminal discriminator 2 has the same input signal and output signal as the delay unit 13 arranged in the digital conversion module 1 at the head end.

[0042] like Figure 4 As shown, it is the circuit diagram of the discriminator in this application.

[0043] In this embodiment, the discriminator 11 and the end discriminator 2 include: a first transistor module 111, a second transistor module 112, a third transistor module 113, and a fourth transistor module 114 that are electrically connected; the first transistor module 111 is configured with four transistors, including: M1, M2, M3, and M4; the second transistor module 112 is configured with three transistors, including: M5, M7, and M9; the third transistor module 113 is configured with three transistors, including: M6, M8, and M10; the fourth transistor module 114 is configured with two transistors.

[0044] The first transistor module 111, the second transistor module 112, and the third transistor module 113 are configured to: turn on or off the transistors in the first transistor module 111, the second transistor module 112, and the third transistor module 113 according to the level value of the input signal, and determine the level value of the output signal. The level value of the signal is divided into a high level "1" and a low level value "0".

[0045] Exemplarily, the discriminator works as follows: at the beginning of each operation, TP and TN are both low, then transistors M7 to M10 are turned on, points X and Y are pulled to the power supply voltage (VDD), which is a high potential, thereby turning on transistors M3 and M4, and OUTP and OUTN are both low. At this time, transistors M1, M2, M5, and M6 are turned off. Assuming that TP has a rising edge first, that is, Tp is a high level and Tn is a low level, then M8 and M9 are turned off, and VDD no longer injects charge into points X and Y. At the same time, M1 is turned on, and point X begins to discharge (the potential becomes lower), so transistor M6 will be turned on and transistor M4 will be turned off, so that the high potential of point Y continues to be maintained, and the on state of transistor M3 is maintained, and the off state of transistor M5 is maintained. This is a positive feedback, which will eventually make point X a low potential and point Y a high potential. Finally, OUTP is a high level and OUTN is a low level, completing the discrimination. After TP and TN are restored to a low level, transistors M7 to M10 are turned on again, and the levels of points X and Y are restored to a high potential, waiting for the next rising edge of TP and TN.

[0046] It is worth noting that the structure of the discriminator is not limited, and other devices with a discriminative function such as latches may also be used for discrimination.

[0047] like Figure 5 As shown is a schematic diagram of the structure of the delay unit in this application.

[0048] like Figure 7 As shown, it is a circuit diagram of the delay unit in this application.

[0049] In this embodiment, the delay unit 13 includes: two electrically connected first inverters 131; the first inverter 131 is configured with two transistors. The delay unit is formed by two inverters connected in series, wherein Tin is the input rising edge signal, and Tdelay is the output rising edge signal after a delay period.

[0050] like Figure 6 As shown, it is a waveform diagram of the delay unit in the present application when it is running.

[0051] like Figure 8 As shown, it is a structural schematic diagram of the fast and slow selector in this application.

[0052] In this embodiment, the speed selector 12 includes: an electrically connected first signal generator 121, a second signal generator 122, a custom AND gate 123, and a custom OR gate 124; the speed selector is composed of two signal generators, a custom AND gate 123 and a custom OR gate 124.

[0053] The first signal generator 121 is configured to: output a first rising edge signal and a first falling edge signal according to a first input signal; the first falling edge signal is an inverse signal of the first rising edge signal, and the first falling edge signal and the first rising edge signal are output simultaneously; the second signal generator 122 is configured to: output a second rising edge signal and a second falling edge signal according to a second input signal; the second falling edge signal is an inverse signal of the second rising edge signal, and the second falling edge signal and the second rising edge signal are output simultaneously.

[0054] The custom AND gate 123 is configured to output a slow signal according to the first rising edge signal and the second rising edge signal; the custom OR gate 124 is configured to output a fast signal according to the first rising edge signal, the first falling edge signal, the second rising edge signal, and the second falling edge signal; wherein, if the time when the first input signal is input to the first signal generator 121 is earlier than the time when the second input signal is input to the second signal generator 122, then the first input signal has the same waveform as the fast signal, and the second input signal has the same waveform as the slow signal.

[0055] Exemplarily, the fast-slow selector receives two rising edge signals Tp and Tn, outputs a fast signal Early and a slow signal Late, and the time difference between the Early signal and the Late signal is substantially the same as the time difference between the Tp signal and the Tn signal.

[0056] like Fig. 9As shown, it is a waveform diagram of the fast and slow selector in the present application when it is running. If the Tp signal arrives before the Tn signal, the waveform of the Early signal is similar to that of the Tp signal, and the waveform of the Late signal is similar to that of the Tn signal; conversely, if the Tp signal arrives after the Tn signal, the waveform of the Early signal is similar to that of the Tn signal, and the waveform of the Late signal is similar to that of the Tp signal.

[0057] like Fig.10 As shown, it is a circuit diagram of the signal generator in this application.

[0058] In this embodiment, the first signal generator 121 and the second signal generator 122 include: a fifth transistor module 1211 and a sixth transistor module 1212 which are electrically connected; the fifth transistor module 1211 is configured with four transistors, and the sixth transistor module 1212 is configured with six transistors; the fifth transistor module 1211 is configured to: output the first rising edge signal or the second rising edge signal according to the first input signal or the second input signal; the sixth transistor module 1212 is configured to: output the first falling edge signal or the second falling edge signal according to the first input signal or the second input signal.

[0059] Exemplarily, the signal generator is composed of five inverters. The signal generator receives a rising edge signal, such as a Tp signal, and outputs a rising edge signal A and a falling edge signal ~A after a delay.

[0060] The transistor size ratio of the fifth transistor module 1211 is 2:2:3:8; the transistor size ratio of the sixth transistor module 1212 is 3:3:4:4:4:8. Fig. 9 The unit size is marked in the middle (e.g. 4x means 4 times the unit size, 6x means 6 times the unit size).

[0061] like Fig.11 As shown, it is a waveform diagram of the signal generator in the present application when it is running. Signal ~A is the inverted signal of signal A, and the time difference between the occurrence time of its falling edge and the occurrence time of the rising edge of signal A is very small and can be ignored.

[0062] like Fig.12 As shown, it is the circuit diagram of the custom AND gate in this application.

[0063] In this embodiment, the custom AND gate 123 includes: a seventh transistor module 1231 and an eighth transistor module 1232 which are electrically connected; the seventh transistor module 1231 is configured with eight transistors, including: M1 to M8; the eighth transistor module 1232 is configured with two transistors.

[0064] The custom AND gate 123 is further configured to turn on or off the transistors in the seventh transistor module 1231 according to the first rising edge signal and the second rising edge signal, and output a slow signal.

[0065] Exemplarily, the working principle of the custom AND gate 123 is as follows: at the beginning of each operation, A and B are both low, transistors M1 to M4 are turned off, transistors M5 to M8 are turned on, and point Y is pulled to the power supply voltage (VDD), so the Late signal is low. If the rising edge of the A signal has arrived, but the rising edge of the B signal has not arrived, that is, the A signal is high and the B signal is low, then transistors M2, M3, M7, and M8 are turned on, and transistors M1, M4, M5, and M6 are turned off, and point Y continues to be pulled to VDD, so the Late signal is still low. If the rising edge of the A signal has not arrived, but the rising edge of the B signal has arrived, that is, the A signal is low and the B signal is high, then transistors M1, M4, M5, and M6 are turned on, and transistors M2, M3, M7, and M8 are turned off, and point Y continues to be pulled to VDD, so the Late signal is still low. If the rising edges of both the A signal and the B signal arrive, that is, both the A signal and the B signal are high, the transistors M1, M2, M3, and M4 are turned on, and the transistors M5, M6, M7, and M8 are turned off, and the Y point is pulled to the ground (VSS), so the Late signal is high, that is, the slow signal Late is generated.

[0066] In summary, only when the rising edges of the A signal and the B signal arrive, the custom AND gate 123 will generate the slow signal Late, thereby realizing the function of distinguishing and transmitting the latest arriving signal between the A signal and the B signal.

[0067] like Fig.13 Shown is the circuit diagram of the custom OR gate in this application.

[0068] In this embodiment, the custom OR gate 124 includes: A ninth transistor module 1241 and a tenth transistor module 1242 are electrically connected; the ninth transistor module 1241 is configured with twelve transistors, including: M1 to M12; the tenth transistor module 1242 is configured with two transistors.

[0069] The custom OR gate 124 is further configured to turn on or off the transistors in the ninth transistor module 1241 and output a fast signal according to the first rising edge signal, the first falling edge signal, the second rising edge signal, and the second falling edge signal.

[0070] Exemplarily, the working principle of the custom OR gate 124 is as follows: at the beginning of each operation, A and B are both low level, ~A and ~B are both high level, transistors M1 to M4 are turned off, transistors M5 and M8 are also turned off, transistors M6 and M8 are turned on, transistors M9 to M12 are also turned on, and point X is pulled to the power supply voltage (VDD), so the Early signal is low level. If the rising edge of the A signal has arrived, but the rising edge of the B signal has not arrived, that is, the A signal is high level, the ~A signal is low level, the B signal is low level, and the ~B signal is high level, then transistors M1, M2, M5, M6, M10, and M11 are turned on, and transistors M3, M4, M7, M8, M9, and M12 are turned off, and point X is pulled to ground (VSS), so the Early signal is high level, that is, the fast signal Early is generated. If the rising edge of the A signal has not arrived, but the rising edge of the B signal has arrived, that is, the A signal is at a low level, the ~A signal is at a high level, the B signal is at a high level, and the ~B signal is at a low level, then the transistors M3, M4, M7, M8, M9, and M12 are turned on, the transistors M1, M2, M5, M6, M10, and M11 are turned off, and the X point is pulled to the ground (VSS), so the Early signal is at a high level, that is, the fast signal Early is generated. If the rising edges of both the A signal and the B signal arrive, that is, both the A signal and the B signal are at a high level, and the ~A signal and the ~B signal are at a low level, then the transistors M1, M2, M3, M4, M5, and M7 are turned on, the transistors M4, M8, M9, M10, M11, and M12 are turned off, and the X point is pulled to the ground (VSS), so the Early signal is at a high level, that is, the fast signal Early is generated.

[0071] In summary, as long as the rising edge of the A signal or the B signal arrives, the custom OR gate 124 will generate a fast signal Early, thereby realizing the function of distinguishing and transmitting the earliest signal of the A signal and the B signal.

[0072] It is worth noting that the structures of the custom AND gate and the custom OR gate are not limited, and other types of custom AND gates and custom OR gates can also replace the custom AND gate and custom OR gate in the fast and slow selector in this application.

[0073] In this embodiment, the output logic circuit 3 includes: a second inverter 31 and at least one multiplexer 32 which are electrically connected.

[0074] like Fig.14 , which is a schematic diagram of the structure of the second inverter in this application.

[0075] The second inverter 31 is configured to output a first high-bit digital code signal according to the first discrimination sub-signal and the second discrimination sub-signal.

[0076] like Fig.15, which is a schematic diagram of the structure of a multiplexer in the present application under an embodiment.

[0077] The multiplexer 32 is configured to output a second high-order digital code signal according to the third discrimination sub-signal and the fourth discrimination sub-signal. If there is one digital conversion module 1 and the TDC is 2b, that is, a circuit structure with two discriminators is provided, the terminal discriminator 2 generates the third discrimination sub-signal and the fourth discrimination sub-signal correspondingly and inputs them into the multiplexer 32, and outputs a second high-order digital code signal.

[0078] like Fig.16 , which is a schematic diagram of the structure of a multiplexer in another embodiment of the present application.

[0079] If there are multiple digital conversion modules 1, for example, TDC 3b is used, that is, a circuit structure with three discriminators is provided, then the first discrimination sub-signal and the second discrimination sub-signal generated by the discriminator 11 of the digital conversion module 1 provided between the digital conversion module 1 at the head end and the terminal discriminator 2 are input to the digital conversion module 1 at the head end and the terminal discriminator 2 at the end. Fig.15 The end discriminator 2 generates the third discrimination sub-signal and the fourth discrimination sub-signal and inputs them into the multiplexer 32; Fig.16 Multiplexer 32 in.

[0080] Exemplarily, the output logic circuit 3 outputs the final digital code signal according to the results of all discriminators, and is composed of 1 inverter and N-1 multiplexers (MUX), where N represents the number of bits of TDC. The input of the second inverter 31 is the output signal OUTP0 of the first discriminator, and the highest bit digital code signal is output. It can be understood that the input of the second inverter 31 is a fixed control signal OUTP0, and no judgment is required, so there is no need to set a multiplexer, and only an inverter that receives one control signal can be set.

[0081] In this embodiment, the input of the first MUX is the output signals OUTP1 and OUTN1 of the second discriminator, which are controlled to be the OUTP0 signal, and the second high-order digital code signal is output. The input of the second MUX is the output signals OUTP2 and OUTN2 of the third discriminator, which are controlled to be the output signal of the first MUX, and the third high-order digital code signal is output. In particular, starting from the second MUX, the input of the subsequent i-th MUX is the output signals OUTPi and OUTNi of the i+1-th discriminator, which are controlled to be the output signal of the i-1-th MUX, and the i+1-th high-order digital code signal is output. The output logic circuit 3 outputs the logic circuit truth table (taking TDC as 3b as an example, that is, a circuit structure with three discriminators) as shown in the following table:

[0082] In this embodiment, the output logic circuit 3 is further configured to output a quantization result according to the first high-bit digital code signal and the second high-bit digital code signal.

[0083] Exemplarily, the advantages of displaying digital code signals in the form of quantized results are mainly reflected in the following aspects: 1. Improve data representation accuracy: Quantization is the process of converting continuous physical quantities into discrete digital quantities. In digital communication and data processing, quantization can convert analog signals into digital signals, thereby achieving accurate representation and processing of signals. Digital code signals are displayed as quantized results, which can more accurately describe subtle changes in signals and improve data representation accuracy.

[0084] 2. Convenient data storage and transmission: The quantized digital code signal has a fixed number of bits and format, which makes data storage and transmission more convenient. Compared with traditional analog signals, digital signals have stronger anti-interference ability and more stable transmission performance. In addition, digital codes are also convenient for encryption and decryption processing, which improves data security.

[0085] 3. Support efficient data compression: Quantized digital codes can be efficiently compressed through various compression algorithms. These compression algorithms can use the correlation and redundancy between digital signals to reduce data storage space and transmission bandwidth. In the case of limited data transmission and storage resources, digital codes can significantly improve resource utilization efficiency through quantization results.

[0086] 4. Easy signal processing and analysis: Digital signal processing technology is already quite mature, including various algorithms such as filtering, transformation, and detection. These algorithms can be directly applied to the quantized digital code to achieve efficient signal processing and analysis. In addition, the digital code is also easy to interface with computers and other digital devices to achieve automated and intelligent signal processing and analysis.

[0087] like Fig.17 The figure shows the spectrum analysis diagram of the quantization results in this application.

[0088] For example, in Cadence Virtuoso software, a 3b TDC circuit is built and simulated. The circuit operating speed is set to 1 GHz, the delay time of the delay unit is designed to be 10 ps, ​​the input time difference is set to plus or minus 40 ps, ​​the input signal frequency is set to 498 MHz, and the test results are analyzed by spectrum. Fig.17The horizontal axis represents the signal frequency in megahertz (MHz); the vertical axis represents the amplitude in decibels (dB); 1st represents the fundamental wave, 2nd, 3rd, etc. respectively represent the second harmonic, third harmonic, etc. The spectrum analysis shows that the signal-to-noise ratio (SNR) of the output signal is 20.5dB, the signal-to-noise distortion ratio (SNDR) is 19.7dB, the spurious-free dynamic range (SFDR) is 26.9dB, the total harmonic distortion (THD) is -27.91dB, and the effective number of bits (ENOB) is 2.99b. The results are excellent, indicating that the time-to-digital converter provided by this application has good dynamic performance.

[0089] The above specific implementation methods further explain in detail the purpose, technical solutions and beneficial effects of the embodiments of the present application. It should be understood that the above are only specific implementation methods of the embodiments of the present application and are not used to limit the protection scope of the embodiments of the present application. Any modifications, equivalent substitutions, improvements, etc. made on the basis of the technical solutions of the embodiments of the present application should be included in the protection scope of the embodiments of the present application.

Claims

1. A time-to-digital converter of a successive approximation structure, characterized in that: include: At least one digital conversion module (1) electrically connected in sequence and an end discriminator (2) electrically connected to the digital conversion module (1) at the end; and also comprising an output logic circuit (3) electrically connected to each of the digital conversion modules (1) and the end discriminator (2); The digital conversion module (1) is configured as follows: Receiving a first time signal group; the first time signal group is an initial time signal group or a time signal group output by a digital conversion module (1) located at the front end of the digital conversion module (1); According to the first time signal group, a first discrimination signal group is output to the output logic circuit (3), and a selection delay processing operation is performed on the first time signal group to obtain a second time signal group; the second time signal group is used to input the digital conversion module (1) located at the rear end of the digital conversion module (1), or is used to input the end discriminator (2); the end discriminator (2) is configured as follows: Receiving the second time signal group sent by the digital conversion module (1) electrically connected to the end discriminator (2); Outputting a second discrimination signal group to the output logic circuit (3) according to the second time signal group; The output logic circuit (3) is configured as follows: A digital code signal is outputted based on all of the first discrimination signal group and the second discrimination signal group.

2. The time-to-digital converter of the successive approximation structure according to claim 1, characterized in that: The first time signal group includes: a first time signal and a second time signal; the first discrimination signal group includes: a first discrimination sub-signal and a second discrimination sub-signal; The digital conversion module (1) comprises: a discriminator (11), wherein the discriminator (11) is configured to: receiving the first time signal and the second time signal; According to the first time signal and the second time signal, the first discrimination sub-signal and the second discrimination sub-signal are output to the output logic circuit (3).

3. The time-to-digital converter of the successive approximation structure according to claim 2, characterized in that: The time at which the first time signal is input into the digital conversion module (1) is earlier than the time at which the second time signal is input into the digital conversion module (1); The second time signal group includes: a delay signal and a slow signal; the second discrimination signal group includes: a third discrimination sub-signal and a fourth discrimination sub-signal; the selection delay processing operation includes: a fast and slow selection processing operation and a delay processing operation; The digital conversion module (1) further comprises: a speed selector (12) and a delay unit (13); the speed selector (12) is electrically connected to the discriminator (11) and the delay unit (13); The fast / slow selector (12) is configured: receiving the first time signal and the second time signal; Performing a fast / slow selection processing operation on the first time signal and the second time signal, obtaining a fast signal based on the first time signal; obtaining a slow signal based on the second time signal; the fast signal is used to input into the delay unit (13); The delay unit (13) is configured: receiving the fast signal; Performing a delay processing operation on the fast signal to obtain a delayed signal; The end discriminator (2) is further configured as follows: Receiving the delayed signal and the slow signal sent by the digital conversion module (1) electrically connected to the end discriminator (2); According to the delay signal and the slow signal, the third discrimination sub-signal and the fourth discrimination sub-signal are output to the output logic circuit (3).

4. The time-to-digital converter of the successive approximation structure according to claim 3, characterized in that: The discriminator (11) and the terminal discriminator (2) include: An electrically connected first transistor module (111), a second transistor module (112), a third transistor module (113), and a fourth transistor module (114); The first transistor module (111) is configured with four transistors; the second transistor module (112) and the third transistor module (113) are configured with three transistors; and the fourth transistor module (114) is configured with two transistors; The first transistor module (111), the second transistor module (112), and the third transistor module (113) are configured as follows: According to the level value of the input signal, the transistors in the first transistor module (111), the second transistor module (112) and the third transistor module (113) are turned on or off to determine the level value of the output signal.

5. The time-to-digital converter of the successive approximation structure according to claim 3, characterized in that: The delay unit (13) comprises: Two first inverters (131) are electrically connected; the first inverter (131) is configured with two transistors.

6. The time-to-digital converter of the successive approximation structure according to claim 3, characterized in that: The speed selector (12) comprises: An electrically connected first signal generator (121), a second signal generator (122), a custom AND gate (123), and a custom OR gate (124); The first signal generator (121) is configured to: output a first rising edge signal and a first falling edge signal according to a first input signal; the first falling edge signal is an inverse signal of the first rising edge signal, and the first falling edge signal and the first rising edge signal are output simultaneously; The second signal generator (122) is configured to: output a second rising edge signal and a second falling edge signal according to a second input signal; the second falling edge signal is an inverse signal of the second rising edge signal, and the second falling edge signal and the second rising edge signal are output simultaneously; The custom AND gate (123) is configured to: output a slow signal according to the first rising edge signal and the second rising edge signal; The custom OR gate (124) is configured to: output a fast signal according to the first rising edge signal, the first falling edge signal, the second rising edge signal, and the second falling edge signal; If the time when the first input signal is input to the first signal generator (121) is earlier than the time when the second input signal is input to the second signal generator (122), the first input signal has the same waveform as the fast signal, and the second input signal has the same waveform as the slow signal.

7. The time-to-digital converter of the successive approximation structure according to claim 6, characterized in that: The first signal generator (121) and the second signal generator (122) include: An electrically connected fifth transistor module (1211) and a sixth transistor module (1212); the fifth transistor module (1211) is configured with four transistors, and the sixth transistor module (1212) is configured with six transistors; The fifth transistor module (1211) is configured to: output the first rising edge signal or the second rising edge signal according to the first input signal or the second input signal; The sixth transistor module (1212) is configured to: output the first falling edge signal or the second falling edge signal according to the first input signal or the second input signal; The transistor size ratio in the fifth transistor module (1211) is 2:2:3:8; The transistor size ratio in the sixth transistor module (1212) is 3:3:4:4:4:

8.

8. The time-to-digital converter of the successive approximation structure according to claim 6, characterized in that: The custom AND gate (123) includes: A seventh transistor module (1231) and an eighth transistor module (1232) electrically connected; the seventh transistor module (1231) is configured with eight transistors, and the eighth transistor module (1232) is configured with two transistors; The custom AND gate (123) is further configured as: According to the first rising edge signal and the second rising edge signal, the transistors in the seventh transistor module (1231) are turned on or off to output a slow signal.

9. The time-to-digital converter of a successive approximation structure according to claim 6, characterized in that: The custom OR gate (124) includes: A ninth transistor module (1241) and a tenth transistor module (1242) electrically connected; the ninth transistor module (1241) is configured with twelve transistors, and the tenth transistor module (1242) is configured with two transistors; The custom OR gate (124) is further configured as: According to the first rising edge signal, the first falling edge signal, the second rising edge signal, and the second falling edge signal, the transistors in the ninth transistor module (1241) are turned on or off to output a fast signal.

10. The time-to-digital converter of a successive approximation structure according to claim 3, characterized in that: The output logic circuit (3) comprises: An electrically connected second inverter (31) and at least one multiplexer (32); The second inverter (31) is configured to: output a first high-order digital code signal according to the first discrimination sub-signal and the second discrimination sub-signal; The multiplexer (32) is configured to: output a second high-order digital code signal according to the third discrimination sub-signal and the fourth discrimination sub-signal; The output logic circuit (3) is further configured as: A quantization result is output according to the first high-bit digital code signal and the second high-bit digital code signal.

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