Semiconductor detection layout, layout design method and layout design system

Abstract

The invention provides a semiconductor detection layout, a layout design method and a layout design system.The semiconductor detection layout is arranged on a wafer and located in a cutting channel of the wafer, the semiconductor detection layout comprises a plurality of semiconductor function layers, and the semiconductor function layers are stacked on the wafer to form a stacked structure; the impedance wiring or the metal wiring is arranged in the semiconductor function layer, the wiring width of the semiconductor function layer is gradually increased or unchanged in the stacking direction of the semiconductor function layer, and the wiring width is the width of the impedance wiring or the width of the metal wiring; and the contact columns are electrically connected with the adjacent impedance wires or the adjacent metal wires, and the width of the contact columns is consistent with the maximum width of the contacted wires. According to the invention, the consistency of a plurality of detection layouts on the wafer can be improved, the design efficiency of the detection layouts can be improved, and the occupied area of the detection layouts is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor detection layout, a layout design method and a layout design system. Background Art

[0002] The design of integrated circuits is very complex. A chip can easily use millions to billions of logic gates (gate count), and the electrical parameters of each logic gate and other devices must meet the standards at the same time, otherwise the chip may not function properly. A wafer usually has tens to tens of thousands of chips, so it is very important to maintain the uniformity of the process. In the wafer manufacturing process, the monitoring of the key electrical and physical properties of the wafer requires not only that the entire wafer meets the standard (SPEC), but also that each wafer produced meets this standard. Therefore, process monitoring and control (PCM) must be introduced to improve quality monitoring.

[0003] During the wafer development process, due to the different structural designs and process configurations on the wafer, the number of design combinations of test keys used to monitor process quality is huge, occupying too much space. In addition, the design of the test keys is rigid and it is difficult to cope with different experimental and testing requirements. Summary of the invention

[0004] The purpose of the present invention is to provide a semiconductor detection layout, a layout design method and a layout design system, which can not only improve the consistency of the detection layout on the wafer, but also improve the design efficiency of the detection layout and reduce the footprint of the detection layout.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions: The present invention provides a semiconductor detection layout, which is arranged on a wafer and located in a cutting path of the wafer, wherein the semiconductor detection layout comprises: A plurality of semiconductor functional layers, wherein the plurality of semiconductor functional layers are stacked on the wafer to form a stacked structure; Impedance wiring or metal wiring, arranged in the semiconductor functional layer, wherein along the stacking direction of the semiconductor functional layer, the wiring width of the semiconductor functional layer increases or remains unchanged, wherein the wiring width is the width of the impedance wiring or the width of the metal wiring; and The contact pillar is electrically connected to the adjacent impedance wiring or the adjacent metal wiring, wherein the width of the contact pillar is consistent with the maximum width of the contacted wiring.

[0006] In one embodiment of the present invention, along the stacking direction of the stacking structure, the width of the rear wiring layer is an integer multiple of the width of the front wiring layer, and the width of the rear wiring layer is at least 1 times the width of the front wiring layer.

[0007] In one embodiment of the present invention, the semiconductor functional layer is one of a MOS transistor, a gate oxide layer, a polysilicon gate field effect transistor, an N-type junction, a P-type junction, a block resistance, a contact resistance, an isolation structure, a metal capacitor and a polysilicon capacitor.

[0008] The present invention provides a layout design method, based on a semiconductor detection layout as described above, comprising the following steps: Establishing a database of the semiconductor detection layout; Input the number of semiconductor functional layers and the wiring width of the bottom functional layer; Taking the wiring width of the current functional layer as a first width, and screening a test structure from the database according to the wiring width of the bottom functional layer, the level of the current functional layer and the first width; In the test structure, marking the semiconductor functional layer located at a level below the current functional layer as a next functional layer, and using the wiring width of the next functional layer as a second width; Screening out the test structures whose second width is smaller than the first width; Updating the next functional layer as a new current functional layer, and rescreening the test structure until the level of the current functional layer reaches the top layer of a preset stacking structure; and Output any of the screened test structures as a semiconductor inspection layout for testing.

[0009] In one embodiment of the present invention, the step of selecting the test structure from the database includes: Comparing the current stacking structure with the test structure in the database layer by layer; and A first test structure is obtained from the database, wherein the first test structure has the same number of layers and layer wiring width as the current stacking structure.

[0010] In one embodiment of the present invention, the step of screening out the test structure includes: Setting a first wiring width range; Acquire the wiring width of the current functional layer as a first width; Filtering out a second wiring width range from the first wiring width range, wherein a width value in the second wiring width range is greater than or equal to the first width; and A portion of the first test structure is reserved as a second test structure, wherein in the second test structure, the wiring width of the next functional layer is within the second wiring width range.

[0011] In an embodiment of the present invention, after the next functional layer is updated to the new current functional layer, if the new current functional layer is the top layer of the preset stacking structure, the current second test structure is output.

[0012] In one embodiment of the present invention, after the next functional layer is updated to the new current functional layer, if the new current functional layer does not reach the top layer of the preset stacking structure, the number of layers of the semiconductor functional layer is re-input.

[0013] In one embodiment of the present invention, when the number of layers of the semiconductor functional layer remains unchanged, the step of re-inputting the number of layers of the semiconductor functional layer is skipped.

[0014] The present invention provides a layout design system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the above layout design methods when executing the computer program.

[0015] As described above, the present invention provides a semiconductor detection layout, a layout design method, and a layout design system, which can automatically design and adjust the detection layout in the wafer process, and are used to implement wafer acceptability testing. In addition, the layout design method and system provided by the present invention can cope with various test requirements in the integrated circuit manufacturing process, and can adaptively change the detection layout structure when the number of test layers changes, which can not only avoid the whole wafer redesign causing process or experimental delays, but also avoid excessive wafer area occupation caused by too many test patterns, and can also improve the consistency of the detection layout on the entire wafer. Therefore, according to a semiconductor detection layout, a layout design method, and a layout design system provided by the present invention, it is possible to improve process efficiency and reduce wafer area occupation.

[0016] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0018] Figure 1Schematic diagram of the regional distribution structure of the wafer surface in one embodiment of the present invention.

[0019] Figure 2 Schematic diagram of the distribution structure of test keys on a wafer in one embodiment of the present invention.

[0020] Figure 3 Schematic diagram of the hierarchical distribution structure of test keys in one embodiment of the present invention.

[0021] Figure 4 The figure is a schematic diagram of the top view of the test key in one embodiment of the present invention.

[0022] Figure 5 Schematic diagram of the structure of a database in one embodiment of the present invention.

[0023] Figure 6 Flow chart of a layout design method in one embodiment of the present invention.

[0024] Figure 7 FIG. 1 is a schematic diagram after layer jumping in one embodiment of the present invention.

[0025] Figure 8 The structure principle block diagram of the layout design system in one embodiment of the present invention.

[0026] Fig. 9 The present invention is a block diagram of the structural principle of a computer-readable storage medium in one embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Wafer Acceptance Test (WAT) is conducted after wafer product tape-out and before quality inspection to measure the electrical parameters of the test key. The purpose of wafer acceptability test is to detect the process conditions of each wafer product, evaluate the quality and stability of the semiconductor manufacturing process, and determine whether the wafer product meets the electrical specification requirements of the process technology platform by testing the electrical parameters of the test key on the wafer. Therefore, WAT data can be used as a quality certificate for wafer product delivery. In addition, WAT data can also reflect the actual production situation of the production line. By collecting and analyzing WAT data, the production line situation can be monitored, the trend of production line changes can be determined, and early warnings can be issued for possible situations. Figure 1 and Figure 2As shown, the wafer acceptability test is based on a test key TK, wherein the test key TK is placed in the dicing street 102. Figure 1 As shown, Figure 1 It is only a schematic diagram, and chip particles 101 and cutting paths 102 are arranged on the wafer 100. A plurality of chip particles 101 are distributed on the wafer 100, and are spaced at a preset distance to cover the wafer 100 as much as possible. The cutting paths 102 are distributed in a grid, and the cutting paths 102 are arranged in adjacent chip particles 101.

[0029] See also Figure 1 and Figure 2 As shown, the test key TK is set in the cutting path 102. And in the detection layout provided by the present invention, the test key TK includes a test pattern and a pad 103. There are multiple pads 103 in the cutting path 102, and the multiple pads 103 are equidistantly distributed in the cutting path 102, and the multiple pads 103 are distributed along the length direction of the cutting path 102. In this embodiment, the test pattern is set between adjacent pads 103. This embodiment is illustrated by the contact resistance Rc in the CMOS transistor. The contact resistance includes a stacking structure. The stacking structure is distributed between the pads 103. In some embodiments of the present invention, the pad 103 can be the top functional layer of the stacking structure, and specifically the top metal layer of the stacking structure. In this embodiment, the pad 103 can be used to connect the test probe after the chip is packaged. Specifically, when the wafer 100 is subjected to WAT testing, the test probe is connected to the pad 103 to obtain the electrical performance of the test pattern, and to measure whether the measured electrical parameters meet the standards. In the present invention, the test pattern of the test key TK has various types, and specifically includes active devices, passive devices and isolation structures on the wafer process platform, etc. In the present invention, the test pattern of the test key TK can be but not limited to MOS transistors, gate oxide integrity (Gate Oxide Integrity, GOI), polysilicon gate field effect transistors, N-type junctions, P-type junctions, block resistance Rs, contact resistance Rc, isolation structures, metal capacitors (MIM Capacitors) and polysilicon capacitors (PIP Capacitors), etc.

[0030] See also Figures 1 to 4 As shown, in one embodiment of the present invention, the wafer 100 includes a substrate, wherein the device structure and electrical structure of the chip particle 101 are formed on the substrate. To form the chip particle 101, a plurality of functional layers are formed on the substrate. Wherein, while forming the chip particle 101, the structure of the test key TK is formed by a process. Therefore, the test key TK includes a plurality of semiconductor functional layers, and the number of the semiconductor functional layers is consistent with the number of the semiconductor functional layers of the wafer 100. Figure 3 A schematic diagram of the distribution hierarchy of a test key TK is shown. Figure 37 semiconductor functional layers M1 to M7 are shown. The semiconductor functional layers are metal layers. In this embodiment, the semiconductor functional layers include impedance wiring, wherein the semiconductor functional layers are stacked and the impedance wirings of adjacent semiconductor functional layers can be connected through contact holes Via. In this embodiment, the semiconductor functional layers are metal layers. Figure 3 The contact hole V6 between the sixth metal layer M6 and the seventh metal layer M7 is shown. In this embodiment, the impedance wiring and the contact hole both have a width. Taking the width of the first metal layer M1 as 1 times the width, the width of the impedance wiring arranged and stacked on the first metal layer M1 is greater than or equal to the width of the first metal layer M1. Figure 3 As shown, the impedance wiring width of the second metal layer M2 to the sixth metal layer M6 is 1 times the width, and the impedance wiring width of the seventh metal layer M7 is, for example, 8 times the width. Figure 3 and Figure 4 As shown, the width of the contact hole is equal to the impedance wiring width of the connected metal layer, and specifically, the width of the contact hole is equal to the maximum impedance wiring width of the connected metal layer. Figure 3 As shown, the width of the contact hole V6 is 8 times the width. Figure 4 A schematic diagram of top view wiring of multiple metal layers is shown. The present invention does not limit the wiring shape of the metal layer in the test key TK, but only limits the key size of the test key TK, such as the impedance wiring width.

[0031] See also Figures 1 to 5 As shown, in one embodiment of the present invention, in the stacking structure, along the stacking direction, the impedance wiring width remains unchanged or increases, and the impedance wiring width of multiple metal layers is an integer multiple of the impedance wiring width of the first metal layer M1. The contact hole width is equal to the maximum metal width of the contacted metal layer. Among them, taking the width of the first metal layer M1 as a reference, the impedance wiring width of the metal layer and the contact hole width can be 1 times the width, 2 times the width, 4 times the width, 8 times the width, etc., where the width is a multiple. According to the requirements of the process platform, the width multiple base can be adjusted. For example, the upper impedance wiring width can also be 3 times the width, 5 times the width, 7 times the width, etc. In this embodiment, the top functional layer and the sub-top functional layer are connected through contact holes. According to the number of metal layers and the impedance wiring width of the stacked metal layers below the top functional layer, the width of the top functional layer also changes accordingly. Therefore, the impedance wiring width of the top functional layer can be 1 times the width, 2 times the width, 4 times the width, 8 times the width, etc. As Figure 5As shown, the impedance wiring width of the first metal layer M1 is 1 times the width, and the impedance wiring width of the second metal layer M2 to the Nth metal layer can be 1 times the width, 2 times the width, 4 times the width, 8 times the width, and so on. When the impedance wiring width of the second metal layer M2 is, for example, 2 times the width, the impedance wiring width of the third metal layer M3 is at least 2 times the width. For example, the impedance wiring width of the third metal layer M3, the fourth metal layer M4, and the fifth metal layer M5 is at least 2 times the width. Then the impedance wiring width of the sixth metal layer M6 is at least 2 times the width. For example, the impedance wiring width of the sixth metal layer M6, the seventh metal layer M7, and the eighth metal layer M8 is 4 times the width. For example, if the number of metal layers is 9, then the impedance wiring width of the top functional layer can be 4 times the width or 8 times the width. Therefore, according to the impedance wiring widths of different metal layers, a variety of test keys TK can be combined.

[0032] See also Figures 1 to 6 As shown, in one embodiment of the present invention, a database is established according to the impedance wiring width combination mode of the stacked structure. Figure 5 As shown, after determining the bottom semiconductor functional layer, when the number of semiconductor functional layers is determined, the design scheme of the stacking structure can be automatically obtained by retrieving data from the database. Among them, the semiconductor functional layer whose wiring width has been determined is the current functional layer, and the next semiconductor functional layer whose wiring width is to be determined is the next functional layer. Along the stacking direction, the single or multiple semiconductor functional layers at the bottom are the bottom functional layers, and the single semiconductor functional layer at the top is the top functional layer. Specifically, as Figure 6 As shown, based on the design rules provided by the present invention, the present invention provides a layout design method, and the layout design method includes steps S10 to S90.

[0033] Step S10, presetting the number of semiconductor functional layers and the impedance wiring width of the bottom functional layer.

[0034] Step S20: Taking the impedance wiring width of the current functional layer as the first width.

[0035] Step S30: Based on the impedance wiring width of the current functional layer, obtain the test structure in the database.

[0036] Step S40: taking the impedance wiring width of the next functional layer in the test structure as the second width.

[0037] Step S50: determine whether the second width is greater than or equal to the first width.

[0038] Step S60: When the second width is greater than or equal to the first width, the next functional layer in the test structure is updated as the current functional layer.

[0039] Step S70: After step S60, determine whether the current functional layer is the top functional layer. If the current functional layer is not the top functional layer, return to step S10.

[0040] Step S80: If the current functional layer is the top functional layer, the current test structure is used as a test key.

[0041] Step S90: In step S50, when the second width is smaller than the first width, the current test structure is screened out and the process returns to step S30.

[0042] See also Figures 1 to 6 As shown, in one embodiment of the present invention, in step S10, the number of metal layers and the impedance wiring width of the bottom functional layer are preset. The bottom functional layer includes at least the first metal layer M1. According to the layout design requirements, the first three metal layers including the first metal layer M1, or the first two metal layers, etc. can be preset. For example, when the number of metal layers is 10, the impedance wiring widths of several metal layers can be preset to quickly define and obtain the test structure that meets the design rules. Then in step S20, the first width is obtained. Taking the first metal layer M1 as the bottom functional layer as an example, in step S20, the first metal layer M1 is first used as the current functional layer, and the next functional layer of the current functional layer is the second metal layer M2. The width of the current functional layer is the impedance wiring width of the first metal layer M1, that is, 1 times the width. In step S30, based on the impedance wiring width of the current functional layer, the test structure in the database is obtained. The test structure refers to a plurality of stacked structures preset in the database. Based on the impedance wiring width of the current functional layer, the number of layers of the current functional layer is first obtained, and then the impedance wiring width of the current functional layer is obtained. If the impedance wiring width of the first metal layer M1 is 1 times the width, then all test structures of the impedance wiring width of the first metal layer M1 being 1 times the width are obtained from the database. For another example, the current functional layer is the second metal layer M2, and the impedance wiring width of the second metal layer M2 is 2 times the width. Then the current functional layer is the second metal layer M2, and the first width is 2 times the width. Therefore, in step S30, a test structure of the first metal layer M1 being 1 times the thickness and the second metal layer M2 being 2 times the thickness is obtained. And so on.

[0043] See also Figures 1 to 6As shown, in one embodiment of the present invention, in step S40, there are multiple corresponding test structures in the database. Based on the acquired test structure, the next functional layer of the current functional layer is acquired. The impedance wiring width of the next functional layer is the second width. At this time, there are many possibilities for the second width, as long as the second width is greater than or equal to the first width, it complies with the design rules. Therefore, step S50 is executed to filter out the test structures whose second width is less than the first width, such as step S90. After filtering out the current test structure, return to step S30 and re-acquire a new test structure until the second width in the test structure is greater than or equal to the first width. When the second width is greater than or equal to the first width, step S60 is executed to update the next functional layer in the current test structure to the current functional layer. For example, the impedance wiring width of the third metal layer M3 is 4 times, and when the first metal layer M1 is 1 times thick, the second metal layer M2 is 2 times thick, and the third metal layer M3 is 4 times thick, in step S60, the third metal layer M3 is updated to the current functional layer. In this embodiment, in the step of obtaining the second width of the next functional layer, a width data can be randomly obtained by a machine, or the minimum impedance wiring width can be preferentially obtained according to the selected level. For example, in the metal layers ranked 1 to 5, when the second width is selected, the impedance wiring width is 1 times the width to 4 times the width. In the metal layers ranked 6 to 10, when the second width is selected, the impedance wiring width is 6 times the width to 10 times the width. When selecting the second width of the next functional layer, the impedance wiring width with the smallest value in the width range is given first priority, thereby reducing the footprint of the stacked structure.

[0044] See also Figures 1 to 6 As shown, in one embodiment of the present invention, in step S70, if the current functional layer after update is the top functional layer, step S80 is executed. The top functional layer is the metal layer with the largest level. For example, if the number of metal layers is 9, the ninth metal layer M9 is the top functional layer. In step S80, the current test structure is used as the test key TK. And in this embodiment, the top functional layer in the stacked structure can be used as the pad 103. In step S70, if the current functional layer after update is not the top functional layer, return to step S10, update the value of the first width, and continue to obtain the second width of the next functional layer, so as to obtain the test structure until the impedance wiring width of all metal layers is determined. After determining the metal wiring thickness of the metal layer, the contact hole width between adjacent metal layers can be determined. In this embodiment, the contact hole width is the maximum impedance wiring width of the connected metal layer. In this embodiment, the impedance wiring width of the top functional layer can be set to the maximum width to quickly obtain the test structure.

[0045] See also Figures 1 to 7As shown, in one embodiment of the present invention, in step S70, if the updated current functional layer is not yet the top functional layer, then return to step S10. Since the number of steps in the chip manufacturing process is nearly a thousand, and the process needs to be closely monitored and the process improvement plan needs to be continuously studied, changes in the wafer manufacturing method may occur during the wafer process cycle, and temporary testing is required at this time. If the test plan changes, the number of metal layers must be changed. For example, after the bottom functional layer is formed, the number of metal layers is temporarily changed to 3 layers for experimental testing needs. As Figure 7 As shown, the first metal layer M1 and the second metal layer M2 are the bottom functional layers that have been formed. If the original solution is adopted, when the experimental test requirements are received, the original metal layer cannot be packaged and tested, and the original test key TK can only be overturned and the structure of the test key TK can only be redesigned. On the wafer 100, it is necessary to make changes to the level, which involves many test keys TK to be changed, so the original design scheme is difficult to meet temporary experimental needs. And the design of various test keys TK will greatly occupy the wafer area. According to the technical solution provided by the present invention, for this application situation, layer jumping can be directly implemented. Specifically, after determining whether the current functional layer is the top functional layer, if the current functional layer is not the top functional layer, directly return to step S10 and reset the number of metal layers at this time. For example, if Figure 7 As shown, the number of metal layers temporarily replaced is three layers, then the next functional layer is the third metal layer, and the third metal layer is also the top functional layer. The width of the third metal layer can be directly set to 4 times the maximum value of the impedance wiring width in the preset range or 8 times the maximum value of the impedance wiring width. Therefore, the width of the contact hole at this time is also changed to 4 times the width or 8 times the width. According to the layout design method provided by the present invention, the structure of the test key TK can be automatically and timely adjusted to adapt to various test requirements of the process. And according to the semiconductor layout design method provided by the present invention, while being able to adapt to the process requirements, it can also avoid the wafer occupying too large an area due to the adaptive change of the test key TK. In this embodiment, if the number of layers of the semiconductor functional layer has not changed, the step of presetting the number of metal layers at this time can also be directly skipped, and step S20 is executed.

[0046] See also Figures 1 to 7As shown, in other embodiments of the present invention, when the test pattern is a MOS transistor, the integrity of the gate oxide layer, a polysilicon gate field effect transistor, an N-type junction, a P-type junction, a block resistance Rs, a contact resistance Rc, an isolation structure, a metal capacitor and a polysilicon capacitor, etc. For passive devices, such as the block resistance Rs and the contact resistance Rc, the width of the impedance wiring width remains unchanged or increases along the stacking direction of the stacked structure. And along the stacking direction of the stacked structure, the width of the contact hole remains unchanged or increases. The contact hole is used to connect the impedance wiring of adjacent layers, or for the metal wiring of adjacent semiconductor functional layers of the metal interconnect structure. For active devices, such as MOS transistors and polysilicon gate field effect transistors, the metal wiring width of the metal interconnect structure remains unchanged or increases along the stacking direction of the stacked structure. And along the stacking direction of the stacked structure, the width of the contact hole remains unchanged or increases.

[0047] See also Figure 8As shown, the present invention also provides a layout design system, the layout design system includes a processor 200 and a memory 300, the memory 300 stores program instructions, and the processor 200 runs the program instructions to implement the above-mentioned layout design method. The processor 200 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components; the memory 300 may include a random access memory (RAM), and may also include a non-volatile memory, such as at least one disk storage. The memory 300 can also be an internal memory of the random access memory (RAM) type, and the processor 200 and the memory 300 can be integrated into one or more independent circuits or hardware, such as: an application-specific integrated circuit (ASIC). It should be noted that the computer program in the above-mentioned memory 300 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a layout design system, or a network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention.

[0048] See also Fig. 9As shown, the present invention also proposes a computer-readable storage medium 401, wherein the computer-readable storage medium 401 stores computer instructions 400, and the computer instructions 400 are used to enable the computer to execute the above-mentioned layout design method. The computer-readable storage medium 401 can be an electronic medium, a magnetic medium, an optical medium, an electromagnetic medium, an infrared medium, or a semiconductor system or a propagation medium. The computer-readable storage medium 401 can also include a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random access memory (RAM), a read-only memory (ROM), a hard disk, and an optical disk. The optical disk can include a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-RW), and a DVD.

[0049] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor detection layout, characterized in that: The semiconductor detection layout is arranged on a wafer, and the semiconductor detection layout is located in a cutting path of the wafer, wherein the semiconductor detection layout comprises: A plurality of semiconductor functional layers, wherein the plurality of semiconductor functional layers are stacked on the wafer to form a stacked structure; Impedance wiring or metal wiring, arranged in the semiconductor functional layer, wherein along the stacking direction of the semiconductor functional layer, the wiring width of the semiconductor functional layer increases or remains unchanged, wherein the wiring width is the width of the impedance wiring or the width of the metal wiring; and The contact pillar is electrically connected to the adjacent impedance wiring or the adjacent metal wiring, wherein the width of the contact pillar is consistent with the maximum width of the contacted wiring.

2. A semiconductor detection layout according to claim 1, characterized in that: Along the stacking direction of the stacking structure, the width of the rear wiring layer is an integer multiple of the width of the front wiring layer, and the width of the rear wiring layer is at least 1 times the width of the front wiring layer.

3. A semiconductor detection layout according to claim 1, characterized in that: The semiconductor functional layer is one of a MOS transistor, a gate oxide layer, a polysilicon gate field effect transistor, an N-type junction, a P-type junction, a block resistor, a contact resistor, an isolation structure, a metal capacitor and a polysilicon capacitor.

4. A layout design method, based on a semiconductor detection layout as claimed in claim 1, characterized in that: The following steps are involved: Establishing a database of the semiconductor detection layout; Input the number of semiconductor functional layers and the wiring width of the bottom functional layer; Taking the wiring width of the current functional layer as a first width, and screening a test structure from the database according to the wiring width of the bottom functional layer, the level of the current functional layer and the first width; In the test structure, marking the semiconductor functional layer located at a level below the current functional layer as a next functional layer, and using the wiring width of the next functional layer as a second width; Screening out the test structures whose second width is smaller than the first width; Updating the next functional layer as a new current functional layer, and rescreening the test structure until the level of the current functional layer reaches the top layer of a preset stacking structure; as well as Output any of the screened test structures as a semiconductor inspection layout for testing.

5. A layout design method according to claim 4, characterized in that: The step of selecting the test structure from the database comprises: Comparing the current stacking structure with the test structure in the database layer by layer; and A first test structure is obtained from the database, wherein the first test structure has the same number of layers and layer wiring width as the current stacking structure.

6. A layout design method according to claim 5, characterized in that: The step of screening out the test structure comprises: Setting a first wiring width range; Acquire the wiring width of the current functional layer as a first width; Filtering out a second wiring width range from the first wiring width range, wherein a width value in the second wiring width range is greater than or equal to the first width; and A portion of the first test structure is reserved as a second test structure, wherein in the second test structure, the wiring width of the next functional layer is within the second wiring width range.

7. A layout design method according to claim 6, characterized in that: After the next functional layer is updated to be the new current functional layer, if the new current functional layer is the top layer of the preset stacking structure, the current second test structure is output.

8. A layout design method according to claim 7, characterized in that: After the next functional layer is updated as the new current functional layer, if the new current functional layer does not reach the top layer of the preset stacking structure, the number of layers of the semiconductor functional layer is re-input.

9. A layout design method according to claim 8, characterized in that: When the number of the semiconductor functional layers remains unchanged, the step of re-inputting the number of the semiconductor functional layers is skipped.

10. A layout design system, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the layout design method as claimed in any one of claims 4 to 9 when executing the computer program.

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