A semiconductor detection layout, a layout design method and a layout design system

Abstract

The present invention provides a semiconductor detection layout, a layout design method and a layout design system. The semiconductor detection layout is disposed on a wafer, and the semiconductor detection layout is located in a dicing channel of the wafer. The semiconductor detection layout includes: a plurality of semiconductor functional layers, which are stacked on the wafer to form a stacked structure; impedance wiring or metal wiring, which is disposed in the semiconductor functional layers. Along the stacking direction of the semiconductor functional layers, the wiring width of the semiconductor functional layers increases or remains unchanged, where the wiring width is the width of the impedance wiring or the width of the metal wiring; and contact posts, which are electrically connected to adjacent impedance wiring or electrically connected to adjacent metal wiring, where the width of the contact posts is consistent with the maximum width of the contacted wiring. The present invention can not only improve the consistency of multiple detection layouts on the wafer, but also improve the design efficiency of the detection layout and reduce the floor area of the detection layout.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and manufacturing, and particularly to a semiconductor detection layout, a layout design method, and a layout design system. Background Art

[0002] The design of integrated circuits is very complex. A single chip often uses millions to billions of logic gates (gate count), and the electrical parameters of each logic gate and other devices must meet the standards simultaneously, otherwise the chip may not operate properly. And a single wafer usually has dozens to tens of thousands of chips. Therefore, it is very important to maintain the uniformity of the manufacturing process. In the wafer manufacturing process, the monitoring of the key electrical and physical properties of the wafer not only requires the entire wafer to meet the standards (SPEC), but also requires each produced wafer to meet this standard. Therefore, process control monitoring (PCM) must be introduced to improve quality control.

[0003] During the wafer development process, due to different structural designs and process configurations on the wafer, the number of design combinations of test keys used to monitor the process quality is huge, and the floor area is too large. Moreover, the design of the test keys is rigid and difficult to meet different experimental and test requirements. Summary of the Invention

[0004] The purpose of the present invention is to provide a semiconductor detection layout, a layout design method, and a layout design system, which can not only improve the consistency of the detection layout on the wafer, but also improve the design efficiency of the detection layout and reduce the floor area of the detection layout.

[0005] To solve the above technical problems, the present invention is realized through the following technical solutions:

[0006] The present invention provides a semiconductor detection layout, which is arranged on a wafer, and the semiconductor detection layout is located in the scribe line of the wafer, wherein the semiconductor detection layout includes:

[0007] A plurality of semiconductor functional layers, and the plurality of semiconductor functional layers are stacked on the wafer to form a stacked structure;

[0008] Impedance wiring or metal wiring, which is arranged in the semiconductor functional layer, wherein along the stacking direction of the semiconductor functional layer, the wiring width of the semiconductor functional layer increases or remains unchanged, and the wiring width is the width of the impedance wiring or the width of the metal wiring; and

[0009] Contact posts, which are electrically connected to adjacent impedance wiring or electrically connected to adjacent metal wiring, and the width of the contact posts is consistent with the maximum width of the contacted wiring.

[0010] In an embodiment of the present invention, along the stacking direction of the stacking structure, the wiring width of the later layer is an integer multiple of the wiring width of the previous layer, and the wiring width of the later layer is at least 1 times the wiring width of the previous layer.

[0011] In an embodiment of the present invention, the semiconductor functional layer is one of a MOS transistor, a gate oxide layer, a polysilicon gate field effect transistor, an N-type junction, a P-type junction, a sheet resistance, a contact resistance, an isolation structure, a metal capacitor, and a polysilicon capacitor.

[0012] The present invention provides a layout design method, based on a semiconductor detection layout as described above, including the following steps:

[0013] Establish a database of the semiconductor detection layout;

[0014] Input the number of layers of the semiconductor functional layer and the wiring width of the bottom functional layer;

[0015] Take the wiring width of the current functional layer as the first width, and screen test structures from the database according to the wiring width of the bottom functional layer, the level of the current functional layer, and the first width;

[0016] In the test structure, mark the semiconductor functional layer located in the next level below the current functional layer as the next functional layer, and take the wiring width of the next functional layer as the second width;

[0017] Screen out the test structures with the second width less than the first width;

[0018] Update the next functional layer to the new current functional layer, and re-screen the test structures until the level of the current functional layer reaches the top layer of the preset stacking structure; and

[0019] Output any of the screened test structures as the semiconductor detection layout for testing.

[0020] In an embodiment of the present invention, the step of screening the test structures from the database includes:

[0021] Compare the current stacking structure with the test structures in the database layer by layer; and

[0022] Obtain a first test structure from the database, where the first test structure has the same number of layers and hierarchical wiring width as the current stacking structure.

[0023] In an embodiment of the present invention, the step of screening out the test structures includes:

[0024] Set a first wiring width range;

[0025] Obtain the wiring width of the current functional layer as the first width;

[0026] Filter out a second wiring width range from the first wiring width range, where the width values in the second wiring width range are greater than or equal to the first width; and

[0027] Retain a part of the test structures in the first test structure as the second test structure, where in the second test structure, the wiring width of the next functional layer is within the second wiring width range.

[0028] In an embodiment of the present invention, after updating the next functional layer to the new current functional layer, if the new current functional layer is the top layer of the preset stacked structure, output the current second test structure.

[0029] In an embodiment of the present invention, after updating the next functional layer to the new current functional layer, if the new current functional layer has not reached the top layer of the preset stacked structure, re-enter the number of layers of the semiconductor functional layer.

[0030] In an embodiment of the present invention, when the number of layers of the semiconductor functional layer remains unchanged, skip the step of re-entering the number of layers of the semiconductor functional layer.

[0031] The present invention provides a layout design system, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the layout design method as described in any one of the above when executing the computer program.

[0032] As described above, the present invention provides a semiconductor detection layout, a layout design method, and a layout design system, which can automatically design and adjust the detection layout in the wafer manufacturing process and are used to implement wafer acceptability testing. Moreover, the layout design method and system provided by the present invention can meet various testing requirements in the integrated circuit manufacturing process, and can adaptively change the detection layout structure when the number of testing layers changes. It can not only avoid the delay of the manufacturing process or experiment caused by the re-design of the entire wafer, but also avoid the excessive occupation of wafer area caused by too many test patterns, and can also improve the consistency of the detection layout on the entire wafer. Therefore, according to the semiconductor detection layout, layout design method, and layout design system provided by the present invention, the manufacturing efficiency can be improved, and the wafer area occupation can be reduced.

[0033] Of course, it is not necessary for any product implementing the present invention to achieve all the above advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0035] Figure 1 It is a schematic diagram of the regional distribution structure on the surface of a wafer in an embodiment of the present invention.

[0036] Figure 2 It is a schematic diagram of the distribution structure of test keys on a wafer in an embodiment of the present invention.

[0037] Figure 3 It is a schematic diagram of the hierarchical distribution structure of test keys in an embodiment of the present invention.

[0038] Figure 4 It is a schematic diagram of the top view layout structure of test keys in an embodiment of the present invention.

[0039] Figure 5 It is a schematic diagram of the structure of a database in an embodiment of the present invention.

[0040] Figure 6 It is a flowchart of a layout design method in an embodiment of the present invention.

[0041] Figure 7 It is a schematic diagram after layer skipping in an embodiment of the present invention.

[0042] Figure 8 It is a block diagram of the structural principle of a layout design system in an embodiment of the present invention.

[0043] Figure 9 It is a block diagram of the structural principle of a computer-readable storage medium in an embodiment of the present invention. Detailed implementation manners

[0044] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0045] The Wafer Acceptance Test (WAT) is conducted after the wafer product has completed the chip fabrication process and before quality inspection, and is used to measure the electrical parameters of test keys. The purpose of the Wafer Acceptance Test is to detect the process conditions of each wafer product by testing the electrical parameters of the test keys on the wafer, evaluate the quality and stability of the semiconductor manufacturing process, and determine whether the wafer product meets the electrical specification requirements of the process technology platform. Therefore, WAT data can be used as a quality certificate for wafer product delivery. In addition, WAT data can also reflect the actual production situation of the production line. By collecting and analyzing WAT data, the situation of the production line can be monitored, the trend of changes in the production line can be judged, and early warnings can be issued for possible situations. As Figure 1 and Figure 2 shown, the Wafer Acceptance Test is based on test key TK, where test key TK is placed in the scribe lane 102. Figure 1 As Figure 1 shown for illustrative purposes only, chip particles 101 and scribe lanes 102 are provided on wafer 100. A plurality of chip particles 101 are distributed on wafer 100 and, on the premise of a preset distance interval, cover wafer 100 as much as possible. The scribe lanes 102 are distributed in a grid pattern, and the scribe lanes 102 are provided between adjacent chip particles 101.

[0046] Please refer to Figure 1 and Figure 2As shown, the test key TK is disposed in the scribing lane 102. In the detection layout provided by the present invention, the test key TK includes a test pattern and a bonding pad 103. Among them, there are multiple bonding pads 103 in the scribing lane 102, and the multiple bonding pads 103 are evenly distributed in the scribing lane 102 and are distributed along the length direction of the scribing lane 102. In this embodiment, the test pattern is disposed between adjacent bonding pads 103. This embodiment takes the contact resistance Rc in a CMOS transistor as an example for illustration. The contact resistance includes a stacked structure. The stacked structure is distributed between the bonding pads 103. In some embodiments of the present invention, the bonding pad 103 may be the top functional layer of the stacked structure, specifically the top metal layer of the stacked structure. In this embodiment, the bonding pad 103 can be used to connect a test probe after chip packaging. Specifically, when performing a WAT test on the wafer 100, the test probe is connected to the bonding pad 103, so as to obtain the electrical performance of the test pattern and measure whether the measured electrical parameters meet the standards. In the present invention, there are various types of test patterns of the test key TK, and specifically include active devices, passive devices, isolation structures, etc. on the wafer process platform. In the present invention, the test pattern of the test key TK can be and is not limited to MOS transistors, Gate Oxide Integrity (GOI), polysilicon gate field effect transistors, N-type junctions, P-type junctions, sheet resistance Rs, contact resistance Rc, isolation structures, metal capacitors (MIM Capacitor), polysilicon capacitors (PIP Capacitor), etc.

[0047] Please refer to Figures 1 to 4 As shown, in an embodiment of the present invention, the wafer 100 includes a substrate, and the device structure and electrical structure of the chip particle 101 are formed on the substrate. To form the chip particle 101, multiple functional layers are formed on the substrate. Among them, while forming the chip particle 101, the structure of the test key TK is formed through a manufacturing process. Therefore, the test key TK includes multiple semiconductor functional layers, and the number of semiconductor functional layers is the same as the number of semiconductor functional layers of the wafer 100. As Figure 3 shown in a schematic diagram of the distribution level of a test key TK. Figure 3 shows seven semiconductor functional layers M1 to M7. The semiconductor functional layers are metal layers. In this embodiment, the semiconductor functional layers include impedance wirings, and the semiconductor functional layers are stacked, and the impedance wirings of adjacent semiconductor functional layers can be connected through contact holes Via. In this embodiment, the semiconductor functional layers are metal layers. As Figure 3 shown in the contact hole V6 between the sixth metal layer M6 and the seventh metal layer M7. In this embodiment, both the impedance wiring and the contact hole have widths. Taking the width of the first metal layer M1 as 1 times the width, the width of the impedance wiring disposed and stacked on the first metal layer M1 is greater than or equal to the width of the first metal layer M1. AsFigure 3 As shown, the impedance wiring width of the second metal layer M2 to the sixth metal layer M6 is 1 times the width, and the impedance wiring width of the seventh metal layer M7 is, for example, 8 times the width. And as Figure 3 and Figure 4 shown, the width of the contact hole is equal to the impedance wiring width of the connected metal layer, and specifically, the width of the contact hole is equal to the maximum impedance wiring width of the connected metal layer. As Figure 3 shown, the width of the contact hole V6 is 8 times the width. Figure 4 A top view wiring schematic diagram of multiple metal layers is shown. Among them, the present invention does not limit the wiring shape of the metal layer in the test key TK, but only limits the key dimensions of the test key TK, such as the impedance wiring width.

[0048] Please refer to Figures 1 to 5 shown, in an embodiment of the present invention, in the stacked structure, along the stacking direction, the impedance wiring width remains unchanged or increases, and the impedance wiring widths of multiple metal layers are integer multiples of the impedance wiring width of the first metal layer M1. The contact hole width is equal to the maximum metal width of the contacted metal layer. Among them, based on the width of the first metal layer M1, the impedance wiring width of the metal layer and the contact hole width can be 1 times the width, 2 times the width, 4 times the width, 8 times the width, etc., where the width multiple. According to different requirements of the process platform, the width multiple base can be adjusted. For example, the upper layer impedance wiring width can also be 3 times the width, 5 times the width, 7 times the width, etc. In this embodiment, the top functional layer and the sub-top functional layer are connected through a contact hole. According to the number of metal layers and the impedance wiring width of the stacked metal layers below the top functional layer, the width of the top functional layer also changes accordingly. Therefore, the impedance wiring width of the top functional layer can be 1 times the width, 2 times the width, 4 times the width, 8 times the width, etc. As Figure 5 shown, if the impedance wiring width of the first metal layer M1 is 1 times the width, then the impedance wiring widths of the second metal layer M2 to the Nth metal layer can be 1 times the width, 2 times the width, 4 times the width, 8 times the width, etc. When the impedance wiring width of the second metal layer M2 is, for example, 2 times the width, then the impedance wiring width of the third metal layer M3 is at least 2 times the width. For example, the impedance wiring widths of the third metal layer M3, the fourth metal layer M4, and the fifth metal layer M5 are at least 2 times the width. Then the impedance wiring width of the sixth metal layer M6 is at least 2 times the width. For example, the impedance wiring widths of the sixth metal layer M6, the seventh metal layer M7, and the eighth metal layer M8 are 4 times the width. For example, if the number of metal layers is 9 layers, then at this time the impedance wiring width of the top functional layer can be 4 times the width or 8 times the width. Therefore, according to the impedance wiring widths of different metal layers, multiple test keys TK can be combined.

[0049] Please refer to Figures 1 to 6As shown, in an embodiment of the present invention, a database is established according to the impedance wiring width combination mode of the stacking structure. As Figure 5 shown, after determining the semiconductor functional layer at the bottom and in the case of determining the number of semiconductor functional layers, the design scheme of the stacking structure can be automatically obtained by retrieving data from the database. Among them, the semiconductor functional layer with the wiring width already determined currently is the current functional layer, and the next semiconductor functional layer to determine the wiring width is the next functional layer. Along the stacking direction, the single or multiple semiconductor functional layers at the bottom are the bottom functional layers, and the single semiconductor functional layer at the top is the top functional layer. Specifically, as Figure 6 shown, based on the design rules provided by the present invention, the present invention provides a layout design method, and the layout design method includes steps S10 to step S90.

[0050] Step S10, preset the number of semiconductor functional layers and the impedance wiring width of the bottom functional layer.

[0051] Step S20, use the impedance wiring width of the current functional layer as the first width.

[0052] Step S30, based on the impedance wiring width of the current functional layer, obtain the test structure in the database.

[0053] Step S40, use the impedance wiring width of the next functional layer in the test structure as the second width.

[0054] Step S50, judge whether the second width is greater than or equal to the first width.

[0055] Step S60, when the second width is greater than or equal to the first width, update the next functional layer in the test structure to the current functional layer.

[0056] Step S70, after step S60, judge whether the current functional layer is the top functional layer. If the current functional layer is not the top functional layer, return to step S10.

[0057] Step S80, if the current functional layer is the top functional layer, use the current test structure as the test key.

[0058] Step S90, in step S50, when the second width is less than the first width, screen out the current test structure and return to step S30.

[0059] Please refer to Figures 1 to 6As shown, in an embodiment of the present invention, in step S10, the number of metal layers and the impedance wiring width of the bottom functional layer are preset. The bottom functional layer includes at least the first metal layer M1. According to the layout design requirements, for example, the first 3 metal layers including the first metal layer M1, or the first 2 metal layers, etc. can be preset. For example, when the number of metal layers is 10, the impedance wiring widths of several more metal layers can be preset to quickly define and obtain a test structure that meets the design rules. Then in step S20, the first width is obtained. Taking the first metal layer M1 as the bottom functional layer as an example, in step S20, first, the first metal layer M1 is used as the current functional layer, and then the next functional layer of the current functional layer is the second metal layer M2. The width of the current functional layer is the impedance wiring width of the first metal layer M1, that is, 1 times the width. In step S30, based on the impedance wiring width of the current functional layer, the test structures in the database are obtained. The test structures refer to various stacked structures preset in the database. Among them, based on the impedance wiring width of the current functional layer, first, the layer number where the current functional layer is located is obtained, and then the impedance wiring width of the current functional layer is obtained. If the impedance wiring width of the first metal layer M1 is 1 times the width, then the test structures with the impedance wiring width of the first metal layer M1 being 1 times the width in the database are obtained. Another example is that the current functional layer is the second metal layer M2, and the impedance wiring width of the second metal layer M2 is 2 times the width. Then the current functional layer is the second metal layer M2, and the first width is 2 times the width. Therefore, in step S30, the test structure with the first metal layer M1 being 1 times the thickness and the second metal layer M2 being 2 times the thickness is obtained. And so on.

[0060] Please refer to Figures 1 to 6As shown, in an embodiment of the present invention, in step S40, there are multiple corresponding test structures in the database. Based on the obtained test structures, the next functional layer of the current functional layer is obtained. The impedance routing width of the next functional layer is the second width. At this time, there are many possibilities for the second width. As long as the second width is greater than or equal to the first width, it conforms to the design rules. Therefore, step S50 is executed to screen out the test structures with the second width less than the first width. As in step S90, after screening out the current test structure, return to step S30 to obtain a new test structure again until the second width in the test structure is greater than or equal to the first width. When the second width is greater than or equal to the first width, step S60 is executed to update the next functional layer in the current test structure to the current functional layer. For example, the impedance routing width of the third metal layer M3 is 4 times. When the first metal layer M1 is 1 time thick, the second metal layer M2 is 2 times thick, and the third metal layer M3 is 4 times thick, in step S60, the third metal layer M3 is updated to the current functional layer. In this embodiment, in the step of obtaining the second width of the next functional layer, a width data can be randomly obtained by a machine, or the minimum impedance routing width can be preferentially obtained according to the selected layer. For example, among the metal layers sorted from 1 to 5, when selecting the second width, the impedance routing width is from 1 time width to 4 times width. Among the metal layers sorted from 6 to 10, when selecting the second width, the impedance routing width is from 6 times width to 10 times width. When selecting the second width of the next functional layer, the impedance routing width with the smallest value within the width range is given the first priority, so as to reduce the floor area of the stacked structure.

[0061] Please refer to Figures 1 to 6 As shown, in an embodiment of the present invention, in step S70, if the updated current functional layer is the top functional layer, then step S80 is executed. Among them, the top functional layer is the metal layer with the largest layer number. For example, if the number of metal layers is 9 layers, then the ninth metal layer M9 is the top functional layer. In step S80, the current test structure is used as the test key TK. And in this embodiment, the top functional layer in the stacked structure can be used as the pad 103. In step S70, if the updated current functional layer is not yet the top functional layer, then return to step S10 to update the value of the first width and continue to obtain the second width of the next functional layer, so as to obtain the test structure until the impedance routing widths of all metal layers are determined. After determining the metal wiring thickness of the metal layer, the contact hole width between adjacent metal layers can be determined. In this embodiment, the contact hole width is the maximum impedance routing width of the connected metal layers. In this embodiment, the impedance routing width of the top functional layer can be set to the maximum width to quickly obtain the test structure.

[0062] Please refer to Figures 1 to 7As shown, in one embodiment of the present invention, in step S70, if the updated current functional layer is not yet the top functional layer, then return to step S10. Since the number of steps in the chip manufacturing process is nearly a thousand, and the process needs to be closely monitored and the process improvement plan needs to be continuously studied, changes in the wafer manufacturing method may occur during the wafer process cycle, and temporary testing is required at this time. If the test plan changes, the number of metal layers must be changed. For example, after the bottom functional layer is formed, the number of metal layers is temporarily changed to 3 layers for experimental testing needs. As Figure 7 As shown, the first metal layer M1 and the second metal layer M2 are the bottom functional layers that have been formed. If the original solution is adopted, when the experimental test requirements are received, the original metal layer cannot be packaged and tested, and the original test key TK can only be overturned and the structure of the test key TK can only be redesigned. On the wafer 100, it is necessary to make changes to the level, which involves many test keys TK to be changed, so the original design scheme is difficult to meet temporary experimental needs. And the design of various test keys TK will greatly occupy the wafer area. According to the technical solution provided by the present invention, for this application situation, layer jumping can be directly implemented. Specifically, after determining whether the current functional layer is the top functional layer, if the current functional layer is not the top functional layer, directly return to step S10 and reset the number of metal layers at this time. For example, if Figure 7 As shown, the number of metal layers temporarily replaced is three layers, then the next functional layer is the third metal layer, and the third metal layer is also the top functional layer. The width of the third metal layer can be directly set to 4 times the maximum value of the impedance wiring width in the preset range or 8 times the maximum value of the impedance wiring width. Therefore, the width of the contact hole at this time is also changed to 4 times the width or 8 times the width. According to the layout design method provided by the present invention, the structure of the test key TK can be automatically and timely adjusted to adapt to various test requirements of the process. And according to the semiconductor layout design method provided by the present invention, while being able to adapt to the process requirements, it can also avoid the wafer occupying too large an area due to the adaptive change of the test key TK. In this embodiment, if the number of layers of the semiconductor functional layer has not changed, the step of presetting the number of metal layers at this time can also be directly skipped, and step S20 is executed.

[0063] See also Figures 1 to 7As shown, in other embodiments of the present invention, when the test patterns are MOS transistors, the integrity of the gate oxide layer, polysilicon gate field effect transistors, N-type junctions, P-type junctions, sheet resistance Rs, contact resistance Rc, isolation structures, metal capacitors, and polysilicon capacitors, etc. For passive devices, such as sheet resistance Rs and contact resistance Rc, along the stacking direction of the stacked structure, the width of the impedance wiring remains unchanged or increases. And along the stacking direction of the stacked structure, the width of the contact holes remains unchanged or increases. The contact holes are used to connect the impedance wirings of adjacent layers or the metal wirings of adjacent semiconductor functional layers in the metal interconnect structure. For active devices, such as MOS transistors and polysilicon gate field effect transistors, along the stacking direction of the stacked structure, the width of the metal wirings in the metal interconnect structure remains unchanged or increases. And along the stacking direction of the stacked structure, the width of the contact holes remains unchanged or increases.

[0064] Please refer to Figure 8As shown in the figure, the present invention also provides a layout design system. The layout design system includes a processor 200 and a memory 300. The memory 300 stores program instructions, and the processor 200 runs the program instructions to implement the above-mentioned layout design method. The processor 200 can be a general-purpose processor, including a central processing unit (CPU for short), a network processor (NP for short), etc.; it can also be a digital signal processor (DSP for short), an application specific integrated circuit (ASIC for short), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components; the memory 300 may include a random access memory (RAM for short), and may also include a non-volatile memory, such as at least one disk memory. The memory 300 can also be an internal memory of the random access memory (RAM) type. The processor 200 and the memory 300 can be integrated into one or more independent circuits or hardware, such as: an application specific integrated circuit (ASIC). It should be noted that when the computer program in the above-mentioned memory 300 can be implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a layout design system, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention.

[0065] Please refer to Figure 9As shown, the present invention also provides a computer-readable storage medium 401, which stores computer instructions 400 for causing the computer to execute the above-mentioned layout design method. The computer-readable storage medium 401 may be an electronic medium, a magnetic medium, an optical medium, an electromagnetic medium, an infrared medium, or a semiconductor system or a propagation medium. The computer-readable storage medium 401 may also include semiconductor or solid-state memories, magnetic tapes, removable computer disks, random access memories (RAMs), read-only memories (ROMs), hard disks, and optical disks. The optical disks may include compact disk-read only memories (CD-ROMs), compact disk-read / write (CD-RWs), and digital versatile disks (DVDs).

[0066] The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A layout design method, characterized in that: The following steps are involved: Establishing a database of semiconductor detection layouts, wherein the semiconductor detection layouts include multiple semiconductor functional layers, and impedance wiring or metal wiring, wherein the multiple semiconductor functional layers are stacked on a wafer to form a stacked structure, and the impedance wiring and the metal wiring are arranged in the semiconductor functional layers; Input the number of semiconductor functional layers and the wiring width of the bottom functional layer; Taking the wiring width of the current functional layer as a first width, and screening a test structure from the database according to the wiring width of the bottom functional layer, the level of the current functional layer and the first width; In the test structure, marking the semiconductor functional layer located at a level below the current functional layer as a next functional layer, and using the wiring width of the next functional layer as a second width; Screening out the test structures whose second width is smaller than the first width; Updating the next functional layer as a new current functional layer, and rescreening the test structure until the level of the current functional layer reaches the top layer of a preset stacking structure; as well as Output any of the screened test structures as a semiconductor inspection layout for testing.

2. A layout design method according to claim 1, characterized in that: The step of selecting the test structure from the database comprises: Comparing the current stacking structure with the test structure in the database layer by layer; and A first test structure is obtained from the database, wherein the first test structure has the same number of layers and layer wiring width as the current stacking structure.

3. A layout design method according to claim 2, characterized in that: The step of screening out the test structure comprises: Setting a first wiring width range; Acquire the wiring width of the current functional layer as a first width; Filtering out a second wiring width range from the first wiring width range, wherein a width value in the second wiring width range is greater than or equal to the first width; and A portion of the first test structure is reserved as a second test structure, wherein in the second test structure, the wiring width of the next functional layer is within the second wiring width range.

4. A layout design method according to claim 3, characterized in that: After the next functional layer is updated to be the new current functional layer, if the new current functional layer is the top layer of the preset stacking structure, the current second test structure is output.

5. A layout design method according to claim 4, characterized in that: After the next functional layer is updated as the new current functional layer, if the new current functional layer does not reach the top layer of the preset stacking structure, the number of layers of the semiconductor functional layer is re-input.

6. A layout design method according to claim 5, characterized in that: When the number of the semiconductor functional layers remains unchanged, the step of re-inputting the number of the semiconductor functional layers is skipped.

7. A semiconductor detection layout, based on a layout design method as claimed in claim 1, characterized in that: The semiconductor detection layout is arranged on a wafer, and the semiconductor detection layout is located in a cutting path of the wafer, wherein the semiconductor detection layout comprises: A plurality of semiconductor functional layers, wherein the plurality of semiconductor functional layers are stacked on the wafer to form a stacked structure; Impedance wiring or metal wiring, arranged in the semiconductor functional layer, wherein along the stacking direction of the semiconductor functional layer, the wiring width of the semiconductor functional layer increases or remains unchanged, wherein the wiring width is the width of the impedance wiring or the width of the metal wiring; and The contact pillar is electrically connected to the adjacent impedance wiring or the adjacent metal wiring, wherein the width of the contact pillar is consistent with the maximum width of the contacted wiring.

8. A semiconductor detection layout according to claim 7, characterized in that: Along the stacking direction of the stacking structure, the width of the rear wiring layer is an integer multiple of the width of the front wiring layer, and the width of the rear wiring layer is at least 1 times the width of the front wiring layer.

9. A semiconductor detection layout according to claim 7, characterized in that: The semiconductor functional layer is one of a MOS transistor, a gate oxide layer, a polysilicon gate field effect transistor, an N-type junction, a P-type junction, a block resistor, a contact resistor, an isolation structure, a metal capacitor and a polysilicon capacitor.

10. A layout design system, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the layout design method according to any one of claims 1 to 6 when executing the computer program.

Images