Power supply control circuit, related power supply and method for operating power supply

Abstract

The invention relates to a power supply control circuit, a related power supply and a method of operating a power supply. A power supply control circuit for a power supply is provided that includes a PFC converter configured to generate a bus voltage, an electronic converter, and an auxiliary power supply configured to generate an auxiliary supply voltage. The PFC converter includes a PFC control circuit configured to drive the PFC converter to adjust the bus voltage to a requested value. When the output power is greater than a threshold value, the power supply control circuit supplies an auxiliary supply voltage to the PFC control circuit. When the output power is less than a threshold, the circuitry compares the bus voltage to an upper threshold and a lower threshold. When the bus voltage is greater than the upper threshold, the circuit disables the supply of the auxiliary supply voltage to the PFC control circuit. The circuit supplies an auxiliary supply voltage to the PFC control circuit when the bus voltage is less than a lower threshold.

Description

Technical Field

[0001] Embodiments of the present description relate to a power supply control circuit for a two-stage power supply including a power factor correction (PFC) electronic converter, such as a boost converter. Background Art

[0002] Switching mode power supplies are known in the art. For example, Figure 1 A typical two-stage electronic power supply is shown.

[0003] In the example considered, the power supply comprises two input terminals 200a and 200b configured to receive an AC input voltage V in,AC , such as 230VAC at 50Hz or 110VAC at 60Hz, and two output terminals 202a and 202b, which are configured to provide a regulated output voltage V to the load 30 out or the regulated output current i out .

[0004] Specifically, in the example considered, the AC input voltage V in,AC The DC voltage is converted into a DC voltage via a rectifier circuit 206 (eg, a bridge rectifier), i.e., the input terminal of the rectifier circuit is coupled to the input terminals 200a and 200b, and the output terminals 208a and 208b of the rectifier circuit provide a DC voltage V in,DC Typically, the filter circuit 204 is connected between the input terminals 200 a and 200 b and the input terminal of the rectifier circuit 206 .

[0005] In the example considered, the power supply consists of two stages:

[0006] The first stage 210 is configured to receive a DC voltage V via terminals 208a and 208b. in,DC and generates a regulated DC voltage V at two terminals 212a and 212b bus ;and

[0007] The second stage 214 is configured to receive a voltage V via terminals 212a and 212b. bus and produces a regulated output voltage V at output terminals 202a and 202b out or the regulated output current i out .

[0008] In particular, as described, for example, in US Pat. No. US6,222,746B1, such a two-stage architecture has the following advantages: the first stage 210 may be an electronic converter with power factor correction (PFC), which thus generates a regulated voltage V bus, while improving the power factor of the power supply. For example, the first stage is usually implemented using a PFC boost converter. bus Depending on the value of and the power requirements of the load 30, the second stage 214 can be implemented using various electronic converters, such as buck, buck-boost, flyback, forward, half-bridge or full-bridge converters.

[0009] For example, Figure 2A An example of a PFC boost converter 210 is shown.

[0010] Specifically, in the example considered, stage 210 comprises:

[0011] an inductor L1 , such as an inductor, which is (eg directly) connected between the positive terminal 208 a and the switching node SN;

[0012] an electronic switch SW1, e.g. a field effect transistor (FET), e.g. a metal oxide semiconductor field effect transistor (MOSFET), e.g. an n-channel FET, e.g. an NMOS, having a current path connected (e.g. directly) between the switch node SN and the negative terminal 208 b;

[0013] another electronic switch SW2, such as a diode or another FET, such as a p-channel FET, such as a PMOS, having a current path connected (e.g. directly) between the switch node SN and the positive terminal 212a, wherein the negative terminal 212b is connected to the negative terminal 208b; and

[0014] A capacitor COUT is connected (eg, directly) between terminals 212a and 212b.

[0015] Optionally, stage 210 may also include a capacitor CIN connected (e.g., directly) between terminals 208a and 208b. Typically, the respective capacitance between terminals 208a and 208b should be small so as not to significantly affect the power factor of the power supply. In fact, in PFC stage 210, the voltage V at terminals 208a and 208b is in,DC Basically corresponds to a positive sine half wave.

[0016] In the example considered, the PFC stage 210 further comprises a PFC control circuit 2112 configured to generate a drive signal DRV1 for the electronic switch SW1 and optionally the electronic switch SW2 (if controllable electronic switches are used).

[0017] like Figure 2B As shown in FIG. , the PFC control circuit 2112 is generally configured to switch between SW Drive electronic switch SW1, switching period T SW include:

[0018] Switch-on phase T ON , wherein the switch SW1 is closed and the diode / switch SW2 is open, thereby increasing the current flowing through the inductor L1; and

[0019] Turn off phase T OFF , wherein the switch SW1 is opened and the diode / switch SW2 is closed, whereby the current of the inductor L1 flows to the output terminal 212a / 212b through the diode / switch SW2, thereby charging the capacitor COUT.

[0020] Therefore, the increase in the current flowing through the inductor L1 during the on-state depends on the on-duration T ON The duration and input voltage V in,DC Specifically, assuming the ideal behavior of the boost converter, when the on-time T ON Keep constant, during the on time T ON At the end, the input current i received via terminals 208a and 208b in,DC The peak value and voltage V in,DC The boost converter is therefore particularly suitable for use in a PFC converter.

[0021] The various operating modes of a PFC boost converter are known in the art. For example, STMicroelectronics, Application note AN2761, "Solution for designing a transition mode PFC preregulator with the L6562A", November 2009, Doc ID 14690Rev2, or Sam Abdel-Rahman, Franz Stückler, Ken Siu, Application Note, "PFC boost converter design guide - 1200W design example", Revision 1.1, 2016-02-22, may be cited in this context.

[0022] Essentially, the PFC control circuit 2112 may be configured to operate the boost converter in three modes: continuous conduction mode (CCM), discontinuous conduction mode (DCM), or critical conduction mode (CrCM), also commonly referred to as transition mode (TM).

[0023] like Figure 2A As schematically shown in FIG. 1 , the common point of these control schemes is that the voltage sensor 2110 is used to generate a feedback signal FB1, which indicates the voltage V at the terminal 212a / 212b. bus(and preferably proportional thereto.) For example, in the example considered, the voltage sensor 2110 is implemented using a resistor divider comprising two resistors R1 and R2 connected between the terminals 212a and 212b.

[0024] In the example considered, the feedback signal FB1 is fed to the error amplifier 2114, which is configured to generate an error signal according to the feedback signal FB1 and the indication voltage V bus The reference signal REF1 of the requested value generates the error signal V COMP1 Typically, the error amplifier 2114 (e.g., an operational amplifier) ​​has an associated feedback / compensation network 2118 that allows the error amplifier 2114 to be implemented as a regulator having integral (I) and / or proportional (P) components and an optional differential (D) component. More specifically, the error amplifier 2114 typically provides a current signal that is converted by the feedback / compensation network 2118 into a voltage error signal V COMP1 .

[0025] Then, the driving circuit 2116 is configured to COMP1 Generate (multiple) drive signals DRV1 (for switch SW1 and optional switch SW2). For example, as mentioned above, the drive circuit 2116 can generate a drive signal DRV1 (for switch SW1 and optional switch SW2) according to the signal V COMP1 Change the on time T ON .

[0026] Typically, feedback via error amplifier 2114 represents an outer (slow) control loop, while driver circuit 2116 may also implement an inner (fast) control loop, for example, to directly regulate the current flowing through inductor L1. Figure 2A As schematically shown in , for this purpose, the boost converter may further comprise a current sensor 2120, such as a resistor RS, configured to generate a signal CS indicative of (and preferably proportional to) the current flowing through the inductor L1 at least during one of the on or off periods.

[0027] on the contrary, Figure 3 A generic regulated DC / DC converter 214 scheme is shown.

[0028] Specifically, a common switch mode DC / DC converter includes:

[0029] a switching stage 2140 comprising one or more electronic switches SW and one or more reactive components, such as an inductor L and / or a capacitor C;

[0030] A measurement circuit 2142 is configured to generate a signal indicating the output current i (based on whether the converter is providing a regulated current or a regulated voltage). out Or output voltage Vout (and preferably proportional thereto) to a feedback signal FB2, such as a resistor divider including two resistors R3 and R4 connected between terminals 202a and 202b; and

[0031] The control circuit 2144 is configured to generate one or more drive signals DRV2 for one or more electronic switches SW.

[0032] For example, with regard to Figure 2A Similar to the description, the control circuit 2144 may further include:

[0033] An error amplifier 2146 having an associated feedback network 2150, wherein the error amplifier 2146 is configured to provide a feedback signal FB2 and an output current i out Or output voltage V out The reference signal REF2 of the requested value generates the error signal V COMP2 ;as well as

[0034] The driving circuit 2148 is configured to COMP2 One or more drive signals DRV2 are generated.

[0035] As described, for example, in U.S. Pat. No. 11,258,354 B2, when the load 30 is connected to the terminals 202a and 202b, the above-mentioned modes DCM, CCM and CrCM are generally used. In contrast, when no load 30 is connected to the terminals 202a and 202b, or generally when the load between the terminals 202a and 202b is small, the regulation using the modes DCM, CCM and CrCM generally becomes inefficient, and the control circuit 2144 can be switched to a burst mode (BM), wherein the control circuit 2144 activates the switching of (multiple) electronic switches SW in one or more switching cycles, and then deactivates the switching. Similarly, the control circuit 2112 of the converter 210 can also be configured to selectively switch to a burst mode under low load conditions.

[0036] For example, the control circuit 2112 (or similarly the control circuit 2144) may be configured to generate a control signal based on the feedback signal FB1 (FB2) or based on the error signal V COMP1 (V COMP2 ) directly activates the burst mode.

[0037] For example, under low / light load conditions, the corresponding output voltage V bus (V out ) can be increased, and the control circuit 2112 (2144) can be configured as follows: when the voltage V bus (V out) exceeds the upper threshold, the burst mode is activated, for example by simply stopping the switching activity, and when the voltage V bus (V out ) falls below a lower threshold, the normal operating mode (DCM, CCM or CrCM) is activated, for example by resuming switching activity.

[0038] In contrast, when using the error amplifier 2114 (2146) and an integrating component (e.g., a capacitor) in the feedback network 2118 (2150), the corresponding error signal V COMP1 (V COMP2 ) will decrease as the load decreases. Essentially, when the voltage V bus (V out )When using output voltage regulation, the error signal V COMP1 (V COMP2 ) is proportional to the current supplied by converter 210 (214). Therefore, in this case, control circuit 2112 (2144) can be configured to COMP1 (V COMP2 ) falls below the lower threshold, for example by simply stopping the switching activity, and when the error signal V COMP1 (V COMP2 ) exceeds the upper threshold, the normal operating mode (DCM, CCM or CrCM) is activated, for example, by resuming switching activity. For example, if the error signal V COMP1 (V COMP2 ) is below the lower threshold, the control circuit 2112 (2144) prohibits switching activity. In this way, the current supplied by the converter 210 (214) is stopped. In any case, for example due to power loss or because the load 30 still consumes energy, the voltage V bus (V out ) and similarly the feedback signal FB1 (FB2) decreases. This results in the error signal V COMP1 (V COMP2 ) increases. Therefore, when the error signal V COMP1 (V COMP2 ) exceeds the upper threshold, the control circuit 2112 / 2144 can restart the switching of transferring energy to the load.

[0039] like Figure 4As shown in , control circuits 2112 and 2144 have recently been proposed, which support communication from the control circuit 2144 of the converter 214 to the control circuit 2112 of the PFC converter 210 via the signal EXT_BM in burst mode. For example, in this context reference may be made to the data sheet “Digital combo multi-mode PFC and time-shift LLC resonant controller” of the integrated circuit STNRG011, which is an integrated circuit comprising both the control circuit 2112 for the PFC converter 210 and the control circuit 2144 for the LLC electronic converter 214.

[0040] For example, the control circuit 2144 can be configured to set the signal EXT_BM to high when the control circuit 2144 has activated the burst mode, for example due to the signal FB2 exceeding the upper threshold or the error signal VCOMP2 falling below the lower threshold. Therefore, the signal EXT_BM is provided to the PFC control circuit 2112. For example, the PFC control circuit 2112 can deactivate the switching activity of the boost converter, in particular the electronic switch SW1, in response to the signal EXT_BM. This mechanism allows synchronizing the BM state of the first stage 210 with the BM state of the second stage 214, thereby improving the efficiency of the entire system consisting of two conversion stages. In this way, the BM state is applied to both stages by the second stage.

[0041] Typically, the PFC control circuit 2112 may include both an external burst mode (EBM) function as well as an (internal) BM function, i.e., the PFC control circuit 2112 may stop the switching activity when at least one of the following conditions is met:

[0042] When the signal EXT_BM is set to a given logic level; or

[0043] When the signal FB2 exceeds the upper threshold or preferably the error signal V COMP2 When it drops below the lower threshold. Summary of the invention

[0044] In view of the above circumstances, various embodiments of the present disclosure provide technical solutions for improving the operation of the PFC stage 210 .

[0045] According to one or more embodiments, one or more of the above objects are achieved by a power supply control circuit having unique elements as specifically set out in the accompanying claims.In addition, embodiments relate to related power supplies and methods.

[0046] The claims form an integral part of the technical teaching of the description provided herein.

[0047] As mentioned before, various embodiments of the present disclosure relate to a power supply control circuit for a power supply. The power supply includes: two input terminals, which are configured to be connected to a main power supply to receive an AC input voltage, and two output terminals, which are configured to be connected to a load. In addition, the power supply includes a rectifier circuit, a PFC electronic converter, and an electronic converter. Specifically, the rectifier circuit is configured to generate a rectified input voltage from the AC input voltage. The PFC electronic converter is configured to generate a bus voltage from the rectified input voltage. The electronic converter is configured to generate a regulated output voltage or a regulated output current from the bus voltage at two output terminals. For example, the electronic converter may include a control circuit, wherein the control circuit and the power supply control circuit are integrated in the same integrated circuit.

[0048] Specifically, in various embodiments, the PFC electronic converter includes a PFC control circuit, the PFC control circuit including a terminal for receiving a supply voltage, wherein the PFC control circuit is configured to drive the PFC electronic converter when powered via the supply voltage so as to adjust the bus voltage to a requested value. For example, in various embodiments, the PFC electronic converter is a boost converter, the boost converter including a positive input terminal and a negative input terminal for receiving a rectified input voltage, a positive output terminal and a negative output terminal for providing the bus voltage, an inductor connected between the positive input terminal and a switch node, an electronic switch connected between the switch node and the negative terminal, and another diode or another electronic switch connected between the switch node and the positive output terminal. In addition, the boost converter includes a feedback circuit, the feedback circuit is configured to generate a feedback signal proportional to the bus voltage, wherein the PFC control circuit is configured to drive the electronic switch and optionally another electronic switch when powered via the supply voltage so as to adjust the feedback signal to a reference value, the reference value indicating the requested value of the bus voltage.

[0049] In various embodiments, the power supply further comprises an auxiliary power supply configured to generate an auxiliary supply voltage. For example, the auxiliary power supply may comprise a capacitor and a charging circuit configured to charge the capacitor via the rectified input voltage. In this regard, in various embodiments, the electronic converter is a flyback converter comprising a transformer having an auxiliary winding, wherein the auxiliary winding is connected to the capacitor via a diode.

[0050] Specifically, in various embodiments, the power control circuit is configured to generate a signal indicating the output power provided via the two output terminals. For example, for this purpose, the power control circuit may estimate a signal proportional to the output voltage and a signal proportional to the output current, and generate a signal indicating the output power by multiplying the signal proportional to the output voltage and the signal proportional to the output current. Alternatively, the power control circuit may estimate a signal proportional to the bus voltage and a signal proportional to the current provided to the electronic converter, and generate a signal indicating the output power by multiplying the signal proportional to the output voltage and the signal proportional to the output current. Alternatively, the electronic converter may be configured to generate a regulated output voltage, and the signal indicating the output power may be proportional to the output current provided via the two output terminals. Alternatively, the electronic converter may be configured to generate a regulated output current, and the signal indicating the output power may be proportional to the output voltage at the two output terminals. For example, when the electronic converter is based on a flyback converter, the output voltage may be estimated by sampling the voltage at the auxiliary winding during the off period of the flyback converter.

[0051] In various embodiments, the power control circuit is configured to determine whether the signal indicates that the output power is greater than a threshold value. In response to determining that the signal indicates that the output power is greater than the threshold value, the power control circuit supplies the auxiliary supply voltage to the PFC control circuit. For example, in various embodiments, the power control circuit includes a terminal configured to be connected to a setting resistor, wherein the threshold value is defined via a resistance value of the setting resistor.

[0052] Conversely, in response to determining that the signal indicates that the output power is less than the threshold, the power control circuit generates a signal indicating the bus voltage. Specifically, in various embodiments, the power control circuit verifies whether the signal indicates that the bus voltage is greater than the upper threshold, and in response to determining that the signal indicates that the bus voltage is greater than the upper threshold, the power control circuit prohibits the supply of the auxiliary supply voltage to the PFC control circuit, thereby shutting down the PFC control circuit. In addition, the power control circuit verifies whether the signal indicates that the bus voltage is less than the lower threshold, and in response to determining that the signal indicates that the bus voltage is less than the lower threshold, the power control circuit supplies the auxiliary supply voltage to the PFC control circuit. For example, in various embodiments, the lower threshold is selected to be between 45% and 55% of the requested value of the bus voltage, and the upper threshold is selected to be between 55% and 65% of the requested value of the bus voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, which are provided purely by way of non-limiting examples, and in which:

[0054] Features and advantages of the present disclosure will become apparent from the following detailed description of practical embodiments thereof, illustrated by way of non-limiting example in the accompanying drawings, in which:

[0055] Figure 1 A first example of a two-stage power supply comprising a PFC converter stage and a DC / DC converter stage is shown;

[0056] Figure 2A and Figure 2B An example of a PFC boost converter is shown;

[0057] Figure 3 An example of a common DC / DC electronic converter is shown;

[0058] Figure 4 A second example of a two-stage power supply is shown;

[0059] Figure 5 An embodiment of a two-stage power supply configured to generate an auxiliary supply voltage is shown;

[0060] Figure 6 An embodiment of a two-stage power supply including a power control circuit is shown;

[0061] Figure 7 An embodiment of a flyback DC / DC electronic converter is shown;

[0062] Figure 8 An embodiment of an output voltage estimation circuit is shown;

[0063] Fig. 9 An embodiment of an output power estimation circuit is shown; and

[0064] Fig.10 Shows Figure 6 An embodiment of the operation of a power supply control circuit. DETAILED DESCRIPTION

[0065] In the following description, various specific details are described to provide a thorough understanding of the embodiments. The embodiments may be provided without one or more of these specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the embodiments.

[0066] References to "an embodiment" or "one embodiment" within the scope of this specification are intended to indicate that a particular configuration, structure, or characteristic associated with the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment," "in one embodiment," that may appear throughout this specification do not necessarily refer to the same embodiment. Furthermore, particular configurations, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.

[0067] The reference signs used herein are provided for convenience only and therefore do not limit the protective scope or range of the embodiments.

[0068] Described below Figures 5 to 10 In, reference has been made Figures 1 to 4 The components, elements or assemblies described are designated by the same reference numerals used previously in these drawings. The description of these elements has been made, and the description of these elements will not be repeated below so as not to burden this detailed description.

[0069] As described above, in many applications, the power supply actually includes two electronic converters, wherein the first stage implements the PFC electronic converter 210. In fact, without such a PFC converter, the electronic converter 214 would be directly connected to the rectified input voltage V in,DC .

[0070] In this case, a larger input capacitor CIN is usually used to stabilize the DC voltage V in,DC and supplies the downstream switching converter 214. In fact, the input capacitor CIN needs to supply sufficient power during each half cycle of the input voltage Vin. Unfortunately, when a larger input capacitor CIN is used, the line current i in,DC is usually no longer sinusoidal and includes high peaks. This means a significant reduction in the power factor and the resulting high harmonic content causes distortion and line noise. In contrast, when a PFC stage 210 is used, the stage attempts to reduce the line current i in,DC The curve of the voltage V in,DC The (half-sine) curve is synchronized to improve the power factor of the converter.

[0071] A high power factor also allows to reduce the peak current and therefore allows, for example, to improve the efficiency of energy transportation, transmission and distribution, the size of cables (especially neutral cables in three-phase systems) and power transformers can be reduced. Similarly, by avoiding high current pulses, failures of network protection devices can be avoided. Finally, the same power requires less current, and vice versa, at the same current, more power is available at the wall socket. For these reasons, the harmonic current emissions of low-power commercial equipment with an input current ≤16A per phase should be limited, as described, for example, in the reference standard IEC61000-3-2. For example, the standard IEC61000-3-2 identifies four different categories in which equipment connected to the power grid is divided into:

[0072] A: Equipment that does not belong to categories B, C or D (audio equipment, household appliances, balanced three-phase equipment, stage lighting and professional studio lighting, etc.);

[0073] B: Portable tools, non-professional equipment for arc welding;

[0074] C: Lighting equipment (lamps and lamps) with an input active power ≥ 5W;

[0075] D: IT equipment with input active power ≥75W and ≤600W (PC, PC monitor, printer, ac adapter for laptop PC, etc.), TV receiver, some types of refrigerators and freezers.

[0076] One of the main disadvantages of using a PFC pre-regulator is that the overall efficiency of such a two-stage architecture is reduced (the total efficiency is given by the product of the efficiencies of any single stage), and this requires a specific control strategy to limit the inefficiency of the system. For example, as mentioned before, in prior art solutions, the efficiency of the system is usually improved by activating the burst mode of the PFC stage 210 under light load conditions, whereby the PFC stage still produces a regulated output voltage V bus However, in this case, the control circuit of the PFC converter 210 must remain switched on in order to manage the burst mode.

[0077] In this regard, power loss can be further reduced by turning off the PFC stage 210 under given load conditions. For example, for devices belonging to category D (power adapters and chargers are included in this category), the PFC stage is not required when the input power is below 75W. Therefore, in this case, the power supply can be configured as:

[0078] When the power supply is operated at an input power greater than 75W, the PFC stage is turned on; and

[0079] When the power supply is operated at less than 75W input power, the PFC stage is shut down.

[0080] For example, when the PFC boost converter 210 is used, the output capacitor COUT can be charged via the diode SW2 in this case, whereby the output capacitor COUT can still supply the second-stage electronic converter 214. However, in this case, the voltage V bus will have ripple, and will be at most the (rectified) input voltage V in,DC value, which can also correspond to a wide range of different mains supply voltages V in , for example, the range is from 85VAC to 264VAC. This means, for example, that the design at voltage V bus An electronic converter 214 having high efficiency over the entire variable range of 210 may be complex. In fact, in a conventional power supply having a PFC converter 210, the bus voltage V generated by the activated PFC converter 210 is bus Approximately in the 400V range.

[0081] In addition, the power supply must properly manage the transient from light load to heavy load, because the PFC converter 210 may take some time to recover steady-state operation, thereby causing the bus voltage V bus For example, at low mains voltages (e.g., 110VAC for the US input voltage), the bus voltage V bus may drop below the allowed input voltage of converter 214 .

[0082] Therefore, converter 214 must manage a wide range of load conditions and input voltages V bus , thus, it is difficult to optimize the converter 214. For example, if the converter 214 includes a peak current mode control and a constant switching period T SW If the flyback converter 214 is operated in quasi-resonant mode (i.e., with a variable switching frequency), the primary peak current increases until the overcurrent protection may be triggered, resulting in a temporary loss of output voltage regulation.

[0083] For this reason, the converter 214 must use larger reactive components, for example, in order to manage a higher root mean square (RMS) of the input current, which in turn results in higher conduction losses, for example due to higher power losses in the magnetic components. Similarly, a large capacitor COUT may be required in order to provide sufficient energy during load transitions.

[0084] Therefore, simply turning off the PFC stage may be inefficient for the second-stage converter 214. In this regard, improved solutions are known in the art. For example, Y. Jang, MM Jovanovic, and DL Dillman, "Light-Load Efficiency Optimization Method", 2009 Twenty-Fourth Annual IEEE Applied Power Electronics Conference and Exposition, Washington, DC, USA, 2009, pp. 1138-1144, doi: 10.1109 / APEC.2009.4802806 proposed a technical solution in which the PFC stage 210 is periodically activated and deactivated. Specifically, in this technical solution, the PFC converter is deactivated near the zero crossing point of the line voltage and activated near the peak of the line voltage. Therefore, this technical solution allows the PFC stage to be temporarily deactivated while still obtaining a regulated bus voltage V bus .

[0085] U.S. Patent Application Publication No. US2015 / 0155776A1 discloses a similar technical solution, in which the PFC stage is deactivated near the zero crossing point of the line voltage. However, in this case, the PFC stage 210 is activated within a given time period (centered at the peak moment), wherein the time period (also referred to as the modulated phase angle) is determined according to the load conditions.

[0086] The inventors have observed that the above technical solution requires additional circuitry in order to determine the zero-crossing region of the input voltage. In addition, although the switching stage of the PFC converter 210 may be disabled, the control circuit 2112 of the PFC converter 210 remains enabled in order to regulate the bus voltage V bus , so that power losses still occur, which can be relevant under medium load conditions and especially light load conditions.

[0087] Embodiments of a technical solution will now be described in the following which allow improving the efficiency of the power supply while also providing a suitable transient response.

[0088] Figure 5 is shown configured to generate an auxiliary supply voltage V aux The power supply 20a basically includes Figure 1 The blocks already shown, namely:

[0089] Two input terminals 200a and 200b are configured to receive an AC input voltage V in,AC ;

[0090] The rectifier circuit 206 and the optional filter circuit 204 are configured to generate a rectified input voltage V in,DC ;

[0091] The PFC electronic converter 210a is configured to receive a DC voltage V in,DC and generates a regulated DC voltage V bus ,as well as

[0092] Another DC / DC electronic converter 214a is configured to receive a voltage V bus and generates a regulated output voltage V at two output terminals 202a and 202b out or the regulated output current i out .

[0093] As described above, the PFC electronic converter 210a (eg, implemented via a boost converter) includes a control circuit 2112a configured to control the voltage V bus and optional indication of AC input voltage V in,AC The phase signal of the oscillation (for example, the rectified input current i in,DC Or the rectified input voltage V in,DC ) to drive one or more electronic switches of the PFC electronic converter 210a.

[0094] In the embodiment considered, the control circuit 2112a of the PFC electronic converter 210a is not connected via the voltage V in_DC Or bus voltage V bus supply, but via another DC voltage V aux (e.g., having a value in the range of 1.5 to 10 V) is supplied. In various embodiments, the voltage V aux Via another voltage source (eg, receiving a voltage V in DC , bus voltage V bus and / or output voltage V out ) generates, and / or voltage V aux Generated by PFC electronic converter 210a and / or electronic converter 214a.

[0095] For example, according to U.S. Patent Application Publication No. US 2006 / 061337 A1, which is incorporated herein by reference for this purpose, the voltage V aux can be connected via capacitor C aux supply.

[0096] In various embodiments, the capacitor C aux Based on the rectified input voltage V in_DCFor example, the circuit 216 may include a diode 2160 and a resistor 2162 connected in series between the terminal 208a and the first terminal of the capacitor, wherein the capacitor C aux The second terminal of the capacitor C is connected to ground, for example corresponding to terminal 208b or 212b. Therefore, when the input voltage is applied to input terminals 200a and 200b, capacitor C aux In various embodiments, a Zener diode Dz or another voltage limiting circuit may be connected to the capacitor C aux , so that the capacitor V aux The voltage at is limited to the maximum value.

[0097] In various embodiments, circuit 216 may be used primarily or only during the pre-charge phase. In this case, once converter 210a and / or converter 214a are operating / switching, capacitor C aux is charged via converter 210a and / or converter 214a. For example, when a PFC boost converter is used, Figure 2A The inductor L1 shown in the figure can be replaced by the primary winding of the transformer, wherein an additional rectifying circuit (for example, implemented by a diode) is connected between the secondary winding of the transformer and the capacitor C aux Additionally or alternatively, a capacitor C aux For example, when a flyback converter 214a is used, the transformer of the flyback converter 214a may include another auxiliary winding, wherein an additional rectifying circuit (for example, implemented by a diode) is connected between the auxiliary winding of the transformer and the capacitor C aux between.

[0098] In various embodiments, the supply voltage of the control circuit 2112a and the optional control circuit 2144a may therefore correspond to the voltage V aux , or it can be based on the voltage V aux For example, an additional voltage regulator (eg, a linear regulator) may be used to generate the supply voltage for the control circuit 2112a and the optional control circuit 2144a. Typically, such an additional voltage regulator is included in an integrated circuit including the corresponding control circuit.

[0099] For generating a supply voltage V for a control circuit 2112a of the PFC converter 210a and optionally also for a control circuit 2144a of the electronic converter 214a aux This technical solution is known in the art.

[0100] Figure 6 An embodiment of a power supply 20b according to the present disclosure is shown. Specifically, the power supply 20b further includes:

[0101] Two input terminals 200a and 200b are configured to receive an AC input voltage V in,AC ;

[0102] The rectifier circuit 206 and the optional filter circuit 204 are configured to generate a rectified input voltage V in,DC ;

[0103] The PFC electronic converter 210a is configured to receive a DC voltage V in,DC and generates a regulated DC voltage V bus ,as well as

[0104] Another DC / DC electronic converter 214a is configured to receive a voltage V bus and generates a regulated output voltage V at two output terminals 202a and 202b out or the regulated output current i out .

[0105] For a general description of these circuits, refer to Figures 1 to 3 and Figure 5 In the embodiment considered, the power supply 20b is again configured to generate an auxiliary DC voltage V in the range, for example, between 1.5 and 10 V. aux As about Figure 5 As described, such a DC voltage V aux For example, the rectified input voltage V in_DC , bus voltage V bus and / or output voltage V out Additionally, the voltage V aux The voltage may be generated by the PFC electronic converter 210a and / or the electronic converter 214a. For example, in various embodiments, the voltage is generated via the capacitor C aux Provided that the capacitor is charged via the pre-charging circuit 216 and (at least) via the electronic converter 214a. Optionally, a voltage limiting circuit, such as a Zener diode Dz, is configured to limit the capacitor C aux The voltage at .

[0106] In various embodiments, the control circuit 2144a of the electronic converter 214a may be directly supplied with the voltage V aux Or from the auxiliary voltage V aux For example, in various embodiments, the control circuit 2144a (the integrated circuit) may include a receiving voltage V aux Additional internal voltage regulator.

[0107] In contrast, the supply voltage V of the control circuit 2112a of the PFC converter 210a isPFC The power control circuit 40 controls the voltage V aux , bus voltage V bus and a control signal PE is generated, the control signal PE indicating the output power P supplied by the power supply 20b out In various embodiments, the control circuit 2112a (the integrated circuit) may include a receiving voltage V PFC Additional internal voltage regulator.

[0108] As mentioned previously, the circuit 40 also receives a control signal PE indicating whether the output power supplied by the power supply 20b (i.e., the power supplied via the terminals 2002a and 2002b) is above or below a given threshold. For example, in various embodiments, the control circuit 40 may receive a control signal PE1 indicating whether the power P supplied via the terminals 202a and 202b is above or below a given threshold. out For example, in the embodiment considered, the signal PE1 is provided by the output power estimation circuit 42, which is configured to monitor the voltage V at the terminals 202a and 202b, for example. out and the output current i provided via terminals 202a and 202b out Thus, in various embodiments, circuit 42 may determine a signal indicative of (and preferably proportional to) the output power by converting the estimated output power P out The signal PE1 is generated by comparing with the output power threshold.

[0109] In addition to explicitly monitoring the output power P out In addition, the power estimation circuit 42 may also be configured to monitor the voltage V at the terminals 212a and 212b, for example. bus and the corresponding current provided to the electronic converter 214a to monitor the indicated output power P out , for example, other power levels of the power provided to the electronic converter 214a. Thus, in various embodiments, the circuit 42 may generate the signal PE1 by comparing the estimated power provided to the converter 214a with a power threshold.

[0110] In addition to providing additional power estimation circuitry 42, power supply 20b may also reuse existing signals. Figure 3 In the electronic converter 214 shown in FIG. 1 , the error signal V of the electronic converter 214a is COMP2 The requested output power may have been indicated in order to obtain the requested output voltage V out (in the case of a regulated voltage generator) or the requested output current i out(In the case of a regulated current generator). Therefore, in this case, the control circuit 2144a or another circuit can be controlled by converting the error signal V COMP2 The signal PE2 is generated by comparing with the threshold.

[0111] Furthermore, in the case of a regulated voltage generator, the output voltage V out Corresponding to the requested value. Therefore, in various embodiments, the power supply 20b, such as the control circuit 2144a or the power estimation circuit 42, is configured to monitor the output current i out And by measuring the output current i out The signal PE is generated by comparing it with the current threshold. Similarly, in the case of a regulated current generator, the output current i out Corresponding to the requested value. Therefore, in various embodiments, the power supply 20b, such as the control circuit 2144a or the power estimation circuit 42, is configured to monitor the output voltage V out And by measuring the output voltage V out The signal PE is generated by comparing with the voltage threshold.

[0112] Therefore, in various embodiments, the power supply circuit 20, for example, the control circuit 2144a or the power estimation circuit 42 is configured to monitor the power P provided by the power supply circuit 20b. out , such as output power or power provided to converter 214a, and generates a control signal PE indicating whether the one or more signals indicate the power P provided by power circuit 20b. out Above or below the power threshold, that is, when the power P provided by the power supply circuit 20b out When the power P provided by the power supply circuit 20b is higher than the power threshold, the signal PE is set to the first logic level. out Below the power threshold, the signal PE is set to a second logic level. For example, in various embodiments, the signal PE may be generated by the control circuit 2144a of the electronic converter 214a and may correspond to the external burst mode signal EXT_BM described in document US Pat. No. 6,222,746 B1. Alternatively, a separate output power estimation circuit 42 may be provided.

[0113] For example, Figure 7An embodiment of an electronic converter 214a based on a flyback converter is shown. The flyback converter includes a transformer T, which includes a primary winding T1 and a secondary winding T2. Specifically, a first terminal of the primary winding T1 is (e.g. directly) connected to a (positive) input terminal 212a, and a second terminal of the primary winding T1 is (e.g. directly) connected to a (negative) input terminal 212b via (a current path of) an electronic switch SW, which (negative) input terminal typically represents ground. Therefore, the electronic switch SW is configured to selectively connect the primary winding to the input terminals 212a and 212b, i.e., the bus voltage V bus For example, in the embodiment considered, the electronic switch SW is implemented using an n-channel field effect transistor (FET), such as an n-channel metal oxide semiconductor field effect transistor (MOSFET), i.e. NMOS. In this case, the drain terminal of the transistor SW is connected to the second terminal of the primary winding T1, which represents the switching node SN of the flyback converter, and the source terminal of the transistor SW is connected to the terminal 212b.

[0114] In addition, in the embodiment considered, the diode D and the secondary winding T2 are (e.g., directly) connected in series between the output terminals 202a and 202b. For example, the first terminal of the secondary winding T2 can be connected to the (positive) output terminal 202a via the diode D (e.g., directly), and the second terminal of the secondary winding T2 can be (e.g., directly) connected to the (negative) output terminal 202b. Typically, in addition to the diode D or as an alternative to the diode D, an electronic switch can be used. Therefore, the diode (and / or the electronic switch) D is configured to selectively connect the secondary winding T2 to the output terminals 202a and 202b. In addition, the capacitor C is typically (e.g., directly) connected between the terminals 202a and 202b.

[0115] As is known, the conventional flyback converter 214a is operated via a control circuit 2144a, which is basically configured to drive the electronic switch SW with a corresponding drive signal DRV2 so as to convert the output voltage V provided via the terminals 202a and 202b to out Or output current i out To a given reference value. For example, for this purpose, the control circuit 2144a is configured to use a corresponding duration T ON and T OFF The two switching states of periodically drive the switch SW. In the interval T ON During this period, when switch SW is closed and diode / switch D is open, the primary winding T1 of transformer T1 is connected (directly) to the input voltage V in Therefore, the primary current I in transformer T priand magnetic flux increases, thereby storing energy in the transformer T. In this case, the capacitor C supplies energy to the output terminals 202a and 202b (i.e., the load 30). On the contrary, in the interval T OFF During this period, when switch SW is open and diode / switch D is closed, the primary current I pri drops to zero, and the secondary side current I sec Starts to flow in the secondary winding, and energy from the transformer core T recharges the capacitor C and supplies the load 30 .

[0116] In various embodiments, the flyback converter 214a further comprises a snubber circuit / clamp circuit 2152. For example, in the embodiment under consideration, the clamp circuit 2152 is connected in parallel with the primary winding T1 of the transformer T and comprises a series connection of a clamp capacitor CS and a diode DS, i.e., the clamp capacitor CS and the diode DS are connected in series between the terminals of the primary winding T1. Typically, an electronic switch may be used in addition to or as an alternative to the diode DS. Typically, the resistor RS is connected in parallel with the capacitor CS (e.g., directly). Thus, the diode / switch DS is configured to selectively connect the capacitor CS (and optionally the resistor RS) in parallel with the primary winding T1. In essence, the addition of the capacitor CS and the diode / switch DS allows the leakage inductance L to be reduced. S The energy in the primary winding T1 is transferred to the clamping capacitor CS. Specifically, when the control circuit 210 turns off the electronic switch SW, the switch node SN (between the primary winding T1 and the drain terminal of the electronic switch SW, e.g., the transistor SW) rises as in a normal flyback converter (without clamping). In any case, when the voltage at the switch node SN bypasses the voltage at the clamping capacitor CS, the diode / switch DS is turned on, and the primary current I pri also flows to capacitor CS until the primary current I pri When the switch DS is used, the energy stored on the capacitor CS can be returned to the system by turning on the electronic switch DS. Alternatively, the capacitor CS can be discharged via the resistor RS.

[0117] As mentioned before, the control circuit 2144a is configured to generate a drive signal DRV2 for an electronic switch SW connected in series with the primary winding T1 between the terminals 212a and 212b, wherein the intermediate node between the primary winding T1 and the electronic switch SW represents the switch node SN, wherein a capacitance CSN is associated with the switch node SN, which capacitance is schematically shown via a capacitance connected between the switch node SN and the terminal 212b (ground). Typically, the capacitance CSN includes a parasitic capacitance CSW of the electronic switch SW, possible other parasitic capacitances (e.g., of a trace of a corresponding printed circuit board), and optionally one or more capacitors connected to the switch node SN.

[0118] In the embodiment considered, the control circuit 2144a has associated therewith the following circuits:

[0119] Feedback circuit 2142 is configured to provide an indication of the output quantity to be regulated (e.g., output voltage V out ) of the feedback signal FB2; and

[0120] The current measurement circuit 2154 is configured to generate a signal CS indicating (at least) the current during the on period T ON The current I flowing through the primary winding T1 during pri (e.g. proportional thereto).

[0121] For example, in Figure 7 In the embodiment, the current measurement circuit 2154 is implemented using a current sensor, such as a resistor RCS, which is connected in series with the switch SW, for example, connected between the source terminal of the corresponding n-channel FET SW and the terminal 212b (ground), wherein the voltage at the resistor RCS (corresponding to the signal CS) is proportional to the current flowing through the switch SW.

[0122] Therefore, in various embodiments, the control circuit 2144a is configured to generate the drive signal DRV2 according to the signals CS and FB2. Specifically, when using peak current control with a constant switching frequency, the control circuit 2144a can:

[0123] When the signal CS reaches a given reference value, the electronic switch SW is turned off, for example, the signal DRV2 is set to low, wherein the reference value is determined according to the feedback signal FB2; and

[0124] In a fixed switching period T SW The electronic switch SW is then turned off.

[0125] In various embodiments, the feedback circuit 2142 or the control circuit 2144a may thus implement a regulator having at least one integral (I) component, thereby increasing / decreasing a reference value for comparison with the signal CS until the output quantity (V out or I out ) corresponds to a given request value.

[0126] In various embodiments, the control circuit further includes a circuit configured to generate a voltage V at the switch node SN indicating SN The valley monitoring circuit 2156 of the valley signal ZCD in the off period T is configured to generate a signal indicating that the transformer T is (at least) in the off period T. OFFsignals of magnetization and demagnetization during the period. For example, in the embodiment considered, the valley / demagnetization monitoring circuit 2156 is implemented using an auxiliary winding of the transformer T. In the embodiment considered, the demagnetization monitoring circuit 2156 also includes an optional voltage divider, which is implemented for example using two resistors R5 and R6 connected in series (for example directly) between the terminals of the auxiliary winding Taux, wherein preferably one of the terminals of the auxiliary winding Taux is connected to the terminal 212b (ground). Therefore, in the embodiment considered, the voltage at the resistor R6 (corresponding to the signal ZCD) is proportional to the voltage at the terminals of the auxiliary winding Taux. Specifically:

[0127] When the switch SW is closed and the diode / switch D is open, i.e., during the on-time T ON During this period, the voltage at the auxiliary winding Taux is proportional to the input voltage V in proportional;

[0128] When the switch SW is open and the diode / switch D is closed, that is, during the off period T OFF When the current I sec During the first part of the period when the output capacitor C is charged, the voltage at the auxiliary winding Taux is proportional to the output voltage V out proportional; and

[0129] When the switch SW is turned off and the diode / switch D is turned off, that is, during the off period T OFF When the current I sec During the second part when T is zero (whereby the inductance of the transformer T oscillates together with the capacitance at the primary side), the voltage at the auxiliary winding Taux is proportional to the magnetization of the transformer T.

[0130] Therefore, when valley switching or quasi-resonant (QR) switching is used, the control circuit 2112a may be configured as:

[0131] When the signal CS reaches a given reference value, the electronic switch SW is turned off, for example, the signal DRV2 is set to low, wherein the reference value is determined according to the feedback signal FB2; and

[0132] When the signal ZCD reaches zero or becomes negative, the electronic switch SW is closed, for example, the signal DRV2 is set high, which indicates that the voltage V SN Valley value in / demagnetization of transformer T.

[0133] Also in this case, the feedback circuit 2142 or the control circuit 2144a can implement a regulator having at least one integral (I) component, whereby the switch SW is priThe switching activity is related to the voltage V by turning on the switch SW. SN The synchronization of the valley value / transformer demagnetization is achieved, for example, by detecting the negative edge of the voltage across the auxiliary winding Taux of the transformer T, which is connected to a terminal of the control circuit 2144a, which is usually called the zero current detection pin (ZCD pin). Such flyback converters are known in the art. For example, U.S. Patent No. US11,482,945B2 can be cited for this purpose, which is incorporated herein by reference.

[0134] according to Figure 5 In various embodiments, the auxiliary winding Taux can also be used to provide an auxiliary voltage V aux The capacitor C aux For example, Figure 7 In the circuit, the diode Daux is connected between the auxiliary winding Taux and the capacitor C aux In between, thereby basically realizing another output stage of the flyback converter.

[0135] As mentioned before, in the embodiment considered, the voltage at the auxiliary winding Taux indicates that during the off period T OFF During the first part of the period, the output voltage V out : Therefore, to generate the signal PE, the control circuit 1142a or a separate power estimation circuit 42 may monitor the voltage at the auxiliary winding Taux or the resistor R6.

[0136] For example, Figure 8 An embodiment of an output voltage estimation circuit 420 is shown, which may be implemented in the control circuit 1142a or the circuit 42 and is configured to generate an output voltage V out Specifically, in the embodiment considered, the circuit 420 comprises: a terminal ZCD configured to receive a voltage at the auxiliary winding Taux or at the resistor R6, and an analog sample and hold circuit 424 configured to generate a signal V by storing a voltage received via the terminal ZCD in response to the signal SAMPLE. out As mentioned before, when the switch SW is open and the diode / switch D is closed, that is, during the off period T OFF When the current I sec During the first part of the period when the auxiliary winding T is positive and charging the output capacitor C, aux The voltage at the output voltage V outTherefore, the sampling signal SAMPLE can correspond to a trigger signal, which is proportional to the current I sec For example, in a converter operated in CCM, the signal SAMPLE may be asserted during the off period T OFF At the end, for example, just before the switch SW is turned on, the signal SAMPLE may be asserted. In contrast, in a converter operated in DCM or in QR, the signal SAMPLE may be asserted at the secondary current I sec The moment when becomes zero is established. For example, it can be determined by directly measuring the secondary current I sec To detect this moment, or as mentioned before, to detect this moment at the falling edge of the voltage across the ZCD pin.

[0137] In various embodiments, a voltage follower or amplifier 422 may be connected between terminal ZCD and sample and hold circuit 424. Furthermore, in various embodiments, circuit 42 includes an amplifier 426 configured to generate signal V1 by amplifying the signal at the output of sample and hold circuit 424.

[0138] In various embodiments, circuit 420 may also include an analog-to-digital converter (ADC). For example, circuit 422 may be replaced with an ADC, and analog-to-digital conversion may be triggered via signal SAMPLE. Thus, in this case, signal V1 is a digital sample indicating the output voltage.

[0139] Similarly, a circuit can be used to generate an output current indicating i out For example, the document "Feasibility Study on a Novel Robust Current-mode Method" by F. Cacciotto, C. Adragna, IEEE Applied Power Electronics Conference and Exposition–APEC, 2023, March 2023, which is incorporated herein by reference for this purpose, discloses a technical solution for generating a signal (V2) for estimating an output current based on a feedback signal FB2 of an electronic converter.

[0140] Therefore, if Fig. 9 As shown in out When the control circuit 1142a or the circuit 42 may include a circuit 428 configured to output the voltage V according to the indication (measurement or estimation) out The voltage V1 indicates (measures or estimates) the output current i out The voltage V2 and the threshold voltage V TH To generate the signal PE.

[0141] For example, in the embodiment under consideration, the (analog or digital) signals V1 and V2 are provided to a (analog or digital) multiplier 432, which generates a signal indicating the output power P out The signal at the output of the multiplier and the threshold signal V TH The signal at the output of the multiplier 430 is therefore provided to a (analog or digital) comparator 430, which is configured to generate a voltage when the signal at the output of the multiplier 430 is greater than a threshold voltage V TH When the signal PE is set to the first logic level, and when the signal at the output of the multiplier 430 is less than the threshold voltage V TH When the signal PE is set to the second logic level.

[0142] For example, in the embodiment considered, the threshold signal corresponds to a threshold voltage V TH , which threshold voltage is set via the setting resistor RDIS. For example, in the embodiment considered, the circuit 428 includes a current source 434, which is configured to apply a current to the node P-DIS. Therefore, by connecting the resistor RDIS to the node P-DIS, the current provided by the current source 434 produces a voltage drop proportional to the resistance of the resistor RDIS. Therefore, by using the voltage at the node P-DIS as the threshold voltage V TH , the resistor RDIS can be used to set the threshold voltage V TH In various embodiments, resistor RDIS is external to the integrated circuit including circuit 428, for example, node P-DIS may be a pad (of the die) or a pin (of the package die) of the integrated circuit including circuit 42 or control circuit 1142a.

[0143] The regulated output current i out or the regulated output voltage V out In the case of TH Directly with signal V1 (indicating output voltage V out ) or signal V2 (indicating output current i out ) for comparison.

[0144] As mentioned previously, signal PE is used by power control circuit 40. Typically, power control circuit 40 may be integrated in an IC of power estimation circuit 42 or control circuit 2144a. For example, in various embodiments, power estimation circuit 42 and power control circuit 40 are implemented in an integrated circuit of control circuit 2144a, such as a control circuit of a flyback converter.

[0145] Specifically, in various embodiments, in response to determining that the signal PE indicates the output power P outAbove the power threshold, i.e., under high load conditions, the power control circuit 40 is configured to increase the voltage V aux As the voltage V PFC is provided to the control circuit 2112a to turn on the control circuit 2112a. Conversely, in response to the determination signal PE indicating the output power P out Below the power threshold, that is, under light load conditions, the power control circuit 40 is configured to bus Selectively turn on and off the control circuit 2112a. Specifically, for this purpose, the power control circuit 40 is configured as follows:

[0146] In response to determining the bus voltage V bus (reach or) fall below the lower threshold by setting the voltage V aux As the voltage V PFC provided to the control circuit 2112a to turn on the control circuit 2112a; and

[0147] In response to determining the bus voltage V bus (reach or) exceed the upper threshold by setting the voltage V PFC With voltage V aux Open to shut down the control circuit 2112a.

[0148] For example, this is also Fig.10 Specifically, initially, the power supply 20b provides a high output power P out , whereby the comparator circuit 430 sets the signal PE to a first value (eg, low), which indicates that the output power P out Above the power threshold, the power threshold is Fig.10 Indicated as P out,TH Accordingly, since the signal PE has the first value, the power control circuit 40 thus increases the voltage V PFC Connect to voltage V aux The control circuit 2112a is supplied with a voltage V aux , where the control circuit 2112a sets the bus voltage V bus Adjust to the requested value, which is Fig.10 Indicated as V reg .

[0149] In the example considered, the output power is then gradually reduced, for example, whereby the output power drops to a power threshold value P at the instant t1. out,TH Therefore, in response to determining that the output power drops to the power threshold P out,TH Next, the comparator 430 sets the signal PE to a second value (eg, high), which indicates that the output power P out Below power threshold.

[0150] Specifically, in this operation mode, the power control circuit 40 is configured as follows:

[0151] In response to determining the bus voltage V bus Reach (or less than) Fig.10 The voltage V L The lower threshold, for example, by setting the voltage V PFC Connect to voltage V aux The control circuit 2112a is supplied with a voltage V aux ;and

[0152] In response to determining the bus voltage V bus Reach (or exceed) Fig.10 The voltage V H The upper threshold, for example, by setting the voltage V PFC Connect to ground or usually to the voltage V PFC With voltage V aux The voltage V is disconnected and not supplied to the control circuit 2112a. aux .

[0153] Therefore, even when the signal PE has the second value and the control circuit 2112a is turned on, the control circuit 2112a will attempt to increase the bus voltage V bus Adjust to the requested value V reg However, once the bus voltage V bus Reaching the upper threshold V H , then the power control circuit 40 turns off the power supply of the control circuit 2112a. Therefore, at this stage, the control circuit 2112a is turned off and the PFC converter 210a is disabled, thereby, the bus voltage V bus However, once the bus voltage V bus Reaching the lower threshold V L , then the power supply control circuit 40 turns on the power supply of the control circuit 2112a, thereby the PFC converter 210a is activated and increases the bus voltage V again. bus .

[0154] In the example considered, the output power then increases, for example gradually, whereby the output power exceeds the power threshold value P at the instant t2. out,TH Therefore, in response to determining that the output power exceeds the power threshold P out,TH , the comparator 430 sets the signal PE to a first value (eg, low), which indicates that the output power P out Therefore, in response to determining that the signal PE has a first value, the power control circuit 40 increases the voltage V PFC Connect to voltage V aux The control circuit 2112a is supplied with a voltage V aux, where the control circuit 2112a sets the bus voltage V bus Adjust to the requested value V reg .

[0155] Specifically, in various embodiments, the threshold V H Less than the requested voltage / regulated voltage V reg , and the threshold V L Less than the threshold V H For example, as mentioned previously, in various embodiments, the bus voltage V bus Request value / adjustment value V reg The upper threshold V is selected in the range between 300 and 500 V, preferably between 370 and 430 V, for example, selected to be (approximately) 400 V. In various embodiments, the upper threshold V H In the request value / adjustment value V reg is selected within a range between 40% and 70%, for example, is selected to be (approximately) 0.6V reg Finally, the lower threshold V L At the upper threshold V H For example, in various embodiments, the threshold V L In V reg A range between 45% and 55% is selected, and the upper threshold V H In V reg The exact value of the threshold (and the corresponding hysteresis) may depend on the specific design of the power converter and the operating conditions.

[0156] Therefore, the technical solution disclosed in the present disclosure also drives the PFC converter with a pulse sequence similar to the burst mode. However, when the burst mode is used, the corresponding threshold value will be selected between the request value / adjustment value V reg In contrast, the lower threshold is used in the technical solution disclosed in this article, which ensures that the bus voltage V bus , allowing the subsequent electronic converter 214a to still operate at high efficiency and being sufficient to also supply the electronic converter 214a during load transients from light load conditions to heavy load conditions. In addition, compared to the burst mode, the control circuit 2112a of the PFC converter is completely turned off without consuming any energy. In this regard, using the lower threshold under medium and light load conditions can reduce switching losses (which are typically voltage-dependent) and increase the efficiency of the converter.

[0157] Of course, without prejudice to the principle of the present disclosure, the details of construction and the embodiments may vary widely with respect to what is described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure as defined in the appended claims.

[0158] A power supply control circuit for a power supply, the power supply (20b) can be summarized as comprising: two input terminals (200a, 200b) configured to be connected to a main power supply to receive an AC input voltage (V in,AC ); two output terminals (202a, 202b) configured to be connected to a load (30); a rectifier circuit (206) configured to receive an AC input voltage (V in,AC ) generates the rectified input voltage (V in,DC ); a PFC (power factor correction) electronic converter (210a) configured to convert the rectified input voltage (V in,DC ) generates the bus voltage (V bus ); an electronic converter (214a) configured to output a voltage from the bus voltage (V bus ) generates a regulated output voltage (V out ) or the regulated output current (i out ); and auxiliary power supply (C aux ,Dz,216,D aux ), which is configured to generate an auxiliary supply voltage (V aux ); wherein the PFC electronic converter (210a) comprises a PFC control circuit (2112a), the PFC control circuit comprising a circuit for receiving a supply voltage (V PFC ) terminal, and wherein the PFC control circuit (2112a) is configured to, when the supply voltage (V PFC ) is supplied to drive the PFC electronic converter (210a) so as to adjust the bus voltage to the requested value (V reg ), wherein the power supply control circuit (40, 42) is configured to: generate an output power (P) provided via the two output terminals (202a, 202b) out ) signal; determine whether the signal indicates output power (P out ) is greater than the threshold value (P out,TH ); In response to determining that the signal indicates an output power (P out ) is greater than the threshold value (P out,TH ), supplies the auxiliary supply voltage (V aux ); and in response to determining that the signal indicates an output power (P out ) is less than the threshold value (P out,TH ): generates an indication of the bus voltage (V bus ) signal; determine whether the signal indicates the bus voltage (V bus) is greater than the upper threshold (V H ), and in response to determining that the signal indicates that the bus voltage (V bus ) is greater than the upper threshold (V H ), prohibiting the auxiliary supply voltage (V aux ), thereby shutting down the PFC control circuit (2112a); and determining whether the signal indicates that the bus voltage (V bus ) is less than the lower threshold (V L ), and in response to determining that the signal indicates that the bus voltage (V bus ) is less than the lower threshold (V L ), supplies the auxiliary supply voltage (V aux ).

[0159] The auxiliary power supply (C aux ,Dz,216,D aux ) can include a capacitor (C aux ) and a charging circuit (216) configured to charge the input voltage (V in,DC ) for the capacitor (C aux ) for charging.

[0160] The electronic converter (214a) may be a flyback converter comprising a transformer having an auxiliary winding (Taux), wherein the auxiliary winding (Taux) is connected to the flyback converter via a diode (D aux ) is connected to the capacitor (C aux ).

[0161] The PFC electronic converter (210a) may be a boost converter, the boost converter comprising: a circuit for receiving the rectified input voltage (V in,DC ) of the positive input terminal (208a) and the negative input terminal (208b); for providing the bus voltage (V bus ) of the positive output terminal (212a) and the negative output terminal (212b); an inductor (L1) connected between the positive input terminal (208a) and a switch node (SN); an electronic switch (SW1) connected between the switch node (SN) and the negative terminal (208b); another diode or another electronic switch (SW2) connected between the switch node (SN) and the positive output terminal (212a); a feedback circuit (2110) configured to generate a voltage that is proportional to the bus voltage V bus proportional feedback signal (FB1), wherein the PFC control circuit (2112a) is configured to, when the supply voltage (V PFC) is supplied to drive the electronic switch (SW1) and the optional further electronic switch (SW2) so as to adjust the feedback signal (FB1) to a reference value (REF1).

[0162] Generates an output power (P) provided via the two output terminals (202a, 202b) out ) may include: estimating (420) and the output voltage (V out ) is proportional to the signal (V1) and the output current (i out ) is proportional to the output voltage (V out ) is proportional to the signal (V1) and the output current (i out ) is multiplied (432) by a signal (V2) proportional to the output power to generate an output power indicator (P out ) signal; or estimate the bus voltage (V bus ) and a signal proportional to the current supplied to the electronic converter (214a), and by converting the output voltage (V out ) is proportional to the signal (V1) and the output current (i out ) is multiplied (432) by a signal (V2) proportional to the output power to generate an output power indicator (P out ) signal.

[0163] The electronic converter (214a) may be configured to generate a regulated output voltage (V out ) and indicates the output power (P out ) and the output current (i ) provided through the two output terminals (202a, 202b) out ) is proportional; or the electronic converter (214a) can be configured to generate a regulated output current (i out ) and indicates the output power (P out ) and the output voltage (V out ) are proportional.

[0164] The power supply control circuit (40, 42) may include a circuit that controls the auxiliary winding (T aux ) is sampled (424) to estimate the output voltage (V out ).

[0165] The power control circuit (40, 42) may include a terminal configured to be connected to a setting resistor (RDIS), wherein the threshold value (P out,TH ) is defined by the resistance value of the setting resistor (RDIS).

[0166] The lower threshold (V L ) can be in the requested value (V reg ) is selected within the range of 45% to 55%, and the upper threshold (V H ) can be in the requested value (V reg ) is selected in the range of 55% to 65%.

[0167] The electronic converter (214a) may include a control circuit (2142a), wherein the control circuit (2142a) and the power supply control circuit (40, 42) are integrated into the same integrated circuit.

[0168] The power supply (20a) can be summarized as comprising: two input terminals (200a, 200b) configured to be connected to a main power source to receive an AC input voltage (V in,AC ); two output terminals (202a, 202b) configured to be connected to a load (30); a rectifier circuit (206) configured to receive an AC input voltage (V in,AC ) generates a rectified input voltage (V in,DC ); a PFC (power factor correction) electronic converter (214a) configured to convert the rectified input voltage (V in,DC ) generates a bus voltage (V bus ); an electronic converter (214a) configured to output voltage from the bus voltage (V bus ) produces a regulated output voltage (V out ) or the regulated output current (i out ); Auxiliary power supply (C aux ,Dz,216,D aux ), which is configured to generate an auxiliary supply voltage (V aux ); and a power supply control circuit (40, 42) according to any one of the preceding claims.

[0169] A method of operating a power supply (20a) can be summarized as comprising: generating an output power (P) indicative of an output power (P) provided via the two output terminals (202a, 202b) out ) signal; determine whether the signal indicates output power (P out ) is greater than the threshold (P out,TH ); In response to determining that the signal indicates an output power (P out ) is greater than the threshold (P out,TH ), supplies the auxiliary supply voltage (V aux); and in response to determining that the signal indicates an output power (P out ) is less than the threshold value (P out,TH ): Generates an indication of the bus voltage (V bus ) signal; determine whether the signal indicates the bus voltage (V bus ) is greater than the upper threshold (V H ), and in response to determining that the signal indicates that the bus voltage (V bus ) is greater than the upper threshold (V H ), prohibiting the auxiliary supply voltage (V aux ), thereby shutting down the PFC control circuit (2112a); and determining whether the signal indicates that the bus voltage (V bus ) is less than the lower threshold (V L ), and in response to determining that the signal indicates that the bus voltage (V bus ) is less than the lower threshold (V L ), supplies the auxiliary supply voltage (V aux ).

[0170] The various embodiments described above can be combined to provide additional embodiments. In view of the above detailed description, these and other changes can be made to the embodiments. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents enjoyed by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A power control circuit for a power supply device, the power supply device comprising: two input terminals configured to be coupled to a main power source to receive an AC input voltage; two output terminals configured to be coupled to a load; a rectifier circuit configured to generate a rectified input voltage from the AC input voltage; a power factor correction (PFC) electronic converter configured to generate a bus voltage from the rectified input voltage; an electronic converter configured to generate a regulated output voltage or a regulated output current from the bus voltage at the two output terminals; as well as an auxiliary power supply configured to generate an auxiliary supply voltage; wherein the PFC electronic converter comprises a PFC control circuit, the PFC control circuit comprising a terminal for receiving a supply voltage, and wherein the PFC control circuit is configured to: drive the PFC electronic converter when supplied with the supply voltage so as to regulate the bus voltage to a requested value, The power control circuit is configured as follows: generating a signal indicative of output power provided via the two output terminals; determining whether the signal indicates that the output power is greater than a threshold; In response to determining that the signal indicates that the output power is greater than the threshold, supplying the auxiliary supply voltage to the PFC control circuit; and In response to determining that the signal indicates that the output power is less than the threshold: generating a signal indicative of the bus voltage; determining whether the signal indicates that the bus voltage is greater than an upper threshold, and in response to determining that the signal indicates that the bus voltage is greater than the upper threshold, disabling supply of the auxiliary supply voltage to the PFC control circuit, whereby the PFC control circuit is shut down; and A determination is made as to whether the signal indicates that the bus voltage is less than a lower threshold, and in response to determining that the signal indicates that the bus voltage is less than the lower threshold, the auxiliary supply voltage is supplied to the PFC control circuit. 2 . The power supply control circuit of claim 1 , wherein the auxiliary power supply comprises a capacitor and a charging circuit configured to charge the capacitor via the rectified input voltage.

3. The power supply control circuit of claim 2, wherein the electronic converter is a flyback converter comprising a transformer having an auxiliary winding, wherein the auxiliary winding is coupled to the capacitor via a first diode.

4. The power supply control circuit according to claim 1, wherein the PFC electronic converter is a boost converter, the boost converter comprising: a positive input terminal and a negative input terminal for receiving the rectified input voltage; A positive output terminal and a negative output terminal, for providing the bus voltage; an inductor coupled between the positive input terminal and a switch node; a first electronic switch coupled between the switch node and the negative input terminal; a second diode or a second electronic switch coupled between the switch node and the positive output terminal; as well as a feedback circuit configured to generate a feedback signal proportional to the bus voltage, The PFC control circuit is configured to, when powered via the supply voltage, drive the first electronic switch so as to regulate the feedback signal to a reference value. 5 . The power supply control circuit of claim 4 , wherein the PFC control circuit is configured to, when powered via the supply voltage, drive the second electronic switch so as to regulate the feedback signal to the reference value.

6. The power supply control circuit of claim 1 , wherein generating a signal indicative of the output power provided via the two output terminals comprises: estimating a signal proportional to the output voltage and a signal proportional to the output current, and generating a signal indicative of the output power by multiplying the signal proportional to the output voltage and the signal proportional to the output current; or A signal proportional to the bus voltage and a signal proportional to the current provided to the electronic converter are estimated, and a signal indicative of the output power is generated by multiplying the signal proportional to the output voltage and the signal proportional to the output current.

7. The power control circuit according to claim 1, wherein: The electronic converter is configured to generate the output voltage, and the signal indicative of the output power is proportional to the output current provided via the two output terminals; or The electronic converter is configured to produce the regulated output current, and the signal indicative of the output power is proportional to the output voltage at the two output terminals. 8 . The power supply control circuit of claim 3 , wherein the power supply control circuit is configured to estimate the output voltage by sampling a voltage at the auxiliary winding during an off period of the flyback converter.

9. The power control circuit of claim 1, wherein the power control circuit comprises a terminal configured to be coupled to a setting resistor, wherein the threshold value is defined via a resistance value of the setting resistor.

10. The power control circuit of claim 1, wherein the lower threshold is selected within a range between 45% and 55% of the requested value, and the upper threshold is selected within a range between 55% and 65% of the requested value.

11. The power control circuit of claim 1, wherein the electronic converter comprises a control circuit, wherein the control circuit and the power control circuit are integrated into a same integrated circuit.

12. A power supply device, comprising: two input terminals configured to be coupled to a main power source to receive an AC input voltage; two output terminals configured to be coupled to a load; a rectifier circuit configured to generate a rectified input voltage from the AC input voltage; a power factor correction (PFC) electronic converter configured to generate a bus voltage from the rectified input voltage; an electronic converter configured to generate a regulated output voltage or a regulated output current from the bus voltage at the two output terminals; an auxiliary power supply configured to generate an auxiliary supply voltage; as well as The power control circuit is configured as follows: generating a signal indicative of output power provided via the two output terminals; determining whether the signal indicates that the output power is greater than a threshold; In response to determining that the signal indicates that the output power is greater than the threshold, supplying the auxiliary supply voltage to a PFC control circuit; as well as In response to determining that the signal indicates that the output power is less than the threshold: generating a signal indicative of the bus voltage; determining whether the signal indicates that the bus voltage is greater than an upper threshold, and in response to determining that the signal indicates that the bus voltage is greater than the upper threshold, disabling supply of the auxiliary supply voltage to the PFC control circuit, thereby shutting down the PFC control circuit; and A determination is made as to whether the signal indicates that the bus voltage is less than a lower threshold, and in response to determining that the signal indicates that the bus voltage is less than the lower threshold, the auxiliary supply voltage is supplied to the PFC control circuit. 13 . The power supply device of claim 12 , wherein the auxiliary power supply comprises a capacitor and a charging circuit configured to charge the capacitor via the rectified input voltage.

14. The power supply device of claim 13, wherein the electronic converter is a flyback converter comprising a transformer having an auxiliary winding, wherein the auxiliary winding is coupled to the capacitor via a first diode. 15 . The power supply device of claim 12 , wherein the PFC control circuit is configured to drive the second electronic switch when powered via the supply voltage so as to regulate a feedback signal to a reference value.

16. The power supply device of claim 12, wherein generating a signal indicative of the output power provided via the two output terminals comprises: estimating a signal proportional to the output voltage and a signal proportional to the output current, and generating a signal indicative of the output power by multiplying the signal proportional to the output voltage and the signal proportional to the output current; or A signal proportional to the bus voltage and a signal proportional to the current provided to the electronic converter are estimated, and a signal indicative of the output power is generated by multiplying the signal proportional to the output voltage and the signal proportional to the output current.

17. The power supply device according to claim 12, wherein: the electronic converter being configured to produce the regulated output voltage, and the signal indicative of the output power being proportional to the output current provided via the two output terminals; or The electronic converter is configured to produce the regulated output current, and the signal indicative of the output power is proportional to the output voltage at the two output terminals.

18. A method of operating a power supply, comprising: generating a signal indicative of output power provided via two output terminals; determining whether the signal indicates that the output power is greater than a threshold; In response to determining that the signal indicates that the output power is greater than a threshold, supplying an auxiliary supply voltage to a power factor correction (PFC) control circuit; and In response to determining that the signal indicates that the output power is less than a threshold: generating a signal indicative of a bus voltage; determining whether the signal indicates that the bus voltage is greater than an upper threshold, and in response to determining that the signal indicates that the bus voltage is greater than the upper threshold, disabling supply of the auxiliary supply voltage to the PFC control circuit, whereby the PFC control circuit is shut down; and A determination is made as to whether the signal indicates that the bus voltage is less than a lower threshold, and in response to determining that the signal indicates that the bus voltage is less than the lower threshold, the auxiliary supply voltage is supplied to the PFC control circuit.

19. The method of claim 18, wherein generating a signal indicative of the output power provided via the two output terminals comprises: estimating a signal proportional to an output voltage and a signal proportional to an output current, and generating a signal indicative of the output power by multiplying the signal proportional to the output voltage and the signal proportional to the output current; or A signal proportional to the bus voltage and a signal proportional to the current provided to the electronic converter are estimated, and a signal indicative of the output power is generated by multiplying the signal proportional to the output voltage and the signal proportional to the output current.

20. The method according to claim 18, comprising: The output voltage is estimated by sampling a voltage at an auxiliary winding of the converter during an off period of the converter.

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