A fast dynamic response system and method for a DCDC converter

Abstract

The invention discloses a fast dynamic response system and method of a DCDC converter, relates to the technical field of DCDC converters, and solves the technical problem that the detection of load changes in the prior art usually relies on the change of output voltage, while ignoring the limitation of the physical characteristics of capacitor voltage changes, resulting in delayed detection results. The invention jointly judges the load condition of a DCDC topology through an output capacitor current detection circuit and an overshoot or undershoot detection circuit. If the output voltage generated by the DCDC topology exceeds or is lower than the upper threshold voltage or the lower threshold voltage of the overshoot or undershoot detection circuit, the output voltage compensation circuit is turned on to discharge or charge the output capacitor. The reference voltage selection circuit selects a low voltage reference or a high voltage reference, and the GM adjustable error amplifier selects a high bandwidth. The control logic circuit adjusts the duty cycle of the DCDC topology. Timely detection and response to load mutations are achieved, and the power supply stability of the system is effectively improved.

Description

Technical Field

[0001] The invention belongs to the field of DCDC converters, and in particular relates to a fast dynamic response system and method of a DCDC converter. Background Art

[0002] In modern power management modules, DCDC converters have become an indispensable core component due to their excellent large driving capabilities and high energy efficiency. As microcontrollers (MCUs) and other chips are widely used in various smart devices, these devices have increasing requirements for power supply systems, especially the demand for large driving currents. Therefore, to provide stable current for key components such as MCUs, DCDC converters are usually relied on to achieve efficient and reliable power supply.

[0003] A large number of digital modules are integrated inside the MCU, which can cause large mutations in the power supply load current when turned on or off. In the traditional DCDC converter design, when the load current switches from light load to heavy load, it usually causes obvious voltage undershoot; and when the load switches from heavy load to light load, there will often be significant voltage overshoot. Such fluctuations are not only not conducive to the normal operation of the digital module, but may also cause system failures in extreme cases, affecting the reliability of the overall circuit. Therefore, in the design of the DCDC converter, fast response to reduce voltage fluctuations caused by load current changes has become a key technical requirement to ensure power supply stability and system reliability.

[0004] The existing control methods of DCDC converters mainly rely on PWM (Pulse Width Modulation) and PFM (Pulse Frequency Modulation) modes to adjust the output voltage by changing the duty cycle. However, the adjustment of the duty cycle is limited by the loop bandwidth and response speed. Especially when the load current changes drastically, a single adjustment method is difficult to meet the needs of fast response.

[0005] Also, in traditional DCDC converters, the detection of load changes usually relies on changes in the output voltage. A sudden change in the load current will cause a change in the charge and discharge rate of the output capacitor, causing the voltage across the capacitor to increase or decrease. The control loop adjusts the duty cycle according to the change in the capacitor voltage to compensate for the deviation in the output voltage. However, since the change in capacitor voltage is limited by its own physical properties (i.e., the capacitor voltage cannot change suddenly), this detection method has obvious hysteresis.

[0006] Therefore, the present invention provides a fast dynamic response system and method for a DCDC converter. Summary of the invention

[0007] The present invention aims to solve at least one of the technical problems existing in the prior art; to this end, the present invention proposes a fast dynamic response system and method for a DCDC converter, which is used to solve the technical problem that the prior art usually relies on the change of the output voltage for the detection of load changes, but ignores the fact that the change of the capacitor voltage is limited by its own physical characteristics, resulting in a delayed detection result.

[0008] To achieve the above-mentioned object, a first aspect of the present invention provides a fast dynamic response system of a DCDC converter, comprising a DCDC topology, an output capacitor current detection circuit, an overshoot or undershoot detection circuit, an output voltage compensation circuit, a reference voltage selection circuit, a GM adjustable error amplifier, a control logic circuit and a zero-crossing detection circuit;

[0009] The control logic circuit is used to control the DCDC topology to constantly generate an output voltage VOUT;

[0010] The output capacitor current detection circuit is used to detect the change in the output current, analyze the output voltage, and detect the overshoot or undershoot of the output voltage through the overshoot or undershoot detection circuit;

[0011] The output voltage compensation circuit is used to discharge or charge the output capacitor;

[0012] The reference voltage selection circuit is used to adjust the reference voltage;

[0013] The GM adjustable error amplifier is used to change the bandwidth of the error amplifier.

[0014] Preferably, the DCDC topology is connected to an output capacitor current detection circuit; the output capacitor current detection circuit is connected to an overshoot or undershoot detection circuit; the overshoot or undershoot detection circuit is connected to an output voltage compensation circuit, a reference voltage adjustment circuit and a negative end of a GM adjustable error amplifier in sequence; the reference voltage adjustment circuit is connected to the negative end of the GM adjustable error amplifier; the positive end of the GM adjustable error amplifier is connected to a bias voltage, and its output end is connected to a control logic circuit.

[0015] Preferably, the overshoot or undershoot detection circuit is composed of two hysteresis comparators, the positive ends of the hysteresis comparators are respectively connected to two reference voltages, and the negative ends are connected to the output end of the output capacitor current detection circuit; wherein the hysteresis comparator includes a first hysteresis comparator and a second hysteresis comparator.

[0016] Preferably, the overshoot or undershoot detection circuit detects the overshoot or undershoot of the output voltage, including:

[0017] When it is detected that the output voltage undershoots and is lower than the lower threshold voltage VL, the first hysteresis comparator is connected to the gate of the current mirror switch tube TG1, the reference voltage adjustment circuit selects a high voltage reference, and the GM adjustable error amplifier selects a high bandwidth;

[0018] When it is detected that the output voltage rises and is higher than the upper threshold voltage VH, the second hysteresis comparator is connected to the gate of the current mirror switch tube TG2, the reference voltage adjustment circuit selects a low voltage reference, and the GM adjustable error amplifier selects a high bandwidth.

[0019] Preferably, the output voltage compensation circuit includes a bias current mirror, a current mirror switch tube TG1, and a current mirror switch tube TG2; the bias current mirror is connected to the output capacitor through TG1 and TG2.

[0020] Preferably, the lower threshold voltage VL is a minimum threshold voltage, and the upper threshold voltage VH is a maximum threshold voltage.

[0021] Preferably, the source of the current mirror switch tube TG1 is connected to the supply voltage, and the source of the current mirror switch tube TG2 is grounded.

[0022] Preferably, the positive input terminal of the GM adjustable error amplifier is connected to the reference voltage VREF, the reverse input terminal is connected to the output feedback voltage VFB, the input pair tube adopts source negative feedback mode, and the feedback resistance is adjustable to adjust the gm of the error amplifier.

[0023] Preferably, the zero-crossing detection circuit is used to detect reverse flow of the inductor current.

[0024] Preferably, the second aspect of the present invention provides a fast dynamic response method of a DCDC converter, comprising the following steps:

[0025] Step 1: Determine the load condition of the DCDC topology through the output capacitor current detection circuit and the overshoot or undershoot detection circuit;

[0026] Step 2: When the output voltage VOUT generated by the DCDC topology exceeds the upper threshold voltage VH or the lower threshold voltage VL of the overshoot or undershoot detection circuit, the output voltage compensation circuit is turned on to discharge the output capacitor; when the output voltage VOUT generated by the DCDC topology is lower than the upper threshold voltage VH or the lower threshold voltage VL of the overshoot or undershoot detection circuit, the output voltage compensation circuit is turned on to charge the output capacitor;

[0027] Step 3: The reference voltage selection circuit selects a low voltage reference or a high voltage reference, and the GM adjustable error amplifier selects a high bandwidth;

[0028] Step 4: The control logic circuit adjusts the duty cycle of the DCDC topology.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] The output capacitor charge sampling circuit of the present invention adopts a simple and efficient charge detection module, directly samples the change amount of the capacitor charge to judge the load mutation, and uses the characteristic of faster charge change speed to make the detection and feedback proceed in advance, which greatly shortens the response time of the system, enables the converter to quickly adjust when the load mutation occurs, and maintains the stability of the output voltage; significantly reduces the voltage fluctuation amplitude caused by the detection lag, and improves the power supply stability of the system; in order to enhance the response capability to the load mutation, the present invention also introduces an additional current source for directly charging and discharging the output capacitor. When the load current changes, this current source can quickly inject or release charge to quickly adjust the output voltage, greatly accelerating the recovery speed of the output voltage; in addition to the fast charge detection and compensation mechanism, the present invention also optimizes the design of the control loop, which optimizes the change rate of the duty cycle by dynamically adjusting the reference voltage and the bandwidth of the error amplifier. This strategy enables the control system to flexibly adapt to different load changes, ensuring that a stable output voltage can be provided under various conditions, and dynamically adjusting the bandwidth can also help maintain the stability of the system and avoid oscillation or other instability caused by overcompensation. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1 It is a framework diagram of a conventional current mode BUCK type DCDC converter of the present invention;

[0033] Figure 2 An overshoot fast response circuit diagram of a DCDC converter of the present invention;

[0034] In the figure: 1. DCDC topology; 2. Output capacitor current detection circuit; 3. Overshoot or undershoot detection circuit; 4. Output voltage compensation circuit; 5. Reference voltage selection circuit; 6. GM adjustable error amplifier; 7. Control logic circuit; 8. Zero-crossing detection circuit;

[0035] Figure 3 This is a waveform diagram of the output voltage of the conventional current mode BUCK type DCDC of the present invention when the load current suddenly changes from light load to heavy load;

[0036] Figure 4This is a waveform diagram of the output voltage of the conventional current mode BUCK type DCDC of the present invention when the load current suddenly changes from heavy load to light load;

[0037] Figure 5 This is a schematic diagram of a capacitor voltage detection circuit of the present invention;

[0038] Figure 6 This is a schematic diagram of the GM adjustable error amplifier circuit of the present invention;

[0039] Figure 7 This is a schematic diagram of an output voltage compensation circuit of the present invention;

[0040] Figure 8 This is a waveform diagram of the output voltage of the current mode BUCK type DCDC of the present invention when the load current suddenly changes from light load to heavy load;

[0041] Fig. 9 This is a waveform diagram of the output voltage of the current mode BUCK type DCDC of the present invention when the load current suddenly changes from heavy load to light load;

[0042] Fig.10 It is a schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0043] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] See also Figure 1 , a block diagram of a conventional current mode BUCK type DCDC converter. As can be seen from the block diagram, the conventional current mode DCDC structure is not specifically adjusted for rapid dynamic changes in the load. This design relies only on basic current feedback control to maintain the output voltage, but lacks further dynamic response optimization. Therefore, when the load current undergoes a large mutation, such as switching from light load to heavy load or heavy load to light load, the output voltage in the conventional architecture tends to fluctuate significantly.

[0045] In the absence of a compensation mechanism, the sudden change in load current causes the output voltage to recover more slowly, usually manifested as a large voltage undershoot or overshoot. This fluctuation not only affects the voltage regulation performance of the power supply, but may also affect the stability of the powered circuit, especially in applications that require fast dynamic response, such as processors or high-speed communication modules. Therefore, the traditional current mode BUCK type DCDC architecture has certain limitations in dealing with fast load changes, and needs to be further optimized to improve its dynamic response performance.

[0046] See also Figure 2 , the first aspect of the present invention provides a fast dynamic response system of a DCDC converter, including a DCDC topology 1, an output capacitor current detection circuit 2, an overshoot or undershoot detection circuit 3, an output voltage compensation circuit 4, a reference voltage selection circuit 5, a GM adjustable error amplifier 6, a control logic circuit 7 and a zero-crossing detection circuit 8;

[0047] The control logic circuit 7 is used to control the DCDC topology 1 to generate a constant output voltage VOUT;

[0048] The output capacitor current detection circuit 2 is used to detect the change in the output current, analyze the output voltage, and detect the overshoot or undershoot of the output voltage through the overshoot or undershoot detection circuit 3;

[0049] The output voltage compensation circuit 4 is used to discharge or charge the output capacitor;

[0050] The reference voltage selection circuit 5 is used to adjust the reference voltage;

[0051] The GM adjustable error amplifier 6 is used to change the bandwidth of the error amplifier;

[0052] The zero-crossing detection circuit 8 is used to detect the reverse flow of the inductor current.

[0053] The DCDC topology 1 is connected to the output capacitor current detection circuit 2; the output capacitor current detection circuit 2 is connected to the overshoot or undershoot detection circuit 3; the overshoot or undershoot detection circuit 3 is connected to the output voltage compensation circuit 4, the reference voltage adjustment circuit 5 and the negative end of the GM adjustable error amplifier 6 in sequence; the reference voltage adjustment circuit 5 is connected to the negative end of the GM adjustable error amplifier 6; the positive end of the GM adjustable error amplifier 6 is connected to the bias voltage, and its output end is connected to the control logic circuit 7.

[0054] The positive input terminal of the GM adjustable error amplifier 6 is connected to the reference voltage VREF, and the reverse input terminal is connected to the output feedback voltage VFB. The input pair tube adopts a source negative feedback mode, and the feedback resistance is adjustable to adjust the gm of the error amplifier.

[0055] The output voltage compensation circuit 4 includes a bias current mirror, a current mirror switch tube TG1, and a current mirror switch tube TG2; the bias current mirror is connected to the output capacitor through TG1 and TG2; the source of the current mirror switch tube TG1 is connected to the power supply voltage, and the source of the current mirror switch tube TG2 is grounded.

[0056] The overshoot or undershoot detection circuit 3 is composed of two hysteresis comparators, the positive ends of the hysteresis comparators are respectively connected to two reference voltages, and the negative ends are connected to the output end of the output capacitor current detection circuit 2; wherein the hysteresis comparators include a first hysteresis comparator and a second hysteresis comparator.

[0057] The load condition of DCDC topology 1 is determined by the output capacitor current detection circuit 2 and the overshoot or undershoot detection circuit 3. When it is determined that the output voltage has an overshoot or undershoot, the following two conditions are generated:

[0058] The first case: if the output voltage VOUT generated by the DCDC topology 1 exceeds the upper threshold voltage VH of the overshoot or undershoot detection circuit 3, the output voltage compensation circuit 4 is turned on to discharge the output capacitor, the reference voltage selection circuit 5 selects a low voltage reference, and the GM adjustable error amplifier 6 selects a high bandwidth to reduce the output voltage VC at a faster rate. This voltage will adjust the duty cycle of the DCDC topology 1 through the control logic circuit 7 to reduce the duty cycle. The voltage compensation circuit 4 causes the charge in the output capacitor to be released quickly, and the control logic circuit 7 causes the duty cycle of the DCDC topology 1 to decrease, thereby slowing down the charging of the output capacitor; wherein, the lower threshold voltage VL is the minimum threshold voltage.

[0059] The second case: if the output voltage VOUT generated by the DCDC topology 1 is lower than the lower threshold voltage VL of the overshoot or undershoot detection circuit 3, the output voltage compensation circuit 4 is turned on to charge the output capacitor, the reference voltage selection circuit 5 selects a high voltage reference, and the GM adjustable error amplifier 6 selects a high bandwidth to increase the output voltage VC at a faster rate. This voltage will adjust the duty cycle of the DCDC topology 1 through the control logic circuit 7, so that the duty cycle is increased, and the voltage compensation circuit 4 allows the charge in the output capacitor to be quickly replenished; wherein, the upper threshold voltage VH is the maximum threshold voltage.

[0060] See also Figure 3 , the waveform of the output voltage of the traditional current mode BUCK type DCDC when the load current suddenly changes from light load to heavy load. It can be seen from the figure that when the load switches from light load to heavy load, the DCDC topology works in PWM modulation mode. At this time, the undershoot of the output voltage can only be regulated by the VC generated by the error amplifier through the comparison of the output voltage and the feedback voltage. As the output voltage VC increases, the duty cycle of the DCDC topology increases, the charging time of the inductor is extended, and the output voltage recovers slowly. From the simulation results, it can be seen that the load current is 0mA before 300uS, and the load current suddenly changes to 400mA after 300uS. It is observed that the VOUT waveform undershoots to 1.175V and recovers to 1.2V after about 10us.

[0061] See also Figure 4, the waveform of the output voltage of the traditional current mode BUCK type DCDC when the load current suddenly changes from heavy load to light load. It can be seen from the figure that when the load switches from heavy load to light load, the DCDC topology works in PWM modulation mode. At this time, the undershoot of the output voltage can only be regulated by the VC generated by the error amplifier through the comparison of the output voltage and the feedback voltage. As the output voltage VC decreases, the duty cycle of the DCDC topology 1 decreases, slowing down the charging time of the inductor and slowly recovering the output voltage. From the simulation results, it can be seen that the load current was 600mA before 300uS, and the load current suddenly changed to 10mA after 300uS. The VOUT waveform was observed to surge to 1.24V and recover after 36uS.

[0062] See also Figure 5 , capacitor voltage detection circuit, assuming that the output capacitor is C, and its equivalent series resistance is R. The value of N is determined according to the limitation of the layout area. The choice of N determines the size of the series resistor, which is N×R, and the size of the capacitor is C / N. In this way, the on-chip capacitor and the output capacitor in the circuit are connected in parallel, so that the current of the on-chip capacitor will flow through the resistor R2 at a ratio of 1 / N. The positive end of the op amp is connected to a reference voltage VREF, which ensures that the output voltage will not have a negative voltage under any load mutation. When the load current changes, the charge of the output capacitor changes accordingly. This change is manifested as a small signal change through the on-chip capacitor, and this signal is converted into a voltage signal through the series resistor R2.

[0063] Output voltage analysis process: The load current change is marked as I, the branch where the internal capacitor C / N is located is connected in parallel with the output capacitor at a multiple of 1 / N, and the load current change flows through the branch where C / N is located at a multiple of I / N. Due to the existence of the virtual short, the voltage at the negative end of the op amp is VREF, and the current flowing through the resistor R2 is I / N, and the output voltage is VREF-(I×R2) / N. Through this design, the output capacitor current detection circuit 2 can accurately and quickly reflect the change of capacitor charge and provide a reliable voltage signal input for subsequent voltage compensation and dynamic response.

[0064] See also Figure 6 , the circuit diagram of the GM adjustable error amplifier 6, the size of the negative feedback resistor of the source negative feedback circuit is adjusted by the nmos switch, the gm of the amplifier is ≈ 1 / R, so the size of R can be adjusted by turning the switch off and on to indirectly change the gm value and thus change the bandwidth.

[0065] See also Figure 7, Schematic diagram of output voltage compensation circuit 4, the bias current mirror is connected to the output capacitor through transmission gates TG1 and TG2. When the output voltage surges, TG2 is turned on to discharge the capacitor. When the output voltage surges, TG1 is turned on to charge the capacitor to slow down the change of the output voltage.

[0066] See also Figure 8 , the waveform of the output voltage of the current mode BUCK type DCDC of the present invention when the load current changes suddenly from light load to heavy load. It can be seen from the figure that when the load switches from light load to heavy load, the topology of DCDC works in PWM modulation mode. At this time, the undershoot of the output voltage can be recovered not only by the traditional current mode DCDC method, but also by the other two methods:

[0067] 1. Compensation is performed through the output voltage compensation circuit 4;

[0068] Second, VC is adjusted by the reference voltage selection circuit 5 and the GM adjustable error amplifier 6 to increase VC to a higher voltage. The above two methods can quickly adjust the output voltage of the DCDC topology 1. From the simulation results, it can be seen that the load current is 400mA before 300uS, and the load current suddenly changes to 0mA after 300uS. It is observed that the VOUT waveform undershoots to 1.17596V and recovers within 2uS.

[0069] See also Fig. 9 , the waveform of the output voltage of the current mode BUCK type DCDC of the present invention when the load current changes suddenly from heavy load to light load. It can be seen from the figure that when the load switches from heavy load to light load, the topology of DCDC works in PWM modulation mode. At this time, the undershoot of the output voltage can be recovered not only by the traditional current mode DCDC method, but also by the other two methods:

[0070] 1. Release the voltage through the output voltage compensation circuit 4;

[0071] Second, VC is adjusted through the reference voltage selection circuit 5 and the GM adjustable error amplifier 6 to reduce VC to a lower voltage. The above two methods can quickly adjust the output voltage of the DCDC topology 1. From the simulation results, it can be seen that the load current is 600mA before 300uS, and the load current suddenly changes to 10mA after 300uS. It can be observed that the VOUT waveform is significantly improved compared with the traditional model. The overshoot voltage is 1.2357V and it recovers after 27uS.

[0072] The present invention introduces an output capacitor charge sampling circuit and directly uses the change of the output capacitor charge to quickly judge the sudden change of the load current. The charge change of the capacitor is faster than the response of the inductor current, and can be sensed in advance in the initial stage of the load sudden change, and trigger the compensation mechanism. Compared with the traditional inductor feedback mechanism, this method significantly shortens the detection and response time, avoids the excessive amplitude of voltage undershoot and overshoot, and effectively improves the power supply stability and reliability of the system; secondly, the present invention adds multiple adjustment means on the basis of the traditional duty cycle adjustment. On the one hand, the output capacitor is directly charged and discharged by an external current source to achieve rapid compensation; on the other hand, the change speed of the duty cycle is further optimized by adjusting the reference voltage and the bandwidth of the error amplifier. The introduction of the dual adjustment mechanism not only speeds up the recovery speed of the output voltage, but also significantly reduces the voltage fluctuation amplitude. Compared with the prior art, the present invention provides a more flexible and effective adjustment method, so that the DCDC converter performs better in the load sudden change scenario and meets the power supply requirements of higher performance.

[0073] See also Fig.10 A second aspect of the present invention provides a fast dynamic response method of a DCDC converter, comprising the following steps:

[0074] Step 1: Determine the load condition of the DCDC topology 1 by using the output capacitor current detection circuit 2 and the overshoot or undershoot detection circuit 3;

[0075] Step 2: When the output voltage VOUT generated by the DCDC1 topology 1 exceeds the upper threshold voltage VH or the lower threshold voltage VL of the overshoot or undershoot detection circuit 3, the output voltage compensation circuit 4 is turned on to discharge the output capacitor; when the output voltage VOUT generated by the DCDC topology 1 is lower than the upper threshold voltage VH or the lower threshold voltage VL of the overshoot or undershoot detection circuit 3, the output voltage compensation circuit 4 is turned on to charge the output capacitor;

[0076] Step 3: The reference voltage selection circuit 5 selects a low voltage reference or a high voltage reference, and the GM adjustable error amplifier 6 selects a high bandwidth;

[0077] Step 4: The control logic circuit 7 adjusts the duty cycle of the DCDC topology 1 .

[0078] Part of the data in the above formula is calculated by removing the dimension and taking its numerical value. The formula is a formula closest to the actual situation obtained by software simulation of a large amount of collected data; the preset parameters and preset thresholds in the formula are set by technical personnel in this field according to actual conditions or obtained through simulation of a large amount of data.

[0079] The above embodiments are only used to illustrate the technical method of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical method of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical method of the present invention.

Claims

1. A fast dynamic response system of a DCDC converter, characterized in that: It includes a DCDC topology (1), an output capacitor current detection circuit (2), an overshoot or undershoot detection circuit (3), an output voltage compensation circuit (4), a reference voltage selection circuit (5), a GM adjustable error amplifier (6), a control logic circuit (7) and a zero-crossing detection circuit (8); The control logic circuit (7) is used to control the DCDC topology (1) to generate a constant output voltage VOUT; The output capacitor current detection circuit (2) is used to detect the change in the output current, analyze the output voltage, and detect the overshoot or undershoot of the output voltage through the overshoot or undershoot detection circuit (3); The output voltage compensation circuit (4) is used to discharge or charge the output capacitor; The reference voltage selection circuit (5) is used to adjust the reference voltage; The GM adjustable error amplifier (6) is used to change the bandwidth of the error amplifier.

2. A fast dynamic response system of a DCDC converter according to claim 1, characterized in that: The DCDC topology (1) is connected to an output capacitor current detection circuit (2); the output capacitor current detection circuit (2) is connected to an overshoot or undershoot detection circuit (3); the overshoot or undershoot detection circuit (3) is connected to an output voltage compensation circuit (4), a reference voltage adjustment circuit (5) and a negative end of a GM adjustable error amplifier (6) in sequence; the reference voltage adjustment circuit (5) is connected to a negative end of the GM adjustable error amplifier (6); the positive end of the GM adjustable error amplifier (6) is connected to a bias voltage, and its output end is connected to a control logic circuit (7).

3. A fast dynamic response system of a DCDC converter according to claim 1, characterized in that: The overshoot or undershoot detection circuit (3) is composed of two hysteresis comparators, the positive ends of the hysteresis comparators are respectively connected to two reference voltages, and the negative ends are connected to the output end of the output capacitor current detection circuit; wherein the hysteresis comparators include a first hysteresis comparator and a second hysteresis comparator.

4. A fast dynamic response system of a DCDC converter according to claim 3, characterized in that: The overshoot or undershoot detection circuit (3) detects the overshoot or undershoot of the output voltage, comprising: When it is detected that the output voltage undershoots and is lower than the lower threshold voltage VL, the first hysteresis comparator is connected to the gate of the current mirror switch tube TG1, the reference voltage adjustment circuit (5) selects a high voltage reference, and the GM adjustable error amplifier (6) selects a high bandwidth; When it is detected that the output voltage rises and is higher than the upper threshold voltage VH, the second hysteresis comparator is connected to the gate of the current mirror switch tube TG2, the reference voltage adjustment circuit (5) selects a low voltage reference, and the GM adjustable error amplifier (6) selects a high bandwidth.

5. A fast dynamic response system of a DCDC converter according to claim 4, characterized in that: The output voltage compensation circuit (4) comprises a bias current mirror, a current mirror switch tube TG1, and a current mirror switch tube TG2; the bias current mirror is connected to the output capacitor via TG1 and TG2.

6. A fast dynamic response system of a DCDC converter according to claim 5, characterized in that: The lower threshold voltage VL is the minimum threshold voltage, and the upper threshold voltage VH is the maximum threshold voltage.

7. A fast dynamic response system of a DCDC converter according to claim 5, characterized in that: The source of the current mirror switch tube TG1 is connected to the supply voltage, and the source of the current mirror switch tube TG2 is grounded.

8. The fast dynamic response system of a DCDC converter according to claim 1, characterized in that: The positive input terminal of the GM adjustable error amplifier (6) is connected to the reference voltage VREF, and the reverse input terminal is connected to the output feedback voltage VFB. The input pair tube adopts a source negative feedback mode, and the feedback resistance is adjustable to adjust the gm of the error amplifier.

9. The fast dynamic response system of a DCDC converter according to claim 1, characterized in that: The zero-crossing detection circuit (8) is used to detect the reverse flow of the inductor current.

10. A fast dynamic response method of a DCDC converter, based on the fast dynamic response system of a DCDC converter according to any one of claims 1 to 9, characterized in that: The following steps are involved: Step 1: Determine the load condition of the DCDC topology (1) by using the output capacitor current detection circuit (2) and the overshoot or undershoot detection circuit (3); Step 2: When the output voltage VOUT generated by the DCDC topology (1) exceeds the upper threshold voltage VH or the lower threshold voltage VL of the overshoot or undershoot detection circuit (3), the output voltage compensation circuit (4) is turned on to discharge the output capacitor; when the output voltage VOUT generated by the DCDC topology (1) is lower than the upper threshold voltage VH or the lower threshold voltage VL of the overshoot or undershoot detection circuit (3), the output voltage compensation circuit (4) is turned on to charge the output capacitor; Step 3: The reference voltage selection circuit (5) selects a low voltage reference or a high voltage reference, and the GM adjustable error amplifier (6) selects a high bandwidth; Step 4: The control logic circuit (7) adjusts the duty cycle of the DCDC topology (1).

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