Comparison circuit and power stage of switching converter

Abstract

The present application provides a comparison circuit, including: a comparator, for comparing the input voltage of the comparator with the reference voltage of the comparator and generating its output signal; a mode selector, for generating a mode value, if the input voltage is lower than the intermediate voltage, a first logic value is generated, otherwise, a second logic value is generated; a first branch, connected between a first node and a second node, for generating a first voltage drop, the first voltage drop is equal to the difference between the first reference voltage and the reference voltage of the comparator; a second branch, for generating a second voltage drop, the second voltage drop is equal to the difference between the second reference voltage and the reference voltage of the comparator; a selection circuit, for using one of the second node or the third node as the input end of the comparator according to the mode value. In addition, the present application also provides a power stage of a switching converter. The present application uses a single comparator to compare the input voltage with multiple reference voltages, effectively reducing the occupied area of ​​the chip.

Description

[0001] Priority declaration

[0002] This patent application is related to and claims priority from an Indian provisional patent application entitled “Single Comparator Voltage Detection”, filed on July 11, 2024, with serial number 202441053138 and agent file number AURA-364-INPR. This patent application incorporates the entire contents of the Indian provisional patent application, but only insofar as it does not conflict with the description herein. Technical Field

[0003] The present application relates to the technical field of electronic circuits, and in particular to a comparison circuit and a power stage of a switching converter. Background Art

[0004] A comparator is a circuit that generates a first logic value if the comparator's input voltage is greater than the comparator's reference voltage, and a second logic value otherwise. Such a comparator can be used to compare an input voltage of interest to a single reference voltage.

[0005] It is often necessary to compare this input voltage of interest to multiple reference voltages. For example, a circuit or system may be designed to operate at different voltage levels, and it may be necessary to determine whether the input voltage is below or above each voltage level.

[0006] In one method of the prior art, a plurality of comparators are used to compare with a corresponding number of reference voltages. However, this method may not be ideal when the available area on a chip / integrated circuit (IC) is limited. Summary of the invention

[0007] In view of this, it is necessary to propose a comparison circuit and a power stage of a switching converter, which can compare an input voltage with multiple reference voltages using a single comparator, thereby effectively reducing the occupied area of ​​a chip.

[0008] In a first aspect, an embodiment of the present application provides a comparison circuit, comprising:

[0009] a comparator, configured to compare an input voltage of the comparator with a reference voltage of the comparator and generate an output signal of the comparator;

[0010] a mode selector, configured to generate a mode value, wherein if the input voltage is lower than an intermediate voltage, the generated mode value is a first logic value, otherwise, the generated mode value is a second logic value; wherein the intermediate voltage is between a first reference voltage and a second reference voltage of interest, and the first reference voltage is lower than the second reference voltage;

[0011] a first branch connected to a first node to receive the input voltage and generate a first voltage drop relative to the input voltage at a second node; wherein the first voltage drop is equal to a difference between the first reference voltage and a reference voltage of the comparator;

[0012] a second branch connected to the first node to receive the input voltage and generate a second voltage drop relative to the input voltage at a third node; wherein the second voltage drop is equal to a difference between the second reference voltage and a reference voltage of the comparator; and

[0013] A selection circuit is used to use the second node or the third node as the input terminal of the comparator according to the mode value, wherein the mode value indicates whether the output signal of the comparator represents a comparison with the first reference voltage or a comparison with the second reference voltage, and the output signal of the comparator indicates whether the input voltage is higher or lower than the reference voltage compared with it.

[0014] Further, the first branch includes a first resistor, a first current source and a first switch connected in series, and the first resistor and the first current source jointly generate the first voltage drop; the second branch includes a second resistor, a second current source and a second switch connected in series, and the second resistor and the second current source jointly generate the second voltage drop; the selection circuit only turns on one of the first switch and the second switch according to the mode value.

[0015] Furthermore, the mode selector comprises:

[0016] a third resistor and a third current source connected in series with the first node to jointly generate a voltage drop at a fourth node equal to the intermediate voltage; and

[0017] A first inverter is connected to the fourth node and is used to generate the mode value.

[0018] Furthermore, the selection circuit comprises:

[0019] A second inverter connected in series with the first inverter, wherein an output terminal of the second inverter is connected to the first switch, and an output terminal of the first inverter is connected to the second switch.

[0020] Furthermore, the input voltage is the instantaneous voltage of the input signal.

[0021] A second aspect of the present application further provides a power stage of a switching converter, comprising:

[0022] A high-side switch and a low-side switch are connected in series between a power supply and a constant reference potential, the power supply provides an input voltage, the high-side switch and the low-side switch are controlled by a first drive signal and a second drive signal, respectively, the first drive signal and the second drive signal are turned on in a first time period and a second time period respectively to drive a corresponding current in the inductor;

[0023] a gate driver, generating the first drive signal and the second drive signal based on a control signal received from a phase controller, wherein the control signal received in the first time period has a first logic level, and the control signal received in the second time period has a second logic level; and a voltage detection module, comprising:

[0024] A comparator, used to compare an input voltage of the comparator with a reference voltage of the comparator and generate an output voltage of the comparator; when the input voltage of the comparator is less than the reference voltage of the comparator, the output voltage of the comparator is a first output value, otherwise it is a second output value;

[0025] a mode selector, configured to generate a mode value, wherein if the input voltage is lower than the intermediate voltage, the generated mode value is a first logic value, otherwise, the generated mode value is a second logic value; wherein the intermediate voltage is between a first reference voltage and a second reference voltage of interest, and the first reference voltage is lower than the second reference voltage;

[0026] A first branch, configured to receive the input voltage at a first node and generate a first voltage drop relative to the input signal at a second node; wherein the first voltage drop is equal to a difference between the first reference voltage and a reference voltage of the comparator;

[0027] a second branch, configured to receive the input voltage at the first node and generate a second voltage drop relative to the input voltage at a third node; wherein the second voltage drop is equal to a difference between the second reference voltage and a reference voltage of the comparator; and

[0028] a selection circuit for connecting the second node or the third node as an input terminal of the comparator according to the mode value, wherein the mode value indicates whether the output signal of the comparator is a comparison relative to the first reference voltage or a comparison relative to the second reference voltage, and the output signal of the comparator indicates whether the input voltage is higher or lower than the reference voltage for comparison.

[0029] Furthermore, the power stage further comprises:

[0030] A logic block, configured to send a first signal to the gate driver when the mode value is equal to the first logic value and the output signal of the comparator is equal to the first output value, or when the mode value is equal to the second logic value and the output signal of the comparator is equal to the second output value, and to send a second signal otherwise; wherein, if it is determined that the input voltage is lower than the first reference voltage or higher than the second reference voltage, the first drive signal and the second drive signal generated by the gate driver are in an off state.

[0031] In the comparison circuit and the power stage of the switching converter provided by the embodiment of the present application, the voltage detection module uses a single comparator to compare the input voltage with multiple reference voltages. Compared with the prior art that uses multiple comparators to compare the input voltage with multiple reference voltages, the present application can reduce the occupied area of ​​the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The embodiments of the present application will be described in conjunction with the following drawings.

[0033] Figure 1 A block diagram of the system provided in this embodiment.

[0034] Figure 2 Shown is a specific block diagram of a voltage regulator module (VRM) provided in an embodiment of the present application.

[0035] Figure 3 The schematic diagram is a specific circuit diagram of the power stage provided in the embodiment of the present application.

[0036] Figure 4 A schematic diagram of a comparison circuit based on a single comparator provided in the present application.

[0037] Figure 5 FIG. 4 is a timing diagram showing a signal waveform generated at the output terminal of a comparison circuit based on a single comparator in one embodiment.

[0038] In the drawings, like reference numerals generally indicate like, functionally similar and / or structurally similar elements. In the drawings, the first appearance of an element is indicated by the leftmost digit (or digit combination) of the corresponding reference numeral. DETAILED DESCRIPTION

[0039] 1. Overview

[0040] The comparison circuit provided in the present application uses a single comparator to compare an input voltage with a plurality of reference voltages, and indicates a comparison output result and a reference voltage related to the comparison output result.

[0041] In one embodiment of the present application, the comparison circuit includes a single comparator, a mode selector, a first branch, a second branch and a selection circuit. The comparator is used to compare the input voltage of the comparator with the reference voltage of the comparator and generate an output signal of the comparator. The mode selector is used to generate a mode value, and if the input voltage is lower than the intermediate voltage, the mode value generated by the mode selector is a first logic value; otherwise, the generated mode value is a second logic value; wherein the intermediate voltage is between the first reference voltage and the second reference voltage of interest, and the first reference voltage is lower than the second reference voltage. The first branch is connected to a first node to receive an input voltage, and generates a first voltage drop relative to the input voltage at a second node, the first voltage drop being approximately equal to the difference between the first reference voltage and the reference voltage of the comparator.

[0042] The second branch is connected to the first node to receive the input voltage and generates a second voltage drop relative to the input voltage at the third node; wherein the second voltage drop is approximately equal to the difference between the second reference voltage and the reference voltage of the comparator. The selection circuit uses one of the second node or the third node as the input terminal of the comparator according to a mode value, wherein the mode value indicates whether the output signal of the comparator represents a comparison with the first reference voltage or a comparison with the second reference voltage, and the output signal of the comparator indicates whether the input voltage is higher or lower than the reference voltage compared with it.

[0043] In another embodiment of the present application, the first branch includes a first resistor, a first current source, and a first switch connected in series, wherein the first resistor and the first current source jointly generate a first voltage drop. The second branch includes a second resistor, a second current source, and a second switch connected in series, wherein the second resistor and the second current source jointly generate a second voltage drop. The selection circuit only turns on (i.e., switches on) one of the first switch and the second switch according to the mode value.

[0044] In some embodiments of the present application, the mode selector includes a third resistor and a third current source connected in series with the first node, the third resistor and the third current source jointly generating a voltage drop at a fourth node that is equal to the intermediate voltage relative to the input voltage. The first inverter is connected to the fourth node for generating a mode value.

[0045] In another embodiment of the present application, the selection circuit includes a second inverter connected in series with the first inverter, an output terminal of the second inverter is connected to the first switch, and an output terminal of the first inverter is connected to the second switch.

[0046] In one embodiment of the present application, the input voltage is the instantaneous voltage of the input signal.

[0047] The present application will be described below in conjunction with a plurality of embodiments. However, it should be clear to those skilled in the art that the present application may be implemented by omitting one or more specific features or by other methods, components, materials, etc. In other embodiments, known structures, materials, or operations are not described in detail one by one to simplify the features of the present application. In addition, although only some combinations are described here for the sake of brevity, the described features / aspects may be implemented in various combinations.

[0048] 2. System Implementation

[0049] Figure 1 The system 100 includes a power supply 110, a central processing unit (CPU) 120, a memory 130, a network interface 140, and a peripheral device 150. In one embodiment, the system 100 corresponds to a computer (e.g., a desktop computer, a laptop computer, etc.), while in other embodiments, the system 100 may represent other types of systems. It is understood that the number of functional modules included in the system 100 may be greater than 100. Figure 1 More or fewer functional modules may be shown.

[0050] CPU 120 generally represents a processor or a system on chip (SoC), and receives corresponding supply voltages Va and Vb from power supply 110 through lines 112A and 112B, respectively. For example, Va may be smaller than Vb and can be used to power the core part of the CPU. The core part may include an arithmetic logic unit (ALU), a microprogram sequencer, registers, etc. Vb can be used to power the rest of CPU 120, such as input / output (I / O) units, I / O buffers, on-chip peripherals, etc. CPU 120 provides a variety of signals (all considered to be included in this bidirectional line / bus 121) to power supply 110 through a bidirectional line / bus 121, which specify its demand for power supply. These signals can be signals that specify a specific operating mode (in terms of power consumption) in some embodiments, such as PS1, PS2, PS3, etc., which represent "power saving states set to improve efficiency".

[0051] Memory 130 represents a type of memory, which may include both volatile memory and non-volatile memory. For example, in a personal computer, the memory may include magnetic memory (hard disk) and solid-state memory (RAM, flash memory, etc.). Memory 130 receives a supply voltage through line 113 to power various circuits and modules within it.

[0052] The network interface 140 is used to implement bidirectional communication between the system 100 and a computer network (or the Internet in a broad sense). The network interface 140 implements the use of a specific physical layer and data link layer standard (such as Ethernet or Wi-Fi). TM ) electronic circuits required for communication. Network interface 140 may also include a network protocol stack to allow communication with other computers on the same Local Area Network (LAN) and to achieve large-scale network communication through routing protocols such as Internet Protocol (IP). Network interface 140 receives power from a power supply through line 114 to power its internal circuits and modules. Network interface 140 receives / sends data from / to an external system through line 141, and receives / sends data with CPU 120 through line 124.

[0053] The peripheral device 150 is one or more peripheral circuits, such as a speaker, a microphone, a user interface device, etc. The peripheral device 150 receives power from a power source through the line 115 and communicates with external devices through the line 151 .

[0054] The power supply 110 receives power from one or more power sources (e.g., a battery) via line 101 and provides the required supply voltage on lines 112A, 112B, 113, 114, and 115. In one embodiment, the power supply 110 includes one or more multi-phase DC-DC converters to generate the supply voltage. The power supply 110 receives signals from the CPU 120 via line 121, which may indicate the power consumption mode in which the CPU 120 operates during a specific time period, and the power consumption mode represents the amount of power that the CPU 120 may obtain / consume from the power supply 110. The power supply 110 responds to the power consumption mode signal by controlling the multi-phase DC-DC converter to reduce or increase the current output according to the specific content of the power consumption mode signal (e.g., PS1, PS2, and PS3).

[0055] In one embodiment, the power supply 110 is a voltage regulator module (VRM), sometimes also referred to as a processor power module (PPM), which includes one or more step-down (buck) switching converters for generating one or more lower voltages from a high voltage power supply. However, in other embodiments, other types of DC-DC converters, such as boost converters, buck-boost converters, hysteresis converters, etc., can be used instead of buck converters. Using VRM, multiple devices / integrated circuits (ICs) that require different supply voltages can be installed on the same platform, such as a computer motherboard of a personal computer. An embodiment of a voltage regulator module (VRM) will be described in detail below.

[0056] 3. Voltage Regulator Module (VRM)

[0057] Figure 2 What is shown is a specific block diagram of the voltage regulation module provided in an embodiment of the present application. Figure 1 The power supply 110 in the embodiment is a voltage regulation module implemented in the form of a multi-phase switching converter, which generates two regulated voltages, namely two power supply rails (power rails), namely Va (node ​​240 or rail-A) and Vb (node ​​250 or rail-B), wherein node 240 can also be regarded as power supply rail A, namely rail-A, and node 250 can also be regarded as power supply rail B, namely rail-B. Figure 2 In the figure, the power supply for providing the regulated voltages Va and Vb is labeled 201, and its voltage is Vin. In one embodiment of the voltage regulation module 110, Vin is approximately 21 V. The figure also shows a supply voltage Vcc (node ​​202), which may be provided by the phase controller 210 and can be used to power the modules in each power stage described below.

[0058] The voltage regulation module 110 includes a phase controller 210, power stages (or smart power stages) SPSA-1 to SPSA-3, SPSB-1 ​​to SPSB-4, inductors 225A-1 to 225A-3 and 227B-1 to 227B-4, and capacitors 226A-1 to 226A-3 and 228B-1 to 228B-4. Va (node ​​240) is generated by a three-phase buck converter (having three power stages, i.e., SPSA-1 to SPSA-3), while Vb (node ​​245) is generated by a four-phase buck converter (having four power stages, i.e., SPSB-1 ​​to SPSB-4). Nodes / lines 240 and 250 correspond to Figure 1 For simplicity, Figure 2Other power supply circuits that generate power on lines 113, 114, and 115 are not shown. In other embodiments, voltage regulation module 110 may have more or fewer power rails and power levels for each power rail.

[0059] In one embodiment, each power stage and phase controller are implemented as separate integrated circuits (ICs). However, in other embodiments, the power stages and phase controllers may be implemented differently.

[0060] The phase controller 210 works in conjunction with the power stage of one or more power rails to produce a regulated voltage as an output. Figure 2 In the example of , the phase controller 210 works in conjunction with one or more of the power stages SPSA-1 to SPSA-3 to generate a regulated voltage Va (node ​​240). Similarly, the phase controller 210 works in conjunction with one or more of the power stages SPSB-1 ​​to SPSB-4 to generate a regulated voltage Vb (node ​​250). Therefore, the regulated voltage Va (node ​​240) and the regulated voltage Vb (node ​​250) are treated as input voltages provided to the phase controller 210 to enable one or more feedback loops within the phase controller 210 to regulate Va and Vb. The phase controller 210 also receives inductor current information (i.e., the current flowing through each inductor) from each power stage to perform various operations, such as current mode control for voltage regulation, current limiting, short circuit protection, and balancing the current generated by each power stage in the same converter (or "power rail") so that the current of each power stage of the same power rail is substantially equal in magnitude. Other signals flowing between the phase controller 210 and the power stages will be described below.

[0061] The combination of the phase controller 210 (the corresponding circuit inside), a power stage, and the corresponding inductor and capacitor constitute "one phase" of a power rail. Therefore, for example, the power stage SPSA-1, the inductor 225A-1, the capacitor 226A-1 and the corresponding circuit inside the phase controller 210 constitute a single buck converter and is one phase of the three-phase buck converter. It should be noted that although each phase is shown as having its own independent capacitor (such as capacitor 226A-1), in another embodiment, only one larger capacitor (with a larger capacitance value) may be used at node 240 (and node 250). In other embodiments, multiple capacitors are placed near the load powered by the corresponding supply voltage. For simplicity, a single power stage is also referred to as one phase of the power rail. Each power stage is also connected to a capacitor (bootstrap capacitor) so that when the high-side switch is an N-channel metal-oxide-semiconductor field effect transistor (MOSFET), the high-side switch operation can be enabled.

[0062] Each power stage may include a high-side switch, a low-side switch, gate drive circuits for the two switches, a temperature monitoring circuit, and an inductor current sensing circuit / module for providing information indicating the magnitude of the inductor current to the phase controller 210. Although the high-side switch and the low-side switch of the power stage can be considered to "drive" the inductor, the current provided by the power stage, and therefore the corresponding inductor current, generally depends on the load current drawn from the supply voltage. Each power stage takes a power supply (all of which can be the same power supply) as an input, which is connected to the high-side switch (described in detail below). An embodiment of a power stage will be described in detail below.

[0063] 4. Power level (SPS)

[0064] Figure 3 A specific schematic diagram of the power level is provided for the embodiment of the present application. Figure 2 The illustrated power stage SPSB- 1 includes a gate driver 310 , a high-side switch 320 , a low-side switch 330 , a fault communication module 340 , a voltage detection module 350 , and a current detection module 360 ​​. Figure 3Also illustrated are the inductor 227B-1 and capacitor 228B-1 corresponding to the power stage. When used to implement an integrated circuit, P31 to P36 represent pins of the power stage SPSB-1. In other embodiments, P31 to P35 represent circuit nodes. Current "IL" represents the inductor current flowing through the inductor 227B-1. Vcc (node ​​202) is used to power modules 310, 340, 350 and 360. The drain of the high-side switch 320 is connected to Vin (node ​​201).

[0065] The power stage SPSB-1, in combination with the inductor 325, the capacitor 326 and the phase controller 210, provides a regulated voltage Vb as an output at the node 250. For simplicity, Figure 3 Not shown are various other modules / circuits that the power stage 300 may include, such as a level converter of the gate driver 310 , a temperature sensor, etc. Figure 2 All other power stages in (Rail-B and optionally Rail-A) can be implemented in a manner similar to power stage SPSB-1, as further described below.

[0066] The gate driver 310 receives the pulse width modulation (PWM) signal PWMB-1 (line 216) from the phase controller 210, and generates corresponding voltages en-HS and en-LS on lines 312 and 313 according to the logic level of the PWM signal, so as to turn on and off the high-side switch 320 and the low-side switch 330 respectively in corresponding time intervals, which is indicated by the logic level of the PWM signal. The high-side switch 320 and the low-side switch 330 are implemented by N-channel MOSFETs, and the gate driver 310 drives the gates of these MOSFETs. The high-side switch 320 and the low-side switch 330 can also be implemented by adopting other methods.

[0067] exist Figure 3 In the embodiment, when PWMB-1 is at a logic high level, the gate driver 310 generates corresponding voltages en-HS and en-LS on lines 312 and 313, respectively, to turn on the high-side switch 320 and turn off the low-side switch 330. When PWMB-1 is at a logic low level, the gate driver 310 generates corresponding appropriate voltages en-HS and en-LS on lines 312 and 313, respectively, to turn off the high-side switch 320 and turn on the low-side switch 330. When PWMB-1 is in a high-impedance state (High-impedance, also called an intermediate level), the gate driver 310 generates corresponding appropriate voltages en-HS and en-LS on lines 312 and 313, respectively, to turn off the high-side switch 320 and the low-side switch 330 at the same time. The gate driver 310 can be implemented in a known manner.

[0068] As described below, the voltage detection module 350 is used to determine whether the input voltage Vin is within an acceptable range, for example, between an undervoltage / lower limit value Vin_uv and an overvoltage / upper limit value Vin_ov. The acceptable range may also include these two limit values ​​Vin_uv and Vin_ov. As described below, when / if Vin is not within the acceptable range, the voltage detection module 350 sets the tri-state signal 351, otherwise the tri-state signal 351 is maintained in an open circuit or high impedance state. When / if Vin is not within the acceptable range, the gate driver 310 receives the set signal 351 and responds to the drive signals 312 and 313 to turn off the corresponding power switches 320 and 330. When the set signal 351 also appears on pin P32, the output of the current detection module 360 ​​is disconnected from the line 361.

[0069] The current sensing module 360 ​​is used to determine the magnitude (e.g., instantaneous magnitude) of the inductor current through the inductor 227B-1 and provide information indicating the magnitude of the inductor current at its output node (located inside the module 360) via line 351, which is connected to the output pin P32. Pin P32 is connected to the phase controller 210 via line CSB-1 (line 218). The current sensing module 360 ​​can determine the magnitude of the inductor current by any of a variety of known methods. For example, in Figure 3 , the current sensing module 360 ​​receives input signals 325 and 335 from the high-side switch 320 and the low-side switch 330 , respectively.

[0070] In one embodiment, when the corresponding switch is in the on state and current flows through the switch and the inductor 227-1, the signals 325 and 335 represent the voltage drops across the high-side switch and the low-side switch, respectively. The current detection module 360 ​​obtains the instantaneous amplitude of the inductor current (or the reduced instantaneous amplitude of the inductor current) based on these voltage drops. In one embodiment, the current detection module 360 ​​provides / reports the inductor current information in the form of a (replicated) current (sensed current), the amplitude of which is reduced relative to the instantaneous amplitude of the inductor current. However, in other alternative embodiments, the current detection module 360 ​​can also be configured to provide this information in the form of a voltage or a digital value.

[0071] When the gate drive module 310 turns off the power switches 320 and 330 in response to the indication received via the signal 351 (i.e., the input voltage Vin is not within the acceptable range), the current sensing module 360 ​​includes an internal switch (or other suitable circuit) for disconnecting its output node from the line 351 (and therefore from the pin P32). At this time, the set signal 351 is provided to the pin P32 and transmitted to the phase controller 210 via the line CSB-1 (line 218). This disconnection can be achieved in a known manner, and for the sake of brevity, the mechanism and command for disconnection are not described herein. After receiving the set signal 351, the phase controller 210 can take an adapted manner to indicate this state to the user.

[0072] As described above, the power stage SPSB-1 ​​may need to detect multiple voltages to ensure that it is in the best working state. For example, it may be necessary to check / detect whether the input voltage Vin (node ​​201) is undervoltage (lower than the lower reference value / lower reference voltage Vin_uv, such as 4.2V) or overvoltage (higher than the upper reference value / upper reference voltage Vin_ov, such as 22V). In other words, it may be necessary to compare the input voltage Vin with multiple reference voltages to determine whether Vin is within an acceptable range.

[0073] According to the voltage detection module 350 provided in the present application, it is helpful to compare the input voltage (for example, Vin) with multiple reference voltages. As described in the "Background Technology" section, in the existing method, a separate comparator is used for each of the multiple comparisons (comparisons with multiple reference voltages). The use of multiple comparators will lead to corresponding increased power consumption and occupy a larger area. According to the voltage detection module 350 provided in the present application, only one comparator is used to compare Vin with multiple reference voltages. An embodiment of this comparison circuit based on a single comparator will be described in detail below.

[0074] 5. Comparison circuit based on a single comparator

[0075] Figure 4 Schematic diagram of a comparison circuit based on a single comparator provided in the present application. Comparison circuit 400 includes comparator 410, branch circuits 420A and 420B, selection circuit 430, mode selector (circuit) 450, logic input (circuit) 460, and logic block 470. Input voltage Vin is connected to node 405 via node 406. Figure 3 The line 201 in the figure is connected and received at the node 405. Each circuit / module in the figure will be described in detail below.

[0076] The comparator 410 compares the input voltage provided at the non-inverting ("+") input terminal 411 with the reference voltage Vref at the inverting ("-") input terminal 412, and generates an output signal of the comparator at the output terminal 415. A logical value of 0 (LOW) of the output signal of the comparator indicates that the input voltage (detection voltage) of the comparator is less than the reference voltage Vref. Conversely, a logical value of 1 (HIGH) of the output signal of the comparator indicates that the input voltage of the comparator is greater than the reference voltage Vref. For the purpose of illustration, it is assumed that the reference voltage Vref is 1.3V, although any convenient value of the reference voltage Vref may be selected, because if the reference voltage Vref is different from 1.3V, the values ​​of the resistors and current sources in the comparison circuit 400 may also need to be correspondingly different.

[0077] In general, the present application implements multiple comparisons by using a single comparator 410 and different operating modes, each of which defines a different reference voltage to be compared with Vref. To illustrate this, it can be assumed that there are two operating modes, corresponding to undervoltage and overvoltage, respectively. However, in other embodiments, multiple operating modes can be defined and used as the basis for comparison with a corresponding number of more different reference voltages, which will be apparent to those skilled in the art upon reading this article.

[0078] As will be seen from the detailed description below, for the two operating modes, a mode (value) indicates whether the output signal of the comparator (output terminal 415) represents a comparison with a lower reference voltage or a higher reference voltage, and the output signal of the comparator (output terminal 415) indicates whether the input voltage Vin is higher or lower than the reference voltage compared thereto.

[0079] Subcircuits 420A and 420B each operate to provide a corresponding voltage drop (relative to Vin) adapted to the respective operating modes, and provide the resulting voltage to the non-inverting input terminal (+) of the comparator. Specifically, subcircuit 420A includes a resistor R1 (line 421A), a current source I1 (line 428), and a switch S2 connected in series, thereby generating a voltage drop of I1*R1 between nodes 405 (Vin) and 425A. Subcircuit 420B includes a resistor R2 (line 421B), a current source I2 (line 428), and a switch S1 connected in series, thereby generating a voltage drop of I2*R2 between nodes 405 and 425B.

[0080] It will be appreciated that any desired R and I values ​​may be selected for each subcircuit / operating mode. In general, each reference / threshold voltage (such as the lower reference value and the upper reference value mentioned above) is defined by the following formula:

[0081] Vth=Vref+R*I;

[0082] Wherein, Vth is the reference / threshold voltage; Vref is the fixed voltage at the inverting input terminal (-) of the comparator 410; and "*" represents a multiplication operator.

[0083] The resistor R is chosen to facilitate the realization of the current I. For example, a threshold / reference voltage of 4.2V can be achieved using a 100kΩ (100,000 ohms) resistor and a current of 29uA (microamps). The same resistor R can also be used for a threshold / reference voltage of 22V, but this will require a current of 187uA, which may be too high in current comparator circuit implementations (for example, in power stages). Similarly, if a 900kΩ resistor is used to achieve a threshold of 4.2V, the current will be too small, which may cause other effects, such as a slower startup time of the comparator circuit.

[0084] For ease of explanation, assume that R1 = 100kΩ and I1 = 29uA, from which the lower limit reference value Vin_uv of branch circuit 420A is 4.2V (= 1.3V + 100kΩ * 29uA); assume that R2 = 900kΩ and I2 = 23uA, from which the upper limit reference value Vin_ov of branch circuit 420B is 22V (= 1.3V + 900kΩ * 23uA). It can be understood that the voltage drop in each branch circuit is designed to be equal to the difference between the corresponding reference voltage (lower limit or upper limit) and the reference voltage Vref of the comparator. According to the above values ​​of R1, I1, R2 and I2, the voltage drops on R1 and R2 can be obtained to be 2.9V and 20.7V respectively. During operation, the detection threshold in the comparison circuit can be changed by modifying the values ​​of I1 and I2, as described below.

[0085] The mode selector (circuit) 450 generates a mode (value) for selecting one of the specific different branch circuits (operating modes) connected to the non-inverting input terminal (+) of the comparator 410. Since this embodiment has only two modes, the mode selector 450 generates the mode value according to whether the input voltage Vin is lower than the "middle voltage" (or mode switching voltage): if Vin is lower than the middle voltage, the generated mode value is a first logic value 1, otherwise, the generated mode value is a second logic value 0. The "middle voltage" here is any conveniently set value between the lower reference voltage Vin_uv and the upper reference voltage Vin_ov.

[0086] In one embodiment of the present application, the mode selection of the mode selector 450 is performed based on the IR voltage drop, and the voltage generated thereby is supplied to the inverter 457. Therefore, the mode selector 450 includes a resistor R3 (line 451) and a current source I3 (line 458) connected in series between Vin and the ground terminal to generate a voltage drop R3*I3, thereby generating a voltage equal to [Vin-(R3*I3)] at the node 455.

[0087] In one embodiment of the present application, R3=800kΩ, I3=10uA, and the corresponding voltage drop on the resistor R3 is 8V. The logic flip point of the inverter 457 defines the mode threshold voltage of Vin. The inverter 457 is connected to the node 455, and when Vin<=[8V+VtripN1], a mode value 1 is generated at its output; when Vin>[8V+VtripN1], a mode value 0 is generated; wherein VtripN1 is the flip point of the inverter 457. In one embodiment, the supply voltage Vcc is equal to 3.3V, and VtripN1 is equal to Vcc / 2, i.e., 1.65V.

[0088] The selection circuit 430 receives the mode value from the mode selector 450 and opens (closes) or closes (opens) the switches S1 and S2 accordingly. Specifically, the selection circuit 430 connects the output terminal (referred to as "modeb" at 482) of the inverter 457 included in the mode selector 450 to the circuit for opening / closing the switch S2. The selection circuit 430 also includes another inverter 437 connected in series with the inverter 457, and the output terminal (referred to as "mode" at 481) of the inverter 437 is connected to the circuit for opening / closing the switch S1.

[0089] When Vin<=[8V+VtripN1], modeb=1 and mode=0, so that switch S2 is turned on (ON) and switch S1 is turned off (OFF). In other words, compared with the lower reference value (Vin_uv), the corresponding branch circuit 420A is enabled (i.e., connected to the non-inverting input terminal "+" of the comparator). When Vin>[8V+VtripN1], modeb=0 and mode=1, so that switch S2 is turned off and switch S1 is turned on. In other words, compared with the higher reference value (Vin_ov), the corresponding branch circuit 420B is enabled. Therefore, mode and modeb jointly control different switches to select the corresponding branch circuit for undervoltage or overvoltage detection.

[0090] Therefore, the comparison circuit 400 compares the input voltage Vin with multiple reference voltages (Vin_uv and Vin_ov) in a manner based on a single comparator 410. Such a comparison circuit can be used as part of the voltage detection module 350 to determine whether the input voltage (such as Vin) is within the optimal operating range. The following will describe the working conditions of different components in the comparison circuit 400 under different scenarios (input voltages) through specific examples.

[0091] 6. Working Principle

[0092] Assume 3.3V Vcc (such as Figure 2 and Figure 3 4) has been applied to the various components of the power stage SPSB-1. When Vin is applied (or turned on), the input voltage Vin gradually rises from 0V. As described above, until Vin reaches (8V+VtripN1), the branch circuit 420A is connected to the non-inverting input terminal (+) of the comparator 410. In the case where Vref is fixed at 1.3V, when Vin exceeds (and rises to be higher than) 4.2V (Vin_uv as described above), the output signal (output terminal 415) of the comparator 410 switches from a logic low level to a logic high level. In response to the output signal of the comparator 410 becoming a logic high level, the logic block 470 reduces the previously set I1 value by a preset value (for example, 1uA) to ensure that the original undervoltage threshold (Vth_uv) is increased by a corresponding voltage value, so that when Vin is lower than the new threshold voltage (Vth_euv) later, the undervoltage is detected. Therefore, the comparison circuit provides a hysteresis characteristic for undervoltage detection.

[0093] After that, as Vin continues to rise above 4.2V, when Vin exceeds (8V+VtripN1) (i.e., the lower reference voltage Vin_uv), the operating mode changes, and sub-circuit 420B is connected to the non-inverting input terminal (+) of comparator 410 (sub-circuit 420A is disconnected from it at this time). When the operating mode changes or later, Vin is still less than 22V, so the value of (Vin-I2*R2) is less than 1.3V Vref, and the output signal of comparator 410 is again at a logic low level. The initial value of I2 is programmed (for example, set to 24uA) to set the overvoltage threshold at 21V (early overvoltage threshold, Vth_eov). As Vin continues to rise, when / if Vin exceeds (and rises above) 21V, the output signal of comparator 410 switches from a logic low level to a logic high level.

[0094] At some point after the output signal of the comparator (output terminal 415) becomes a logic high level, the logic block 470 reduces the previously set I2 value (for example, to 23uA), which ensures that the early overvoltage threshold (Vth_eov) will increase by a corresponding voltage value so that thereafter, when Vin rises above the new threshold voltage (Vth_ov, 22V), the overvoltage can be detected. Therefore, a hysteresis characteristic is also provided for overvoltage detection. Whether it is the hysteresis characteristic in undervoltage detection or overvoltage detection, it can ensure that when Vin is at or very close to the respective thresholds, the output signal of the comparator will not repeatedly switch between the logic high level and the logic low level due to the noise on Vin.

[0095] It is understood that the comparator output signal and the value of mode / modeb can be logically combined to generate a final logic signal indicating an undervoltage state, an overvoltage state, etc. These logic signals can be processed and, when an abnormal condition occurs at Vin, can serve as a basis for disabling (turning off) the two power switches 320 and 330 and signaling such an abnormal condition to the phase controller 210.

[0096] The following will explain how the comparison circuit 400 generates the above logic signal as its output signal by way of example.

[0097] 7. Generate logical output

[0098] Reference again Figure 4 , the blanking circuit 460 generates a blanking pulse (referred to as "blank" at 483) that is briefly set to a high level when the mode value changes from 1 to 0 or from 0 to 1. In this embodiment, the blanking circuit 460 is implemented by a delay element and an XOR gate. The signal "blank" is built into a high level for the delay duration provided by the delay element, and the logic block 470 can use this signal to ensure that the correct logic output is generated only after the transient state / effect (interference) generated by switching between different branch circuits disappears.

[0099] Logic block 470 includes logic circuits (not shown) for generating the desired logic output according to the mode value, the output signal of the comparator (output terminal 415) and the value of the blanking pulse. In this embodiment, logic block 470 also includes logic circuits for switching the amplitude of the current source (29uA or 23uA) when the operating mode changes.

[0100] In one embodiment, the comparator output signal (output terminal 415), the mode signal and the blanking signal are combined in the logic block 470 to define the respective states of the four logic outputs, namely:

[0101] 1. Vin_ov (logic output terminal 484), used to indicate overvoltage status;

[0102] 2. Vin_eov (logic output terminal 485), used to indicate an early overvoltage condition, which can serve as an early indication or warning of an overvoltage condition;

[0103] 3. Vin_uv (logic output terminal 486), used to indicate undervoltage status;

[0104] 4. Vin_euv (logic output terminal 487), used to indicate an early undervoltage condition, which can serve as an early indication or warning of an undervoltage condition.

[0105] It should be noted that the logic circuits for generating the above four signals can be designed in a convenient and known manner. For example, an AND gate can be used, whose inputs are the value of modeb, the inverse of the output signal (output terminal 415) and the inverse of blank, to generate the Vin_uv signal, which indicates an undervoltage state when it is a logic high level. Similarly, another AND gate can be input with the value of mode, the output signal (output terminal 415) and the inverse of blank to generate the Vin_ov signal, which indicates an overvoltage state when it is a logic high level. The output of an OR gate, whose input signals are Vin_ov (logic output terminal 484) and Vin_uv (logic output terminal 486), the output signal of which can be provided to line 351.

[0106] Figure 5 FIG. 1 is a timing diagram showing a signal waveform generated by the output of a comparison circuit based on a single comparator in one embodiment. Specifically, Figure 5 The waveforms of signals Vin (node ​​405), Vin_uv (logic output terminal 486), Vin_euv (logic output terminal 487), Vin_ov (logic output terminal 484), Vin_eov (logic output terminal 485), mode (line 481) and blank (line 483) are shown.

[0107] When Vin gradually rises from zero, mode and all logic outputs are at logic low levels except Vin_euv and Vin_uv which are at logic high levels. When Vin exceeds and is higher than the undervoltage reference / threshold voltage (Vth_uv = 4.2V) at t541, the Vin_uv signal becomes a logic low level. When Vin exceeds and is higher than the early undervoltage threshold (in one embodiment, Vth_euv = 5V) at t542, the early undervoltage signal (Vin_euv) becomes a logic low level. Vin continues to rise and exceeds the mode switching voltage (Vth_mode = 8V + VtripN1) at t543, at which time mode becomes a logic high level.

[0108] It is understandable that due to the stabilization delay, transient interference will occur at the output when the mode is switched (especially when the resistor branch changes). Therefore, a fixed width blanking pulse is generated to lock the output at the correct logic level until the circuit stabilizes. When the mode value changes from 0 to 1, the resistor branch switches and the threshold is changed to the threshold required for overvoltage detection. When Vin exceeds the early overvoltage threshold (in one embodiment, Vth_eov = 21V) at t544, the Vin_eov signal becomes a logic high level. Then, when Vin reaches the overvoltage threshold (Vth_ov = 22V) at t545, the Vin_ov signal becomes a logic high level.

[0109] On the contrary, when Vin gradually decreases from the highest voltage, all signals except Vin_uv and Vin_euv are at a logic high level. When Vin is lower than Vth_ov at t561, the Vin_ov signal becomes a logic low level. When Vin is lower than Vth_eov at t562, the Vin_eov signal becomes a logic low level. When Vin is lower than Vth_mode at t563, mode becomes a logic low level and a blanking signal (pulse) is generated to avoid transient interference during the stabilization process. When Vin is lower than Vth_euv at t564, the Vin_euv signal becomes a logic high level. When Vin is lower than Vth_uv at t565, the Vin_uv signal becomes a logic high level.

[0110] For ease of explanation, Figure 5 The ramp waveform of Vin is shown in Figure 1. Figure 4 The circuit in the figure is shown in Figure 1.16 after Vin has stabilized to its final value ( Figure 5 any value in the slope shown) before it starts to work (or is turned on), Figure 5 The logic levels of the logic signals shown in are also correct.

[0111] Therefore, the voltage detection module 350 uses a single comparator 410 and dual-mode operation to detect whether Vin (node ​​201) is below the undervoltage threshold or above the overvoltage threshold. This dual-mode design achieves seamless switching between modes while being able to detect 4 states (undervoltage, early undervoltage, overvoltage, and early overvoltage). It is further understood that the above design is an integrated, area-efficient, and low-power solution that can be used on-chip without the need for external devices.

[0112] 8. Conclusion

[0113] The "one embodiment", "an embodiment" or similar expressions mentioned in the specification means that the specific features, structures or characteristics described in connection with the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment", "in an embodiment" and similar expressions appearing throughout the specification may, but not necessarily, all refer to the same embodiment.

[0114] Although in the diagram, although each endpoint / node is shown as having a direct connection to other endpoints (i.e., "connected to"), it should be understood that there may be other additional components in the connection lines that are suitable for a particular environment, and therefore, these connections can be regarded as being "electrically coupled" to the same connection endpoint.

[0115] It should be understood that the specific types of transistors mentioned above (e.g., NMOS, PMOS, etc.) are only used as examples. However, for those skilled in the relevant art, by reading the public documents provided herein, alternative embodiments using different configurations and transistors will be obvious. For example, NMOS transistors can be replaced with PMOS (P-type MOS) transistors, while the connections of the power supply terminal and the ground terminal are exchanged accordingly.

[0116] Therefore, in this application, the power supply and ground terminals are referred to as constant reference potentials, the source (emitter) and drain (collector) of the transistor (providing a current path when the transistor is turned on and providing an open circuit when the transistor is turned off) are referred to as current terminals, and the gate (base) is referred to as the control terminal.

[0117] Although various embodiments of the present application have been described above, it should be understood that these embodiments are provided only as examples and are not intended to set limitations. Therefore, the breadth and scope of the present application should not be limited to the description of any specific embodiment above, but should be strictly defined in accordance with the claims and their equivalent principles.

Claims

1. A comparison circuit, characterized in that: The comparison circuit comprises: a comparator, configured to compare an input voltage of the comparator with a reference voltage of the comparator and generate an output signal of the comparator; a mode selector, configured to generate a mode value, wherein if the input voltage is lower than an intermediate voltage, the generated mode value is a first logic value, otherwise, the generated mode value is a second logic value; wherein the intermediate voltage is between a first reference voltage and a second reference voltage of interest, and the first reference voltage is lower than the second reference voltage; a first branch connected to a first node to receive the input voltage and generate a first voltage drop relative to the input voltage at a second node; wherein the first voltage drop is equal to a difference between the first reference voltage and a reference voltage of the comparator; a second branch connected to the first node to receive the input voltage and generate a second voltage drop relative to the input voltage at a third node; wherein the second voltage drop is equal to a difference between the second reference voltage and a reference voltage of the comparator; and A selection circuit is used to use one of the second node or the third node as an input terminal of the comparator according to the mode value, wherein the mode value indicates whether the output signal of the comparator represents a comparison with the first reference voltage or a comparison with the second reference voltage, and the output signal of the comparator indicates whether the input voltage is higher or lower than the reference voltage compared with it.

2. The comparison circuit according to claim 1, characterized in that: The first branch includes a first resistor, a first current source and a first switch connected in series, and the first resistor and the first current source jointly generate the first voltage drop; the second branch includes a second resistor, a second current source and a second switch connected in series, and the second resistor and the second current source jointly generate the second voltage drop; The selection circuit turns on only one of the first switch and the second switch according to the mode value.

3. The comparison circuit according to claim 2, characterized in that: The mode selector comprises: a third resistor and a third current source connected in series with the first node to jointly generate a voltage drop at a fourth node that is equal to the intermediate voltage relative to the input voltage; and A first inverter is connected to the fourth node and is used to generate the mode value.

4. The comparison circuit according to claim 3, characterized in that: The selection circuit comprises: A second inverter connected in series with the first inverter, wherein an output terminal of the second inverter is connected to the first switch, and an output terminal of the first inverter is connected to the second switch.

5. The comparison circuit according to claim 4, characterized in that: The input voltage is the instantaneous voltage of the input signal.

6. A power stage of a switching converter, characterized in that include: A high-side switch and a low-side switch are connected in series between a power supply and a constant reference potential, the power supply provides an input voltage, the high-side switch and the low-side switch are controlled by a first drive signal and a second drive signal, respectively, the first drive signal and the second drive signal are turned on in a first time period and a second time period respectively to drive a corresponding current in the inductor; a gate driver for generating the first drive signal and the second drive signal based on a control signal received from a phase controller, wherein the control signal received during the first time period has a first logic level and the control signal received during the second time period has a second logic level; and Voltage detection module, including: A comparator, used to compare an input voltage of the comparator with a reference voltage of the comparator and generate an output signal of the comparator; when the input voltage of the comparator is less than the reference voltage of the comparator, the output signal of the comparator is a first output value, otherwise it is a second output value; a mode selector, configured to generate a mode value, wherein if the input voltage is lower than the intermediate voltage, the generated mode value is a first logic value, otherwise, the generated mode value is a second logic value; wherein the intermediate voltage is between a first reference voltage and a second reference voltage of interest, and the first reference voltage is lower than the second reference voltage; A first branch, connected to a first node to receive the input voltage, and generating a first voltage drop relative to the input signal at a second node; wherein the first voltage drop is equal to a difference between the first reference voltage and a reference voltage of the comparator; a second branch connected to the first node to receive the input voltage and generate a second voltage drop relative to the input voltage at a third node; wherein the second voltage drop is equal to a difference between the second reference voltage and a reference voltage of the comparator; and A selection circuit is used to use one of the second node or the third node as an input terminal of the comparator according to the mode value, wherein the mode value indicates whether the output signal of the comparator represents a comparison with the first reference voltage or a comparison with the second reference voltage, and the output signal of the comparator indicates whether the input voltage is higher or lower than the reference voltage for comparison.

7. The power stage according to claim 6, characterized in that Also includes: A logic block, configured to send a first signal to the gate driver when the mode value is equal to the first logic value and the output signal of the comparator is equal to the first output value, or when the mode value is equal to the second logic value and the output signal of the comparator is equal to the second output value, and to send a second signal otherwise; wherein, if it is determined that the input voltage is lower than the first reference voltage or higher than the second reference voltage, the first drive signal and the second drive signal generated by the gate driver are both in an off state.

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