Circuit board and electronic device package

Abstract

The invention provides a circuit board and an electronic device package. The circuit board includes: a substrate having a first surface and a second surface opposite to each other, including an insulating layer disposed between the first surface and the second surface, and having a cavity penetrating the substrate in a direction perpendicular to the first surface; a first wiring pattern embedded in the insulating layer on the first surface to achieve signal transmission; and a first enhancement pattern embedded in the insulating layer on the first surface, disposed around the cavity to be spaced apart from an edge of the cavity, and configured to be separated from the first wiring pattern.

Description

Technical Field

[0001] The present disclosure relates to a circuit board and an electronic device package. Background Art

[0002] With the trend of miniaturization and multifunctionality of electronic products, semiconductor packaging technology is becoming highly integrated and high-performance. The existing interposer POP (package-on-package) packaging technology has limitations in heat dissipation effect due to the thickness restriction of the mounted chip. Therefore, the panel level packaging (PLP) packaging technology that relaxes the chip thickness restriction and improves the heat dissipation effect is attracting attention.

[0003] PLP package uses prepreg (PPG) type printed circuit board. PPG is made of resin and glass fabric stacked together.

[0004] If a smear removal process is performed after cavity processing, the glass fiber is etched, which may cause cracks in the PPG resin area due to mechanical / physical loads during the packaging process.

[0005] These cracks may cause coating defects when coating the photosensitive dielectric material in the PLP packaging process. Therefore, it is necessary to improve the structure of the circuit board and the method of manufacturing the circuit board to ensure the quality of the cavity area of ​​the printed circuit board as the chip mounting area. Summary of the invention

[0006] An aspect of the embodiment seeks to provide a circuit board and an electronic device package capable of suppressing cracks in a resin region at an edge of a cavity of a printed circuit board.

[0007] However, the embodiments of the present disclosure are not limited to the above-described embodiments, and may be variously extended within the scope of the technical concept included in the present disclosure.

[0008] A circuit board according to an embodiment includes: a substrate having a first surface and a second surface opposite to each other, including an insulating layer arranged between the first surface and the second surface, and having a cavity penetrating the substrate in a direction perpendicular to the first surface; a first wiring pattern embedded in the insulating layer on the first surface to achieve signal transmission; and a first reinforcement pattern embedded in the insulating layer on the first surface, arranged around the cavity to be spaced apart from an edge of the cavity, and separated from the first wiring pattern.

[0009] The first reinforcement pattern may include metal.

[0010] The first reinforcement pattern may be electrically isolated.

[0011] The first reinforcement pattern may be covered by the insulating layer such that the first reinforcement pattern is not exposed to the cavity.

[0012] The first reinforcement pattern may have the same height as that of the first wiring pattern.

[0013] The first wiring pattern may be spaced apart from the first reinforcement pattern in a direction away from the cavity.

[0014] The circuit board may also include: a second wiring pattern, which is arranged on the second surface of the substrate to achieve signal transmission; a second reinforcement pattern, which is arranged on the second surface of the substrate, surrounds the cavity and is spaced apart from the edge of the cavity, and is separated from the second wiring pattern; and a via, which is embedded in the insulating layer and connects the first wiring pattern and the second wiring pattern to each other.

[0015] The second reinforcement pattern may protrude from the second surface to have the same height as that of the second wiring pattern.

[0016] The second wiring pattern may be spaced apart from the second reinforcement pattern in a direction away from the cavity.

[0017] The first reinforcement pattern and the second reinforcement pattern may be disposed such that at least a portion of the first reinforcement pattern and the second reinforcement pattern overlap each other in a direction perpendicular to the first surface.

[0018] The first reinforcement pattern may include a plurality of reinforcement pads spaced apart from each other along the edge of the cavity.

[0019] The first reinforcement pattern may be configured to be continuously connected along the edge of the cavity and to surround the cavity.

[0020] The cavity may include four sides, and the first reinforcement pattern may include a reinforcement pad disposed at each of the four sides.

[0021] The first reinforcement pattern may extend from the first surface into the insulating layer.

[0022] A central axis of the first reinforcement pattern along a thickness direction of the circuit board may be offset from a central axis of the second reinforcement pattern along the thickness direction of the circuit board.

[0023] According to another embodiment, an electronic device package includes: a substrate having a first surface and a second surface opposite to each other, including an insulating layer arranged between the first surface and the second surface, and having a cavity penetrating the substrate in a direction perpendicular to the first surface; a first wiring pattern embedded in the insulating layer on the first surface to achieve signal transmission; a first reinforcement pattern embedded in the insulating layer on the first surface, arranged around the cavity to be spaced apart from an edge of the cavity, and separated from the first wiring pattern; a redistribution layer arranged on the first surface of the substrate; and an electronic device accommodated in the cavity and connected to the redistribution layer.

[0024] The electronic device package may further include: an insulating protection layer disposed between the first surface of the substrate and the redistribution layer to cover the first reinforcement pattern.

[0025] The first reinforcement pattern may be electrically isolated.

[0026] The first reinforcement pattern may be covered by the insulating layer such that the first reinforcement pattern is not exposed to the cavity.

[0027] The first wiring pattern may be spaced apart from the first reinforcement pattern in a direction away from the cavity.

[0028] According to the circuit board of the embodiment, packaging yield is ensured by suppressing the occurrence of cracks in the resin region at the edge of the cavity during a panel level packaging (PLP) process.

[0029] In addition, coating defects can be improved when coating photosensitive dielectric (PID) materials in the PLP process. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a cross-sectional view illustrating an electronic device package according to an embodiment, the electronic device package showing that an electronic device is mounted on a circuit board.

[0031] Figures 2 to 14 2 is a cross-sectional process diagram illustrating a method of manufacturing a circuit board according to an embodiment.

[0032] Fig.15 is a bottom view of a circuit board according to an embodiment.

[0033] Figures 16 to 18 is a top view of a circuit board according to other embodiments. DETAILED DESCRIPTION

[0034] Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. The drawings and descriptions are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same or similar reference numerals represent the same or similar elements. In the drawings, some constituent elements are exaggerated, omitted or schematically shown, and the size of each constituent element does not fully reflect the actual size.

[0035] The drawings are only used to help understand the exemplary embodiments disclosed in this specification, and it should be understood that the technical concepts disclosed herein are not limited to the drawings, but include all modifications, equivalents or alternatives falling within the concepts and technical scope of the present disclosure.

[0036] Although the terms "first", "second", etc. are used to explain various constituent elements, the constituent elements are not limited by these terms. These terms are only used to distinguish one constituent element from another constituent element.

[0037] Furthermore, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. More specifically, when an element is referred to as being "directly on" another element, there are no intervening elements. Furthermore, when an element is referred to as being "on" or "over" a reference element, it can be located above or below the reference element and is not necessarily referred to as being "on" or "over" the reference element in a direction opposite to the direction of gravity.

[0038] Throughout the specification, the terms "include" or "have" are intended to list the presence of stated features, integers, steps, operations, constituent elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, constituent elements, components and / or combinations thereof. Therefore, unless explicitly described to the contrary, the words "include" or "have" will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0039] Additionally, throughout the specification, “in a plan view” or “on a plane” means observing a target portion from above, and “in a cross-sectional view” or “on a cross section” means observing a cross section formed by vertically cutting the target portion from the side.

[0040] Throughout the specification, the term "connected" not only means that two or more constituent elements are directly connected, but also may mean that two or more constituent elements are indirectly connected through another constituent element, that two or more constituent elements are electrically connected as well as physically connected, or that two or more constituent elements may be integrated while being represented by different names according to position or function.

[0041] Figure 1is a cross-sectional view illustrating an electronic device package according to an embodiment, the electronic device package showing that an electronic device is mounted on a circuit board.

[0042] Reference Figure 1 According to an embodiment, the electronic device package 100 may be configured to mount the electronic device 70 on the circuit board 101. The electronic device 70 may include various devices such as active components, passive components, and integrated circuits (ICs), and may be, for example, a semiconductor chip. The circuit board 101 may be used for a semiconductor package and may be configured as a printed circuit board.

[0043] The circuit board 101 includes a substrate 110 having a first surface 110a and a second surface 110b opposite to each other and including an insulating layer 112, and wiring patterns 121 and 122 disposed inside or on the surface of the substrate 110. The substrate 110 has a cavity 119 penetrating the substrate 110 in a direction perpendicular to the first surface 110a. Reinforcement patterns 131 and 132 may be disposed inside and / or on the surface of the insulating layer 112 around the cavity 119.

[0044] The wiring patterns 121 and 122 may include a first wiring pattern 121 and a second wiring pattern 122, the first wiring pattern 121 being embedded in the insulating layer 112 on the first surface 110a, and the second wiring pattern 122 being disposed on the second surface 110b of the substrate 110. The first wiring pattern 121 and the second wiring pattern 122 may both be configured to implement signal transmission. The first wiring pattern 121 and the second wiring pattern 122 may be connected to each other through a via 124 embedded in the insulating layer 112.

[0045] The reinforcement patterns 131 and 132 may include a first reinforcement pattern 131 embedded in the insulating layer 112 on the first surface 110a. In other words, the first reinforcement pattern 131 extends from the first surface 110a into the insulating layer 112. The first reinforcement pattern 131 may be disposed around the cavity 119 to be spaced apart from the edge of the cavity 119, and may be spaced apart from the first wiring pattern 121. That is, the first reinforcement pattern 131 may be configured as a physical isolation pattern or an electrical isolation pattern, so that the first reinforcement pattern 131 is not used for signal transmission, or the first reinforcement pattern 131 may be connected to a ground pattern. The first reinforcement pattern 131 may be electrically isolated. The first reinforcement pattern 131 may include a metal, specifically, copper (Cu).

[0046] Based on the direction parallel to the first surface 110a, the first reinforcement pattern 131 is covered by the insulating layer 112 so that the first reinforcement pattern 131 is not exposed to the cavity 119. In the height measured in the direction perpendicular to the first surface 110a, the first reinforcement pattern 131 may have the same height as the height of the first wiring pattern 121. Here, "the same height" may include the case where the height may vary due to limitations and / or errors in the manufacturing process or measurement method in the relevant technical field. The first wiring pattern 121 may be spaced apart from the first reinforcement pattern 131 in the direction away from the cavity 119.

[0047] The reinforcement patterns 131 and 132 may include a second reinforcement pattern 132 disposed on the second surface 110b of the substrate 110. The second reinforcement pattern 132 may be disposed around the cavity 119 to be spaced apart from the edge of the cavity 119, and may be configured to be spaced apart from the second wiring pattern 122. That is, the second reinforcement pattern 132 may be configured as a physical isolation pattern or an electrical isolation pattern so that the second reinforcement pattern 132 is not used for signal transmission. The second reinforcement pattern 132 may include metal, specifically, copper (Cu).

[0048] The second reinforcement pattern 132 may protrude from the second surface 110b to have the same height as that of the second wiring pattern 122. Here, "the same height" may include a case where the height may vary due to limitations and / or errors in a manufacturing process or a measurement method in the relevant technical field. The second wiring pattern 122 may be arranged to be spaced apart from the second reinforcement pattern 132 in a direction away from the cavity 119. The second reinforcement pattern 132 may be arranged so that at least a portion of the second reinforcement pattern 132 overlaps with the first reinforcement pattern 131 along a direction perpendicular to the first surface 110a. Alternatively, the second reinforcement pattern 132 overlaps with at least a portion of the first reinforcement pattern 131 along a direction perpendicular to the first surface 110a. For example, the central axis of the first reinforcement pattern 131 along the thickness direction of the circuit board 100 (the direction perpendicular to the first surface 110a) may deviate from the central axis of the second reinforcement pattern 132 along the thickness direction of the circuit board 100.

[0049] As described above, by providing the metal reinforcement patterns 131 and 132 around the cavity 119 on the substrate 110 including the insulating resin, cracks may be suppressed from occurring in the resin region on the edge of the cavity 119 during a panel level packaging (PLP) process.

[0050] The electronic device package 100 may be a fan-out type semiconductor package, and in the cavity 119 of the circuit board 101, the connection end of the electronic device 70 may be disposed at one side of the first surface 110a of the substrate 110. The redistribution layer 150 may be disposed on the first surface 110a of the substrate 110 so that the electronic device 70 may be connected, and the first wiring pattern 121 of the circuit board 101 may also be connected to the redistribution layer 150. The connection pad 151 is disposed on the other surface of the redistribution layer 150, and the connection terminal 154 may be connected to the connection pad 151. Adjacent connection pads 151 may be spaced apart by an insulating member 152.

[0051] At least a portion of the electronic device 70 and the second surface 110b of the substrate 110 may be covered by the sealing member 92. The sealing member 92 may cover at least a portion of the second reinforcement pattern 132 and the second wiring pattern 122 disposed on the second surface 110b. The second wiring pattern 122 disposed on the second surface 110b may be partially exposed from the sealing member 92 and used as a connection pad.

[0052] The insulating protective layer 141 may be disposed between the first surface 110a of the substrate 110 and the redistribution layer 150. The insulating protective layer 141 may be an underfill resin that may fill the gap to protect the connection between the electronic device 70 and the redistribution layer 150. The insulating protective layer 141 may include a photosensitive dielectric (PID) resin disposed between the substrate 110 and the redistribution layer 150. The first surface 110a of the circuit board 101 is provided with a first reinforcement pattern 131 of a metal surrounding an edge of the cavity 119, thereby reducing coating defects when the photosensitive dielectric resin is coated in the PLP process.

[0053] Figures 2 to 14 2 is a cross-sectional process diagram illustrating a method of manufacturing a circuit board according to an embodiment.

[0054] Reference Figures 2 to 5 , a carrier substrate 60 is prepared, a first seed layer 81 is disposed on at least one surface of the carrier substrate 60, and a first wiring pattern layer 121A and a first reinforcement pattern layer 131A are formed on the first seed layer 81 by a circuit forming process. The carrier substrate 60 may be a substrate having a copper foil layer 62 stacked on both sides of an insulating material 61, and the first seed layer 81 and the copper foil layer 62 may be separated from each other (see Figure 2 ). The plating resist pattern 83 formed by exposure and development may be formed in a portion of the carrier substrate 60 other than a portion where the first wiring pattern layer 121A and the first reinforcement pattern layer 131A are to be formed (see Figure 3 The first wiring pattern layer 121A and the first reinforcement pattern layer 131A may be formed by plating a conductive metal on a portion of the first seed layer 81 exposed by the opening of the patterned plating resist pattern 83 (see Figure 4 After forming the first wiring pattern layer 121A and the first reinforcement pattern layer 131A, the plating resist pattern 83 is removed (see Figure 5 ).

[0055] The first seed layer 81 can be applied without limitation as long as it is a conductive metal used as a circuit in the field of circuit boards, and copper (Cu) is generally used. The first wiring pattern layer 121A and the first reinforcement pattern layer 131A can be connected to the first seed layer 81 of the carrier substrate 60, and can include the same type of metal as the first seed layer 81. For example, the first seed layer 81, the first wiring pattern layer 121A, and the first reinforcement pattern layer 131A can include copper (Cu).

[0056] In the present embodiment, it is shown that the first wiring pattern layer 121A and the first reinforcement pattern layer 131A are formed on both sides of the carrier substrate 60, but the first wiring pattern layer 121A and the first reinforcement pattern layer 131A may be formed only on one surface of the carrier substrate 60, and this also falls within the scope of the present disclosure.

[0057] Reference Figure 6 , the insulating layer 112 is stacked so that the first wiring pattern layer 121A and the first reinforcement pattern layer 131A are embedded in the insulating layer 112, and the second seed layer 85 is formed on the upper surface of the insulating layer 112. The second seed layer 85 may be formed to form the second wiring pattern layer 122A and the second reinforcement pattern layer 132A. Any conductive metal may be used without limitation, but copper may be generally used.

[0058] The insulating layer 112 may include a resin insulating layer. The insulating layer 112 may be made of a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or an insulating material formed by impregnating a reinforcing material such as glass fiber or an inorganic filler in the above resin. For example, the insulating layer 112 may be made of a prepreg. The insulating layer 112 may also include, but is not limited to, a thermosetting resin and / or a photocurable resin.

[0059] Reference Figures 7 to 10 , the second wiring pattern layer 122A and the second reinforcement pattern layer 132A may be formed on the insulating layer 112 by a circuit forming process. The second wiring pattern layer 122A and the second reinforcement pattern layer 132A may be formed in a method similar to the method of forming the first wiring pattern layer 121A and the first reinforcement pattern layer 131A. At this time, in order to form a via 124 connecting the first wiring pattern layer 121A and the second wiring pattern layer 122A, the insulating layer 112 may be partially etched to expose a portion of the first wiring pattern layer 121A (see Figure 7 ), a plating process may be performed on the exposed portion of the first wiring pattern layer 121A.

[0060] The plating resist pattern 87 formed by exposure and development may be formed in a portion of the second seed layer 85 except for a portion where the second wiring pattern layer 122A and the second reinforcement pattern layer 132A are to be formed (see Figure 8 The second wiring pattern layer 122A and the second reinforcement pattern layer 132A may be formed by plating a conductive metal on portions of the second seed layer 85 exposed by the openings of the patterned plating resist pattern 87 (see Fig. 9 After forming the second wiring pattern layer 122A and the second reinforcement pattern layer 132A, the plating resist pattern 87 is removed (see Fig.10 ). This completes the embedded pattern substrate portions on both sides of the carrier substrate 60.

[0061] According to the illustrated embodiment, each embedded pattern substrate portion is illustrated as including one insulating layer 112 and first and second wiring pattern layers 121A and 122A, which are metal layers disposed on both sides of the insulating layer 112. However, the present disclosure is not limited thereto, and each embedded pattern substrate portion may include a greater number of built-up insulating layers and a greater number of built-up wiring pattern layers, which is also within the scope of the present disclosure.

[0062] Reference Fig.11 , the copper foil layer 62 of the carrier substrate 60 is separated from the insulating material 61 to prepare an embedded pattern substrate having an ETS (embedded trace substrate) structure. A pair of embedded pattern substrates can be obtained by separating the insulating material 61 and the copper foil layer 62 of the carrier substrate 60, and a separate process can be applied to each of the pair of embedded pattern substrates.

[0063] Reference Fig.12 , yes Fig.11 The embedded pattern substrate obtained in the embodiment of the present invention is soft-etched to remove the first seed layer 81 and the second seed layer 85. After removing the first seed layer 81 and the second seed layer 85, the first wiring pattern layer 121A and the first reinforcement pattern layer 131A embedded in the insulating layer 112 respectively form the first wiring pattern 121 and the first reinforcement pattern 131. The second wiring pattern layer 122A and the second reinforcement pattern layer 132A provided on one surface of the insulating layer 112 respectively form the second wiring pattern 122 and the second reinforcement pattern 132.

[0064] Reference Fig.13 and Fig.14 , etched in Fig.12 The center of the embedded pattern substrate obtained in the embodiment is drilled to form a cavity 119. The cavity process can be performed by selecting from various known processes, such as laser drilling, mechanical drilling, router processing and etching. The electronic device 70 can be accommodated in the cavity 119 (see Fig.14 ).

[0065] Fig.15 is a bottom view of a circuit board according to an embodiment. Fig.15 A first surface of a circuit board on which an embedded pattern is formed is shown.

[0066] Reference Fig.15 The circuit board 102 according to the present embodiment includes a first reinforcement pattern 1312 embedded in the insulating layer 112 on the first surface 110a of the substrate 110. The first reinforcement pattern 1312 may include a plurality of reinforcement pads disposed along an edge of the cavity 119 to be spaced apart from each other.

[0067] The ground pattern 138 may be disposed on the first surface 110a of the substrate 110, and the ground pattern 138 may have a shape surrounding the cavity 119. At this time, a plurality of reinforcement pads of the first reinforcement pattern 1312 may be connected to the ground pattern 138. That is, the first reinforcement pattern 1312 may have a shape protruding toward the cavity 119 from an edge of the ground pattern 138 surrounding the cavity 119 in a direction parallel to the first surface 110a.

[0068] Figures 16 to 18 is a top view of a circuit board according to other embodiments.

[0069] Reference Fig.16 The circuit board 103 according to the present embodiment includes a first reinforcement pattern 1313 embedded in the insulating layer 112 on the first surface 110a of the substrate 110, and the first reinforcement pattern 1313 may include a plurality of reinforcement pads spaced apart from each other along the edge of the cavity 119. At this time, the plurality of reinforcement pads of the first reinforcement pattern 1313 may each have an isolated shape spaced apart from the ground pattern 138 surrounding the cavity 119.

[0070] Reference Fig.17 The circuit board 104 according to the present embodiment includes a first reinforcement pattern 1314 embedded in the insulating layer 112 on the first surface 110a of the substrate 110, and the first reinforcement pattern 1314 may include a reinforcement pad disposed at each of four sides of the cavity 119. At this time, the plurality of reinforcement pads of the first reinforcement pattern 1314 may each have an isolated arrangement spaced apart from the ground pattern 138 surrounding the cavity 119.

[0071] Reference Fig.18 The circuit board 105 according to the present embodiment includes a first reinforcement pattern 1315 embedded in the insulating layer 112 on the first surface 110a of the substrate 110, and the first reinforcement pattern 1315 may be configured to be continuously connected along the edge of the cavity 119 and surround the cavity 119. At this time, the first reinforcement pattern 1315 may have an isolated shape spaced apart from the ground pattern 138 surrounding the cavity 119.

[0072] While the present disclosure has been described in connection with what are presently considered to be practical embodiments, it should be understood that the present disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A circuit board, comprising: a substrate having a first surface and a second surface opposite to each other, including an insulating layer disposed between the first surface and the second surface, and having a cavity penetrating the substrate in a direction perpendicular to the first surface; a first wiring pattern embedded in the insulating layer on the first surface to achieve signal transmission; as well as A first reinforcement pattern is embedded in the insulating layer on the first surface, is disposed around the cavity to be spaced apart from an edge of the cavity, and is separated from the first wiring pattern.

2. The circuit board according to claim 1, wherein: The first reinforcement pattern includes metal.

3. The circuit board according to claim 1, wherein: The first reinforcement pattern is electrically isolated.

4. The circuit board according to claim 1, wherein: The first reinforcement pattern is covered by the insulating layer so that the first reinforcement pattern is not exposed to the cavity.

5. The circuit board according to claim 1, wherein: The first reinforcement pattern has the same height as that of the first wiring pattern.

6. The circuit board according to claim 1, wherein: The first wiring pattern is spaced apart from the first reinforcement pattern in a direction away from the cavity.

7. The circuit board according to claim 1, further comprising: A second wiring pattern, disposed on the second surface of the substrate to achieve signal transmission; a second reinforcing pattern disposed on the second surface of the substrate, surrounding the cavity and spaced apart from the edge of the cavity, and separated from the second wiring pattern; as well as A via is embedded in the insulating layer and connects the first wiring pattern and the second wiring pattern to each other.

8. The circuit board according to claim 7, wherein: The second reinforcement pattern protrudes from the second surface to have the same height as that of the second wiring pattern.

9. The circuit board according to claim 7, wherein: The second wiring pattern is spaced apart from the second reinforcement pattern in a direction away from the cavity.

10. The circuit board according to claim 7, wherein: The first reinforcement pattern and the second reinforcement pattern are disposed such that the second reinforcement pattern and at least a portion of the first reinforcement pattern overlap each other in a direction perpendicular to the first surface.

11. The circuit board according to claim 1, wherein: The first reinforcement pattern includes a plurality of reinforcement pads spaced apart from each other along the edge of the cavity.

12. The circuit board according to claim 1, wherein: The first reinforcement pattern is configured to be continuously connected along the edge of the cavity and to surround the cavity.

13. The circuit board according to claim 1, wherein: The cavity comprises four sides, And the first reinforcement pattern includes a reinforcement pad disposed at each of the four side surfaces.

14. The circuit board according to claim 7, wherein: The first reinforcement pattern extends from the first surface into the insulating layer.

15. The circuit board according to claim 14, wherein: A central axis of the first reinforcement pattern along a thickness direction of the circuit board is offset from a central axis of the second reinforcement pattern along the thickness direction of the circuit board.

16. An electronic device package, comprising: a substrate having a first surface and a second surface opposite to each other, including an insulating layer disposed between the first surface and the second surface, and having a cavity penetrating the substrate in a direction perpendicular to the first surface; a first wiring pattern embedded in the insulating layer on the first surface to achieve signal transmission; a first reinforcing pattern embedded in the insulating layer on the first surface, disposed around the cavity to be spaced apart from an edge of the cavity, and separated from the first wiring pattern; a redistribution layer disposed on the first surface of the substrate; as well as An electronic device is received in the cavity and connected to the redistribution layer.

17. The electronic device package of claim 16, further comprising: An insulating protection layer is disposed between the first surface of the substrate and the redistribution layer to cover the first reinforcement pattern.

18. The electronic device package of claim 16, wherein: The first reinforcement pattern is electrically isolated.

19. The electronic device package of claim 16, wherein: The first reinforcement pattern is covered by the insulating layer so that the first reinforcement pattern is not exposed to the cavity.

20. The electronic device package of claim 16, wherein: The first wiring pattern is spaced apart from the first reinforcement pattern in a direction away from the cavity.

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