Instruction stream generation method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides an instruction stream generation method and device, electronic equipment and a storage medium, and relates to the technical field of computers, and the method comprises the steps: obtaining instruction stream description information generated based on a preset operation code sequence; determining a first register code corresponding to each instruction description entry based on a register identifier corresponding to each instruction description entry in the instruction stream description information; the first register codes corresponding to the same register identifier are the same; and based on the first register codes and the operation code identifiers corresponding to the instruction description entries in the instruction stream description information, generating first instructions corresponding to the instruction description entries, and obtaining a first instruction stream formed by the first instructions corresponding to the instruction description entries. According to the scheme, the instruction streams with the fixed instruction sequence and the register dependency relationship can be generated, the problem of the processor core can be accurately positioned when the instruction streams are used for testing, and the testing accuracy of the instruction streams used for testing the processor core can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, and in particular to an instruction stream generation method, device, electronic device and storage medium. Background Art

[0002] At present, with the continuous development of computer technology, the design of the central processing unit (CPU) is becoming more and more complex. How to verify the CPU during the design and development process is becoming more and more important in the CPU development process.

[0003] In the related art, an instruction generator is usually used to randomly generate a continuous stream of instruction streams to input into the simulated CPU core or CPU physical core, and the CPU is tested by observing the processing and response of these instruction streams. In these instruction streams, not only instructions with different opcodes are required, but also instruction pairs consisting of opcode pairs with dependencies are required, so as to test whether the CPU can correctly process different instructions and instruction combinations.

[0004] However, when testing by randomly selecting opcodes and randomly generating instruction streams, due to the complexity of the processor core, a completely random instruction stream will cause the test results to be non-reproducible, and occasional errors cannot be accurately located. It is difficult to accurately locate defects in the processor core. Therefore, when testing the processor core using the instruction stream generated by the prior art, there is a problem of poor test accuracy. Summary of the invention

[0005] The embodiments of the present invention provide an instruction stream generation method, device, electronic device and storage medium, which can generate an instruction stream with high test accuracy when testing a processor core.

[0006] In order to solve the above problem, an embodiment of the present invention discloses an instruction stream generation method, the method comprising: Acquire instruction flow description information generated based on a preset operation code sequence; wherein the instruction flow description information includes instruction description entries consisting of operation code identifiers and register identifiers corresponding to each preset operation code in the preset operation code sequence; Determine, based on the register identifier corresponding to each instruction description entry in the instruction stream description information, a first register code corresponding to each instruction description entry; wherein first register codes corresponding to the same register identifier are the same; Based on the first register code and operation code identifier corresponding to each instruction description entry in the instruction stream description information, a first instruction corresponding to each instruction description entry is generated to obtain a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein the first instruction stream is used to test the central processing unit.

[0007] On the other hand, an embodiment of the present invention discloses an instruction stream generating device, the device comprising: An acquisition module, used to acquire instruction flow description information generated based on a preset operation code sequence; wherein the instruction flow description information comprises instruction description entries consisting of operation code identifiers and register identifiers corresponding to each preset operation code in the preset operation code sequence; an encoding module, configured to determine a first register encoding corresponding to each instruction description entry based on a register identifier corresponding to each instruction description entry in the instruction stream description information; wherein first register encodings corresponding to the same register identifier are the same; An instruction stream module is used to generate a first instruction corresponding to each instruction description entry based on the first register code and operation code identifier corresponding to each instruction description entry in the instruction stream description information, and obtain a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein the first instruction stream is used to test the central processing unit.

[0008] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the aforementioned method.

[0009] The embodiment of the present invention further discloses a computer-readable storage medium on which instructions are stored. When executed by one or more processors, the processors execute the method as described above.

[0010] The embodiment of the present invention includes the following advantages: in the instruction stream generation method provided in the embodiment of the present invention, instruction stream description information generated based on a preset operation code sequence is obtained; wherein, the instruction stream description information includes instruction description entries consisting of operation code identifiers and register identifiers corresponding to each preset operation code in the preset operation code sequence; based on the register identifiers corresponding to each instruction description entry in the instruction stream description information, the first register codes corresponding to each instruction description entry are determined; wherein, the first register codes corresponding to the same register identifiers are the same; based on the first register codes and operation code identifiers corresponding to each instruction description entry in the instruction stream description information, the first instructions corresponding to each instruction description entry are generated, and the first instruction stream consisting of the first instructions corresponding to each instruction description entry is obtained. In this way, an instruction stream with a fixed instruction sequence can be automatically generated through a preset operation code sequence, and the instructions in the generated instruction stream can share the same register encoding, so that the same register corresponding to the same register encoding is operated through the same or different instructions in the instruction stream with a fixed instruction sequence, and a register dependency relationship is generated. Therefore, an instruction stream with a fixed instruction sequence and a register dependency relationship can be generated through this scheme, and when these instruction streams are tested, it is helpful to accurately locate the problem of the processor core, and it is helpful to improve the test accuracy of the instruction stream when the processor core is tested. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0012] Figure 1 is a flowchart of a method for generating an instruction stream provided by an embodiment of the present invention; Figure 2 is a block diagram of an instruction stream generating device provided by an embodiment of the present invention; Figure 3 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] Reference Figure 1, shows a flow chart of the steps of an instruction stream generation method provided by an embodiment of the present invention, such as Figure 1 As shown, the method may specifically include the following steps: Step 101, obtaining instruction flow description information generated based on a preset opcode sequence; wherein the instruction flow description information includes instruction description entries consisting of opcode identifiers and register identifiers corresponding to each preset opcode in the preset opcode sequence.

[0015] In an embodiment of the present invention, a preset opcode sequence represents a sequence formed by arranging a plurality of opcodes in a certain order. The preset opcode sequence may consist of opcodes only, and the preset opcode sequence may also be determined by extracting opcodes corresponding to each instruction in a preset instruction stream. Exemplarily, a preset opcode sequence consisting of three opcodes may be [ADD, SUB, ADD]. The preset instruction stream may represent an instruction stream that has been generated. For example, if a user generates an instruction stream by other means and hopes to continue to generate a similar instruction stream according to the instruction sequence of the instruction stream for further testing, the instruction stream may be used as the preset instruction stream.

[0016] In an embodiment of the present invention, corresponding instruction flow description information can be generated according to a preset opcode sequence. The instruction flow description information includes instruction description entries that correspond one to one in the preset opcode sequence, and each instruction description entry can be composed of an opcode identifier and a register identifier. The opcode identifier is used to indicate the opcode corresponding to the instruction description entry in the preset opcode sequence.

[0017] Depending on the different opcode identifiers corresponding to the instruction description entries, the number and type of register identifiers corresponding to the instruction description entries may also be different. For example, the register identifier can be further divided into a destination register identifier and a source register identifier. Exemplarily, since the opcode identifier ADD can be used to add register data in two source registers and store the addition result in a destination register, the instruction description entry corresponding to the opcode identifier ADD can have 2 source register identifiers (rs0, rs1) and 1 destination register identifier (rd); since the opcode identifier LUI (Load Upper Immediate) is used to load an immediate value into the high bit of a register, its corresponding instruction description entry may have only 1 destination register identifier (rd).

[0018] Using the above example, the instruction flow description information corresponding to the preset operation code sequence [ADD, SUB, ADD] can be described in the following Table 1: Table 1

[0019] As described in Table 1 above, the operation code identifier corresponding to the first instruction description entry in the instruction stream description information is ADD, and the corresponding three register identifiers are rd=udf_str0, rs0=12, rs1=20, where udf_str0 is the register identifier of the destination register rd, and 12 and 20 are the register identifiers of the source registers rs0 and rs1 respectively; the operation code identifier corresponding to the second instruction description entry is SUB, and the corresponding three register identifiers are rd=udf_str1, rs0=32, rs1=7, where udf_str1 is the register identifier of the destination register rd, and 32 and 7 are the register identifiers of the source registers rs0 and rs1 respectively; the operation code identifier corresponding to the third instruction description entry is ADD, and the corresponding three register identifiers are rd=3, rs0=udf_str0, rs1=udf_str1, where 3 is the register identifier of the destination register rd, and udf_str0 and udf_str1 are the register identifiers of the source registers rs0 and rs1 respectively. It should be noted that the above register identifiers are expressed in the form of numbers, strings, etc., and the embodiment of the present invention does not make any specific limitation.

[0020] Step 102: Determine a first register code corresponding to each instruction description entry based on a register identifier corresponding to each instruction description entry in the instruction flow description information; wherein first register codes corresponding to the same register identifier are the same.

[0021] In an embodiment of the present invention, the instruction flow description information may include one or more groups of identical register identifiers, that is, different instruction description entries in the instruction flow description information may have the same register identifier, and the same instruction description entry may also have the same register identifier. As shown in Table 1 above, the rd register identifier of the first instruction description entry in the instruction flow description information may be the same as the rs0 register identifier of the third instruction description entry.

[0022] In an embodiment of the present invention, a corresponding register code can be generated for each register identifier in the instruction stream description information, thereby obtaining a first register code corresponding to each instruction description entry. During the generation process, the first register codes generated for the same register identifier can be made the same.

[0023] In an embodiment of the present invention, the same register identifiers possessed by different instruction description entries may be used to indicate that the instructions to be generated by different instruction description entries use the same registers, so that there may be dependencies between the registers operated by the instructions generated by different or the same instruction description entries, and these dependencies may include but are not limited to write-after-read dependencies, read-after-write dependencies, write-after-write dependencies, read-after-read dependencies, etc. Exemplarily, the write-after-read dependency indicates that during the execution of the instruction stream, the source register used when the subsequent instruction is executed is the same as the destination register of the preceding instruction, that is, the execution of the subsequent instruction uses the output data of the preceding instruction as its input data.

[0024] Specifically, the method of generating the corresponding first register code according to the register identifier can be a rule-based calculation, for example, the register identifier can be used as the input of an encoding function, and the output of the encoding function can be obtained as the first register code corresponding to the register identifier; it can also be randomly generated, for example, a number can be randomly generated for each register identifier as the corresponding first register code; it can also be randomly selected within a preset code range, for example, a register code library can be pre-set, and then for each register identifier, a code is randomly selected from the above register code library as the corresponding first register code; when the register identifier is a number, the register identifier can also be directly used as the corresponding first register code. The embodiment of the present invention does not specifically limit the method of generating the first register code.

[0025] Exemplarily, the instruction stream description information shown in Table 1 above can directly use the register identifier of the digital type as the first register code of the corresponding register identifier, and randomly generate the corresponding first register code for the register identifier of the string type, so that the first register codes corresponding to the same register identifier are the same, that is, the first register codes determined according to the same register identifier are the same, and the first register codes corresponding to the instruction description entries shown in Table 2 below can be obtained: Table 2

[0026] Step 103: Based on the first register code and operation code identifier corresponding to each instruction description entry in the instruction stream description information, generate the first instruction corresponding to each instruction description entry, and obtain a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein the first instruction stream is used to test the central processing unit.

[0027] In the embodiment of the present invention, after obtaining the first register code and the operation code identifier corresponding to each instruction description entry in the instruction stream description information, the operation code identifier can be used as the operation code and the first register code can be used as the operand to generate the first instruction corresponding to each instruction description entry, so that the first instructions can be arranged in the order of the corresponding instruction description entries to form a first instruction stream. Therefore, the first instruction stream can include dependent instruction pairs that share the same register.

[0028] Exemplarily, according to the first register code and the operation code identifier corresponding to each instruction description entry shown in Table 2 above, the first instruction corresponding to each instruction description entry may be generated as shown in Table 3 below: Table 3

[0029] The three first instructions shown in the above Table 3 can form a first instruction stream. In the first instruction stream, the first instruction 1 is executed first, and the execution result is written into register 25. Then the first instruction 2 is executed, and the execution result is written into register 13. Finally, the first instruction 3 is executed to perform calculations based on the data in registers 25 and 13, and the execution result is written into register 3. Thus, the above first instruction 1 and the first instruction 3 form a dependent instruction pair with a read-after-write dependency relationship. The first instruction 2 and the first instruction 3 also form a dependent instruction pair with a read-after-write dependency relationship.

[0030] Through the above operations, the instruction sequence of the first instruction in the first instruction stream is the same as the preset opcode sequence, and the first instruction stream may include dependent instruction pairs that share the same register, so that the first instruction stream including the dependent instruction pairs in a specific instruction sequence can be quickly generated. The first instruction stream can be used to test the processor core, thereby helping to improve the test efficiency of the processor test based on the instruction stream.

[0031] In summary, in an instruction stream generation method provided by an embodiment of the present invention, instruction stream description information generated based on a preset opcode sequence is obtained; wherein the instruction stream description information includes instruction description entries consisting of opcode identifiers and register identifiers corresponding to each preset opcode in the preset opcode sequence; based on the register identifiers corresponding to each instruction description entry in the instruction stream description information, the first register codes corresponding to each instruction description entry are determined; wherein the first register codes corresponding to the same register identifiers are the same; based on the first register codes and opcode identifiers corresponding to each instruction description entry in the instruction stream description information, the first instructions corresponding to each instruction description entry are generated, and the first instruction stream consisting of the first instructions corresponding to each instruction description entry is obtained. In this way, an instruction stream with a fixed instruction sequence can be automatically generated through a preset opcode sequence, and the instructions in the generated instruction stream can share the same register encoding, so that the same register corresponding to the same register encoding is operated through the same or different instructions in the instruction stream with a fixed instruction sequence, and a register dependency is generated. Therefore, an instruction stream with a fixed instruction sequence and a register dependency can be generated through this scheme, and when these instruction streams are tested, it is helpful to accurately locate the problem of the processor core, and it is helpful to improve the test accuracy of the instruction stream when the processor core is tested.

[0032] Optionally, in some embodiments, the preset opcode sequence may include a dependent opcode pair, and the step of obtaining instruction flow description information generated based on the preset opcode sequence may specifically include: Step 1011: Determine the dependent register corresponding to each opcode in the dependent opcode pair based on the dependency relationship of the dependent opcode pair.

[0033] In the embodiment of the present invention, a dependent opcode pair may be formed between opcodes in the preset opcode sequence, and the dependent opcode pair indicates an opcode pair that can generate an instruction pair with a dependent relationship. The instruction pair with a dependent relationship may operate on the same register when executed, and the above operation may include reading and writing.

[0034] In one embodiment, the dependent opcode pairs can be set by a technician for the opcodes in the preset operation sequence, that is, the dependent opcode pairs can be specified in the preset opcode sequence, thereby forming dependent opcode information as additional information of the preset opcode sequence. The dependent opcode information can indicate the dependent opcode pairs in the preset opcode sequence, and the dependency relationship type of each dependent opcode pair.

[0035] In another embodiment, the preset opcode sequence can be traversed, and the opcodes can be automatically paired to form dependent opcode pairs according to the order and register types between the opcodes in the preset opcode sequence, and the dependency type of each dependent opcode pair can be determined. Specifically, in the process of traversing the preset opcode sequence, an opcode can be selected as a pre-order opcode, and a dependency relationship can be determined. Then, an opcode having the above dependency relationship with the pre-order opcode is selected from the opcodes after the pre-order opcode in the preset opcode sequence as the post-order opcode of the pre-order opcode, and a dependent opcode pair consisting of the pre-order opcode and the post-order opcode is obtained. It should be noted that the dependent opcode pair selected from the preset opcode sequence can be all or part, for example, a preset number can be set, and a preset number of dependent opcode pairs can be selected from the preset opcode sequence. In order to enable two registers corresponding to the same instruction description entry (for example, a source register and a destination register of the same instruction description entry) to form a dependent register pair, the opcodes of the same instruction description entry can also be constructed into a dependent opcode pair.

[0036] In an embodiment of the present invention, each dependent opcode pair may correspond to a dependency relationship, and the dependency relationship is used to indicate the register shared by the dependent opcode pair, that is, the dependent register. A plurality of dependency relationship types may be preset, and different dependency relationship types may correspond to different dependent registers. Exemplarily, the dependency relationship may include type 1, type 2, and type 3; wherein type 1 may indicate that the destination register of the preceding opcode and the first source register of the following opcode in the dependent opcode pair are dependent registers; type 2 may indicate that the destination register of the preceding opcode and the second source register of the following opcode in the dependent opcode pair are dependent registers; type 3 may indicate that the destination register of the preceding opcode and the third source register of the following opcode in the dependent opcode pair are dependent registers. The embodiment of the present invention does not specifically limit the types of dependency relationships, and technicians may flexibly set the types of dependency relationships according to actual needs, and set corresponding methods for determining dependent registers for different types of dependency relationships.

[0037] For example, if the preset operation code sequence is as shown in Table 4 below: Table 4

[0038] Among them, the dependent opcode pairs may include (opcode 1-opcode 2), (opcode 2-opcode 5), (opcode 4-opcode 5), (opcode 7-opcode 8). The dependency relationship of all the above dependent opcode pairs can be type 1. Then the destination register corresponding to the preceding opcode of the above dependent opcode pair and a source register corresponding to the following opcode can be determined as a dependent register pair. For example, it can be determined that the rd of opcode 1 and the rs0 of opcode 2 constitute a dependent register pair, the rd of opcode 2 and the rs1 of opcode 5 constitute a dependent register pair, the rd of opcode 4 and the rs0 of opcode 5 constitute a dependent register pair, and the rd of opcode 7 and the rs0 of opcode 8 constitute a dependent register pair.

[0039] It should be noted that the dependent register corresponding to each opcode in the preset opcode sequence may be determined in the above manner, or may be directly specified and set by a technician, and the embodiment of the present invention does not specifically limit this.

[0040] Optionally, in some embodiments, the dependency may include a read-after-write dependency, a write-after-write dependency, a read-after-write dependency, or a read-after-read dependency. Based on the dependency of the dependent opcode pair, the step of determining the dependent register corresponding to each opcode in the dependent opcode pair may specifically include: Step A1, when the dependency relationship of the dependent opcode pair is the read-after-write dependency relationship, the destination register of the preceding opcode in the dependent opcode pair is used as the dependent register of the preceding opcode, and a source register of the subsequent opcode in the dependent opcode pair is used as the dependent register of the subsequent opcode.

[0041] In the embodiment of the present invention, the dependency relationship may also include a read-after-write dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship. If the dependency relationship of the dependent opcode pair is a read-after-write dependency relationship, it means that the register into which the preceding opcode in the dependent opcode pair writes data should be the same as the register into which the subsequent opcode in the dependent opcode pair reads data, that is, the destination register of the preceding opcode and a source register of the subsequent opcode can be used as dependent registers to constitute a dependent register pair of the dependent opcode pair.

[0042] Exemplarily, in the dependent opcode pair (opcode 1-opcode 2) of the preset opcode sequence shown in Table 4 above, opcode 1 is the preceding opcode and opcode 2 is the succeeding opcode. If the dependency relationship of the dependent opcode pair is a read-after-write dependency relationship, the rd register of opcode 1 can be used as its dependent register, and the rs0 or rs1 register of opcode 2 can be used as its dependent register.

[0043] Step A2, when the dependency relationship of the dependent opcode pair is the write-after-write dependency relationship, the destination register of the preceding opcode in the dependent opcode pair is used as the dependent register of the preceding opcode, and the destination register of the subsequent opcode in the dependent opcode pair is used as the dependent register of the subsequent opcode.

[0044] In an embodiment of the present invention, if the dependency relationship of a dependent opcode pair is a write-after-write dependency relationship, it means that the register into which the preceding opcode in the dependent opcode pair writes data should be the same as the register into which the subsequent opcode in the dependent opcode pair writes data, that is, the destination register of the preceding opcode and the destination register of the subsequent opcode can be used as dependent registers to constitute a dependent register pair of the dependent opcode pair.

[0045] Exemplarily, in the dependent opcode pair (opcode 2-opcode 5) of the preset opcode sequence shown in Table 4 above, opcode 2 is the preceding opcode and opcode 5 is the succeeding opcode. If the dependency relationship of the dependent opcode pair is a write-after-write dependency relationship, the rd register of opcode 2 can be used as its dependent register, and the rd register of opcode 5 can be used as its dependent register.

[0046] Step A3, when the dependency relationship of the dependent opcode pair is the read-after-write dependency relationship, a source register of the preceding opcode in the dependent opcode pair is used as the dependent register of the preceding opcode, and a destination register of the subsequent opcode in the dependent opcode pair is used as the dependent register of the subsequent opcode.

[0047] In an embodiment of the present invention, if the dependency relationship of a dependent opcode pair is a read-then-write dependency relationship, it means that the register used by the preceding opcode in the dependent opcode pair to read data should be the same as the register used by the subsequent opcode in the dependent opcode pair to write data, that is, a source register of the preceding opcode and a destination register of the subsequent opcode can be used as dependent registers to constitute a dependent register pair of the dependent opcode pair.

[0048] Exemplarily, in the dependent opcode pair (opcode 7-opcode 8) of the preset opcode sequence shown in Table 4 above, opcode 7 is the preceding opcode and opcode 8 is the succeeding opcode. If the dependency relationship of the dependent opcode pair is a read-after-write dependency relationship, the rs0 or rs1 register of opcode 7 can be used as its dependent register, and the rd register of opcode 8 can be used as its dependent register.

[0049] Step A4, when the dependency relationship of the dependent opcode pair is the read-after-read dependency relationship, a source register of the preceding opcode in the dependent opcode pair is used as the dependent register of the preceding opcode, and a source register of the subsequent opcode in the dependent opcode pair is used as the dependent register of the subsequent opcode.

[0050] In an embodiment of the present invention, if the dependency relationship of a dependent opcode pair is a read-after-read dependency relationship, it means that the register from which the preceding opcode in the dependent opcode pair reads data should be the same as the register from which the subsequent opcode in the dependent opcode pair reads data, that is, a source register of the preceding opcode and a source register of the subsequent opcode can be used as dependent registers to constitute a dependent register pair of the dependent opcode pair.

[0051] Exemplarily, in the dependent opcode pair (opcode 1-opcode 2) of the preset opcode sequence shown in Table 4 above, opcode 1 is the preceding opcode and opcode 2 is the succeeding opcode. If the dependency relationship of the dependent opcode pair is a read-after-read dependency relationship, the rs0 or rs1 register of opcode 1 can be used as its dependent register, and the rs0 or rs1 register of opcode 2 can be used as its dependent register.

[0052] In the embodiment of the present invention, the dependent registers of each opcode in the dependent opcode pair can be automatically determined according to the dependency relationship of the dependent opcode pair, which helps to improve the efficiency of the scheme in generating instruction streams. In addition, in the case where the opcode corresponds to multiple source registers or destination registers, a register can be randomly selected from multiple registers as a dependent register, which helps to improve the randomness of the subsequent instruction stream, and thus improve the test accuracy when the processor core is tested through an instruction stream with higher randomness.

[0053] Step 1012, generating a register identifier corresponding to a dependent register of each opcode in the dependent opcode pair; wherein the register identifiers corresponding to the dependent registers of each opcode in a dependent opcode pair are the same.

[0054] In an embodiment of the present invention, the preset opcode sequence may include dependent opcodes constituting a dependent opcode pair and independent opcodes that do not belong to any dependent opcode pair. The dependent opcode may correspond to a dependent register, and the independent opcode may correspond to an independent register. In an embodiment of the present invention, the same register identifier may be generated for the dependent registers of the two opcodes in each dependent opcode pair.

[0055] For example, in the dependent opcode pair (opcode 1-opcode 2) shown in Table 4 above, the registers corresponding to each opcode are shown in Table 5 below: Table 5

[0056] The dependent register pair of the dependent opcode pair includes rd of opcode 1 (LUI) and rs0 of opcode 2 (MOVE). The same register identifier, such as 33 or udf_str1, can be generated for the two dependent register pairs, and the corresponding register identifier, such as 10 or udf_str10, can be randomly generated for the independent register rd of opcode 2 (MOVE).

[0057] Step 1013: Generate the instruction flow description information based on the operation code identifier and register identifier corresponding to each operation code in the preset operation code sequence.

[0058] In the embodiment of the present invention, different register identifiers can be generated for independent registers corresponding to each opcode in the preset opcode sequence. The same register identifier can be generated for dependent registers of each dependent opcode pair in the preset opcode sequence. Thus, the register identifiers of all registers corresponding to each opcode in the preset opcode sequence are obtained, and then instruction flow description information can be generated according to the opcode identifier and register identifier corresponding to each opcode in the preset opcode sequence.

[0059] Optionally, the generation process of the above-mentioned register identifier can be randomly generated, randomly selected within a preset identifier range, or sequentially selected in a data set, for example, positive integers are sequentially selected starting from 1 in a set of positive integers as register identifiers, and the embodiment of the present invention does not make specific limitations.

[0060] In an embodiment of the present invention, based on the dependency relationship of the dependent opcode pair, the dependent register corresponding to each opcode in the dependent opcode pair is determined; the register identifier corresponding to the dependent register of each opcode in the dependent opcode pair is generated; wherein the register identifier corresponding to the dependent register of each opcode in the dependent opcode pair is the same; based on the opcode identifier and register identifier corresponding to each opcode in the preset opcode sequence, the instruction stream description information is generated. According to the preset opcode sequence, the corresponding instruction stream description information can be automatically generated, which helps to improve the efficiency of generating the instruction stream based on the preset opcode sequence.

[0061] Optionally, in some embodiments, the step of determining the first register code corresponding to each instruction description entry based on the register identifier corresponding to each instruction description entry in the instruction stream description information may specifically include: Step 1021, determining the encoding rule corresponding to each register identifier in each instruction description entry.

[0062] In the embodiment of the present invention, the opcodes in the preset opcode sequence may have different attributes, such as dependent opcodes and independent opcodes. Therefore, different methods may be used to generate corresponding register codes for different types of opcodes, that is, different encoding rules may be used when generating register codes corresponding to different register identifiers. In addition, since the register types or ranges corresponding to opcodes with different functions are different, different encoding rules may be used for register codes corresponding to different opcodes to ensure stable operation of the instruction stream generated later.

[0063] In one implementation, register identifiers of different identifier types may be set for dependent opcodes and independent opcodes, respectively, so that encoding rules corresponding to each register identifier may be determined according to the identifier type of each register identifier in the instruction description entry.

[0064] In another implementation, register identifiers of different identification types may be set for operation codes of different functions, so that different encoding rules may be used for operation codes of different functions to generate more reasonable register encodings for them. For example, for an ADD operation code, the corresponding encoding rule may be set to Rule 1; for a SUB operation code, the corresponding encoding rule may be set to Rule 2, and so on, which is not specifically limited in the embodiment of the present invention.

[0065] Optionally, in some embodiments, the identification type of the register identification includes a numerical type and a string type, and the step of determining the encoding rule corresponding to each register identification in each instruction description entry may specifically include: Step B1, for a register identifier whose identifier type is the numerical type, determining that the encoding rule corresponding to the register identifier is the first rule.

[0066] Step B2: for a register identifier whose identifier type is the string type, determining that the encoding rule corresponding to the register identifier is the second rule.

[0067] In an embodiment of the present invention, the identification type of the register identification may include a numerical type and a string type. For example, a register identification of a numerical type may be generated for an independent opcode, and a register identification of a string type may be generated for a dependent opcode. Thus, when generating a first instruction stream according to the instruction stream description information, the register identification of each instruction description entry may be analyzed, and for a register identification of a numerical type, the corresponding encoding rule may be determined to be the first rule; and for a register identification of a string type, the corresponding encoding rule may be determined to be the second rule.

[0068] The embodiment itself can generate different types of register identifiers and determine the encoding rules according to the identifier type of the register identifier. Specifically, the register identifier can be generated as a numeric type and a string type, which helps to improve the efficiency of distinguishing the encoding rules corresponding to the register identifier, and the register identifier of the numeric type can also directly participate in the generation process of the subsequent register encoding, which helps to improve the generation efficiency of the subsequent register encoding.

[0069] Step 1022: Based on each register identifier and the encoding rule corresponding to each register identifier, generate a first register encoding corresponding to each register identifier in each instruction description entry.

[0070] In the embodiment of the present invention, the coding rule may include a coding generation method and may also include a coding selection range. For example, one coding rule may be: randomly selecting a positive integer from a positive integer set A as a register code; another coding rule may be: randomly selecting a positive integer from a positive integer set B as a register code; another coding rule may include: inputting a register identifier into a preset equation, and obtaining a value output by the preset equation as the register code; the coding rule may be flexibly set according to actual needs, and the embodiment of the present invention does not specifically limit it.

[0071] In the embodiment of the present invention, by determining the encoding rules corresponding to each register identifier in each instruction description entry, and based on each register identifier and the encoding rules corresponding to each register identifier, the first register encoding corresponding to each register identifier in each instruction description entry is generated. This helps to improve the adaptability of the first register encoding to the corresponding operation code, and helps to improve the execution stability of the first instruction stream generated later.

[0072] Optionally, in some embodiments, based on each register identifier and the encoding rule corresponding to each register identifier, the step of generating the first register encoding corresponding to each register identifier in each instruction description entry may specifically include: Step C1: when the encoding rule of the register identifier corresponding to the instruction description entry is the first rule, use the register identifier as the first register encoding corresponding to the register identifier.

[0073] In an embodiment of the present invention, the encoding rule may specifically include a first rule and a second rule. If the encoding rule of the register encoding corresponding to the instruction description entry is the first rule, the register flag may be directly used as the first register encoding corresponding to the instruction description entry, that is, the encoding method of the first rule is direct encoding based on the register identifier. The encoding rule corresponding to the register identifier of the numerical type may be determined as the first rule.

[0074] Step C2: when the encoding rule of the register identifier corresponding to the instruction description entry is the second rule, obtain a random number generated for the register identifier as a first register code corresponding to the register identifier.

[0075] In an embodiment of the present invention, if the encoding rule of the register encoding corresponding to the instruction description entry is the second rule, a corresponding random number can be generated for the register identifier, and the random number can be used as the first register encoding corresponding to the corresponding instruction description entry. It should be noted that in each round of instruction generation, the first register encoding determined for the same register identifier is the same, that is, if the instruction stream description information contains multiple identical register identifiers corresponding to the second rule, a random number generation can be performed for these identical register identifiers, and the generated random number can be used as the first register encoding for these identical register identifiers, thereby determining the first register encoding corresponding to multiple identical register identifiers through one random number generation, thereby improving encoding efficiency.

[0076] In the embodiment of the present invention, the encoding rule corresponding to the register identifier of the string type may be determined as the second rule, or the encoding rule corresponding to the register identifier of the numerical type may be determined as the second rule, which is not specifically limited in the embodiment of the present invention.

[0077] For example, if there is a preset operation code sequence Seq as shown in Table 4, the source register and the destination register required for each operation code in the preset operation code sequence Seq are shown in Table 6 below: Table 6

[0078] Among them, opcode 1 and opcode 2 can be set as a dependent opcode pair, opcode 2 and opcode 5 can be set as a dependent opcode pair, opcode 4 and opcode 5 can be set as a dependent opcode pair, opcode 7 and opcode 8 can be set as a dependent opcode pair, and the dependency relationships of all the above dependent opcode pairs are read-after-write dependencies. Then, the destination register corresponding to the preceding opcode of the above dependent opcode pair and a source register corresponding to the following opcode can be determined as a dependent register pair. For example, it can be determined that the rd of opcode 1 and the rs0 of opcode 2 constitute a dependent register pair, the rd of opcode 2 and the rs1 of opcode 5 constitute a dependent register pair, the rd of opcode 4 and the rs0 of opcode 5 constitute a dependent register pair, and the rd of opcode 7 and the rs0 of opcode 8 constitute a dependent register pair.

[0079] A string type register identifier can be generated for each dependent register in Table 6 above, and a numeric type register identifier can be generated for each independent register, to obtain the instruction flow description information shown in Table 7 below: Table 7

[0080] For register identifiers of numerical type, the corresponding encoding rule can be set to the first rule, that is, the register identifier is directly used as its corresponding register encoding. For register identifiers of string type, the corresponding encoding rule can be set to the second rule, that is, the random number generated for the register identifier is used as its corresponding register encoding. It should be noted that the above instruction flow description information can be stored in a file, for example, the instruction flow description information is recorded in a txt format file.

[0081] The file corresponding to the instruction stream description information can be read, and the register identifiers of each string type can be extracted from the instruction stream description information shown in Table 7: udf_str1, udf_str2, udf_str3, and udf_str4. The random library of Python can be used to randomly generate a random number for each of the above four register identifiers, for example, udf_str1=6, udf_str2=34, udf_str3=27, and udf_str4=12. Then the dictionary in Python can be used to establish a mapping relationship. For example, a dictionary named reg_idx is defined, and the above four register identifiers are used as keys and their corresponding random numbers are used as values ​​to obtain the reg_idx dictionary shown below: reg_idx={} reg_idx[udf_str1]=6; reg_idx[udf_str2]=34; reg_idx[udf_str3]=27; reg_idx[udf_str4]=12.

[0082] Then, each instruction description entry of the instruction stream description information shown in Table 7 above can be parsed, the opcode identifier and register identifier of each instruction description entry can be extracted, the register identifier of the numerical type can be directly determined as the corresponding register code, and for the register identifier of the string type, the corresponding random number can be read from the reg_idx dictionary as the corresponding register code, and the first instruction corresponding to each instruction description entry can be generated according to the opcode identifier and register code of each instruction description entry, so that the first instruction stream shown in Table 8 below can be generated.

[0083] Table 8

[0084] It should be noted that, in addition to the register operand corresponding to the register, the above-mentioned first instruction may also require other operands, such as immediate numbers. For other operands, they can be completed by random generation or by preset values, which is not specifically limited in the embodiment of the present invention.

[0085] Optionally, in some embodiments, after the step of determining the first register code corresponding to each instruction description entry based on the register identifier corresponding to each instruction description entry in the instruction stream description information, the following steps may also be performed: Step D1, based on the register identifier corresponding to each instruction description entry in the instruction stream description information, determine the second register code corresponding to each instruction description entry; wherein the second register codes corresponding to the same register identifier are the same.

[0086] Step D2, based on the second register code and operation code identifier corresponding to each instruction description entry in the instruction stream description information, generate the second instruction corresponding to each instruction description entry, and obtain a second instruction stream composed of the second instructions corresponding to each instruction description entry.

[0087] In the embodiment of the present invention, after each time a corresponding instruction stream is generated based on the instruction stream description information, a corresponding register code can be regenerated for the instruction description entry based on the instruction stream description information, and a corresponding instruction stream can be generated again based on the regenerated register code, thereby realizing an instruction stream batch generation operation based on the instruction stream description information.

[0088] Specifically, after generating the first instruction stream, based on the register identifier corresponding to each instruction description entry in the instruction stream description information, the second register encoding corresponding to each instruction description entry can be determined, and the second register encoding corresponding to the same register identifier can be kept the same. The method for generating the second register encoding is the same as the method for generating the first register encoding, and the embodiments of the present invention will not be repeated. The corresponding second instruction stream can be further generated according to the second register encoding.

[0089] It should be noted that, since the register code can be obtained by random selection or generation of random numbers during the generation process, some or all of the second register codes may differ from the corresponding first register codes, so that the second instruction stream composed of second instructions generated based on the second register code is different from the first instruction stream.

[0090] In an embodiment of the present invention, the second register code corresponding to each instruction description entry can be determined based on the register identifier corresponding to each instruction description entry in the instruction stream description information; wherein, the second register code corresponding to the same register identifier is the same; based on the second register code and the operation code identifier corresponding to each instruction description entry in the instruction stream description information, the second instruction corresponding to each instruction description entry is generated, and a second instruction stream composed of the second instructions corresponding to each instruction description entry is obtained. Thus, it is possible to generate instruction streams in batches with fixed instruction sequences and dependency relationships realized through different dependent registers, which helps to improve the efficiency of generating instruction streams for testing, and further improve the testing efficiency of the processor core.

[0091] Optionally, in some embodiments, after the step of obtaining the second instruction stream consisting of the second instructions corresponding to each instruction description entry, the first instruction stream and the second instruction stream may be spliced ​​to obtain a target instruction stream, or each second instruction in the second instruction stream may be inserted into the first instruction stream to obtain a target instruction stream. Thus, multiple instruction streams generated in batches are merged into a longer target instruction stream. The target instruction stream can be used to test a large number of different dependent register combinations under a fixed instruction sequence at one time, which helps to improve the efficiency of testing the processor core.

[0092] Reference Figure 2 , shows a block diagram of an instruction stream generating device provided by an embodiment of the present invention, such as Figure 2 As shown, the device may specifically include: The acquisition module 201 is used to acquire instruction flow description information generated based on a preset operation code sequence; wherein the instruction flow description information includes instruction description entries consisting of operation code identifiers and register identifiers corresponding to each preset operation code in the preset operation code sequence; An encoding module 202, configured to determine a first register encoding corresponding to each instruction description entry based on a register identifier corresponding to each instruction description entry in the instruction stream description information; wherein first register encodings corresponding to the same register identifier are the same; The instruction stream module 203 is used to generate the first instruction corresponding to each instruction description entry based on the first register code and operation code identifier corresponding to each instruction description entry in the instruction stream description information, and obtain a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein the first instruction stream is used to test the central processing unit.

[0093] Optionally, the preset operation code sequence includes a dependent operation code pair, and the acquisition module includes: A relationship submodule, configured to determine, based on the dependency relationship of the dependent opcode pair, a dependent register corresponding to each opcode in the dependent opcode pair; A register identification submodule, used to generate a register identification corresponding to a dependent register of each opcode in the dependent opcode pair; wherein the register identification corresponding to the dependent register of each opcode in a dependent opcode pair is the same; The description information submodule is used to generate the instruction flow description information based on the operation code identifier and register identifier corresponding to each operation code in the preset operation code sequence.

[0094] Optionally, the dependency relationship includes a read-after-write dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship, and the relationship submodule includes: A first relation unit is used for, when the dependency relation of the dependent opcode pair is the read-after-write dependency relation, using a destination register of a preceding opcode in the dependent opcode pair as a dependent register of the preceding opcode, and using a source register of a subsequent opcode in the dependent opcode pair as a dependent register of the subsequent opcode; A second relationship unit is used to use, when the dependency relationship of the dependent opcode pair is the write-after-write dependency relationship, a destination register of a preceding opcode in the dependent opcode pair as a dependent register of the preceding opcode, and a destination register of a subsequent opcode in the dependent opcode pair as a dependent register of the subsequent opcode; A third relationship unit is used for, when the dependency relationship of the dependent opcode pair is the read-after-write dependency relationship, using a source register of a preceding opcode in the dependent opcode pair as a dependent register of the preceding opcode, and using a destination register of a subsequent opcode in the dependent opcode pair as a dependent register of the subsequent opcode; The fourth relationship unit is used to use a source register of a preceding opcode in the dependent opcode pair as a dependent register of the preceding opcode, and use a source register of a subsequent opcode in the dependent opcode pair as a dependent register of the subsequent opcode when the dependency relationship of the dependent opcode pair is the read-after-read dependency relationship.

[0095] Optionally, the encoding module includes: The encoding rule submodule is used to determine the encoding rule corresponding to each register identifier in each instruction description entry; The first register encoding submodule is used to generate a first register encoding corresponding to each register identifier in each instruction description entry based on each register identifier and an encoding rule corresponding to each register identifier.

[0096] Optionally, the identifier type of the register identifier includes a numerical type and a string type, and the encoding rule submodule includes: A first rule unit, configured to determine, for a register identifier whose identifier type is the numerical type, that an encoding rule corresponding to the register identifier is a first rule; The second rule unit is used to determine, for a register identifier whose identifier type is the string type, that the encoding rule corresponding to the register identifier is a second rule.

[0097] Optionally, the first register encoding submodule includes: a first encoding unit, configured to use the register identifier as a first register encoding corresponding to the register identifier when an encoding rule of the register identifier corresponding to the instruction description entry is the first rule; The second encoding unit is used to obtain a random number generated for the register identifier as a first register code corresponding to the register identifier when the encoding rule of the register identifier corresponding to the instruction description entry is the second rule.

[0098] Optionally, the encoding module is further used to determine the second register encoding corresponding to each instruction description entry based on the register identifier corresponding to each instruction description entry in the instruction stream description information; wherein the second register encoding corresponding to the same register identifier is the same; The instruction stream module is also used to generate a second instruction corresponding to each instruction description entry based on the second register code and operation code identifier corresponding to each instruction description entry in the instruction stream description information, and obtain a second instruction stream composed of the second instructions corresponding to each instruction description entry.

[0099] In summary, in the instruction stream generation device provided by the embodiment of the present invention, instruction stream description information generated based on a preset opcode sequence is obtained; wherein, the instruction stream description information includes instruction description entries consisting of opcode identifiers and register identifiers corresponding to each preset opcode in the preset opcode sequence; based on the register identifiers corresponding to each instruction description entry in the instruction stream description information, the first register codes corresponding to each instruction description entry are determined; wherein, the first register codes corresponding to the same register identifiers are the same; based on the first register codes and opcode identifiers corresponding to each instruction description entry in the instruction stream description information, the first instructions corresponding to each instruction description entry are generated, and the first instruction stream consisting of the first instructions corresponding to each instruction description entry is obtained. In this way, an instruction stream with a fixed instruction sequence can be automatically generated through a preset opcode sequence, and the instructions in the generated instruction stream can share the same register encoding, so that the same register corresponding to the same register encoding is operated through the same or different instructions in the instruction stream with a fixed instruction sequence, and a register dependency relationship is generated. Therefore, an instruction stream with a fixed instruction sequence and a register dependency relationship can be generated through this scheme, and when these instruction streams are tested, it is helpful to accurately locate the problem of the processor core, and it is helpful to improve the test accuracy of the instruction stream when the processor core is tested.

[0100] Reference Figure 3 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 3 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the instruction stream generation method of the above embodiment. The executable instructions can form a program.

[0101] An embodiment of the present invention provides a computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors, enables the processors to execute the instruction stream generation method of the aforementioned embodiment.

[0102] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0103] Those skilled in the art should understand that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes. It should be noted that all actions of acquiring signals, information or data in the present invention are carried out under the premise of complying with the corresponding data protection laws and policies of the country of residence and with the authorization given by the owner of the corresponding device. The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the process Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0104] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0105] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0106] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0107] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0108] The above is a detailed introduction to an instruction stream generation method, an instruction stream generation device, an electronic device and a storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for generating an instruction stream, characterized in that: The method comprises: Acquire instruction flow description information generated based on a preset operation code sequence; wherein the instruction flow description information includes instruction description entries consisting of operation code identifiers and register identifiers corresponding to each preset operation code in the preset operation code sequence; Determine, based on the register identifier corresponding to each instruction description entry in the instruction stream description information, a first register code corresponding to each instruction description entry; wherein first register codes corresponding to the same register identifier are the same; Based on the first register code and operation code identifier corresponding to each instruction description entry in the instruction stream description information, a first instruction corresponding to each instruction description entry is generated to obtain a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein the first instruction stream is used to test the central processing unit.

2. The instruction stream generation method according to claim 1, characterized in that: The preset opcode sequence includes a dependent opcode pair, and the obtaining of instruction flow description information generated based on the preset opcode sequence includes: Determining dependent registers corresponding to each opcode in the dependent opcode pair based on the dependency relationship of the dependent opcode pair; Generate a register identifier corresponding to the dependent register of each opcode in the dependent opcode pair; wherein the register identifiers corresponding to the dependent registers of each opcode in a dependent opcode pair are the same; The instruction flow description information is generated based on the operation code identifier and the register identifier corresponding to each operation code in the preset operation code sequence.

3. The instruction stream generation method according to claim 2, characterized in that: The dependency relationship includes a read-after-write dependency relationship, a write-after-write dependency relationship, a read-after-write dependency relationship, or a read-after-read dependency relationship, and determining the dependent register corresponding to each opcode in the dependent opcode pair based on the dependency relationship of the dependent opcode pair includes: In the case where the dependency relationship of the dependent opcode pair is the read-after-write dependency relationship, a destination register of a preceding opcode in the dependent opcode pair is used as a dependent register of the preceding opcode, and a source register of a subsequent opcode in the dependent opcode pair is used as a dependent register of the subsequent opcode; In the case where the dependency relationship of the dependent opcode pair is the write-after-write dependency relationship, the destination register of the preceding opcode in the dependent opcode pair is used as the dependent register of the preceding opcode, and the destination register of the subsequent opcode in the dependent opcode pair is used as the dependent register of the subsequent opcode; In the case where the dependency relationship of the dependent opcode pair is the read-after-write dependency relationship, a source register of a preceding opcode in the dependent opcode pair is used as a dependent register of the preceding opcode, and a destination register of a subsequent opcode in the dependent opcode pair is used as a dependent register of the subsequent opcode; In the case where the dependency relationship of the dependent opcode pair is the read-after-read dependency relationship, a source register of the preceding opcode in the dependent opcode pair is used as the dependent register of the preceding opcode, and a source register of the subsequent opcode in the dependent opcode pair is used as the dependent register of the subsequent opcode.

4. The instruction stream generation method according to claim 1, characterized in that: The determining, based on the register identifier corresponding to each instruction description entry in the instruction stream description information, the first register code corresponding to each instruction description entry includes: Determine the encoding rules corresponding to each register identifier in each instruction description entry; Based on each register identifier and an encoding rule corresponding to each register identifier, a first register encoding corresponding to each register identifier in each instruction description entry is generated.

5. The instruction stream generation method according to claim 4, characterized in that: The identification type of the register identification includes a numerical type and a string type, and the determining of the encoding rule corresponding to each register identification in each instruction description entry includes: For a register identifier whose identifier type is the numerical type, determining that the encoding rule corresponding to the register identifier is the first rule; For a register identifier whose identifier type is the string type, it is determined that the encoding rule corresponding to the register identifier is the second rule.

6. The instruction stream generation method according to claim 5, characterized in that: The generating, based on each register identifier and the encoding rule corresponding to each register identifier, the first register encoding corresponding to each register identifier in each instruction description entry includes: When the encoding rule of the register identifier corresponding to the instruction description entry is the first rule, using the register identifier as the first register encoding corresponding to the register identifier; When the encoding rule of the register identifier corresponding to the instruction description entry is the second rule, a random number generated for the register identifier is obtained as a first register code corresponding to the register identifier.

7. The instruction stream generation method according to claim 1, characterized in that: After determining the first register code corresponding to each instruction description entry based on the register identifier corresponding to each instruction description entry in the instruction stream description information, the method further includes: Determine the second register code corresponding to each instruction description entry based on the register identifier corresponding to each instruction description entry in the instruction stream description information; wherein the second register codes corresponding to the same register identifier are the same; Based on the second register code and the operation code identifier corresponding to each instruction description entry in the instruction stream description information, a second instruction corresponding to each instruction description entry is generated to obtain a second instruction stream consisting of the second instructions corresponding to each instruction description entry.

8. An instruction stream generating device, characterized in that: The device comprises: An acquisition module, used to acquire instruction flow description information generated based on a preset operation code sequence; wherein the instruction flow description information comprises instruction description entries consisting of operation code identifiers and register identifiers corresponding to each preset operation code in the preset operation code sequence; an encoding module, configured to determine a first register encoding corresponding to each instruction description entry based on a register identifier corresponding to each instruction description entry in the instruction stream description information; wherein first register encodings corresponding to the same register identifier are the same; An instruction stream module is used to generate a first instruction corresponding to each instruction description entry based on the first register code and operation code identifier corresponding to each instruction description entry in the instruction stream description information, and obtain a first instruction stream composed of the first instructions corresponding to each instruction description entry; wherein the first instruction stream is used to test the central processing unit.

9. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the instruction stream generation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Instructions are stored thereon, and when executed by one or more processors, the processors are caused to execute the instruction stream generation method according to any one of claims 1 to 7.

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