Failure mode influence analysis method and device and computer storage medium

Abstract

The invention provides a failure mode influence analysis method and device based on hardware architecture design specifications and a computer storage medium. The method comprises the following steps: in response to an analysis request of a hardware architecture design specification, dividing the hardware architecture design specification into a plurality of levels of architecture components; obtaining a hardware component function of each architecture component of the plurality of levels of architecture components; obtaining an interface relationship among the plurality of levels of architecture components according to a dependency relationship of upper and lower levels of the components among the plurality of levels of architecture components; and performing failure mode influence analysis on the hardware architecture design specifications by taking the plurality of levels of architecture components and the functions and interface relationships of the hardware components as input, and generating an analysis file of the hardware architecture design specifications. Through the failure mode influence analysis method, port analysis is performed on architecture components of different levels in an architecture design specification, the dependency relationship and the signal transmission relationship of each structure node are clarified, a clear and definite failure transmission path is provided, and the risk analysis difficulty is further reduced.

Description

Technical Field

[0001] The present application relates to the technical field of quality management, and in particular to a failure mode effect analysis method, a failure mode effect analysis device and a computer storage medium based on hardware architecture design specifications. Background Art

[0002] As the penetration rate of new energy vehicles increases year by year, the complexity of motor controllers gradually increases, and their functions gradually improve, the number of hardware components contained in them is also increasing. In order to prevent unexpected safety accidents caused by factors such as systematic failures and random hardware failures, functional safety requirements have emerged. With the continuous improvement of the functional safety development process, FMEA (Failure Mode and Effects Analysis) has developed more and more detailed analysis methods as an important analysis method and development process delivery document.

[0003] However, the existing FMEA family analysis methods all follow the seven-step method proposed by the AIAG / VDA FMEA Handbook. Among them, structural analysis, functional analysis, and failure analysis are often divided into modules and structures at the architectural level based on the judgment of experts and engineers and past project experience in the early stage of project development. However, such divisions often fail to conduct a comprehensive and complete analysis of the designed architecture, which will result in the lack of functional implementation and corresponding failure analysis in functional analysis and failure analysis. Summary of the invention

[0004] In order to solve the above technical problems, the present application proposes a failure mode effect analysis method, a failure mode effect analysis device and a computer storage medium based on hardware architecture design specifications.

[0005] In order to solve the above technical problems, the present application proposes a failure mode impact analysis method based on hardware architecture design specifications, and the failure mode impact analysis method includes:

[0006] In response to an analysis request for the hardware architecture design specification, dividing the hardware architecture design specification into a plurality of levels of architecture components;

[0007] Obtaining a hardware component function of each of the plurality of levels of architectural components;

[0008] According to the dependency relationship between the components at the upper and lower levels of the plurality of levels of architecture components, the interface relationship between the plurality of levels of architecture components is obtained;

[0009] The several levels of architecture components, and their hardware component functions and interface relationships are used as input to perform failure mode impact analysis of the hardware architecture design specification, and generate an analysis file of the hardware architecture design specification.

[0010] The method of using the several levels of architecture components, and the hardware component functions and interface relationships as input to perform failure mode impact analysis of the hardware architecture design specification and generate an analysis file of the hardware architecture design specification includes:

[0011] Inputting the several levels of architecture components into structural analysis, performing failure mode effect analysis to obtain structural analysis files;

[0012] Inputting the hardware component functions of the several levels of architecture components into functional analysis, performing failure mode effect analysis to obtain a functional analysis file;

[0013] Input the interface relationship of the several levels of architecture components into failure analysis, perform failure mode impact analysis to obtain failure analysis files;

[0014] The structural analysis file, the functional analysis file, and the failure analysis file are integrated into an analysis file of the hardware architecture design specification.

[0015] The hardware component functions of the several levels of architecture components include the functions of each of the architecture components supporting component operation, the detection functions included in the architecture components, and the response functions included in the architecture components.

[0016] Wherein, the failure mode effect analysis method further includes:

[0017] Obtain all interfaces and interface properties contained in each of the architecture components;

[0018] The dependency relationships between the upper and lower components of the architecture components are analyzed according to the interface properties of the different architecture components.

[0019] The dependency relationship between the upper and lower components includes the signal input from the upper component to the lower component, and the signal output from the lower component to the upper component.

[0020] Wherein, the failure mode effect analysis method further includes:

[0021] The several levels of architecture components are input into non-functional analysis, and failure mode effect analysis is performed to obtain non-functional failure analysis files.

[0022] The influencing factors of the non-functional analysis include temperature, vibration, water, dust, electromagnetic interference, and / or noise interference.

[0023] In order to solve the above technical problems, the present application also proposes a failure mode effect analysis device, which includes:

[0024] A component partitioning module, configured to, in response to an analysis request of the hardware architecture design specification, partition the hardware architecture design specification into a plurality of levels of architecture components;

[0025] A component function module, used to obtain a hardware component function of each of the plurality of levels of architectural components;

[0026] A component interface module, used to obtain the interface relationship between the components of the plurality of levels of architecture according to the dependency relationship between the components of the plurality of levels of architecture;

[0027] The architecture analysis module is used to use the several levels of architecture components, and their hardware component functions and interface relationships as input to perform failure mode impact analysis of the hardware architecture design specification, and generate an analysis file of the hardware architecture design specification.

[0028] In order to solve the above technical problems, the present application also proposes a failure mode effect analysis device, which includes a memory and a processor coupled to the memory; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the failure mode effect analysis method as described above.

[0029] In order to solve the above technical problems, the present application also proposes a computer storage medium, wherein the computer storage medium is used to store program data, and when the program data is executed by a computer, it is used to implement the above failure mode effect analysis method.

[0030] Compared with the prior art, the beneficial effects of the present application are as follows: the failure mode impact analysis device responds to the analysis request of the hardware architecture design specification, divides the hardware architecture design specification into several levels of architecture components; obtains the hardware component function of each architecture component of the several levels of architecture components; obtains the interface relationship between the several levels of architecture components according to the dependency relationship between the upper and lower components of the several levels of architecture components; uses the several levels of architecture components, and their hardware component functions and interface relationships as input to perform failure mode impact analysis of the hardware architecture design specification, and generates an analysis file of the hardware architecture design specification. Through the above-mentioned failure mode impact analysis method, the architecture components of different levels in the architecture design specification are analyzed, the dependency relationship and signal transmission relationship of each structural node are clarified, and a clear and definite failure transmission path is provided, thereby reducing the difficulty of risk analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] in:

[0033] Figure 1 This is the basic flow chart of the traditional FMEA analysis provided by this application;

[0034] Figure 2 It is a flowchart of an embodiment of a failure mode effect analysis method based on hardware architecture design specifications provided by the present application;

[0035] Figure 3 yes Figure 2 The specific flow diagram of step S14 of the failure mode effect analysis method shown;

[0036] Figure 4 It is a structural schematic diagram of an embodiment of a failure mode effect analysis device provided by the present application;

[0037] Figure 5 is a structural schematic diagram of another embodiment of the failure mode effect analysis device provided by the present application;

[0038] Figure 6 It is a structural diagram of an embodiment of a computer storage medium provided by the present application. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] FMEA (Failure Mode and Effects Analysis), failure mode and consequences analysis. As the most basic analysis method in the FMEA analysis family, its main purpose is to analyze the various subsystems and components that constitute the product and the procedures of the product service process one by one during the product design stage, find out the potential failure mode, analyze the possible consequences, and assess the risk, so as to take measures in advance to reduce the severity of the failure mode. After a long period of engineering development practice, the main body of the FMEA analysis method can now be carried out according to the seven-step method, namely: (1) Planning and preparation, this step determines the project, establishes a team, selects tools, etc.; (2) Structural analysis, this step divides the structure of the analyzed product and system; (3) Functional analysis, this step identifies the function of each structure divided in the previous step; (4) Failure analysis, this step identifies the failure mode of each function analyzed in the previous step and forms a failure chain; (5) Risk analysis, this step evaluates the severity, occurrence and detection of each failure mode in the previous step; (6) Optimization, this step optimizes the high-risk failure modes according to the results of the risk analysis in the previous step; (7) Documentation of results, the above six-step analysis process is delivered as an FMEA document.

[0042] FMEA analysis method, as the most basic analysis method in the FMEA analysis family, although it has a complete analysis process and is the basis of other FMEA family analysis methods, its own analysis involves relatively few contents. As a qualitative analysis method, it cannot give a characterization of the overall failure rate of the analyzed system. During the analysis process, it only analyzes the basic functions of each component of the system, without considering the various detection methods, safety mechanisms and fault responses set up by the system. In the functional safety development process, it is also impossible to analyze whether the failure violates the safety goal, and whether the failure mode that violates safety is covered by the corresponding safety mechanism.

[0043] FMEA-MSR (FMEA for Monitoring and System Response) analysis method: FMEA-MSR, supplementary FMEA for monitoring and system response. The main process of this analysis method is based on the seven-step analysis method of FMEA, namely planning and preparation, structural analysis, failure analysis, risk analysis, optimization, and result documentation. Unlike the FMEA analysis method, the system studied by FMEA-MSR needs to include at least one sensor, one control unit, and one actuator. Compared with the FMEA analysis method, it adds structural, functional, and failure analysis related to sensor monitoring and system response. Furthermore, FMEA-MSR replaces the occurrence (O) and detection (D) in FMEA with the frequency of occurrence (F) and the degree of detection (M). FMEA-MSR focuses more on the evaluation of the probability of related failures of products and systems during user use, and the probability of being detected after the failure occurs.

[0044] FMEA-MSR is a supplementary FMEA for monitoring and system response developed based on the FMEA analysis method. Compared with the traditional FMEA analysis method, this analysis method takes into account various monitoring, detection methods and system responses to failures in system design, and supplements some missing analysis links in the FMEA analysis method. However, this analysis method does not analyze whether functional failures, detection method failures, and system response failures violate safety goals in the functional safety development process, and whether there are corresponding safety mechanism coverage.

[0045] SFMEA has multiple definitions, and can refer to System FMEA, Software FMEA, and in the functional safety development process, SFMEA specifically refers to Safety FMEA. The SFMEA mentioned later in this article also specifically refers to Safety FMEA.

[0046] SFMEA, as a newly proposed FMEA family analysis method in the functional safety development process, supplements the missing analysis link of the FMEA analysis method in the functional safety development process. It takes into account whether the failure of each function will violate the safety goal and whether there is a corresponding safety mechanism coverage. However, it does not focus on the monitoring and detection methods of the system settings and the system response, and lacks analysis of the failure of the safety mechanism and fault response itself.

[0047] The above three FMEA analysis methods all inherit the analysis method of basic FMEA, and also have the same limitations as basic FMEA, that is, they generally do not consider the failure mode of double-point failure and cannot perform basic quantitative analysis.

[0048] This application proposes a FAME analysis method based on hardware architecture design specifications in the hardware development process.

[0049] Please refer to Figure 1 , Figure 1 This is the basic flow chart of the traditional FMEA analysis provided by this application. As mentioned above, the traditional FMEA analysis method usually adopts the seven-step method for analysis. Since the seven-step method is the basis of each analysis method in the FMEA family, it is explained in detail below:

[0050] 1. Planning and preparation: In this step, the scope, purpose, objectives and document writing specifications of FMEA need to be clarified; the personnel arrangement, roles and responsibilities of FMEA analysis work need to be determined.

[0051] 2. Structural analysis: In this step, you need to understand the system structure defined in the FMEA scope and disassemble the system structure. Usually, the system structure can be disassembled into systems, subsystems, and components. After the system structure is disassembled, you need to use tools to visualize the disassembly results, usually in the form of tables, structure diagrams, and structure trees.

[0052] 3. Functional analysis: Based on the structural analysis in the second step, analyze the functions of the system, subsystems and components. In this step, it is necessary to clarify the correctness and accuracy of the functional description.

[0053] 4. Failure analysis: Based on the functional analysis in the third step, the possible failure modes of the system, subsystem and component functions are analyzed. In this step, the correctness and accuracy of the failure mode description must be clarified.

[0054] 5. Risk analysis: Based on functional analysis and failure analysis, evaluate the risk of failure consequences that may be caused by each failure mode, and clarify the existing preventive measures and detection measures. According to the degree of perfection of the existing preventive measures and detection measures, each failure mode is scored with S (severity), O (occurrence), and D (detection), so as to obtain the RPN (Risk Priority Number) and AP (Action Priority) values ​​of each failure mode.

[0055] 6. Optimization: Based on the risk analysis in the fifth step, optimization is required for failure modes with large RPN and AP values. Usually, the O (occurrence) and D (detection) scores can be reduced by adding preventive measures and detection measures, thereby reducing the RPN and AP values ​​of the failure mode.

[0056] 7. Documentation of results: The analysis results of the above six steps are compiled into delivery documents that meet standards and corporate specifications.

[0057] The basic process of FMEA-MSR and SFMEA is similar to the FMEA analysis process and will not be repeated here.

[0058] To solve the problems of the above three analysis processes, this application provides a FAME analysis method based on hardware architecture design specifications. For details, please refer to Figure 2 .in, Figure 2 It is a flow chart of an embodiment of a failure mode effect analysis method based on hardware architecture design specifications provided in this application.

[0059] The failure mode effect analysis method of the present application is applied to a failure mode effect analysis device, wherein the failure mode effect analysis device of the present application can be a server, a terminal device, or a system in which a server and a terminal device cooperate with each other. Accordingly, the various parts included in the failure mode effect analysis device, such as various units, sub-units, modules, and sub-modules, can all be set in the server, can all be set in the terminal device, or can be set in the server and the terminal device respectively.

[0060] Furthermore, the above-mentioned server can be hardware or software. When the server is hardware, it can be implemented as a distributed server cluster consisting of multiple servers, or it can be implemented as a single server. When the server is software, it can be implemented as multiple software or software modules, such as software or software modules used to provide distributed servers, or it can be implemented as a single software or software module, which is not specifically limited here.

[0061] like Figure 2 As shown, the specific steps are as follows:

[0062] Step S11: In response to an analysis request for the hardware architecture design specification, the hardware architecture design specification is divided into several levels of architecture components.

[0063] In the embodiment of the present application, the hardware architecture design specification is one of the delivery documents on the left side based on the V process development logic in the functional safety development project. The hardware architecture design specification may record a hardware system, the system includes various structural modules, and the structural module is composed of various hardware components. It can be understood that the individual components in the hardware components are specifically the smallest structural elements that constitute the circuit structure, such as resistors, inductors, capacitors, diodes, transistors and other components, and the modular circuit structure in the structural module is composed of multiple components, with specific connection structures between components, achieving specific circuit effects, and can be integrated into a general module or general chip. The circuit structure, such as a power module, a filter module, a controller and other circuit structures, can all be used as the analysis object for the failure mode impact analysis in this embodiment, and can be set according to the actual working conditions and requirements, and is not limited here.

[0064] Specifically, the hardware architecture design specification of the present application can represent the hardware system in the form of a physical block diagram. In this case, the physical block diagram of the hardware architecture design specification needs to clearly indicate the interface of each component.

[0065] The failure mode impact analysis device divides each architecture component according to the physical block diagram of the hardware architecture design specification, that is, the hardware architecture design specification is divided into a first-level architecture block diagram and a second-level architecture block diagram, etc. This application takes the two-level architecture division as an example for explanation, and in other embodiments, a three-level architecture block diagram, a four-level architecture block diagram, a five-level architecture block diagram, etc. can also be divided, which are not listed one by one here.

[0066] Among them, each component in the first-level architecture diagram fully indicates the interface relationship, interface quantity and interface definition between each other. The second-level architecture diagram fully indicates the interface relationship, interface quantity and interface definition between internal elements and fully indicates the interface relationship, interface quantity and interface definition of the second-level architecture diagram.

[0067] Specifically, when designing the hardware architecture, this application can select various solutions for evaluation and give reasons for the final selection. In an example of optional architecture evaluation, the control methods, reliability and cost comparisons of the low-voltage side ASC solution and the high-voltage side ASC solution are listed, and the final selected solution is clarified based on the comparison results.

[0068] Optional Architecture Assessment Example

[0069]

[0070]

[0071]

[0072] In the optional architecture evaluation example, the control methods, reliability and cost comparisons of the low-voltage side ASC solution and the high-voltage side ASC solution are listed, and the final selected solution is determined based on the comparison results.

[0073] Step S12: Obtain the hardware component function of each architecture component of several levels of architecture components.

[0074] In the embodiment of the present application, the failure mode effect analysis device needs to clearly describe the functions implemented by the component, including the functions supporting the operation of the component, the detection functions included in the component, and the response functions included in the component.

[0075] In a specific example, the basic functions of the power management module include but are not limited to the following functions:

[0076] 1. Competitive power supply input, power supply to the entire board module through power conversion.

[0077] 2. It has the function of actively shutting down the input power supply to reduce the static power consumption of the single board.

[0078] 3. Equipped with overvoltage / undervoltage detection function for each output power supply.

[0079] 4. With MCU monitoring function, the MCU can be reset.

[0080] 5. With SPI communication and protection functions.

[0081] 6. The SBC chip has chip over-temperature protection function.

[0082] 7. With fault register flag function.

[0083] 8. It has the MCU safety unit monitoring function and can output safety signals to put the system into a safe state.

[0084] Step S13: according to the dependency relationship between the components at the upper and lower levels of the several-level architecture components, the interface relationship between the several-level architecture components is obtained.

[0085] In the embodiment of the present application, the failure mode effect analysis device needs to clearly state all interfaces contained in the component and clarify the interface attributes. Furthermore, the failure mode effect analysis device also needs to analyze the upper and lower dependencies of the architecture components, that is, the signals input from the upper architecture component to the lower architecture component, and the signals output from the lower architecture component to the upper architecture component.

[0086] In a specific example, the hardware architecture design specification fully describes the interfaces included in each architecture component, as well as its properties and descriptions:

[0087]

[0088]

[0089] For the dependency relationship between the superior and subordinate architecture components in the hardware architecture design specification, that is, the signal interaction relationship, the superior and subordinate relationship and the signal transmission relationship can be represented by diagrams.

[0090] Furthermore, the failure mode effect analysis device can also focus on possible failures of components caused by differences in the environment and operating conditions, that is, to explain in detail the non-functional impacts that the architecture components may be affected by.

[0091] Non-functional causes of component failure

[0092]

[0093] Step S14: taking several levels of architecture components, and their hardware component functions and interface relationships as inputs to perform failure mode impact analysis of the hardware architecture design specification, and generating an analysis file of the hardware architecture design specification.

[0094] In an embodiment of the present application, after the failure mode effect analysis device analyzes all components included in the architecture design, it can output a hardware architecture design specification, which completely analyzes all components included in the hardware design, the interactive interfaces contained in the components, and the interactive relationships between the components. This file serves as input for FMEA analysis.

[0095] Please continue to read Figure 3 , Figure 3 yes Figure 2 The specific flow chart of step S14 of the failure mode effect analysis method is shown.

[0096] like Figure 3 As shown, the specific steps are as follows:

[0097] Step S141: Input several levels of architecture components into the structural analysis, perform failure mode effect analysis and obtain structural analysis files.

[0098] In the embodiment of the present application, the planning of FMEA analysis is basically the same as the preparation of conventional FMEA analysis, except that the FMEA analysis of the present application uses the hardware architecture design as the analysis input. The failure mode effect analysis device uses the components and elements in the hardware architecture design specification as the primary structure and secondary structure of the FMEA structure analysis. For example, the primary structure of the hardware architecture design specification is: power management module; the secondary structure is: KL30 entry, SBC module, LDO module, DC-DC module, other power modules, and drive part power supply.

[0099] Step S142: Input the hardware component functions of several levels of architecture components into the functional analysis, perform failure mode impact analysis and obtain a functional analysis file.

[0100] In the embodiment of the present application, the failure mode impact analysis device lists the functions in the hardware architecture design specification one by one into the primary structure and the secondary structure.

[0101] The functional analysis structure of the SBC module includes but is not limited to: F_Generate internal power supply, F_Internal logic power supply, F_Generate intermediate stage power supply, F_Power supply to the next stage, F_Sleep / wake-up, F_Reset management, F_SPI communication, NF_Performance, D_V_BST overvoltage monitoring, D_V_STBY overvoltage monitoring, D_V_STBY undervoltage monitoring, and D_+5V_IO overvoltage monitoring.

[0102] Step S143: Input the interface relationship of several levels of architecture components into the failure analysis, perform failure mode impact analysis and obtain a failure analysis file.

[0103] In the embodiment of the present application, the failure mode impact analysis device uses HAZOP guide words to perform failure analysis on the above functions. Commonly used HAZOP guide words include: loss, too large, too small, etc. Specifically, the failure mode impact analysis device uses the element interface and component interface analysis in the hardware architecture design specification to deduce the cause of the failure upward and the impact of the failure downward. Regarding the possible failure conditions of the internal power supply generated by F_ in the functional analysis structure of the SBC module: More_VST1 overvoltage, Less_VST1 undervoltage, Jitter_VST1 spike, Loss_VST1 loss, Late_VST1 power-on delay is too large.

[0104] Step S144: Integrate the structural analysis file, the functional analysis file, and the failure analysis file into an analysis file of the hardware architecture design specification.

[0105] In the present application, the failure mode impact analysis device responds to the analysis request of the hardware architecture design specification, divides the hardware architecture design specification into several levels of architecture components; obtains the hardware component function of each architecture component of the several levels of architecture components; obtains the interface relationship between the several levels of architecture components according to the dependency relationship between the upper and lower components of the several levels of architecture components; uses the several levels of architecture components, and their hardware component functions and interface relationships as input to perform failure mode impact analysis of the hardware architecture design specification, and generates an analysis file of the hardware architecture design specification. Through the above-mentioned failure mode impact analysis method, the architecture components of different levels in the architecture design specification are analyzed, the dependency relationship and signal transmission relationship of each structural node are clarified, and a clear and definite failure transmission path is provided, thereby reducing the difficulty of risk analysis.

[0106] This application uses hardware architecture design specifications to guide FMEA for structural analysis. In the architecture design specifications, each first-level architecture component and second-level architecture component are fully analyzed, and used as the first-level architecture node and second-level architecture node in the FMEA analysis, which simplifies the FMEA structural analysis process and improves the completeness and correctness of the FMEA structural analysis, avoiding the risk of missing some key structures in the structural analysis step.

[0107] This application uses the hardware architecture design specification to guide FMEA for risk analysis. In the architecture design specification, the internal interface, external interface, and interface properties of each first-level architecture component and second-level architecture component are fully analyzed. It provides a complete and clear failure transmission link for FMEA risk analysis, reducing the difficulty of FMEA failure analysis. For each failure listed in FMEA, the failure impact analysis of the lowest level on the higher level can be completed from top to bottom through the interface.

[0108] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0109] In order to implement the above failure mode effect analysis method, the present application also proposes a failure mode effect analysis device, for details, please refer to Figure 4 , Figure 4 It is a structural schematic diagram of an embodiment of a failure mode effect analysis device provided by the present application.

[0110] The failure mode effect analysis device 300 of this embodiment includes:

[0111] The component partitioning module 31 is used to divide the hardware architecture design specification into several levels of architecture components in response to an analysis request of the hardware architecture design specification.

[0112] The component function module 32 is used to obtain the hardware component function of each architecture component of the plurality of levels of architecture components.

[0113] The component interface module 33 is used to obtain the interface relationship between the components of the plurality of levels of architecture according to the dependency relationship between the components of the plurality of levels of architecture.

[0114] The architecture analysis module 34 is used to use the several levels of architecture components, and their hardware component functions and interface relationships as input to perform failure mode impact analysis of the hardware architecture design specification, and generate an analysis file of the hardware architecture design specification.

[0115] In order to implement the above failure mode effect analysis method, this application also proposes another failure mode effect analysis device, please refer to Figure 5 , Figure 5 It is a structural schematic diagram of another embodiment of the failure mode effect analysis device provided by the present application.

[0116] The failure mode effect analysis apparatus 400 of this embodiment includes a processor 41 , a memory 42 , an input / output device 43 , and a bus 44 .

[0117] The processor 41 , the memory 42 , and the input / output device 43 are respectively connected to the bus 44 . The memory 42 stores program data. The processor 41 is used to execute the program data to implement the failure mode effect analysis method described in the above embodiment.

[0118] In the embodiment of the present application, the processor 41 may also be referred to as a CPU (Central Processing Unit). The processor 41 may be an integrated circuit chip having the ability to process signals. The processor 41 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, or discrete hardware components. A general-purpose processor may be a microprocessor or the processor 41 may also be any conventional processor, etc.

[0119] This application also provides a computer storage medium, please continue to refer to Figure 6 , Figure 6 It is a schematic diagram of the structure of an embodiment of a computer storage medium provided in the present application. The computer storage medium 600 stores a computer program 61. When the computer program 61 is executed by a processor, it is used to implement the failure mode effect analysis method of the above embodiment.

[0120] When the embodiments of the present application are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk.

[0121] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A failure mode effect analysis method based on hardware architecture design specifications, characterized in that: The failure mode effect analysis method comprises: In response to an analysis request for the hardware architecture design specification, dividing the hardware architecture design specification into a plurality of levels of architecture components; Obtaining a hardware component function of each of the plurality of levels of architectural components; According to the dependency relationship between the components at the upper and lower levels of the plurality of levels of architecture components, the interface relationship between the plurality of levels of architecture components is obtained; The several levels of architecture components, and their hardware component functions and interface relationships are used as input to perform failure mode impact analysis of the hardware architecture design specification, and generate an analysis file of the hardware architecture design specification.

2. The failure mode effect analysis method according to claim 1, characterized in that: The method of using the several levels of architecture components, and the functions and interface relationships of the hardware components as input to perform failure mode impact analysis of the hardware architecture design specification and generating an analysis file of the hardware architecture design specification includes: Inputting the several levels of architecture components into structural analysis, performing failure mode effect analysis to obtain structural analysis files; Inputting the hardware component functions of the several levels of architecture components into functional analysis, performing failure mode effect analysis to obtain a functional analysis file; Input the interface relationship of the several levels of architecture components into failure analysis, perform failure mode impact analysis to obtain failure analysis files; The structural analysis file, the functional analysis file, and the failure analysis file are integrated into an analysis file of the hardware architecture design specification.

3. The failure mode effect analysis method according to claim 2, characterized in that: The hardware component functions of the several levels of architecture components include the functions of each of the architecture components supporting component operations, the detection functions included in the architecture components, and the response functions included in the architecture components.

4. The failure mode effect analysis method according to claim 1, characterized in that: The failure mode effect analysis method further includes: Obtain all interfaces and interface properties contained in each of the architecture components; The dependency relationships between the upper and lower components of the architecture components are analyzed according to the interface properties of the different architecture components.

5. The failure mode effect analysis method according to claim 4, characterized in that: The dependency relationship between the upper and lower components includes the signal input from the upper component to the lower component, and the signal output from the lower component to the upper component.

6. The failure mode effect analysis method according to claim 1, characterized in that: The failure mode effect analysis method further includes: The several levels of architecture components are input into non-functional analysis, and failure mode effect analysis is performed to obtain non-functional failure analysis files.

7. The failure mode effect analysis method according to claim 6, characterized in that: The influencing factors of the non-functional analysis include temperature, vibration, water, dust, electromagnetic interference, and / or noise interference.

8. A failure mode effect analysis device, characterized in that: The failure mode effect analysis device comprises: A component partitioning module, configured to, in response to an analysis request of the hardware architecture design specification, partition the hardware architecture design specification into a plurality of levels of architecture components; A component function module, used to obtain a hardware component function of each of the plurality of levels of architectural components; A component interface module, used to obtain the interface relationship between the plurality of levels of architecture components according to the dependency relationship between the plurality of levels of architecture components; The architecture analysis module is used to use the several levels of architecture components, and their hardware component functions and interface relationships as input to perform failure mode impact analysis of the hardware architecture design specification, and generate an analysis file of the hardware architecture design specification.

9. A failure mode effect analysis device, characterized in that: The failure mode effect analysis device includes a memory and a processor coupled to the memory; The memory is used to store program data, and the processor is used to execute the program data to implement the failure mode effect analysis method according to any one of claims 1 to 7.

10. A computer storage medium, characterized in that: The computer storage medium is used to store program data, and when the program data is executed by a computer, it is used to implement the failure mode effect analysis method according to any one of claims 1 to 7.

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