Delay table generation method, wiring method, electronic equipment and computer readable medium
By filtering and generating virtual netlists, obtaining delay data and storing it in preset tables, the problem of delay table generation in the prior art is solved, and more efficient and accurate delay table generation is achieved.
Patent Information
- Application Number
- CN202411655595.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-04-11
AI Technical Summary
The existing method of generating delay tables is too long and has low efficiency, making it difficult to meet developers' demand for quickly obtaining delay data in wiring design.
By obtaining the chip netlist of the target chip, filtering out general units that meet the preset conditions, generating virtual netlists based on the connection relationship between general units, using the general unit at the center of the virtual netlist as the starting unit to obtain delay data, and storing these data in the preset table to obtain the delay table.
This method greatly shortens the time of delay table generation, improves development efficiency, and ensures that there are no channels between general units by generating virtual netlists, thereby improving the accuracy of delay table data.
Smart Images
Figure CN119808678A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and more specifically, to a delay table generation method, a wiring method, an electronic device, and a computer-readable medium. Background Art
[0002] When designing the wiring of a Field-Programmable Gate Array (FPGA), developers need to design the wiring based on a delay table. The delay table can provide the shortest delay data between two wiring units on the FPGA chip. The delay table can provide guidance for the wiring design. Developers select a suitable wiring path based on the data in the delay table and actual needs. However, the existing method for generating a delay table is too time-consuming and the efficiency of generating a delay table is low. Summary of the invention
[0003] The present application proposes a delay table generation method, a wiring method, an electronic device and a computer-readable medium to improve the above-mentioned defects.
[0004] In a first aspect, the present application provides a delay table generation method, the method comprising: obtaining a chip netlist corresponding to a target chip, the chip netlist comprising a plurality of wiring units and a connection relationship between the wiring units, the wiring units corresponding to logic blocks on the target chip; screening out general units that meet preset conditions from the wiring units of the chip netlist; adding a plurality of the general units to the netlist based on the connection relationship between the general units to obtain a virtual netlist, the length of the virtual netlist being at least 2 times the length of the chip netlist, and the width of the virtual netlist being at least 2 times the width of the chip netlist; taking the general unit at the center position of the virtual netlist as the starting unit, obtaining delay data from the starting unit to each target unit, the target unit being a general unit other than the starting unit in the virtual netlist; storing the delay data corresponding to each target unit in a preset table to obtain a delay table.
[0005] Optionally, for a possible implementation, the screening out general units that meet preset conditions from the wiring units in the chip netlist includes: searching for an alternative path group in which no channel exists in the alternative path group corresponding to each wiring unit in the chip netlist, wherein the alternative path group corresponding to the wiring unit includes the shortest delay path between the wiring unit and each other wiring unit connected to it; and treating the wiring unit corresponding to the alternative path group in which no channel exists as a general unit that meets the preset conditions.
[0006] Optionally, for a possible implementation, the wiring unit corresponding to the alternative path group where no channel exists is used as a general unit that meets preset conditions, including: using the wiring unit corresponding to the alternative path group where no channel exists as a temporary wiring unit; if the wiring unit connected to each signal line of the temporary wiring unit is included in the virtual netlist, using the temporary wiring unit as a general unit that meets the preset conditions.
[0007] Optionally, for a possible implementation, the length of the virtual netlist is the sum of the target length and a preset distance, the width of the virtual netlist is the sum of the target width and the preset distance, the target length is twice the length of the chip netlist, the target width is twice the width of the chip netlist, and the preset distance is twice the longest span of the general unit.
[0008] Optionally, for a possible implementation, the length of the virtual netlist is greater than the sum of the target length and a preset distance, the width of the virtual netlist is greater than the sum of the target width and the preset distance, the target length is twice the length of the chip netlist, the target width is twice the width of the chip netlist, and the preset distance is twice the longest span of the general unit.
[0009] Optionally, for a possible implementation, taking the general unit at the center position of the virtual netlist as the starting unit and obtaining the delay data from the starting unit to each target unit includes: taking the general unit at the center position of the virtual netlist as the starting unit, and obtaining the delay data from the starting unit to each target unit based on the Bellman-Ford algorithm.
[0010] Optionally, for a possible implementation, the delay data corresponding to each target unit is stored in a preset table to obtain a delay table, including: obtaining the relative position of the target unit and the starting unit as a reference position; obtaining a central cell of the preset table, the number of rows of the preset table being the same as the number of rows of general units in the virtual netlist, and the number of columns of the preset table being the same as the number of columns of general units in the virtual netlist; taking a cell whose relative position to the central cell is the reference position as a target cell; storing the delay data corresponding to each target unit in the target cell corresponding to the preset table to obtain a delay table.
[0011] In the second aspect, the present application also provides a wiring method, which includes: obtaining a starting logic block and a target logic block of a wiring chip; determining whether there is a channel on the shortest delay path between the starting logic block and the target logic block; if there is no channel, obtaining the shortest delay data between the starting logic block and the target logic block based on a delay table, wherein the delay table is obtained based on the aforementioned delay table generation method.
[0012] In a third aspect, the present application also provides an electronic device, comprising: one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory, the one or more applications are configured to be executed by the one or more processors, and the one or more applications are configured to execute the above method.
[0013] In a fourth aspect, the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a program code executable by a processor, and when the program code is executed by the processor, the processor executes the above method.
[0014] The present application proposes a method for generating a delay table. First, a corresponding chip netlist is obtained through a target chip, and a general unit that meets a preset condition is screened out based on the wiring unit of the chip netlist. Then, multiple general units are added to the netlist based on the connection relationship between the general units to obtain a virtual netlist. Secondly, the general unit at the center of the virtual netlist is used as the starting unit to obtain the delay data from the starting unit to each target unit. Finally, the delay data corresponding to each target unit is stored in a preset table to obtain a delay table. On the one hand, the present application only needs to select a starting unit for expansion to obtain a delay table. There is no need to wait in the process of obtaining delay data, which can greatly shorten the time for obtaining delay data, thereby shortening the time for generating a delay table and improving development efficiency. On the other hand, the present application adds multiple general units to the netlist based on the connection relationship between general units to obtain a virtual netlist, so that there is no channel between the general units in the virtual netlist, and more accurate delay data can be obtained, thereby improving the accuracy of the delay table data.
[0015] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0017] Figure 1 A flow chart of a method for generating a delay table provided in an embodiment of the present application is shown;
[0018] Figure 2 A method flow chart of a delay table generation method provided by another embodiment of the present application is shown;
[0019] Figure 3 A method flow chart of a delay table generation method provided by another embodiment of the present application is shown;
[0020] Figure 4 A method flow chart of a delay table generation method provided by another embodiment of the present application is shown;
[0021] Figure 5 A method flow chart of a delay table generation method provided by another embodiment of the present application is shown;
[0022] Figure 6 A method flow chart of a wiring method provided by an embodiment of the present application is shown;
[0023] Figure 7 A schematic diagram of a wiring chip provided in an embodiment of the present application is shown;
[0024] Figure 8 A schematic diagram of a virtual netlist provided in an embodiment of the present application is shown;
[0025] Fig. 9 A structural block diagram of an electronic device provided in an embodiment of the present application is shown;
[0026] Fig.10 A structural block diagram of a computer-readable storage medium provided in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0027] In order to make those skilled in the art better understand the present application scheme, the technical scheme in the present application embodiment will be clearly and completely described below in conjunction with the drawings in the present application embodiment. Obviously, the described embodiment is only a part of the present application embodiment, rather than all the embodiments. The components of the present application embodiment usually described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application for protection, but merely represents the selected embodiment of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0028] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.
[0029] When designing FPGA wiring, developers need to design wiring based on a delay table. The delay table can provide the shortest delay data between two wiring units on the FPGA chip. The delay table can provide guidance for wiring design. Developers can choose a suitable wiring path based on the data in the delay table and actual needs. The existing method for generating delay tables mainly relies on chip netlist mapping and expansion generation. This generation method requires pre-selection of multiple expansion starting points. Multi-point expansion requires multiple generation of delay data. This method takes too long to generate delay tables, and the efficiency of generating delay tables is low.
[0030] Therefore, in an embodiment of the present application, a delay table generation method, a wiring method, an electronic device and a computer-readable medium are provided to solve or partially solve the above-mentioned problems.
[0031] It should be noted that a chip netlist is a data structure that can exist in the form of a text file or be displayed in the form of a table. Its core function is to describe the components and their connection relationships in the chip circuit. When the chip netlist exists in the form of text, the text contains data such as component name, type, connection port, and node. When the chip netlist exists in the form of a table, the components and the connection relationship between components can be reflected in the form of a table, which is convenient for the staff to view intuitively. The chip netlists in this application are all in tabular form.
[0032] See also Figure 1 , which shows a method flow chart of a delay table generation method provided in an embodiment of the present application, the method specifically includes steps S110 to S150.
[0033] Step S110: Obtain a chip netlist corresponding to the target chip, wherein the chip netlist includes a plurality of wiring units and connection relationships between the wiring units, and the wiring units correspond to logic blocks on the target chip.
[0034] It should be noted that the delay table generated in the present application is a delay table of a target chip. After the delay table is generated, the delay table is used to guide the wiring design of a wiring chip, and the model of the wiring chip is the same as the model of the target chip.
[0035] The corresponding chip netlist can be obtained based on the target chip. Specifically, the chip netlist of the target chip can be obtained based on the development tools provided by the chip manufacturer. The length and width of the chip netlist are the same as or proportional to the actual length and width of the target chip. The logic blocks on the target chip correspond to the wiring units on the chip netlist. Since the target chip is evenly distributed with multiple logic blocks and the connection relationship between each logic block, the chip netlist also includes multiple evenly distributed wiring units and the connection relationship between each wiring unit.
[0036] The logic block can realize at least one logic function, and therefore, a wiring unit is used to represent the logic block that can realize at least one logic function.
[0037] The target chip may be a programmable chip or a non-programmable chip.
[0038] Step S120: screening out common units that meet preset conditions from the wiring units in the chip netlist.
[0039] It should be noted that, in theory, the delay data between any two wiring units in the chip netlist needs to be saved in the delay table. This not only takes a long time to obtain the delay data between any two wiring units in the chip netlist, but also requires a lot of storage space to store the delay data between any two wiring units in the chip netlist. On the development side, it is necessary to update the delay table multiple times to obtain the delay data between any two wiring units in the chip netlist, and save the delay data between any two wiring units in the chip netlist in the delay table. This is obviously unrealistic.
[0040] To this end, some delay data can be obtained and stored in a delay table. When using the delay table, an interoperable method can be adopted, that is, the equivalent delay data stored in the delay table is replaced. For details, please refer to the subsequent embodiments. Since an interoperable method is to be adopted, it is necessary to ensure that the equivalent delay data is universal, that is, when the equivalent delay data is obtained, it is not affected by the channel. In other words, in the process of generating the delay table, there is no channel on the shortest delay path corresponding to the delay data stored in the delay table.
[0041] When using equivalent delay data, if there is no channel on the target wiring path of the wiring chip, the corresponding equivalent delay data is directly used as the delay estimation of the target wiring path. When there is a channel on the target wiring path of the wiring chip, the delay estimation of the target wiring path is obtained based on the actual channel on the wiring path and the equivalent delay data. For details, please refer to the subsequent embodiments.
[0042] To this end, in order to generate equivalent delay data and save it in the delay table, it is necessary to screen out general units that meet the preset conditions from the wiring units in the chip netlist. Specifically, in the alternative path group corresponding to each wiring unit in the chip netlist, an alternative path group without a channel can be searched, wherein the alternative path group corresponding to the wiring unit includes the shortest delay path between the wiring unit and each other wiring unit connected thereto; a wiring unit corresponding to the alternative path group without a channel is used as a general unit that meets the preset conditions. Please refer to the subsequent embodiments for details.
[0043] Step S130: Add multiple universal units to the netlist based on the connection relationship between the universal units to obtain a virtual netlist, wherein the length of the virtual netlist is at least twice the length of the chip netlist, and the width of the virtual netlist is at least twice the width of the chip netlist.
[0044] It should be noted that the netlist represents the components and the connection relationships between the components in a table-based form, multiple universal units are added to the netlist based on the connection relationships between the universal units, and the universal units in the netlist are connected based on the connection relationships between the universal units to obtain a virtual netlist, and the universal units and the connection relationships between the universal units can be intuitively viewed from the virtual netlist.
[0045] Step S140: Taking the common unit at the center of the virtual netlist as the starting unit, obtaining the delay data from the starting unit to each target unit, wherein the target unit is the common unit other than the starting unit in the virtual netlist.
[0046] Specifically, the starting unit may be determined based on the virtual netlist, and then delay data of the shortest delay path from the starting unit to each target unit may be obtained.
[0047] The delay data between the start unit and the target unit in the virtual netlist can be obtained through existing tools, such as static timing analysis (STA) tools.
[0048] It should be noted that the chip netlist includes multiple evenly distributed wiring units, but there may be channels between the wiring units. Existing methods require selecting at least 4 starting points on the chip netlist for expansion, obtaining the delay data between the 4 starting points to the target unit and saving it in the delay table. In addition, when selecting the starting point, it is also necessary to consider avoiding channels on the path. This method increases the workload of developers and makes the process cumbersome.
[0049] It should be noted that expansion can be understood as taking the starting point as the starting unit and obtaining the shortest delay data between the starting unit and the target unit. When one of the starting points is used for expansion, some wiring units are occupied, resulting in the need to wait for a period of time for the expansion of other starting points. Therefore, the more starting points are selected for expansion, the longer it takes to obtain the delay data, and the longer it takes to generate the delay table.
[0050] To this end, the present application adds multiple universal units to the netlist based on the connection relationship between the universal units to obtain a virtual netlist. The length of the virtual netlist is at least twice the length of the chip netlist, and the width of the virtual netlist is at least twice the width of the chip netlist. A starting point can be selected based on the chip netlist to obtain delay data without waiting, which can greatly reduce the time consumption of obtaining delay data.
[0051] Step S150: storing the delay data corresponding to each target unit in a preset table to obtain a delay table.
[0052] It should be noted that the delay data corresponding to each target unit needs to be stored at a corresponding position in the preset table for later retrieval.
[0053] In an optional embodiment, the relative position between the target unit and the starting unit is obtained as a reference position; the central cell of a preset table is obtained, and the cell whose relative position to the central cell is the reference position is used as the target cell; the delay data corresponding to each of the target cells is stored in the target cell corresponding to the preset table to obtain a delay table. Please refer to the subsequent embodiments for details.
[0054] The present application proposes a method for generating a delay table. First, a corresponding chip netlist is obtained through a target chip, and a general unit that meets a preset condition is screened out based on the wiring unit of the chip netlist. Then, multiple general units are added to the netlist based on the connection relationship between the general units to obtain a virtual netlist. Secondly, the general unit at the center of the virtual netlist is used as the starting unit to obtain the delay data from the starting unit to each target unit. Finally, the delay data corresponding to each target unit is stored in a preset table to obtain a delay table. On the one hand, the present application only needs to select a starting unit for expansion to obtain a delay table. There is no need to wait in the process of obtaining delay data, which can greatly shorten the time for obtaining delay data, thereby shortening the time for generating a delay table and improving development efficiency. On the other hand, the present application adds multiple general units to the netlist based on the connection relationship between general units to obtain a virtual netlist, so that there is no channel between the general units in the virtual netlist, and more accurate delay data can be obtained, thereby improving the accuracy of the delay table data.
[0055] See also Figure 2 , which shows a method flow chart of a delay table generation method provided in an embodiment of the present application, the method specifically includes steps S210 to S260.
[0056] Step S210: Obtain a chip netlist corresponding to the target chip, wherein the chip netlist includes a plurality of wiring units and connection relationships between the wiring units, and the wiring units correspond to logic blocks on the target chip.
[0057] Among them, step S210 has been introduced in detail in the above embodiment and will not be repeated here.
[0058] Step S220: searching for an alternative path group in which no channel exists in the alternative path group corresponding to each wiring unit in the chip netlist, wherein the alternative path group corresponding to the wiring unit includes the shortest delay path between the wiring unit and each other wiring unit connected thereto.
[0059] Specifically, the alternative path groups corresponding to the multiple wiring units in the chip netlist can be determined first. For an alternative path group, the wiring unit corresponding to the alternative path group is determined as the alternative wiring unit, and it is determined whether there is a channel on the shortest delay path between the alternative wiring unit and each other wiring unit connected to it. If there is a channel on the shortest delay path between the alternative wiring unit and at least one other wiring unit connected to it, it is determined that there is a channel in the alternative path group. If there is no channel on the shortest delay path between the alternative wiring unit and each other wiring unit connected to it, it is determined that there is no channel in the alternative path group. This method can be used to determine whether there is communication between alternative path groups, and then alternative path groups without channels can be found.
[0060] Step S230: treating the wiring units corresponding to the candidate path group without channels as general units that meet preset conditions.
[0061] It should be noted that if there is a channel in the alternative path group corresponding to the wiring unit, the delay data obtained for the alternative path group is not the shortest delay, which will lead to inaccurate delay table data. If there is no channel in the alternative path group corresponding to the wiring unit, it means that the shortest delay data between the wiring unit and other wiring units connected to it is accurate, that is, the wiring unit corresponding to the alternative path group meets the preset conditions.
[0062] Step S240: Add multiple universal units to the netlist based on the connection relationship between the universal units to obtain a virtual netlist, wherein the length of the virtual netlist is at least twice the length of the chip netlist, and the width of the virtual netlist is at least twice the width of the chip netlist.
[0063] Step S250: Taking the common unit at the center of the virtual netlist as the starting unit, obtaining the delay data from the starting unit to each target unit, wherein the target unit is the common unit other than the starting unit in the virtual netlist.
[0064] Step S260: storing the delay data corresponding to each target unit in a preset table to obtain a delay table.
[0065] Among them, step S240 to step S260 have been introduced in detail in the above embodiments and will not be repeated here.
[0066] See also Figure 3, which shows a method flow chart of a delay table generation method provided in an embodiment of the present application, the method specifically includes steps S310 to S370.
[0067] Step S310: Obtain a chip netlist corresponding to the target chip, wherein the chip netlist includes a plurality of wiring units and connection relationships between the wiring units, and the wiring units correspond to logic blocks on the target chip.
[0068] Step S320: searching for an alternative path group in which no channel exists in the alternative path group corresponding to each wiring unit in the chip netlist, wherein the alternative path group corresponding to the wiring unit includes the shortest delay path between the wiring unit and each other wiring unit connected thereto.
[0069] Among them, step S310 to step S320 have been introduced in detail in the above embodiments and will not be repeated here.
[0070] Step S330: using the wiring units corresponding to the candidate path group without channels as temporary wiring units.
[0071] Step S340: If the wiring unit to which each signal line of the temporary wiring unit is connected is included in the virtual netlist, the temporary wiring unit is regarded as a general unit that meets a preset condition.
[0072] It should be noted that although the wiring unit corresponding to the alternative path group where there is no channel is used as a general unit that meets the preset conditions to ensure the accuracy of the delay data, if the wiring unit is located at the edge of the chip netlist and a virtual netlist is obtained based on the wiring unit, the delay data obtained based on the virtual netlist may not cover the actual needs.
[0073] To this end, it is necessary to use the wiring unit corresponding to the alternative path group without a channel as a temporary wiring unit. If the wiring unit connected to each signal line of the temporary wiring unit is included in the virtual netlist, it means that the temporary wiring unit is not at the edge of the chip netlist. The temporary wiring unit is used as a general unit that meets the preset conditions. The virtual netlist obtained based on the general unit and the delay data obtained based on the virtual netlist can cover the needs of chip wiring.
[0074] Step S350: Add multiple universal units to the netlist based on the connection relationship between the universal units to obtain a virtual netlist, wherein the length of the virtual netlist is at least twice the length of the chip netlist, and the width of the virtual netlist is at least twice the width of the chip netlist.
[0075] Step S360: Taking the common unit at the center of the virtual netlist as the starting unit, obtaining the delay data from the starting unit to each target unit, wherein the target unit is the common unit other than the starting unit in the virtual netlist.
[0076] Step S370: storing the delay data corresponding to each target unit in a preset table to obtain a delay table.
[0077] Among them, steps S350 to S370 have been introduced in detail in the above embodiments and will not be repeated here.
[0078] Furthermore, the length of the virtual netlist is the sum of the target length and the preset distance, the width of the virtual netlist is the sum of the target width and the preset distance, the target length is twice the length of the chip netlist, the target width is twice the width of the chip netlist, and the preset distance is twice the longest span of the general unit.
[0079] It should be noted that the farthest span of the universal unit refers to the maximum distance between the universal unit and the universal unit connected to it.
[0080] Exemplarily, taking a universal unit as a starting point, the universal unit has 6 signal lines, each signal line is connected to other universal units, wherein the distance between the universal unit farthest connected by the signal line and the starting point is the farthest span.
[0081] It should be noted that when obtaining the shortest delay data from the starting unit to each target unit, the shortest delay path does not necessarily correspond to the shortest path in terms of geometric relationship. It may be that the path that partially surrounds the target unit is the shortest delay path, and the delay data obtained based on this path is the shortest delay data. To this end, it is necessary to set the length of the virtual netlist to the sum of the target length and the preset distance, and the width of the virtual netlist to the sum of the target width and the preset distance, so that more accurate delay data can be obtained.
[0082] Furthermore, the length of the virtual netlist is greater than the sum of the target length and the preset distance, the width of the virtual netlist is greater than the sum of the target width and the preset distance, the target length is twice the length of the chip netlist, the target width is twice the width of the chip netlist, and the preset distance is twice the longest span of the general unit.
[0083] See also Figure 4 , which shows a method flow chart of a delay table generation method provided in an embodiment of the present application, the method specifically includes steps S410 to S450.
[0084] Step S410: Obtain a chip netlist corresponding to a target chip, wherein the chip netlist includes a plurality of wiring units and connection relationships between the wiring units, and the wiring units correspond to logic blocks on the target chip.
[0085] Step S420: Filter out common units that meet preset conditions from the wiring units in the chip netlist.
[0086] Step S430: Add multiple universal units to the netlist based on the connection relationship between the universal units to obtain a virtual netlist, wherein the length of the virtual netlist is at least twice the length of the chip netlist, and the width of the virtual netlist is at least twice the width of the chip netlist.
[0087] Among them, step S410 to step S430 have been introduced in detail in the above embodiments and will not be repeated here.
[0088] Step S440: Taking the universal cell at the center of the virtual netlist as the starting cell, obtaining the delay data from the starting cell to each target cell based on the Bellman-Ford algorithm, wherein the target cell is a universal cell other than the starting cell in the virtual netlist.
[0089] Specifically, the delay data from the starting unit to each target unit can be obtained based on the Bellman-Ford algorithm, wherein the Bellman-Ford algorithm is a conventional algorithm for solving the single-source shortest path problem, which will not be described in detail here.
[0090] It should be noted that the present application includes but is not limited to using the Bellman-Ford algorithm to obtain the delay data from the starting unit to each target unit, and other algorithms may also be used to obtain the shortest delay data.
[0091] Step S450: storing the delay data corresponding to each target unit in a preset table to obtain a delay table.
[0092] Among them, step S450 has been introduced in detail in the above embodiment and will not be repeated here.
[0093] See also Figure 5 , which shows a method flow chart of a delay table generation method provided in an embodiment of the present application, the method specifically includes steps S510 to S580.
[0094] Step S510: Obtain a chip netlist corresponding to a target chip, wherein the chip netlist includes a plurality of wiring units and connection relationships between the wiring units, and the wiring units correspond to logic blocks on the target chip.
[0095] Step S520: Filter out common units that meet preset conditions from the wiring units in the chip netlist.
[0096] Step S530: Add multiple universal units to the netlist based on the connection relationship between the universal units to obtain a virtual netlist, wherein the length of the virtual netlist is at least twice the length of the chip netlist, and the width of the virtual netlist is at least twice the width of the chip netlist.
[0097] Step S540: Taking the common unit at the center of the virtual netlist as the starting unit, obtaining the delay data from the starting unit to each target unit, wherein the target unit is the common unit other than the starting unit in the virtual netlist.
[0098] Among them, step S510 to step S540 have been introduced in detail in the above embodiments and will not be repeated here.
[0099] Step S550: Acquire the relative position between the target unit and the starting unit as a reference position.
[0100] The relative position of each target unit and the starting unit can be obtained through the virtual netlist as a reference position.
[0101] Step S560: Obtain a central cell of a preset table, wherein the number of rows of the preset table is the same as the number of rows of the general units in the virtual netlist, and the number of columns of the preset table is the same as the number of columns of the general units in the virtual netlist.
[0102] Step S570: taking a cell whose relative position to the central cell is the reference position as a target cell.
[0103] The cell whose relative position to the central cell is the reference position is taken as the target cell, that is, the target cell corresponds to the target cell.
[0104] Step S580: storing the delay data corresponding to each target unit in the target cell corresponding to the preset table to obtain a delay table.
[0105] Each cell in the delay table stores the delay data of the corresponding target unit. Later in the wiring design, the corresponding delay data can be obtained from the delay table.
[0106] It should be noted that the number of rows of the preset table is the same as the number of rows of the general units in the virtual netlist, and the number of columns of the preset table is the same as the number of columns of the general units in the virtual netlist, and the preset table can be pre-acquired.
[0107] See also Figure 6 , which shows a method flow chart of a wiring method provided in an embodiment of the present application, the method specifically includes steps S610 to S630.
[0108] Step S610: Acquire the starting logic block and the target logic block of the wiring chip.
[0109] It should be noted that the wiring chip is a chip that needs to be designed for wiring. The model of the wiring chip is the same as the model of the target chip. When the wiring design is performed on the wiring chip, the starting logic block and the target logic block can be determined according to the requirements.
[0110] Step S620: Determine whether there is a channel on the shortest delay path from the starting logic block to the target logic block.
[0111] It should be noted that in the process of wiring the wiring chip, the shortest delay path between the starting logic block and the target logic block may be partially or fully occupied. Therefore, it is necessary to determine whether there is a channel on the shortest delay path from the starting logic block to the target logic block.
[0112] Step S630: If the channel does not exist, the shortest delay data between the starting logic block and the target logic block is obtained based on the delay table, and the delay table is obtained based on the above-mentioned delay table generation method.
[0113] If there is no channel, the shortest delay data between the starting logic block and the target logic block is obtained based on the delay table. If there is a channel, it is necessary to combine the actual situation from the starting logic block to the target logic block and calculate the shortest delay data under limited resources.
[0114] It should be noted that the delay table only stores part of the delay data. When there is no channel on the shortest delay path between the starting logic block and the target logic block, the shortest delay data between the starting logic block and the target logic block is obtained from the delay table, that is, the equivalent delay data is found from the delay table.
[0115] The equivalent delay data can represent the shortest delay data between the starting logic block and the target logic block. Figure 7 , which shows a schematic diagram of the wiring chip 1, see Figure 8 , which shows a schematic diagram of a virtual netlist 2 corresponding to a wiring chip 1, wherein the intersection of the lines is a universal unit, and the starting logic block A and the target logic block B can be determined according to the requirements. When it is necessary to determine the shortest delay data from logic block A to logic block B according to the delay table, it can be converted to obtain the shortest delay data between the universal unit 21 and the universal unit 22 in the virtual netlist, and then the delay data stored in the target cell corresponding to the universal unit 22 can be obtained from the virtual netlist as the equivalent delay data of the starting logic block A and the target logic block B.
[0116] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.
[0117] In several embodiments provided in the present application, the coupling between modules may be electrical, mechanical or other forms of coupling.
[0118] In addition, each functional module in each embodiment of the present application can be integrated into a processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The above integrated modules can be implemented in the form of hardware or software functional modules.
[0119] Please refer to Fig. 9 , which shows a structural block diagram of an electronic device 700 provided in an embodiment of the present application. The electronic device 700 may be a vehicle system, which may be arranged in a vehicle. The electronic device 700 in the present application may include one or more of the following components: a processor 711, a memory 712, and one or more application programs, wherein the processor 711 is electrically connected to the memory 712, and the one or more program configurations are used to execute the methods described in the various embodiments of the aforementioned test method.
[0120] The processor 711 may include one or more processing cores. The processor 711 uses various interfaces and lines to connect various parts of the entire electronic device 700, and executes various functions and processes data of the electronic device 700 by running or executing instructions, programs, code sets or instruction sets stored in the memory 712, and calling data stored in the memory 712. Optionally, the processor 711 can be implemented in at least one hardware form of digital signal processing (DSP), field programmable gate array (FPGA), and programmable logic array (PLA). The processor 711 can integrate one or a combination of a central processing unit (CPU), a graphics processor (GPU), and a modem. Among them, the CPU mainly processes the operating system, user interface, and computer programs; the GPU is responsible for rendering and drawing display content; and the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 711, but may be implemented separately through a communication chip. Specifically, the method described in the above embodiments may be executed by one or more processors 711 .
[0121] For some embodiments, the memory 712 may include a random access memory (RAM) or a read-only memory (ROM). The memory 712 may be used to store instructions, programs, codes, code sets, or instruction sets. The memory 712 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for implementing at least one function, instructions for implementing the following various method embodiments, etc. The data storage area may also store data created by the electronic device 700 during use, etc.
[0122] Please refer to Fig.10 , which shows a structural block diagram of a computer-readable medium provided in an embodiment of the present application. The computer-readable medium 800 stores program codes, which can be called by a processor to execute the method described in the above method embodiment.
[0123] The computer readable medium 800 can be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer readable medium 800 includes a non-transitory computer-readable storage medium. The computer readable medium 800 has storage space for program code 810 that performs any method step in the above method. These program codes can be read from or written to one or more computer program products. The program code 810 can be compressed, for example, in an appropriate form.
[0124] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. A delay table generation method, characterized in that: The method comprises: Acquire a chip netlist corresponding to a target chip, wherein the chip netlist includes a plurality of wiring units and connection relationships between the wiring units, and the wiring units correspond to logic blocks on the target chip; Filter out common units that meet preset conditions from the wiring units of the chip netlist; Adding a plurality of the universal units to a netlist based on the connection relationship between the universal units to obtain a virtual netlist, wherein the length of the virtual netlist is at least twice the length of the chip netlist, and the width of the virtual netlist is at least twice the width of the chip netlist; Taking the universal unit at the center of the virtual netlist as the starting unit, obtaining the delay data from the starting unit to each target unit, wherein the target unit is the universal unit other than the starting unit in the virtual netlist; The delay data corresponding to each target unit is stored in a preset table to obtain a delay table.
2. The method according to claim 1, characterized in that The step of selecting the common units that meet preset conditions from the wiring units of the chip netlist includes: In the candidate path group corresponding to each wiring unit in the chip netlist, searching for a candidate path group in which no channel exists, wherein the candidate path group corresponding to the wiring unit includes the shortest delay path between the wiring unit and each other wiring unit connected thereto; The wiring units corresponding to the candidate path group without channels are regarded as general units meeting preset conditions.
3. The method according to claim 2, characterized in that The step of using the wiring unit corresponding to the candidate path group without a channel as a general unit satisfying a preset condition includes: Using the wiring unit corresponding to the candidate path group without the channel as a temporary wiring unit; If the wiring unit to which each signal line of the temporary wiring unit is connected is included in the virtual netlist, the temporary wiring unit is regarded as a general unit satisfying a preset condition.
4. The method according to claim 1, characterized in that: The length of the virtual netlist is the sum of the target length and the preset distance, the width of the virtual netlist is the sum of the target width and the preset distance, the target length is twice the length of the chip netlist, the target width is twice the width of the chip netlist, and the preset distance is twice the longest span of the general unit.
5. The method according to claim 1, characterized in that The length of the virtual netlist is greater than the sum of the target length and the preset distance, the width of the virtual netlist is greater than the sum of the target width and the preset distance, the target length is twice the length of the chip netlist, the target width is twice the width of the chip netlist, and the preset distance is twice the longest span of the general unit.
6. The method according to claim 1, characterized in that The method of taking the common unit at the center of the virtual netlist as the starting unit and obtaining the delay data from the starting unit to each target unit includes: The universal unit at the center of the virtual netlist is taken as the starting unit, and the delay data from the starting unit to each target unit is obtained based on the Bellman-Ford algorithm.
7. The method according to claim 1, characterized in that The step of storing the delay data corresponding to each target unit in a preset table to obtain a delay table includes: Obtaining the relative position of the target unit and the starting unit as a reference position; Obtaining a central cell of a preset table, wherein the number of rows of the preset table is the same as the number of rows of the general-purpose cells in the virtual netlist, and the number of columns of the preset table is the same as the number of columns of the general-purpose cells in the virtual netlist; Taking a cell whose relative position to the central cell is the reference position as a target cell; The delay data corresponding to each target unit is stored in the target cell corresponding to the preset table to obtain a delay table.
8. A wiring method, characterized in that: The method comprises: Obtaining a starting logic block and a target logic block of a wiring chip; Determining whether there is a channel on the shortest delay path between the starting logic block and the target logic block; If the channel does not exist, the shortest delay data between the starting logic block and the target logic block is obtained based on a delay table, wherein the delay table is obtained based on the delay table generation method according to any one of claims 1 to 7.
9. An electronic device, characterized in that: include: one or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory, the one or more applications are configured to be executed by the one or more processors, and the one or more applications are configured to execute the method according to any one of claims 1-8.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program codes, which can be called by a processor to execute the method according to any one of claims 1 to 8.