Modularized MOS tube layout structure with standard unit and use method

Abstract

The invention relates to a circuit layout technology for automatically generating analog and mixed signals, in particular to a layout structure with a standard unit-modular MOS (Metal Oxide Semiconductor) tube and a use method. The objective of the invention is to solve the problem that layout generation and layout wiring cannot be automated due to lack of standard structures and non-adjacency of existing automatically generated MOS transistor layouts. According to the main scheme, the MOS transistor layout design of the standard unit-modular structure is included, each standard unit comprises two pieces of virtual polycrystalline silicon, a layout wiring boundary, a power source track and a ground track, the shape and size are regular, the standard unit can be adjacent to the standard unit of the same type in any direction, and the standard unit can be recognized by an EDA tool so as to adapt to the EDA tool and improve layout efficiency. In addition, the invention also provides a use method, which comprises the following steps of: performing automatic layout and wiring through an EDA tool, firstly performing automatic layout and wiring on a circuit formed by NMOS (N-channel Metal Oxide Semiconductor) tubes to form an NMOS module, then performing automatic layout and wiring on a circuit formed by PMOS (P-channel Metal Oxide Semiconductor) tubes to form a PMOS (P-channel Metal Oxide Semiconductor) module, and finally performing automatic wiring on a connection relationship between the two modules. The automatic generation of the circuit structure layout formed by the MOS tubes in the analog and hybrid circuit is realized, so that the layout generation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to a technology for automatically generating analog and mixed signal circuit layouts, and in particular to a layout structure with a standard unit-modular MOS tube and a use method thereof. Background Art

[0002] In the past four decades or even longer, there has been little innovation in analog circuit layout design technology except for parameterized cells (PCELL). PCELL is a tool for generating device layouts. It can generate different device layouts according to the dimensions and parameters set by the physical layout designer. Designers need to manually complete the placement and layout and routing of these layouts to build a complete circuit layout. PCELL has the advantages of programmability, flexibility and adjustable parameters, but the shape and size of the MOS tube layout it generates are irregular, and the port positions of the source, gate, drain and body are not fixed, which has a high degree of freedom. This high degree of freedom also brings the following two main problems:

[0003] 1. Since the MOS tube layouts generated by PCELL have different shapes and sizes, two MOS tube layouts with different sizes and parameters cannot be directly adjacent without violating the design rules (DR). Therefore, the layout occupies a large area, has an irregular shape, and has low area utilization.

[0004] 2. The high-freedom, irregular MOS device layout generated by PCELL is difficult to be recognized and used by existing automated design tools (EDA), which causes the layout of MOS tubes in analog and mixed-signal circuits to rely mainly on manual operations, making the efficiency of analog and mixed circuit layout drawing low. Summary of the invention

[0005] The purpose of the present invention is to solve the problem that the existing automatically generated MOS tube layout lacks a standard structure and cannot be adjacent, resulting in the inability to automate layout generation and layout routing.

[0006] In order to achieve the above object, the present invention adopts the following technical means:

[0007] A standard cell-modular MOS tube layout structure, wherein the layout is divided into an NMOS module and a PMOS module, with spaces between the modules, the NMOS module contains only a standard NMOS cell, the PMOS module contains only a standard PMOS cell, the standard NMOS cell and the standard PMOS cell are collectively referred to as a standard cell, each of the standard cells has two virtual polysilicons, a layout and routing boundary, a power rail and a ground rail, the layout and routing boundary, the power rail and the ground rail are used to allow the standard cells to be arbitrarily adjacent and to make the MOS tube layout structure compatible with EDA tools, the layout and routing boundary is also used to make the shape and size of the standard cells regular, and the two virtual polysilicons are used to separate adjacent standard cells.

[0008] The standard NMOS cell structure includes an N-type implantation region, an active region, a source port, a gate port, a drain port, n identical gate polysilicons, two virtual polysilicons, a layout and wiring boundary, a power rail and a ground rail, as well as parameters such as a channel length, a channel width, and a number of interdigital gates of the transistor, wherein n is equal to the number of interdigital gates of the standard cell; the standard PMOS cell structure includes an N-well, a P-type implantation region, an active region, a source port, a gate port, a drain port, n identical gate polysilicons, two virtual polysilicons, a layout and wiring boundary, a power rail and a ground rail, as well as parameters such as a channel length, a channel width, and a number of interdigital gates of the transistor, wherein n is equal to the number of interdigital gates of the standard cell. The active area, the source port, the gate port, the drain port, and the n gate polysilicon are respectively rectangular structures, the direction parallel to the power rail and the ground rail is called "horizontal", the direction perpendicular to the power rail and the ground rail is called "longitudinal", and the horizontal direction is taken as the left-right direction, and the vertical direction is taken as the front-back direction. The two adjacent sides of the active area, the source port, the gate port, the drain port, and the n gate polysilicon are respectively along the horizontal and vertical directions.

[0009] The gate port is implemented by a metal 1 layer, and the gate port is connected to each gate polysilicon through at least one contact hole; the source port and the drain port are connected to each other by a metal 2 layer; the MOS tube structure also includes n+1 identical metal 1 layers, each of which is rectangular, and its two adjacent sides are respectively along the horizontal and vertical directions, and its horizontal width is equal to the minimum value within the DR allowable range, and the n+1 metal 1 layers are evenly spaced from left to right, and the spacing between two adjacent metal 1 layers is equal to the minimum value within the DR allowable range. The n+1 metal 1 layers are numbered from 1 to n+1 from left to right, and the numbered h hThe metal 1 layer is called the hth metal 1 layer, h = 1, 2, ..., n+1. Among the n+1 metal 1 layers, each metal 1 layer with an odd number is connected to the source port through at least one through hole, each metal 1 layer with an even number is connected to the drain port through at least one through hole, and the n+1 metal 1 layers are respectively connected to the active area through at least one contact hole; the longitudinal lengths of the source port and the drain port are equal and equal to the minimum metal width allowed by DR; the front sides of the source port and the drain port are respectively flush with the front sides of a standard routing track of the process node where the standard unit is located; if The source port, the drain port and the active area are projected onto the same plane, and the source port and the drain port are respectively located between the straight line where the left side and the right side of the active area are located; if the gate port and the active area are projected onto the same plane, the spacing between the gate port and the active area is equal to the minimum value within the DR allowable range; the longitudinal length of each gate polysilicon is equal to the minimum value within the DR allowable range; the rear side of each gate polysilicon of the standard NMOS unit coincides with the rear side of the layout and wiring boundary, and the front side of each gate polysilicon of the standard PMOS unit coincides with the front side of the layout and wiring boundary.

[0010] In the standard cell structure, n gate polysilicons are evenly spaced laterally, and the center spacing between two adjacent gate polysilicons is equal to the common polysilicon center spacing CPP at the process node where the standard cell is located. The lateral width of each gate polysilicon is equal to the length of the channel, and the longitudinal length of the active area is equal to the width of the channel;

[0011] If the n+1 metal 1 layers and the n gate polysilicon layers are projected onto the same plane, the n gate polysilicon layers are located one-to-one in the n gaps between the n+1 metal 1 layers, and there is an equal spacing between each gate polysilicon and the metal 1 layers on its left and right sides, which is the minimum value within the allowable range of DR.

[0012] In the standard cell structure, two virtual polysilicons are arranged at intervals on the left and right. The virtual polysilicon located on the left is called the left virtual polysilicon, and the virtual polysilicon located on the right is called the right virtual polysilicon. The left virtual polysilicon and the right virtual polysilicon are symmetrical with respect to the longitudinal center line of the layout and wiring boundary. The left virtual polysilicon is located on the left side of the leftmost gate polysilicon among the n gate polysilicons, and the center distance between the two is equal to CPP; when the left boundary of the layout and wiring boundary is projected onto the plane where the left virtual polysilicon is located, it will coincide with the longitudinal center line of the left virtual polysilicon. The right virtual polysilicon is located on the right side of the rightmost gate polysilicon among the n gate polysilicons, and the center distance between the two is equal to CPP; when the right boundary of the layout and wiring boundary is projected onto the plane where the right virtual polysilicon is located, it will coincide with the longitudinal center line of the right virtual polysilicon. The lateral width of the virtual polysilicon is the same as the lateral width of the gate polysilicon, and the longitudinal length is equal to a positive integer multiple of the center spacing between the power φ ground tracks in the digital standard cell at the process node where the standard cell is located. The virtual polysilicon is not connected to other parts of the standard cell layout structure.

[0013] The layout and wiring boundary is a frame structure formed by connecting the front boundary, left boundary, rear boundary and right boundary in sequence according to the front, left, rear and right distributions. Its cross section is a rectangle, and the two adjacent sides of the cross section are respectively along the horizontal and vertical directions. The longitudinal length of the cross section of the layout and wiring boundary is equal to a positive integer multiple of the center spacing between the power φ ground tracks in the digital standard cell at the process node where the standard cell is located, and the lateral width is a positive integer multiple of the common polysilicon center spacing CPP at the process node where the standard cell is located.

[0014] If the standard cell is a standard NMOS cell, the N-type injection region is formed inside the layout and wiring boundary, the front edge of the N-type injection region coincides with the front boundary of the layout and wiring boundary, the left edge of the N-type injection region coincides with the left boundary of the layout and wiring boundary, the rear edge of the N-type injection region coincides with the rear boundary of the layout and wiring boundary, and the right edge of the N-type injection region coincides with the right boundary of the layout and wiring boundary.

[0015] If the standard cell is a standard PMOS cell, the P-type injection region is formed inside the layout and wiring boundary, the front edge of the P-type injection region coincides with the front boundary of the layout and wiring boundary, the left edge of the P-type injection region coincides with the left boundary of the layout and wiring boundary, the rear edge of the P-type injection region coincides with the rear boundary of the layout and wiring boundary, and the right edge of the P-type injection region coincides with the right boundary of the layout and wiring boundary.

[0016] In the PMOS module, all standard PMOS cells share an N-well, and the P-type injection regions of the standard PMOS cells are interconnected when they are laterally adjacent. If the N-well, the active region, and the P-type injection region are projected onto the same plane, the P-type injection region is completely inside the N-well, and the active region is completely inside the P-type injection region. In the NMOS module, the N-type injection regions of the standard NMOS cells are interconnected when they are laterally adjacent. If the active region and the N-type injection region are projected onto the same plane, the active region is completely inside the N-type injection region.

[0017] The NMOS cell layout in the present invention does not contain an N-well or a P-type injection region, and the PMOS cell layout in the present invention does not contain an N-type injection region. The advantage is that the area utilization rate of the standard cell layout can be improved, because the N-well and the P-type injection region in the NMOS layout and the N-type injection region in the PMOS layout belong to redundant structures and do not actually flow current or conduction signals. The standard cell layout involved in the present invention does not have these redundant structures. In addition, the cell no longer needs a buffer structure and can also be directly adjacent to other cells of the same type (the same type refers to NMOS and NMOS adjacent, PMOS and PMOS adjacent) without violating DR, so the area utilization rate is higher. The advantage is also that after layout and routing, the N-well parts of all PMOS layouts will be connected to each other to form a large, unified, complete N-well, so that the active areas of all PMOS are away from the edge of the N-well, thereby reducing the well proximity effect, which will increase the threshold voltage of the MOS tube and cause its performance to suffer losses.

[0018] Furthermore, the power rail and the ground rail are respectively rectangular structures, and their two adjacent sides are respectively in the horizontal direction and the vertical direction; the metal layer where the power rail is located is the same as the power rail in the digital standard cell under the process node where the standard cell is located, and the vertical length of the power rail is equal to the width of the power rail in the digital standard cell under the process node where the standard cell is located (the digital standard cell is another set of modules, which already has fixed parameters such as the power rail width, and we need to comply with its fixed parameters before we can use its ready-made software);

[0019] The metal layer where the ground track is located is the same as the ground track in the digital standard cell under the process node where the standard cell is located, and the longitudinal length of the ground track is equal to the width of the ground track in the digital standard cell under the process node where the standard cell is located; if the power track, the ground track and the layout and wiring boundary are projected onto the same plane, the horizontal center line of the power track coincides with the front boundary of the layout and wiring boundary, the horizontal center line of the ground track coincides with the rear boundary of the layout and wiring boundary, the left side of the power track, the left side of the ground track and the left boundary of the layout and wiring boundary are located in the same straight line, and the right side of the power track, the right side of the ground track and the right boundary of the layout and wiring boundary are located in the same straight line.

[0020] If each of the odd-numbered metal 1 layers of the n+1 metal 1 layers of the standard PMOS unit is connected to the power rail, the connection between the source of the standard PMOS unit and the power supply can be achieved; if each of the odd-numbered metal 1 layers of the standard NMOS unit is connected to the ground rail, the grounding of the source of the standard NMOS unit can be achieved.

[0021] Compared with the prior art, the advantage of the standard cell-modular layout structure of the present invention is that the layout structure is divided into NMOS modules and PMOS modules, the module shape is regular, the modules are left empty, and the digital standard cell modules under the process of the standard cell can also be adjacent. The module is composed of standard cells of the same type, and the standard cell structure includes two virtual polysilicon, layout and wiring boundaries, power rails and ground rails. The two virtual polysilicons are used to separate adjacent standard cells so that the two standard cells do not violate DR when they are directly adjacent to each other. The layout and wiring boundaries, power rails and ground rails can make the MOS tube layout structure compatible with EDA tools, and the layout and wiring boundaries can make the shape and size of the layout structure regular. Therefore, the standard cell-modular layout structure of the present invention can improve the overall area utilization of the circuit structure layout; and can be recognized and used by existing EDA tools, so that it can cooperate with existing EDA tools to realize the automatic generation of the circuit structure layout composed of MOS tubes in analog and mixed circuits, and improve the layout efficiency.

[0022] The second technical problem to be solved by the present invention is to provide a method for using a standard unit-modular MOS tube layout structure. The method uses an EDA tool to automatically layout and route the layout structure according to a circuit schematic diagram, thereby realizing automatic generation of a circuit structure layout composed of MOS tubes in analog and mixed circuits. The final generated layout is guaranteed not to violate DR and has a small area, thereby improving layout generation efficiency.

[0023] The technical solution adopted by the present invention to solve the second technical problem is: a method for using a standard unit-modular MOS tube layout structure, comprising the following steps:

[0024] Step (1): setting relevant parameters of a standard unit-modular MOS tube layout structure according to the parameter requirements of each MOS tube in the circuit structure composed of MOS tubes in the analog and hybrid circuits to be automatically laid out and routed as needed, and describing each MOS tube layout structure in GDS format and LEF format to obtain corresponding GDS files and LEF files;

[0025] Step (2): Divide the circuit diagram of the circuit structure composed of MOS tubes in the analog and hybrid circuits that need to be automatically placed and routed into two parts, one of which is completely composed of NMOS and is called an NMOS module, and the other is completely composed of PMOS and is called a PMOS module. Both parts of the circuit diagram are described in Verilog language to form two Verilog files. The connection relationship between the NMOS module and the PMOS module is also described in Verilog language to form a third Verilog file.

[0026] Step (3): Input the obtained GDS file, LEF file and Verilog file describing the NMOS module into the EDA tool;

[0027] Step (4): Run the EDA tool to perform automatic layout and routing to obtain the layout of the NMOS module and the GDS file and LEF file describing the layout;

[0028] Step (5): Input the obtained GDS file, LEF file and Verilog file describing the PMOS module into the EDA tool;

[0029] Step (6): Run the EDA tool to perform automatic layout and routing to obtain the layout of the PMOS module and the GDS file and LEF file describing the layout;

[0030] Step (7): Input all the previously obtained GDS files, LEF files and the Verilog files describing the connection relationship between the two parts of the circuit into the EDA tool;

[0031] Step (8): Run the EDA tool to perform automatic layout and routing to obtain the layout of the complete circuit.

[0032] Through modular design, the present invention realizes a standard unit-modular MOS tube layout structure, solving the problem that the existing automatically generated MOS tube layout lacks a standard structure and cannot realize automatic layout and routing. The specific technical effect analysis is as follows:

[0033] Modular design: By dividing the layout into NMOS and PMOS modules, the modules are composed of the same type of standard cells, and any two MOS tube units of the same type can be directly adjacent without violating the design rule (DR). Compared with the existing technology, this design reduces the redundant structure in the MOS unit layout and greatly reduces the area required for layout. Dividing the circuit into two modules itself does not reduce the area, but when divided into two modules, each module only has the same type of MOS tubes, so each MOS tube layout can have a simpler internal structure and higher area utilization while ensuring adjacency, thereby reducing the overall area.

[0034] Standard cell structure: The standard cell structure includes virtual polysilicon, layout and routing boundaries, power rails and ground rails. The standard cells inside the module do not violate DR when they are directly adjacent, making the MOS tube layout structure compatible with existing EDA tools and improving the efficiency of layout and routing.

[0035] The role of layout and routing boundaries: Layout and routing boundaries not only make the shape and size of standard cells regular, but also ensure that standard cells can be recognized and utilized by existing EDA tools, thereby realizing the automatic generation of circuit structure layouts composed of MOS tubes in analog and mixed circuits.

[0036] Optimization of metal layers: The standard cell contains n+1 metal 1 layers, and the lateral width of each metal 1 layer is equal to the minimum value within the DR allowable range. This enables the standard cell to make full use of the space during layout and further reduces the layout area.

[0037] Setting of power and ground rails: The setting of power rail VDD and ground rail VSS enables standard cells to be regularly arranged in an array by EDA tools, which not only improves the efficiency of layout but also improves the power supply stability of the circuit.

[0038] Simplified usage method: The usage method of the standard unit-modular MOS tube layout structure realizes automatic layout and routing through EDA tools, simplifies the generation process of the circuit structure layout composed of MOS tubes in analog and mixed circuits, and improves the layout generation efficiency.

[0039] In general, compared with the prior art, the advantage of the method for using the standard unit-modular MOS tube layout structure of the present invention is that the generated standard unit structure rules can be recognized and used by existing EDA tools. The MOS tube layout structure is automatically laid out and routed according to the circuit schematic diagram by the EDA tool. The time taken by the EDA tool to automatically lay out and route is extremely short, usually not more than 1 hour. The layout automatically generated by the EDA tool is guaranteed not to violate the DR, and each MOS tube is placed between the alternating power rails and ground rails to improve the power supply stability of the circuit. Each MOS tube is placed between the alternating power rails and ground rails. MOS tubes in the same row can share the same well contact unit (the well contact unit is outside the MOS tube) to connect the body to the power supply or ground, reducing the layout area. In the layout stage, each MOS tube layout will be adjacent to each other as much as possible to reduce the layout area. The user can arbitrarily adjust the aspect ratio, size, metal layer used for routing, input / output port position, layout priority and routing priority of each node in the circuit of the final generated layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a schematic structural diagram of a standard NMOS unit in an NMOS module according to the first embodiment of the present invention;

[0041] Figure 2 Schematic diagram of the structure of a standard PMOS unit in a PMOS module according to the second embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of the structure of the standard NMOS unit layout structure of the third embodiment of the present invention;

[0043] Figure 4 This is a schematic structural diagram of a standard PMOS unit layout structure according to a fourth embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of the structure of left-right adjacent standard cells in Embodiment 5 of the present invention;

[0045] Figure 6 This is a schematic diagram of the structure of the upper and lower adjacent standard units in the sixth embodiment of the present invention;

[0046] Figure 7 Circuit diagrams of circuit structures composed of MOS tubes in analog and mixed circuits that require automatic layout and routing;

[0047] Figure 8 An intermediate layout generated by the method for using the standard unit φ modular MOS tube layout structure of the present invention;

[0048] Fig. 9 The final layout is generated by the method for using the standard unit φ modular MOS tube layout structure of the present invention. DETAILED DESCRIPTION

[0049] One of the technical problems to be solved by the present invention is that the existing automatically generated MOS tube layout does not have a standard structure, and it is impossible to realize layout generation and layout and wiring automation. The technical means provided by the present invention to solve one of the above technical problems is a MOS tube layout structure with a standard unit-modular structure. The layout structure is generally divided into two modules, namely the NMOS module and the PMOS module. The module shape is regular, and the module is composed of the same type of standard units. Any two MOS tube units can be directly adjacent without violating DR. The MOS tube layout design can be compatible with existing EDA tools, automatically generate circuit layouts composed of MOS tubes in analog and mixed circuits, while ensuring that DR is not violated, and optimize the layout area, effectively improving the efficiency of layout design.

[0050] The present invention discloses a standard unit-modular MOS tube layout structure, the main body of the layout is divided into an NMOS module and a PMOS module, and there is space between the modules, and the distance is the minimum value within the DR allowable range. The standard unit-modular MOS tube layout structure of the present invention is further described in detail below in conjunction with the accompanying drawings.

[0051] Embodiment 1: Figure 1As shown, this embodiment is a schematic diagram of the structure of a standard NMOS unit inside an NMOS module. In this embodiment, the number of finger gates of the standard NMOS unit is 4, and the main structure of the standard unit layout includes two virtual polysilicon 6, layout and wiring boundary 1, power rail VDD, ground rail VSS, active area 5, source port S, gate port G, drain port D, N-type injection area 4, and the same four gate polysilicon 3. The active area 5, source port S, gate port G, drain port D, and four gate polysilicon 3 are rectangular structures. The direction parallel to the power and ground rails is called "horizontal", and the direction perpendicular to the power and ground rails is called "vertical", and the horizontal direction is used as the left and right direction, and the vertical direction is used as the front and back direction. The virtual polysilicon 6, active area 5, source port S, gate port G, drain port D and the four gate polysilicon 3 are adjacent to each other. The edges are respectively along the horizontal and vertical directions; the gate port G is implemented by a metal 1 layer, and the gate port G is connected to each gate polysilicon 3 through at least one contact hole 2; the source port S and the drain port D are respectively implemented by a metal 2 layer, and the front side of the source port S is horizontally flush with the front side of the 6th standard routing track among the 9 standard routing tracks under the process node where the standard cell is located, and the vertical length is equal to the vertical length of the 6th standard routing track, and the front side of the drain port D is horizontally flush with the front side of the 8th standard routing track among the 9 standard routing tracks under the process node where the standard cell is located, and the vertical length is equal to the vertical length of the 8th standard routing track, so that the routing implemented by the subsequent EDA tool will not violate the metal-related DR. If the layout and routing boundary 1 is projected to the plane where the metal 1 layer and the metal 2 layer are located, all metal 1 layer and metal 2 layer structures are inside the layout and routing boundary 1 and the size takes the minimum value allowed by the DR, so that the two standard cells do not violate the metal-related DR when they are adjacent to each other on the left and right.

[0052] If the source port S, the drain port D and the active area 5 are projected onto the same plane, the source port S and the drain port D will be located between the straight line on the left side and the straight line on the right side of the active area 5 respectively; if the gate port G and the active area 5 are projected onto the same plane, the spacing between the gate port G and the active area 5 is equal to the minimum value within the allowable range of DR; the longitudinal length of the active area 5 is equal to the channel width of the standard unit; the four gate polysilicons 3 are evenly spaced in the lateral direction, and the center spacing between two adjacent gate polysilicons 3 is equal to the common polysilicon center spacing CPP under the process node where the standard unit is located, the lateral length of each gate polysilicon 3 is equal to the channel length of the standard unit, the longitudinal length of each gate polysilicon 3 is equal to the minimum value within the allowable range of DR, and the rear side of each gate polysilicon 3 coincides with the rear side of the layout and wiring boundary 1.

[0053] In this embodiment, the main structure of the standard unit further includes five metal 1 layers 7, all of which are rectangular structures, and their two adjacent sides are respectively in the horizontal direction and the vertical direction, the horizontal width of each metal 1 layer 7 is equal to the minimum value within the DR allowable range, the five metal 1 layers are evenly spaced from left to right, and the spacing between two adjacent metal 1 layers is equal to the minimum value within the DR allowable range; the five metal 1 layers are numbered from 1 to 5 from left to right, and the metal 1 layer numbered h is called the hth metal 1 layer, h = 1, 2, 3, 4, 5; the five metal 1 layers are evenly spaced from left to right, and the spacing between two adjacent metal 1 layers is equal to the minimum value within the DR allowable range; the five metal 1 layers are numbered from 1 to 5 from left to right, and the metal 1 layer numbered h is called the hth metal 1 layer, h = 1, 2, 3, 4, 5; In layer 7, each metal 1 layer 7 with an odd number is connected to the source port S through at least one through hole 8, each metal 1 layer 7 with an even number is connected to the drain port D through at least one through hole 9, and the five metal 1 layers 7 are connected to the active area 5 through at least one contact hole 10 respectively; if the five metal 1 layers 7 and the four gate polysilicon 3 are projected onto the same plane, then the four gate polysilicon 3 are located one by one in the four gaps formed between the five metal 1 layers 7, and there is an equal spacing between each gate polysilicon 3 and the metal 1 layers 7 on its left and right sides.

[0054] In this embodiment, the layout and wiring boundary 1 is a frame structure formed by sequentially connecting the front boundary, the left boundary, the rear boundary and the right boundary distributed in front, left, rear and right directions, and its cross section is a rectangle, and the two adjacent sides of the cross section are respectively in the horizontal direction and the vertical direction, the longitudinal length of the cross section of the layout and wiring boundary 1 is equal to 1 times the center spacing between the power supply and ground tracks in the digital standard cell at the process node where the standard cell is located, and the lateral width is 5 times the common polysilicon center spacing CPP at the process node where the standard cell is located, the front boundary is the front side of the layout and wiring boundary 1, the rear boundary is the rear side of the layout and wiring boundary 1, the left boundary is the left side of the layout and wiring boundary 1, and the right boundary is the right side of the layout and wiring boundary 1. The inside of the layout and wiring boundary 1 is an N-type implantation region 4, the front side edge of the N-type implantation region 4 coincides with the front boundary of the layout and wiring boundary 1, the left side edge of the N-type implantation region 4 coincides with the left boundary of the layout and wiring boundary 1, the rear side edge of the N-type implantation region 4 coincides with the rear boundary of the layout and wiring boundary 1, and the right side edge of the N-type implantation region 4 coincides with the right boundary of the layout and wiring boundary 1. If the active region 5 and the N-type implantation region 4 are projected onto the same plane, the active region 5 is completely inside the N-type implantation region 4 .

[0055] In this embodiment, it is worth noting that the "power rail VDD" and the "power rail VDD in the digital standard cell at the process node where the standard cell is located" are different, but have the same width, the former corresponds to the latter, the power rail VDD and the ground rail VSS are respectively rectangular structures, and their two adjacent sides are respectively along the horizontal and vertical directions, the metal level where the power rail VDD is located is the same as the power rail VDD in the digital standard cell at the process node where the standard cell is located, the vertical length of the power rail VDD is equal to the width of the power rail VDD in the digital standard cell at the process node where the standard cell is located, and the metal level where the ground rail VSS is located is the same as the digital standard cell at the process node where the standard cell is located. The ground track VSS in the digital standard cell is the same, and the longitudinal length of the ground track VSS is equal to the width of the ground track VSS in the digital standard cell under the process node where the standard cell is located; if the power track VDD, the ground track VSS and the layout and wiring boundary 1 are projected onto the same plane, the power track VDD coincides with the front boundary of the layout and wiring boundary 1 along the horizontal center line, and the ground track VSS coincides with the rear boundary of the layout and wiring boundary 1 along the horizontal center line, the left side of the power track VDD and the left side of the ground track VSS are both located in the same straight line with the left boundary of the layout and wiring boundary 1, and the right side of the power track VDD and the right side of the ground track VSS are both located in the same straight line with the right boundary of the layout and wiring boundary 1.

[0056] In this embodiment, two virtual polysilicon 6 are arranged at intervals on the left and right, the virtual polysilicon on the left is called the left virtual polysilicon 6, and the virtual polysilicon on the right is called the right virtual polysilicon 6, and the left virtual polysilicon 6 and the right virtual polysilicon 6 are symmetrical with respect to the center line of the layout and wiring boundary 1 along the longitudinal direction;

[0057] The left virtual polysilicon 6 is located on the left side of the leftmost gate polysilicon 3 among the four gate polysilicons 3, and the center distance between the two is equal to CPP. When the left boundary of the layout and wiring boundary 1 is projected onto the plane where the left virtual polysilicon 6 is located, it will coincide with the center line of the virtual polysilicon in the longitudinal direction.

[0058] The right virtual polysilicon 6 is located on the right side of the rightmost gate polysilicon 3 among the four gate polysilicons 3, and the center distance between the two is equal to CPP. When the right boundary of the layout and wiring boundary 1 is projected onto the plane where the right virtual polysilicon 6 is located, it will coincide with the center line of the virtual polysilicon in the longitudinal direction.

[0059] The lateral width of the virtual polysilicon 6 is the same as the lateral width of the gate polysilicon 3, and the longitudinal length of the virtual polysilicon 6 is equal to a positive integer multiple of the center spacing between the power-ground rails in the digital standard cell at the process node where the standard cell is located. The virtual polysilicon 6 is not connected to other parts of the standard cell layout structure.

[0060] In this embodiment, the standard cell layout structure has no body pole port. By placing the standard cell layout structure in parallel with the well tap cell (Well Tap Cell) in the digital standard cell library under the process node where it is located, the front boundary of the layout and wiring boundary 1 of the standard cell layout is in the same straight line with the front boundary of the layout and wiring boundary of the well tap cell, and the rear boundary of the layout and wiring boundary 1 of the standard cell layout is in the same straight line with the rear boundary of the layout and wiring boundary of the well tap cell, so that the standard NMOS cell can connect the body pole to the ground. Since the standard cell layout structure of this embodiment has no body pole port, it is only necessary to place the standard cell layout structure in parallel with the well tap cell to connect the body pole of the standard cell to the corresponding power supply or ground, without the need to additionally design a body pole port, and without the need for additional structure to connect the body pole of the standard cell, and multiple standard cell layout structures can share the same well tap cell, so the layout area obtained after the layout and wiring of the standard cell layout structure of this embodiment is smaller.

[0061] In this embodiment, the layout and routing boundary 1, the power rail VDD and the ground rail VSS are used to make the MOS tube layout structure recognized by the EDA tool for layout and adjacent to the adjacent standard cells. The layout and routing boundary 1 is also used to make the shape and size of the standard cell layout structure regular; when adjacent to each other left and right, two adjacent standard cells share a virtual polysilicon 6, and when adjacent to each other up and down, two adjacent standard cells share a power rail VDD or a ground rail VSS, so that any two standard cells will not violate DR when adjacent in any direction. Since the EDA tool will place all cells between the alternating power rail VDD and the ground rail VSS during layout, the setting of the power rail VDD and the ground rail VSS enables the standard cells to be placed in a regular manner by the EDA tool.

[0062] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: Figure 2As shown, this embodiment is a schematic diagram of the structure of a standard PMOS unit inside a PMOS module. In this embodiment, the number of finger gates of the standard unit is 4, and the main structure of the standard unit layout includes two virtual polysilicon 6, layout and wiring boundary 1, power rail VDD, ground rail VSS, active area 5, source port S, gate port G, drain port D, N well 11, P-type injection area 12, and the same 4 gate polysilicon 3. The gate port G is implemented by 1 metal 1 layer, and the gate port G is connected to each gate polysilicon 3 through at least one contact hole 2; the source port S and the drain port D are respectively implemented by 1 metal 1 layer. It belongs to the 2-layer implementation. At the same time, the front side of the source port S is horizontally flush with the front side of the second standard routing track among the 9 standard routing tracks under the process node where the standard cell is located, and the longitudinal length is equal to the longitudinal length of the second standard routing track. The front side of the drain port D is horizontally flush with the front side of the fourth standard routing track among the 9 standard routing tracks under the process node where the standard cell is located, and the longitudinal length is equal to the longitudinal length of the fourth standard routing track, so that the routing implemented by the subsequent EDA tool will not violate the metal-related DR.

[0063] If the source port S, the drain port D and the active area 5 are projected onto the same plane, the source port S and the drain port D will be located between the straight line on the left side and the straight line on the right side of the active area 5 respectively; if the gate port G and the active area 5 are projected onto the same plane, the spacing between the gate port G and the active area 5 is equal to the minimum value within the allowable range of DR; the longitudinal length of the active area 5 is equal to the channel width of the standard unit; the four gate polysilicons 3 are evenly spaced in the lateral direction, and the center spacing between two adjacent gate polysilicons 3 is equal to the common polysilicon center spacing CPP under the process node where the standard unit is located, the lateral length of each gate polysilicon 3 is equal to the channel length of the standard unit, the longitudinal length of each gate polysilicon 3 is equal to the minimum value within the allowable range of DR, and the front side of each gate polysilicon 3 coincides with the front side of the layout and wiring boundary 1.

[0064] In this embodiment, the layout and wiring boundary 1 is a frame structure formed by sequentially connecting the front boundary, the left boundary, the rear boundary and the right boundary distributed in front, left, rear and right directions. Its cross section is a rectangle, and two adjacent sides of its cross section are respectively in the horizontal direction and the vertical direction. The longitudinal length of the cross section of the layout and wiring boundary 1 is equal to 1 times the center spacing between the power φ ground tracks in the digital standard cell at the process node where the standard cell is located, and the lateral width is 5 times the common polysilicon center spacing CPP at the process node where the standard cell is located. The front boundary is the front side of the layout and wiring boundary 1, the rear boundary is the rear side of the layout and wiring boundary 1, the left boundary is the left side of the layout and wiring boundary 1, and the right boundary is the right side of the layout and wiring boundary 1. The interior of the layout and wiring boundary 1 is a P-type injection region 12, the front side edge of the P-type injection region 12 coincides with the front boundary of the layout and wiring boundary 1, the left side edge of the P-type injection region 12 coincides with the left boundary of the layout and wiring boundary 1, the rear side edge of the P-type injection region 12 coincides with the rear boundary of the layout and wiring boundary 1, and the right side edge of the P-type injection region 12 coincides with the right boundary of the layout and wiring boundary 1. If the active region 5 and the P-type implantation region 12 are projected onto the same plane, the active region 5 is completely inside the P-type implantation region 12. If the N-well and the P-type implantation region 12 are projected onto the same plane, the P-type implantation region 12 is completely inside the N-well.

[0065] Embodiment 3: In this embodiment, based on the embodiment 1, among the five metal 1 layers 7, each metal 1 layer 7 with an odd number is connected to the ground track VSS, such as Figure 3 As shown, at this time, the standard cell layout structure of this embodiment can directly realize the grounding of the source of the NMOS tube, and its source port S can be omitted.

[0066] Embodiment 4: In this embodiment, based on the embodiment 2, among the five metal 1 layers 7, each metal 1 layer 7 with an odd number is connected to the power rail VDD, such as Figure 4 As shown, the standard cell layout structure of this embodiment can directly realize the connection between the source of the PMOS tube and the power supply, and the source port S thereof can be omitted.

[0067] Embodiment 5: Based on Embodiment 1, this embodiment shows a layout structure in which standard NMOS cells are adjacent to each other along the left and right boundaries of the layout and wiring, and two standard cells share a virtual polysilicon 6 .

[0068] Embodiment 6: Based on Embodiment 1, this embodiment shows a layout structure in which standard NMOS cells are adjacent to each other along the upper and lower boundaries of the layout and wiring, and two standard cells share a power rail or a ground rail.

[0069] The present invention also discloses a method for using the above standard unit φ modular MOS tube layout structure. The method for using the standard unit φ modular MOS tube layout structure of the present invention is further described in detail below in conjunction with the accompanying drawings.

[0070] Embodiment: A method for using a standard unit φ modular MOS tube layout structure comprises the following steps:

[0071] Step (1): according to the parameter requirements of each MOS tube in the circuit composed of MOS tubes in the analog and hybrid circuits to be automatically placed and routed, the relevant parameters of the modular MOS tube layout structure with standard unit φ are set, and the standard unit layout structure of each MOS tube is described in GDS format and LEF format to obtain the corresponding GDS file and LEF file;

[0072] Step (2): Divide the circuit diagram of the circuit structure composed of MOS tubes in the analog and hybrid circuits that need to be automatically placed and routed into two parts, one of which is completely composed of NMOS and is called an NMOS module, and the other is completely composed of PMOS and is called a PMOS module. Both parts of the circuit diagram are described in Verilog language to form two Verilog files. The connection relationship between the NMOS module and the PMOS module is also described in Verilog language to form a third Verilog file.

[0073] Step (3): Input the obtained GDS file, LEF file and Verilog file describing the NMOS module into the EDA tool;

[0074] Step (4): Run the EDA tool to perform automatic layout and routing to obtain the layout of the NMOS module and the GDS file and LEF file describing the layout.

[0075] Step (5): Input the obtained GDS file, LEF file and Verilog file describing the PMOS module into the EDA tool;

[0076] Step (6): Run the EDA tool to perform automatic layout and routing to obtain the layout of the PMOS module and the GDS file and LEF file describing the layout.

[0077] Step (7): Input all the previously obtained GDS files, LEF files and the Verilog files describing the connection relationship between the two parts of the circuit into the EDA tool;

[0078] Step (8): Run the EDA tool to perform automatic layout and routing to obtain the layout of the complete circuit.

[0079] In this embodiment, the circuit structure composed of MOS transistors in the analog and hybrid circuits that need to be automatically placed and routed involves a total of five MOS transistors, which are respectively denoted as M1, M2, M3, M4, and M5 from bottom to top and from left to right, wherein M1, M2, and M3 are PMOS transistors, forming a PMOS module, and M4 and M5 are NMOS transistors, forming an NMOS module. There are a total of 6 input / output ports, denoted as VIN1, VIN2, VOUT1, VOUT2, Vbl, and Vb2. The connection relationship between each port and the device is as follows: Figure 7 As shown. After designing the corresponding five MOS tube standard cell layouts according to the parameter requirements of each MOS tube, they are described in GDS format and LEF format respectively to obtain the corresponding GDS file and LEF file. The circuit diagram of the circuit structure is described in Verilog language to form three Verilog files. The obtained GDS file and LEF file are input into the EDA tool. First, the Verilog file of the NMOS module is input into the EDA tool. The EDA tool will automatically call the corresponding MOS tube standard cell layout and place the standard cell layouts of the three NMOS tubes, namely M1, M2, and M3, in an array between the alternating power rails VDD and ground rails VSS, and fill in the well contact unit and the filling unit. The obtained NMOS module layout is described in GDS and LEF formats to generate the corresponding GDS file and LEF file. Then input the Verilog file of the PMOS module into the EDA tool. The EDA tool will automatically call the corresponding MOS tube standard cell layout and place the standard cell layouts of the two PMOS tubes, namely M4 and M5, in an array between the alternating power rails VDD and ground rails VSS, and fill in the well contact unit and the filling unit. The obtained PMOS module layout is described in GDS and LEF formats, and the corresponding GDS file and LEF file are generated, such as Figure 8 All the above GDS files, LEF files and the Verilog file describing the connection relationship between the NMOS module and the PMOS module are input into the EDA tool. The EDA tool will automatically route the NMOS module and the PMOS module, complete the connection between the NMOS module and the PMOS module, and determine the input / output port position 13 according to the method specified by the user, as shown in FIG. Fig. 9 shown.

Claims

1. A standard unit-modular MOS tube layout structure, characterized in that: The main body of the layout is divided into NMOS modules and PMOS modules, with spaces between the modules, and the modules are composed of standard cells of the same type; The structure of the standard cell includes two virtual polysilicons (6), a layout and wiring boundary (1), a power rail VDD and a ground rail VSS, and the virtual polysilicon (6) is used to separate adjacent standard cells; The layout and routing boundary (1), the power rail VDD and the ground rail VSS are used to enable the MOS tube layout structure to be recognized by an EDA tool for layout, and to enable the NMOS module and the PMOS module to be adjacent to the digital standard cell module under the process of the standard cell; The layout and routing boundary (1) is also used to make the shape and size of the standard cell layout structure regular; There are two types of standard cells: Standard NMOS cell: located in the NMOS module, the standard cell layout structure also includes an N-type injection region; Standard PMOS cell: located in the PMOS module, the standard cell layout structure also includes an N-well and a P-type injection region.

2. The standard unit-modular MOS tube layout structure according to claim 1, characterized in that: The main layout structure of the standard NMOS unit includes an active area (5), a source port (S), a gate port (G), a drain port (D), an N-type implantation area (4) and n identical gate polysilicon electrodes (3), as well as transistor channel length, channel width, and gate finger number parameters. The main layout structure of the standard PMOS unit includes an active area (5), a source port (S), a gate port (G), a drain port (D), an N well (11), a P-type implantation area (12) and n identical gate polysilicon (3), as well as transistor channel length, channel width, and finger gate number parameters; n is equal to the number of finger gates of the standard unit, the active area (5), the source port (S), the gate port (G), the drain port (D) and the n gate polysilicon (3) are respectively rectangular structures, the direction parallel to the power supply and ground rails is called "horizontal", the direction perpendicular to the power supply and ground rails is called "vertical", and the horizontal direction is regarded as the left-right direction, and the vertical direction is regarded as the front-back direction, the two adjacent sides of the active area, the source port, the gate port, the drain port and the n gate polysilicon are respectively along the horizontal direction and the vertical direction, the vertical length of the active area is equal to the channel width, and the horizontal length of each gate polysilicon is equal to the channel length; If the channel length is less than or equal to the maximum channel length of the digital standard cell library of the process, the upper boundary of the active area of ​​the PMOS cell coincides with the lower boundary of the power rail, and the lower boundary of the active area of ​​the NMOS cell coincides with the upper boundary of the ground rail. Otherwise, the distance between the upper boundary of the active area of ​​the PMOS and the lower boundary of the power rail takes the minimum value allowed by DR, and the distance between the lower boundary of the active area of ​​the NMOS and the upper boundary of the ground rail takes the minimum value allowed by DR. If the channel length is less than or equal to the maximum channel length of the digital standard cell library of the process, the upper boundary of the gate polysilicon of the PMOS cell coincides with the upper layout and wiring boundary, and the lower boundary of the gate polysilicon of the NMOS cell coincides with the lower layout and wiring boundary. Otherwise, the distance between the upper boundary of the gate polysilicon of the PMOS cell and the upper layout and wiring boundary takes the minimum value allowed by DR, and the distance between the lower boundary of the gate polysilicon of the NMOS cell and the lower layout and wiring boundary takes the maximum value allowed by DR. Regardless of the range of the channel length, the distance that the lower boundary of the gate polysilicon of the PMOS cell exceeds the active area takes the minimum value allowed by DR, and the distance that the upper boundary of the gate polysilicon of the NMOS cell exceeds the active area takes the minimum value allowed by DR.

3. The standard unit-modular MOS tube layout structure according to claim 2, characterized in that: The gate port (G) is implemented by using 1 metal 1 layer, and the gate port is connected to each gate polysilicon (3) through at least one contact hole; the source port (S) and the drain port (D) are both implemented by using 1 metal 2 layers; The main structure of the standard cell layout also includes n+1 metal 1 layers (7), each of the n+1 metal 1 layers (7) is a rectangular structure, and its two adjacent sides are respectively along the horizontal and vertical directions, the horizontal width of each metal 1 layer (7) is equal to the minimum value within the DR allowable range, the n+1 metal 1 layers (7) are evenly spaced from left to right, and the spacing between two adjacent metal 1 layers is equal to the minimum value within the DR allowable range, the n+1 metal 1 layers are numbered from 1 to n+1 from left to right, and the metal 1 layer numbered h is called the hth metal 1 layer, h=1, 2, ..., n+1; Among the n+1 metal 1 layers, each metal 1 layer (7) with an odd number is connected to the source port (S) through at least one through hole, and each metal 1 layer (7) with an even number is connected to the drain port (D) through at least one through hole; n+1 metal 1 layers (7) are respectively connected to the active area (5) through at least one contact hole; The longitudinal lengths of the source port (S) and the drain port (D) are equal and both equal to the minimum metal width allowed by DR; The front sides of the source port (S) and the drain port (D) are respectively flush with the front sides of a standard wiring track of the process node where the standard unit is located; If the source port (S), the drain port (D) and the active area (5) are projected onto the same plane, the source port (S) and the drain port (D) will be located between the straight line on the left side and the straight line on the right side of the active area (5), respectively; If the gate port (G) and the active area (5) are projected onto the same plane, the distance between the gate port (G) and the active area (5) is equal to the minimum value within the DR allowable range; the longitudinal length of each gate polysilicon (3) is equal to the minimum value within the DR allowable range; The rear side of each gate polysilicon (3) of the standard NMOS unit coincides with the rear side of the layout and wiring boundary; The front side of each gate polysilicon (3) of the standard PMOS unit coincides with the front side of the layout and wiring boundary.

4. The standard unit-modular MOS tube layout structure according to claim 3, characterized in that: The layout and wiring boundary (1) is a frame structure formed by sequentially connecting the front boundary, the left boundary, the rear boundary and the right boundary distributed in the front, left, rear and right directions, and its cross section is rectangular, and two adjacent sides of the cross section are respectively along the horizontal and vertical directions. The longitudinal length of the cross section of the layout and wiring boundary (1) is equal to a positive integer multiple of the spacing between power supply and ground tracks in the digital standard cell at the process node where the standard cell is located, and the lateral width is a positive integer multiple of the common polysilicon center spacing CPP at the process node where the standard cell is located.

5. The standard unit-modular MOS tube layout structure according to claim 4, characterized in that: The standard NMOS unit layout structure further includes an N-type injection region (4), the front edge of the N-type injection region coincides with the front boundary of the layout and wiring boundary, the left edge of the N-type injection region (4) coincides with the left boundary of the layout and wiring boundary, the rear edge of the N-type injection region coincides with the rear boundary of the layout and wiring boundary, and the right edge of the N-type injection region coincides with the right boundary of the layout and wiring boundary; The standard PMOS unit layout structure further includes an N-well (11) and a P-type injection region (12). The N-well (11) is shared by the standard PMOS units in the PMOS module. A single standard PMOS unit has a P-type injection region (12). The front edge of the P-type injection region (12) coincides with the front boundary of the layout and wiring boundary (1). The left edge of the P-type injection region (12) coincides with the left boundary of the layout and wiring boundary (1). The rear edge of the P-type injection region (12) coincides with the rear boundary of the layout and wiring boundary (1). The right edge of the P-type injection region (12) coincides with the right boundary of the layout and wiring boundary (1).

6. The standard unit-modular MOS tube layout structure according to claim 5, characterized in that: If the N-type implantation region (4) and the active region (5) in the NMOS module are projected onto the same plane, the active region (5) is completely inside the N-type implantation region (4); If the N-well (11), the P-type injection region (12) and the active region (5) in the PMOS module are projected onto the same plane, the P-type injection region (12) is completely inside the N-well (11), and the active region (5) is completely inside the P-type injection region (12).

7. The standard unit-modular MOS tube layout structure according to claim 6, characterized in that: The power rail VDD and the ground rail VSS are respectively rectangular structures, and two adjacent sides thereof are respectively in the horizontal direction and the vertical direction; The metal layer where the power rail VDD is located is the same as the power rail in the digital standard cell at the process node where the standard cell is located, and the longitudinal length of the power rail is equal to the width of the power rail in the digital standard cell at the process node where the standard cell is located; The metal layer where the ground track VSS is located is the same as the ground track in the digital standard cell at the process node where the standard cell is located, and the longitudinal length of the ground track is equal to the width of the ground track in the digital standard cell at the process node where the standard cell is located; If the power rail VDD, the ground rail VSS and the layout and routing boundary (1) are projected onto the same plane, the power rail VDD coincides with the front boundary of the layout and routing boundary along the horizontal center line, the ground rail VSS coincides with the rear boundary of the layout and routing boundary (1) along the horizontal center line, the left side of the power rail VDD and the left side of the ground rail VSS are both located in the same straight line with the left boundary of the layout and routing boundary (1), and the right side of the power rail VDD and the right side of the ground rail VSS are both located in the same straight line with the right boundary of the layout and routing boundary (1); If the source of the MOS tube in the circuit is connected to VDD or VSS, then in the n+1 metal 1 layers of the standard PMOS unit, each metal 1 layer with an odd number is connected to the power rail VDD, and the connection between the source of the PMOS tube and the power rail VDD can be realized; in the metal 1 layer of the standard NMOS unit, each metal 1 layer with an odd number is connected to the ground rail VSS, and the grounding of the source of the NMOS tube can be realized.

8. The standard unit-modular MOS tube layout structure according to claim 7, characterized in that: n gate polysilicon (1) are evenly spaced in the lateral direction, and the center distance between two adjacent gate polysilicon (3) takes the default value of the process, the lateral width of each gate polysilicon (3) is equal to the length of the channel, and the longitudinal length of the active area is equal to the width of the channel; If n+1 metal 1 layers and n gate polysilicon layers are projected onto the same plane, the n gate polysilicon layers (3) are located one by one in the n gaps formed between the n+1 metal 1 layers, and there is an equal distance between each gate polysilicon (3) and the metal 1 layers on its left and right sides.

9. The standard unit-modular MOS tube layout structure according to claim 8, characterized in that: Two virtual polysilicon (6) are arranged at intervals on the left and right, the virtual polysilicon on the left is called the left virtual polysilicon, and the virtual polysilicon on the right is called the right virtual polysilicon, and the left virtual polysilicon and the right virtual polysilicon are symmetrical with respect to the center line of the layout and wiring boundary along the longitudinal direction; The left virtual polysilicon is located on the left side of the leftmost gate polysilicon among the n gate polysilicons (3), and the center distance between the two is equal to CPP. When the left boundary of the layout and wiring boundary (1) is projected onto the plane where the left virtual polysilicon is located, it will coincide with the center line of the left virtual polysilicon along the longitudinal direction. The right virtual polysilicon is located on the right side of the rightmost gate polysilicon among the n gate polysilicons (3), and the center distance between the two is equal to CPP. When the right boundary of the layout and wiring boundary (1) is projected onto the plane where the right virtual polysilicon is located, it will coincide with the center line of the right virtual polysilicon along the longitudinal direction; The lateral width of the two virtual polysilicons is the same as the lateral width of the gate polysilicon, and the longitudinal length is equal to a positive integer multiple of the center spacing between the power-ground rails in the digital standard cell at the process node where the standard cell is located. The two virtual polysilicons are not connected to other parts of the standard cell layout structure.

10. A method for using a standard unit-modular MOS tube layout structure according to any one of claims 1 to 10, characterized in that The following steps are involved: Step (1): setting relevant parameters of a standard unit-modular MOS tube layout structure according to the parameter requirements of each MOS tube in the circuit structure composed of MOS tubes in the analog and hybrid circuits to be automatically laid out and routed as needed, and describing each MOS tube layout structure in GDS format and LEF format to obtain corresponding GDS files and LEF files; Step (2): Divide the circuit diagram of the circuit structure composed of MOS tubes in the analog and hybrid circuits that need to be automatically placed and routed into two parts, one of which is composed entirely of NMOS and is called an NMOS module, and the other is composed entirely of PMOS and is called a PMOS module. Both parts of the circuit diagram are described in Verilog language to form two Verilog files. The connection relationship between the NMOS module and the PMOS module is also described in Verilog language to form a third Verilog file. Step (3): Input the obtained GDS file, LEF file and Verilog file describing the NMOS module into the EDA tool; Step (4): Run the EDA tool to perform automatic layout and routing to obtain the layout of the NMOS module and the GDS file and LEF file describing the layout; Step (5): Input the obtained GDS file, LEF file and Verilog file describing the PMOS module into the EDA tool; Step (6): Run the EDA tool to perform automatic layout and routing to obtain the layout of the PMOS module and the GDS file and LEF file describing the layout; Step (7): Input all the previously obtained GDS files, LEF files and the Verilog files describing the connection relationship between the two parts of the circuit into the EDA tool; Step (8): Run the EDA tool to perform automatic layout and routing to obtain the layout of the complete circuit.

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