Signal accurate long-delay transmission control method and system based on SSD (Solid State Disk)

Abstract

The invention belongs to the technical field of channel delay, and particularly relates to a signal precise large-delay transmission control method and system based on an SSD, the system comprises a transceiver board, a CPU board and an SSD board, and the transceiver board is integrated with an AD converter, a DA converter, a first FPGA module and a DDR module; a second FPGA module is integrated on the CPU board, the SSD board is connected to the CPU board in an inserted mode, counter timing control is carried out at the positions, close to the AD and the DA, of the transceiving board, data can be transmitted to a preceding-stage FIFO of the DA from a path in advance, and the data are cached in advance in each stage of data caching link on the path of the preceding-stage FIFO from the SSD to the DA. And meanwhile, the SSD is controlled to start to supplement new data to complete signal output, so that delay correction is realized, and accurate delay control is completed.

Description

Technical Field

[0001] The present application belongs to the field of channel delay technology, and specifically relates to a signal precision large-delay transmission control method and system based on SSD. Background Art

[0002] In the existing signal delay transmission control method, after the data is converted into digital form by AD, the data is stored and cached using storage media such as BRAM, URAM, and DDR. Then, based on the length and accuracy of the specific delay control, the data is output from the storage medium, and the data is finally transmitted to DA to complete the data output. In the prior art, the typical storage media used are BRAM, URAM, DDR, etc., and one or more combinations thereof are used according to specific needs. Due to the limited storage depth, the requirements cannot be met in the scenario of ultra-long delay transmission control from tens of minutes to several hours. In the prior art, when faced with the demand for large-delay signal transmission, the system is limited by the data storage depth of the data storage medium used, and cannot realize large-delay signal transmission control to achieve the simulation of ultra-long-distance signal delay transmission scenarios; at the same time, it is impossible to handle the inaccurate delay control caused by the delay overhead in the digital signal processing process. Summary of the invention

[0003] Based on the above problems, the present application provides a signal precision large delay transmission control method and system based on SSD, and its technical solution is:

[0004] A signal precision large delay transmission control method based on SSD, comprising the following steps:

[0005] S1.AD converter completes signal acquisition and inputs biphase I and Q data. I / Q data is converted into data clock domain through FIFO1. Its write clock is the transceiver board system clock CLK_SYS, and its read clock is the transceiver board AURORA1 user clock AURORA1USER_CLK1.

[0006] S2. The data is then transmitted to the CPU through the high-speed port AURORA1, at which time AURORA1 is the user clock AURORA1USER_CLK2; the data is then converted into the data clock domain through FIFO2, and its write clock is the CPU's AURORA1 user clock AURORA1 USER_CLK2, and its read clock is the CPU's AURORA2 user clock AURORA2_USER CLK1;

[0007] S3. The data is then transmitted to the data storage board through the high-speed port AURORA2 and written into the SSD mounted on the storage board. After the data is written into the SSD, the data is not continuously output. When the amount of data accumulates to the required long delay time period, the data is controlled to be continuously output from the SSD and transmitted back to the CPU through the high-speed port AURORA2.

[0008] S4. The data is transmitted back to the CPU through AURORA2, at which time AURORA2 is the user clock AURORA2USER_CLK1. The transmitted I / Q data is converted into the data clock domain through FIFO3, and its write clock is the CPU's AURORA2 user clock AURORA2USER_CLK1, and its read clock is the CPU's AURORA1 user clock AURORA1 USER_CLK2.

[0009] S5. The data is then transmitted to the transceiver board through the high-speed port AURORA1. At this time, AURORA1 is the user clock AURORA1USER_CLK1.

[0010] Preferably, in step S5, the data needs to be written into the DDR for caching to ensure that the subsequent process has sufficient data for output; the data output from the DDR is then converted into the data clock domain through FIFO4, and the data returns to the transceiver board system clock CLK_SYS, and finally the output of the delayed signal is completed through the DA converter.

[0011] Preferably, the AD converter and the DA converter are integrated on the transceiver board, and a counter is set between the two. When the system starts working, when the first data is written into FIFO1, the timing starts, and the data is finally stored in the SSD through the transmission path; then the data is controlled to be output from the SSD and transmitted to FIFO4 along the output path; before the data is continuously transmitted back, a certain preset length of data is pre-cached in FIFO3, DDR, and FIFO4; the flow control requires that if the data in FIFO4 is less than the agreed amount, DDR continues to fill it with data, otherwise, the filling of data is suspended; during the process from the start of pre-caching data to the arrival of the counting moment, FIFO4 is suspended from outputting data to the DA; when the counting moment reaches the signal output moment, FIFO4 is controlled to output data to the outside, and at the same time, the SSD is controlled to continue to transmit data back to complete the supplement of new data, thereby completing the continuous transmission of the signal with large delay and high precision.

[0012] Preferably, the flow control steps are as follows: the storage board monitors the data volume of FIFO3 in the CPU board. When the set value of the data volume is reached, the SSD at the storage board end transmits data to FIFO3 via AURORA2, otherwise, data transmission is suspended; the CPU monitors the data volume of FIFO5 in the DDR in the transceiver board. When the set value of the data volume is reached, FIFO3 transmits data to FIFO5 via AURORA1, otherwise, data transmission is suspended; DDR supports simultaneous writing and reading of data, and DDR SDRAM read is given priority; data movers DataMover are configured at both ends of the DDR SDRAM respectively, and FIFO5 is configured in the front stage of DataMoverWrite to complete data clock domain conversion; the data transmitted back to the transceiver board is written to the DDR through FIFO5 and DataMoverWrite, and data of a preset length is written in bursts each time. When DataMover Read monitors that the second data of the preset length starts to be written, DDR starts to output data to the outside through DataMover Read. During the process of DataMover Read outputting data, the data volume in FIFO4 is monitored. When the data is less than the set depth, the data is output, otherwise, the output is suspended; it is ensured that there is always a preset fragment length of data available in the DDR SDRAM.

[0013] A signal precision large delay transmission control system based on SSD, comprising a transceiver board, a CPU board and an SSD board, wherein the transceiver board integrates an AD converter, a DA converter, an FPGA module 1 and a DDR module; the CPU board integrates an FPGA module 2, the SSD board is plugged into the CPU board, the AD converter sends the collected data to the FPGA module 1, the data is sent to the FPGA module 2 by AURORA1 after being cached, and the data is sent to the SSD board by AURORA2 after being cached in the FPGA module 2;

[0014] When data is transmitted back, it is sent from the SSD board to FPGA module 2, and then sent to the DDR module by AURORA1 after being cached. A timer is set between the AD converter and the DA converter, and the data is sent to the DA converter after being cached. At the same time, the SSD board is controlled to start adding new data and complete the signal output. The entire path from SSD to DA is flow controlled, and a counter is used to control the data to be output to DA at a specified time, thereby achieving delay correction.

[0015] Preferably, the main clock of the FPGA module is the system clock CLK_SYS, which supports large cache transmission of dual-phase I and Q data at the same time; the DDR module adopts the user clock, and in the read priority mode, data can be written during the idle time. The data output by the DDR module is transmitted to the DA converter after the clock domain conversion is completed by the FPGA module cache to realize data output.

[0016] Preferably, the system clock is 156.25MHz, supporting large cache transmission of bi-phase I and Q data at the same time, each I and Q data bit width is 16 bits, and the data rate to be processed can be calculated to be 10000Mbps;

[0017] AURORA1 requires a minimum transmission rate of no less than 10000Mbps, using 16 lanes, and a single lane transmission rate of 12.5Gbps; AURORA2 requires a minimum transmission rate of no less than 10000Mbps, using 8 lanes, and a single lane transmission rate of 12.5Gbps; SSD works by simultaneously writing and reading data, with a data transmission rate of no less than 1250MBps. The current data storage depth is 20TB. Calculation shows that data caching can be performed for target data of no less than four hours.

[0018] Preferably, the DDR operating frequency is 2500MHz, the user clock is 312.5MHz, the user data processing width is 512b, and the DDR works in read priority mode. Data can be written during read idle moments. Therefore, the comprehensive data write and read rate is halved to about 80000Mbps. Combined with the data processing efficiency, the requirement of a data processing rate of not less than 10000Mbps is met.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] Signal delay control is completed based on DDR and SSD, breaking the limitation of storage depth of storage medium on delay length control ability adopted by traditional methods; in the context of large delay signal transmission control, precise delay correction control method based on timer and output path data flow control is used to realize precise signal delay transmission control.

[0021] 1. Signal transmission control with large delay: The SSD and DDR data storage capabilities used in this method are stronger, and their large-depth data storage capabilities are used to achieve signal transmission control with large delay.

[0022] 2. Accurate delay transmission control under the background of large signal delay transmission: Utilize the accurate delay correction control method based on timer and output path data flow control to strictly control the data to be accurately output to DA on demand at the required time, so as to automatically correct the error in the delay transmission control process and ensure the accuracy of delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a schematic diagram of the prior art.

[0024] Figure 2 This is the technical principle diagram of this application. DETAILED DESCRIPTION

[0025] The technical solution of the present application is described in detail below through specific embodiments and drawings. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solution of the present application, rather than limitations on the technical solution of the present application, and the specific technical features may be combined with each other.

[0026] The overall block diagram of existing signal delay transmission technology is as follows: Figure 1 As shown, AD receives external input signals for analog-to-digital conversion, and the converted data is written to the storage medium to realize data caching; according to the needs of delay control, the data is read out from the storage medium; finally, the read data is written to the data receiving interface of DA, thereby realizing the delayed transmission and emission of the signal. In the prior art, typical storage media used in signal delay transmission control technology include BRAM, URAM, DDR, etc. According to different delay lengths and delay accuracy requirements, one or several storage media combinations are used to cache and read out intermediate data, thereby realizing signal delay transmission control of different lengths and accuracies. When facing the scenario of high-precision and small-delay signal transmission control, BRAM or URAM is used as the data storage medium; when facing the scenario of low-precision and large-delay signal transmission control, DDR is used as the data storage medium.

[0027] Figure 2 As shown, a signal precision large delay transmission control system based on SSD includes a transceiver board, a CPU board and an SSD board, wherein the transceiver board integrates an AD converter, a DA converter, an FPGA module 1 and a DDR module; the CPU board integrates an FPGA module 2, and the SSD board is plugged into the CPU board; the AD converter sends the collected data to the FPGA module 1, and the data is sent to the FPGA module 2 by AURORA1 after being cached, and the data is sent to the SSD board by AURORA2 after being cached in the FPGA module 2; when the data is transmitted back, it is sent from the SSD board to the FPGA module 2, and is sent to the DDR module through caching and AURORA1, a timer is set between the AD converter and the DA converter, and the data is sent to the DA converter through caching, and at the same time, the SSD board is controlled to start adding new data to complete the signal output, thereby realizing delay correction.

[0028] The method proposes a signal precision large delay transmission control system and method based on SSD and DDR. First, the data collected by AD is cached in SSD via the input transmission path, and then the data is read from SSD and written into DA via the output data transmission path to complete the data delay transmission. The ability of data large delay transmission control is improved by using SSD. At the same time, DDR is configured on the data transmission path and in the front stage of DA, and DDR is used to pre-cache data to ensure the continuity of signal transmission. The present invention proposes a precise delay correction control method based on timer and output path data flow control. In the system, data is transmitted from AD of the transceiver board to CPU board via AURORA, and then transmitted to CPU board via AURO RA is transmitted to the data storage board, and finally the data is stored in the SSD on the storage board mounted on the CPU board. The data read from the SSD is then transmitted to the DA of the transceiver board through two levels of AURORA, and the output path data flow is controlled. Counter timing control is performed on the transceiver board near AD and DA. The data will be transmitted from the path to the front-stage FIFO of DA in advance. Data is pre-cached in each level of data cache link on the front-stage FIFO path from SSD to DA. When the delay control moment arrives, data starts to be transmitted from the front-stage FIFO of DA to DA, and at the same time, the SSD is controlled to start adding new data to complete the signal output, thereby realizing delay correction and completing precise delay control.

[0029] The present invention proposes a signal precision large delay transmission control system and method based on SSD and DDR. The overall block diagram and operation process are as follows: Figure 2 As shown, the overall process needs to complete two major parts: input signal processing and output signal processing.

[0030] Input signal processing includes input signal acquisition, data caching and data clock domain conversion in the transceiver board, high-speed transmission from the transceiver board to the CPU board, and high-speed data transmission from the CPU board to the storage board. The data is finally stored in the SSD module on the storage board.

[0031] Output signal processing includes high-speed transmission of SSD output data from the storage board to the CPU board, high-speed transmission between the CPU board and the transceiver board, data caching of output data in the DDR Module, output data caching in the transceiver board, and data clock domain conversion. The signal is finally output through the DA.

[0032] In this method, the system clock is 156.25MHz, which supports large cache transmission of dual-phase I and Q data at the same time. The bit width of each I and Q data is 16 bits, and the data rate to be processed can be calculated to be 10000Mbps; AURORA1 requires a minimum transmission rate of not less than 10000Mbps. Currently, 16 lanes are used, and the single lane transmission rate is 12.5Gbps. Combined with the transmission efficiency, it can meet the data transmission rate requirements; AURORA2 requires a minimum transmission rate of not less than 10000Mbps. Currently, 8 lanes are used, and the single lane transmission rate is 12.5Gbps. Combined with the transmission efficiency, it can meet the data transmission rate requirements; SSD works in a way of simultaneous data writing and reading, with a data transmission rate of not less than 1250MBps. The current data storage depth is 20TB. It is calculated that data caching can be performed on target data of not less than four hours. DDR is used for data caching at the back end of the SSD. Sufficient data is always stored in DDR to ensure the continuity of DA output data. The DDR operating frequency is 2500MHz, the user clock is 312.5MHz, and the user data processing width is 512b. DDR works in read priority mode and data can be written when the read is idle. Therefore, the comprehensive data write and read rate is halved to about 80000Mbps. Combined with data processing efficiency, the requirement of data processing rate not less than 10000Mbps is met. After the data output by DDR enters FIFO4 and completes the clock domain conversion, it is transmitted to DA to realize data output.

[0033] The present invention proposes a signal precision large delay transmission control system and method based on SSD and DDR. The signal enters the system through AD to complete data acquisition, undergoes high-precision delay control, and finally completes signal output through DA.

[0034] First, the AD completes signal acquisition and inputs bi-phase I and Q data, which is currently in the system clock domain.

[0035] The I / Q data is converted into the data clock domain through FIFO1. Its write clock is the system clock CLK_SYS of the transceiver board, and its read clock is the user clock AURORA1 USER_CLK1 of the transceiver board.

[0036] The data is then transmitted to the CPU board through the high-speed port AURORA1 and enters the CPU board AURORA1 user clock AURORA1USER_CLK2.

[0037] The data is then converted into the data clock domain through FIFO2. Its write clock is the CPU board AURORA1 user clock AURORA1USER_CLK2, and its read clock is the CPU board AURORA2 user clock AURORA2_USER CLK1.

[0038] The data is then transmitted to the data storage board through the high-speed port AURORA2 and written into the SSD on the board.

[0039] The core part of data transmission control with long delay is implemented in the SSD on the storage board. After the data is written to the SSD, the data is not output continuously at first. When the amount of data accumulates to the length of the long delay time period we need, the data is controlled to be continuously output from the SSD and transmitted back to the CPU board through the high-speed port AURORA2. For example, we perform a 20-minute long delay transmission with a data rate of 10000Mbps and a time of 1200 seconds. It can be calculated that the amount of data that needs to be accumulated is about 1.43TB. Of course, in order to achieve precise delay control in the context of data transmission control with long delay, it is also necessary to combine the specific control of SSD data output and data pre-caching. The details will be introduced in the precise delay control section.

[0040] The data is transmitted back to the CPU board through AURORA2, and first enters the CPU board AURORA2 user clock AURORA2 USER_CLK1. The returned I / Q data is converted into the data clock domain through FIFO3, and its write clock is the CPU board AURORA2 user clock AURORA2USER_CLK1, and the read clock is the CPU board AURORA1 user clock AURORA1 USER_CLK2. The data is then transmitted to the transceiver board through the high-speed port AURORA1 and enters the transceiver board AURORA1 user clock AURORA1 USER_CLK1. In order to ensure the continuity of the DA signal output, the data needs to be written to the DDR Module for cache to ensure that there is enough data for output in the subsequent process, thereby ensuring data continuity.

[0041] The data output from the DDR Module is converted into the data clock domain through FIFO4, and the data is returned to the transceiver board system clock CLK_SYS. Finally, the output of the delayed signal is completed through DA.

[0042] The present invention proposes a precise delay correction control method based on a timer and output path data flow control to automatically correct the uncertain data delay transmission error generated during the implementation of the method, so as to ensure high-precision delay control in the context of large delay transmission control. Figure 2It can be seen that the data is collected by AD, and the input data passes through FIFO1, AURORA1, FIFO2, AURORA2, and finally stored in the SSD of the storage board. The entire input data storage process has necessary and uncertain clock cycle overhead, which leads to data delay transmission errors; similarly, the data is output from SSD, passes through AURORA2, FIFO3, AURORA1, DDR Module, FIFO4, and finally output from DA, which will also produce uncertain data delay transmission errors. In order to complete the error correction, we propose an accurate delay correction control method based on timer and output path data flow control.

[0043] When the system starts working, the timing starts when the first data is written into FIFO1, and the data is finally stored in the SSD through the transmission path. Then the data is controlled to be output from the SSD and transmitted to FIFO4 along the output path. FIFO3, DDR Module, and FIFO4 pre-cache half of the data of their storage depth, DDR Module caches a preset length of data (the preset length can be set to 10 times the data storage capacity of FIFO4), and FIFO3 pre-stores half of the depth of data. The flow control requires that if the data of the lower module is less than the agreed amount, the upper module continues to fill it with data, otherwise, the filling of data is suspended. For example, if the data in FIFO4 does not reach the agreed amount, the DDR Module outputs data to it; otherwise, the output is suspended. During the process from the start of pre-caching data to the arrival of the counting moment, FIFO4 is suspended from outputting data to DA. When the counting moment reaches the signal output moment, FIFO4 is controlled to output data to the outside, and the SSD is controlled to continue to return data to complete the supplement of new data, thereby completing the high-precision continuous transmission of the signal with large delay.

[0044] The flow control principle of the present invention is introduced in detail: data flow control is performed during the entire process of data transmission. The storage board monitors the data volume of FIFO3 in the CPU board. When it reaches half of the data volume, the SSD at the storage board end transmits data to FIFO3 via AURORA2, otherwise, data transmission is suspended; the CPU board monitors the data volume of FIFO5 in the DDR Module in the transceiver board. When it reaches half of the data volume, FIFO3 transmits data to FIFO5 via AURORA1, otherwise, data transmission is suspended; the DDR Module supports simultaneous writing and reading of data, and DDR SDRAM reads are given priority. The core part of the module is the DDR SDRAM inside the FPGA, and the data mover DataMover is configured at both ends, and the DataMoverWrite front-end configures FIFO5 to complete the data clock domain conversion. The data transmitted back to the transceiver board is written into DDR through FIFO5 and DataMoverWrite. Each burst writes data of preset length. When DataMover Read monitors that the second preset length of data starts to be written, DDR starts to output data through DataMover Read. During the data output process, DataMover Read monitors the amount of data in FIFO4. When the data is less than half the depth, the data is output. Otherwise, the output is suspended. There is always a preset fragment length of data available in the DDR SDRAM. Based on the above flow control principle, data transmission on demand is guaranteed, thereby ensuring data continuity, and supporting the implementation of precise delay correction control methods.

[0045] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A signal precision and long-delay transmission control method based on SSD, characterized in that: The following steps are involved: S1.AD converter completes signal acquisition and inputs biphase I and Q data. I / Q data is converted into data clock domain through FIFO1. Its write clock is the transceiver board system clock CLK_SYS, and its read clock is the transceiver board AURORA1 user clock AURORA1 USER_CLK1. S2. The data is then transmitted to the CPU through the high-speed port AURORA1, at which time AURORA1 is the user clock AURORA1 USER_CLK2; the data is then converted into the data clock domain through FIFO2, and its write clock is the CPU's AURORA1 user clock AURORA1USER_CLK2, and its read clock is the CPU's AURORA2 user clock AURORA2_USER CLK1; S3. The data is then transmitted to the data storage board through the high-speed port AURORA2 and written into the SSD mounted on the storage board. After the data is written into the SSD, the data is not continuously output. When the amount of data accumulates to the required long delay time period, the data is controlled to be continuously output from the SSD and transmitted back to the CPU through the high-speed port AURORA2. S4. Data is transmitted back to the CPU via AURORA2. At this time, AURORA2 is the user clock AURORA2. USER_CLK1; the returned I / Q data is converted into data clock domain through FIFO3, and its write clock is the CPU's AURORA2 user clock AURORA2USER_CLK1, and its read clock is the CPU's AURORA1 user clock AURORA1 USER_CLK2; S5. The data is then transmitted to the transceiver board through the high-speed port AURORA1. At this time, AURORA1 is the user clock AURORA1 USER_CLK1.

2. The SSD-based signal precision and long-delay transmission control method according to claim 1 is characterized in that: In step S5, the data needs to be written into the DDR for cache to ensure that the subsequent process has enough data for output; the data output from the DDR is then converted into the data clock domain through FIFO4, and the data returns to the transceiver board system clock CLK_SYS, and finally the output of the delayed signal is completed through the DA converter.

3. The SSD-based signal precision and long-delay transmission control method according to claim 1 is characterized in that: The AD converter and DA converter are integrated on the transceiver board, and a counter is set between the two. When the system starts working, the timing starts when the first data is written into FIFO1, and the data is finally stored in the SSD through the transmission path; then the data is controlled to be output from the SSD and transmitted to FIFO4 along the output path; before the data is continuously transmitted back, a certain preset length of data is pre-cached in FIFO3, DDR, and FIFO4; the flow control requires that if the data in FIFO4 is less than the agreed amount, DDR continues to fill it with data, otherwise, the filling of data is suspended; during the process from the start of pre-caching data to the arrival of the counting moment, FIFO4 is suspended from outputting data to the DA; when the counting moment reaches the signal output moment, FIFO4 is controlled to output data to the outside, and at the same time, the SSD is controlled to continue to transmit data back to complete the supplement of new data, thereby completing the continuous transmission of the signal with large delay and high precision.

4. The SSD-based signal precision and long-delay transmission control method according to claim 1 is characterized in that: The flow control steps are as follows: the storage board monitors the data volume of FIFO3 in the CPU board. When the data volume reaches the set value, the SSD at the storage board end transmits data to FIFO3 via AURORA2, otherwise, data transmission is suspended; the CPU monitors the data volume of FIFO5 in the DDR in the transceiver board. When the data volume reaches the set value, FIFO3 transmits data to FIFO5 via AURORA1, otherwise, data transmission is suspended; DDR supports simultaneous writing and reading of data, and DDR SDRAM read is given priority; Data movers DataMover are configured at both ends of the DDR SDRAM respectively, and FIFO5 is configured before DataMoverWrite to complete data clock domain conversion; the data transmitted back to the transceiver board is written to the DDR through FIFO5 and DataMoverWrite, and the data of the preset length is written in bursts each time. When DataMover Read monitors that the second data of the preset length starts to be written, the DDR starts to output data to the outside through DataMover Read. During the process of DataMover Read outputting data, the data volume in FIFO4 is monitored. When the data is less than the set depth, the data is output, otherwise, the output is suspended; it is ensured that there is always a preset fragment length of data available in the DDR SDRAM.

5. A signal precision large delay transmission control system based on SSD, comprising a transceiver board, a CPU board and an SSD board, wherein the transceiver board integrates an AD converter, a DA converter, an FPGA module 1 and a DDR module; the CPU board integrates an FPGA module 2, and the SSD board is plugged into the CPU board, and adopts the signal precision large delay transmission control method based on SSD as claimed in any one of claims 1 to 4, characterized in that: The AD converter sends the collected data to FPGA module 1. After the data is cached, it is sent to FPGA module 2 by AURORA1. After the data is cached in FPGA module 2, it is sent to the SSD board by AURORA2. When data is transmitted back, it is sent from the SSD board to FPGA module 2, and then sent to the DDR module by AURORA1 after being cached. A timer is set between the AD converter and the DA converter, and the data is sent to the DA converter after being cached. At the same time, the SSD board is controlled to start adding new data and complete the signal output. The entire path from SSD to DA is flow controlled, and a counter is used to control the data to be output to DA at a specified time, thereby achieving delay correction.

6. The SSD-based signal precision and long-delay transmission control system according to claim 5 is characterized in that: The main clock of FPGA module 1 is the system clock CLK_SYS, which supports large cache transmission of dual-phase I and Q data at the same time; the DDR module uses the user clock, and in read priority mode, data can be written when the read is idle. The data output by the DDR module is converted in the clock domain by the cache of FPGA module 1, and then transmitted to the DA converter to realize data output.

7. The SSD-based signal precision and long-delay transmission control system according to claim 5 is characterized in that: The system clock is 156.25MHz, supporting large cache transmission of bi-phase I and Q data at the same time. The bit width of each I and Q data is 16 bits, and the data rate to be processed can be calculated to be 10000Mbps. AURORA1 requires a minimum transmission rate of no less than 10000Mbps, uses 16 lanes, and a single lane transmission rate of 12.5Gbps; AURORA2 requires a minimum transmission rate of no less than 10000Mbps, using 8 lanes, and a single lane transmission rate of 12.5Gbps; the SSD works by simultaneously writing and reading data, with a data transmission rate of no less than 1250MBps. The current data storage depth is 20TB, and calculations show that it can cache target data for no less than four hours.

8. The SSD-based signal precision and long-delay transmission control system according to claim 5 is characterized in that: The DDR operating frequency is 2500MHz, the user clock is 312.5MHz, and the user data processing width is 512b. DDR works in read priority mode, and data can be written during read idle time. Therefore, the comprehensive data write and read rate is halved to about 80000Mbps. Combined with the data processing efficiency, it meets the requirement of data processing rate not less than 10000Mbps.

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