Operation method of storage controller, storage controller and storage system

Abstract

The invention provides an operation method of a storage controller, the storage controller and a storage system, and relates to the technical field of semiconductor chips. The method comprises the following steps: in a first operation stage, executing multiple reading operations according to a first reference voltage to obtain a plurality of reading results, and determining a voltage offset direction of a second operation stage according to a plurality of failure bit numbers, and determining a second reference voltage of the second operation stage according to the first reference voltage, the voltage offset of the second operation stage and the voltage offset direction of the second operation stage. The invention aims to solve the problem that the read-write performance is influenced due to overlong read retry time.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to an operating method of a storage controller, a storage controller and a storage system. Background Art

[0002] The threshold voltage of the memory cell will change due to various factors. If the threshold voltage changes, the reading will fail if the reasonable reading voltage is not set. After the reading fails, the reading will be retried. If the reading retry time is too long, it will affect the user experience. Summary of the invention

[0003] Embodiments of the present disclosure provide a storage controller operation method, a storage controller, and a storage system, which are intended to improve the problem that a long read retry time affects the read and write performance.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In a first aspect, a method for operating a storage controller is provided, the method comprising: in a first operation phase, performing multiple read operations according to a first reference voltage to obtain multiple read results, wherein the read results include the number of failed bits. According to the multiple numbers of failed bits, determining the voltage offset direction of the second operation phase, determining the second reference voltage of the second operation phase according to the first reference voltage, the voltage offset of the second operation phase, and the voltage offset direction of the second operation phase, wherein the voltage offset of the second operation phase is less than the voltage offset of the first operation phase, and the voltage offset of the second operation phase is the voltage offset of the second reference voltage relative to the first reference voltage.

[0006] The storage controller operation method provided by the present disclosure dynamically adjusts the voltage offset size of the next operation stage according to the reading result of the previous operation stage, so that the voltage offset of each operation stage is changing, thereby reducing the number of read retries required to find the target read voltage, thereby improving the reading performance of the memory and improving the user's experience. In addition, the storage controller operation method provided by the present disclosure does not require manual intervention by the user, and automatically finds the best reading position through internal iteration of the processor, reducing the user's workload and reducing the complexity of operation.

[0007] In some embodiments, the second reference voltage, the first reference voltage, and the voltage offset in the second reading phase satisfy:

[0008] V n+1 =V n +(-1) m ·S n+1

[0009] Where Vn+1 is the second reference voltage, V n is the first reference voltage, S n+1 is the voltage offset in the second reading stage; when the voltage offset direction in the second reading stage is the same as that in the first reading stage, m is an even number; when the voltage offset direction in the second reading stage is opposite to that in the first reading stage, m is an odd number.

[0010] In some embodiments, before the first operation phase, the method includes: acquiring a target voltage interval, and determining a first reference voltage as an endpoint voltage of the target voltage interval.

[0011] The storage controller operation method provided by the present disclosure avoids multiple readings at unnecessary threshold voltage positions by iterating and continuously adjusting the reference read voltage within a specific voltage range, thereby greatly reducing the read retry time.

[0012] In some embodiments, multiple read operations are performed based on a first reference voltage to obtain multiple read results, including: increasing or decreasing the first reference voltage in sequence to obtain multiple read voltages, and performing read operations based on the multiple read voltages to obtain multiple read results, wherein the read results include the number of failed bits.

[0013] In some embodiments, the voltage offset direction of the second operation stage is determined based on multiple numbers of fail bit bits, including: when the multiple numbers of fail bit bits increase successively, determining the voltage offset direction of the second operation stage to be the opposite direction of the voltage offset direction of the first operation stage; when the multiple numbers of fail bit bits decrease successively, determining the voltage offset direction of the second operation stage to be the same direction as the voltage offset direction of the first operation stage.

[0014] In some embodiments, determining the voltage offset direction of the second operation stage according to the changing trend of the number of fail bits also includes: when the number of fail bits increases first and then decreases, determining that the voltage offset direction of the second operation stage is the opposite direction of the voltage offset direction of the first operation stage.

[0015] In some embodiments, the method further includes: when the number of the plurality of failed bits decreases first and then increases, determining the first reference voltage as the target read voltage.

[0016] In some embodiments, the method further includes: when the voltage offset in the second reading phase is less than a preset threshold, determining the first reference voltage as the target reading voltage.

[0017] The storage controller operation method provided by the present disclosure can automatically stop iteration when the voltage offset drops below a minimum value, thereby ensuring the accuracy and stability of the voltage adjustment operation.

[0018] In a second aspect, a storage controller is provided, which is coupled to a memory. The storage controller includes a processor and an ECC circuit. The ECC circuit is configured to perform multiple read operations according to a first reference voltage in a first operation phase to obtain multiple read results, wherein the read results include the number of failed bits. The processor is configured to determine a voltage offset direction in a second operation phase according to the multiple numbers of failed bits. The processor is also configured to determine a second reference voltage in the second operation phase according to the first reference voltage, a voltage offset in the second operation phase, and a voltage offset direction in the second operation phase. The voltage offset in the second operation phase is less than the voltage offset in the first operation phase, and the voltage offset in the second operation phase is a voltage offset of the second reference voltage relative to the first reference voltage.

[0019] In some embodiments, the second reference voltage, the first reference voltage, and the voltage offset in the second reading phase satisfy:

[0020] V n+1 =V n +(-1) m ·S n+1

[0021] Where V n+1 is the second reference voltage, V n is the first reference voltage, S n+1 is the voltage offset in the second reading stage; when the voltage offset direction in the second reading stage is the same as that in the first reading stage, m is an even number; when the voltage offset direction in the second reading stage is opposite to that in the first reading stage, m is an odd number.

[0022] In some embodiments, the processor is further configured to: obtain a target voltage interval, and determine the first reference voltage as an endpoint voltage of the target voltage interval.

[0023] In some embodiments, the processor is specifically configured to: sequentially increase or decrease the first reference voltage to obtain multiple read voltages, and perform a read operation based on the multiple read voltages to obtain multiple read results, wherein the read results include the number of failed bits.

[0024] In some embodiments, the processor is specifically configured to: when the number of failed bits increases successively, determine that the voltage offset direction of the second operation stage is the opposite direction of the voltage offset direction of the first operation stage; when the number of failed bits decreases successively, determine that the voltage offset direction of the second operation stage is the same direction as the voltage offset direction of the first operation stage.

[0025] In some embodiments, the processor is specifically configured to: when the number of fail bits increases first and then decreases, determine that the voltage offset direction of the second operation phase is the opposite direction of the voltage offset direction of the first operation phase.

[0026] In some embodiments, the processor is further configured to: when the number of the plurality of failed bits decreases first and then increases, determine the first reference voltage as the target read voltage.

[0027] In some embodiments, the processor is further configured to: when the voltage offset in the second reading phase is less than a preset threshold, determine the first reference voltage as the target reading voltage.

[0028] In a third aspect, a storage system is provided, comprising: a memory, and a storage controller, wherein the storage controller is connected to the memory via a flash memory interface circuit; the storage controller is the storage controller provided by any embodiment of the second aspect.

[0029] In a fourth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions; after the computer-executable instructions are executed, any one of the methods in the first aspect above can be implemented.

[0030] In a fifth aspect, an electronic device is provided, including a host such as the storage system provided in the third aspect, wherein the host is connected to the storage system to write data to the storage system or read data stored in the storage system.

[0031] It can be understood that the technical effects of the second to fifth aspects refer to the technical effects of the first aspect and any embodiment thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A block diagram of an electronic device provided for an embodiment of the present disclosure;

[0033] Figure 2 A block diagram of a storage system provided in an embodiment of the present disclosure;

[0034] Figure 3 A schematic diagram of a charge trapping transistor provided in an embodiment of the present disclosure;

[0035] Figure 4 A schematic diagram of storage data of a charge trapping transistor provided by an embodiment of the present disclosure;

[0036] Figure 5 A schematic diagram of the threshold voltage distribution of a memory cell provided in an embodiment of the present disclosure;

[0037] Figure 6 A schematic diagram of threshold voltage distribution of another memory cell provided in an embodiment of the present disclosure;

[0038] Figure 7 A schematic diagram of determining a target read voltage provided by an embodiment of the present disclosure;

[0039] Figure 8 A schematic diagram of a storage controller provided in an embodiment of the present disclosure;

[0040] Fig. 9 A flowchart of a storage controller operation method provided by an embodiment of the present disclosure;

[0041] Fig.10 Another schematic diagram of determining a target read voltage provided by an embodiment of the present disclosure;

[0042] Fig.11 A flowchart of another storage controller operation method provided by an embodiment of the present disclosure;

[0043] Fig.12 Another schematic diagram of determining a target read voltage provided by an embodiment of the present disclosure;

[0044] Fig.13 Another schematic diagram of determining a target read voltage provided by an embodiment of the present disclosure;

[0045] Fig.14 A flowchart of another storage controller operating method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0047] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0049] When describing some embodiments, the term "coupled" and its derivative expressions may be used. For example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. In this case, "coupled" may also be described as "connected". In addition, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0050] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0051] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B. The use of "suitable for" or "configured to" herein is meant to be open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps. In addition, the use of "based on" is meant to be open and inclusive, because a process, step, calculation or other action "based on" one or more conditions or values ​​can be based on additional conditions or beyond values ​​in practice.

[0052] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0053] The embodiments of the present disclosure provide an electronic device, which may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc. Figure 1 , Figure 1A schematic diagram of an electronic device 10 provided by an embodiment of the present disclosure is shown, including a host 100 and a storage system 110. The host 100 is coupled to the storage system 110 to write data to the storage system 110 or read data stored in the storage system 110. The host is also called a master device, and the storage system is also called a slave device. In an electronic device, a slave device can be accessed by different master devices. For example, taking the electronic device as a mobile phone as an example, the central processing unit (CPU) and digital signal processor (DSP) of the mobile phone can all access the storage system as a host.

[0054] For example, see Figure 2 , Figure 2 A schematic diagram of a storage system 110 provided in an embodiment of the present disclosure is shown, the storage system 110 includes a storage controller 111 and a memory 112, the storage controller 111 is coupled to the memory 112 to control the memory 112 to store data. The memory 112 may be a two-dimensional (2-dimension, 2D) memory or a three-dimensional (3-dimension, 3D) memory.

[0055] The storage system 110 may be integrated into various types of storage devices, for example, included in the same package (e.g., a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package). That is, the storage system 110 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0056] In some embodiments, the storage system 110 includes a storage controller 111 and a memory 112, and the storage system 110 can be integrated into a memory card. The memory card includes any one of a personal computer memory card international association (PCMCIA) card (abbreviated as PC card), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD) card, and a UFS.

[0057] Exemplarily, taking the storage medium of the memory 112 as a flash memory, the basic storage unit of the flash memory includes a floating gate field effect transistor or a charge trapping transistor, etc. The embodiment of the present disclosure takes the charge trapping transistor as an example for introduction.

[0058] See also Figure 3 , Figure 3 The schematic diagram of the structure of the charge trapping transistor is shown, including a control gate 211, a charge trapping layer 212, a source 213, a drain 214, a substrate 215, an oxide layer 216 and a tunnel oxide layer 217. The source 213 and the drain 214 are arranged on the substrate 215. The embodiment of the present disclosure takes an N-channel charge trapping layer field effect transistor as an example, the substrate 215 is a P-type semiconductor material, and the source 213 and the drain 214 are N-type semiconductor materials. The substrate material between the source 213 and the drain 214 can form a conductive channel 218, the charge capture layer 212 covers the conductive channel 218, the tunnel oxide layer 217 is located between the charge capture layer 212 and the conductive channel 218, and the charge capture layer 212 is separated from the source 213, the drain 214 and the conductive channel 218. The control gate 211 is arranged on the charge capture layer 212, and an oxide layer 216 is arranged between the control gate 211 and the charge capture layer 212 to separate the control gate 211 from the charge capture layer 212. The oxide layer 216 and the tunnel oxide layer 217 are both made of insulating materials, such as silicon dioxide (SiO2).

[0059] The charge capture layer 212 is made of an insulating material with a high charge capture density. When writing data, the charge capture layer 212 captures electrons, and the threshold voltage of the field effect transistor changes. Data is stored with such characteristics. When erasing data, holes in the channel are injected into the charge capture layer 212 and neutralized with the electrons in the charge capture layer 212 to achieve erasure.

[0060] When the charge trapping layer captures electrons, a higher threshold voltage is required to open the conductive channel due to the shielding effect of the electrons. If the threshold voltage when there are no electrons captured in the charge trapping layer is recorded as V th1 , the threshold voltage when electrons are captured in the charge trapping layer is recorded as V th2 , then assuming that a larger than V th1 And less than V th2 A voltage is applied to try to turn on the charge capture transistor. If the charge capture field effect transistor is turned on, it can be determined that no electrons are captured in the charge capture layer. If the charge capture transistor is not turned on, it can be determined that electrons are captured in the charge capture layer. Based on this logic, when no electrons are captured on the charge capture layer, the charge capture transistor is in the on state, indicating 1. When electrons are captured on the charge capture layer, the charge capture transistor is in the off state, indicating 0. Therefore, such different states can be used to store data, and the storage function is achieved by injecting or capturing electrons in the charge capture layer to change the threshold voltage of the charge capture transistor.

[0061] When a voltage is applied to the control gate, a tunneling effect occurs based on the potential difference between the control gate and the channel, and electrons can be injected into the charge trapping layer or captured by the charge trapping layer. When storing data, the data is stored in the charge trapping layer, and the presence or absence of charge in the charge trapping layer can be used to indicate the data currently stored in the storage unit. For example, see Figure 4 ,like Figure 4 As shown in a, the state of the charge trapping layer with charge is 0, such as Figure 4 As shown in b, the state where the charge trapping layer has no charge is storage 1. The process of storing data in the memory cell is the process of programming the memory cell.

[0062] After the programming operation is completed, the threshold voltage of the memory cell is not constant, but will change due to various factors. This phenomenon is called threshold voltage drift. The causes of threshold voltage drift usually include the following:

[0063] Intrinsic Voltage Shift (IVS): The charge in the memory cell is stored in the floating gate, but these charges drift over time, resulting in changes in the threshold voltage. This intrinsic voltage shift is caused by factors such as charge loss, random noise, and material properties.

[0064] Temperature Effect: Temperature is another important factor that can significantly affect the threshold voltage. As the temperature changes, the energy level distribution of electrons in the material changes, which can cause the threshold voltage to drift. For example, in a high temperature environment, the threshold voltage may increase, while in a low temperature environment, the threshold voltage may decrease.

[0065] And with the increase in the number of uses or the passage of time, the threshold voltage will also shift, so the threshold voltage of the storage cell is affected by a variety of internal and external factors. After the threshold voltage of the storage cell shifts, the threshold voltage distribution is wider. Generally, the threshold voltage will shift to the right, so a higher voltage is required to read the data correctly, which will lead to reduced voltage accuracy.

[0066] After the threshold voltage shifts, if a normal read voltage is still used for reading, a read error will occur.

[0067] For example, see Figure 5 , shows a schematic diagram of the distribution of the threshold voltage of the storage cell when it is not shifted, including the threshold voltage distribution of the storage cell in the P1 storage state before the threshold voltage shift occurs and the threshold voltage distribution of the storage cell in the P2 storage state before the threshold voltage shift occurs, such as the area surrounded by the solid line corresponding to D1 and the area surrounded by the solid line corresponding to D2. When reading data, the storage state of each storage cell is obtained by applying the read voltage Vread1. The read voltage Vread1 is greater than the threshold voltage of the storage cell in the D1 area and less than the threshold voltage of the storage cell in the D2 area. Therefore, before the threshold voltage of the storage cell shifts, when the read voltage Vread1 is used to read the storage cell in the P1 storage state or the P2 storage state, it can be relatively easy to distinguish whether the storage cell is in the P1 storage state or the P2 storage state, thereby obtaining the data stored in the storage cell.

[0068] When the threshold voltage of a memory cell changes, see Figure 6 , the area surrounded by the solid line corresponding to D3 is the threshold voltage distribution of the storage cell in the P1 storage state after the threshold voltage shift occurs, and the area surrounded by the solid line corresponding to D4 is the threshold voltage distribution of the storage cell in the P2 storage state after the threshold voltage shift occurs. Compared with the D1 area and the D2 area, the shapes of the D3 and D4 areas are significantly shifted and widened. Especially near the read voltage Vread1, there is an overlapping area between the two storage states ( Figure 6). In this case, if the read voltage Vread1 is continued to be used to read the data on each storage cell in sequence, the storage cell in storage state P2 may be mistakenly identified as a storage cell in storage state P1, or the storage cell in storage state P1 may be mistakenly identified as a storage cell in storage state P2. In addition, when the threshold voltage of the storage cell is exactly equal to the read voltage Vread1, it is also impossible to accurately determine whether the storage cell is in storage state P1 or storage state P2, increasing the risk of read errors. This situation in which data read errors occur is called a fail bit (Fail bit, Fb), and after each read operation, the number of bits in which data read errors occur in this read operation needs to be counted, and this process is called a fail bit count (Fail bit count, Fbc).

[0069] However, the threshold voltage offset of the storage unit is inevitable. In order to obtain the correct read data, an error correction code (ECC) circuit is set in the storage system. The ECC circuit is used to count the number of bits that have data read errors after each read operation, that is, the number of failed bits. When the statistical value of the number of failed bits is small, the number of bits that need to be corrected by the ECC circuit is also small, the probability of correct reading is greater, and the required reading time is less. Then, the corresponding reading voltage is optimal at this time. Therefore, Figure 6 In the case of the distribution of threshold voltages of two adjacent storage states shown in the figure, by setting the read voltage at the intersection N of the two storage states corresponding to D3 and D4, the statistical value of the number of failed bits can be minimized, thereby determining the read voltage Vread2 corresponding to this position as the target read voltage, and the target read voltage is the optimal read voltage.

[0070] Therefore, how to determine the optimal read voltage setting position when the threshold voltage of the storage cell shifts is a key concern of the industry. One possible implementation method is for the user to continuously adjust the input read voltage until the input read voltage is close to the target read voltage, so as to correctly read the data. That is, the target read voltage is determined by adjusting the read voltage multiple times.

[0071] However, if the target read voltage is far away from the initially set read voltage, it will take a long time to find the target read voltage. Because a fixed step size is used, it is impossible to cross the entire range in one iteration, especially when the target read voltage is far away from the initial read voltage. In this case, the read voltage needs to be adjusted multiple times to gradually approach the target read voltage. Multiple iterations will increase the time required to find the best read position, because different read voltages need to be tried each time, and then the read results are checked to gradually approach the target read voltage. Since the user needs to traverse the voltage read retry table (read ret ry table) pre-given by the manufacturer in sequence, the reading process will be more time-consuming and the reading efficiency will be reduced.

[0072] For example, see Figure 7 , the threshold voltage interval [A, B] is the voltage interval given by the voltage read retry table, the target read voltage is at the position of the threshold voltage E, and the initial set read voltage is at the position of the threshold voltage A, so the optimal read voltage and the initial set read voltage are far apart. In this case, firstly, a read operation is performed based on the read voltage A to obtain the read result when the read voltage is A, and then a judgment is made based on the read result to determine that the target read voltage requirement is not met. Therefore, it is necessary to adjust the read voltage and set it to the next value in the voltage read retry table, that is, the position of the threshold voltage C, and then a read operation is performed based on the read voltage C to obtain the read result when the read voltage is C. This process is the first voltage adjustment process. Continue to adjust the read voltage and move the read voltage to the right until the fourth voltage adjustment is completed, and move the read voltage to the position of the threshold voltage E. It should be noted that in the above voltage adjustment process, the value of each voltage adjustment is the same. A read operation is performed based on the read voltage E to obtain the read result when the read voltage is E, and then a judgment is made based on the read result to determine that the target read voltage requirement is met, and the read voltage E is determined as the target read voltage.

[0073] In the above embodiment, the target read voltage is exactly in the voltage range given by the voltage read retry table. In actual applications, due to the increase in user usage scenarios, the number of voltage read retry tables will also increase. Therefore, it is necessary to traverse all the voltage ranges given by the voltage read retry table and continuously adjust the read voltage to determine the target read voltage, resulting in a longer time required to find the target read voltage, which affects the user experience.

[0074] In order to solve the above problems, an embodiment of the present disclosure provides a solution: according to the read result of the previous operation stage, the voltage offset of the next operation stage is dynamically adjusted, so that the voltage offset of each operation stage is changing, thereby reducing the number of read retries required to determine the target read voltage and improving the read performance of the memory.

[0075] Figure 8 A schematic diagram of a storage controller 111 provided according to an embodiment of the present disclosure is shown. The storage controller 111 may include a processor 311 , a cache 312 , an ECC circuit 313 , a host interface circuit 314 , and a flash memory interface circuit 315 .

[0076] The processor 311 can communicate with the host 100 through the host interface circuit 314, and perform logical operations to control the operation of the storage controller 111. For example, the processor 311 can load programming commands, data files or data structures in response to a request received from the host 100 or an external device, perform various operations or generate commands and addresses. For example, the processor 311 can generate various commands for performing programming operations, read operations, erase operations and parameter setting operations. In some possible examples, the processor 311 can generate commands without a request from the host 100, for example, the processor 311 can generate commands for background operations such as garbage collection for the memory 112, or the processor 311 can also generate commands for training the quality of bus transmission signals between the storage controller 111 and the memory 112.

[0077] The ECC circuit 313 may perform an error detection and correction function on the read data read from the memory 112. For example, the ECC circuit 313 may generate a parity bit for the write data to be written to the memory 112, and the generated parity bit may be stored in the memory 112 together with the write data. When reading data from the memory 112, the ECC circuit 313 may correct errors in the read data using the parity bit read from the memory 112 together with the read data, and may output the error-corrected read data.

[0078] The host interface circuit 314 may send data or commands to the host 100, or receive data or commands from the host 100. For example, a command sent from the host 100 to the host interface circuit 314, data to be written to the memory 112, etc., and a response to a command sent from the host interface circuit 314 to the host 100, data to be read from the memory 112, etc. The host interface circuit 314 may also include a protocol for exchanging data between the host 100 and the storage controller 111. For example, the host interface circuit 314 can communicate with the host 100 through at least one of the following various interface protocols: universal serial bus (USB) protocol, Microsoft Management Console (MMC) protocol, peripheral component interconnect (PCI) protocol, PCI high-speed (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer system interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronic (IDE) protocol, FireWire protocol, etc.

[0079] The flash interface circuit 315 can communicate with the memory 112 using a communication protocol according to the control of the processor 311, including the communication of commands, addresses and data. The flash interface circuit 315 can send data to be written to the memory 112 to the memory 112, or can receive data read from the memory 112. The flash interface circuit 315 can be implemented to comply with standard protocols such as Toggle or Open NAND Flash Interface (ONFI). Exemplarily, taking the ONFI protocol as an example, the storage controller 111 and the memory 112 can be connected through the ONFI bus.

[0080] Specifically, when the processor 311 is working, it executes the following Fig. 9 The operation method shown includes steps S901-903, and the processor 311 can execute at least one of steps S901, S902 or S903.

[0081] Before executing step S902, an erase voltage needs to be applied to the word line to perform an erase operation on the memory cell coupled to the word line. After completing the erase operation on the memory cell coupled to the word line, the memory cell needs to be programmed to a different storage state. After completing the erase and programming operations on the memory cell in the memory, the memory controller can execute the solution of the present disclosure to determine the target read voltage.

[0082] See also Fig. 9 , the operating method of the storage controller provided by the embodiment of the present disclosure includes:

[0083] S901: In a first operation phase, performing multiple read operations according to a first reference voltage to obtain multiple read results, wherein the read results include the number of failed bits.

[0084] In the process of determining the target read voltage, it is usually necessary to perform multiple voltage offset operations to gradually approach or locate the target read voltage. Each voltage offset operation corresponds to an operation stage. In each operation stage, multiple read operations need to be performed. These read operations are based on the reference voltage set in the current operation stage to generate multiple read results. This process is called automatic voltage detection (AVD). This process is to collect enough read results to determine the best read voltage or make more precise voltage adjustments in the next operation stage. Therefore, this process is iterative step by step, and through multiple operation stages and multiple read operations, the target read voltage is finally found to ensure the accuracy and reliability of the data. The read result includes the number of failed bits, which refers to the number of bits detected to produce errors or failures during the data reading or writing process. The number of failed bits can quantify the extent of read errors.

[0085] Exemplarily, the number of failed bits is calculated by comparing the difference between the data actually read and the expected data. In the storage controller, the main function of the ECC circuit 313 is to detect and correct errors in the data. When reading data, the ECC circuit 313 will compare with the original data. If an error is detected, that is, the data bit does not match the expected value, the ECC circuit 313 will record the number of failed bits detected. This process is the failure bit number statistics. Therefore, the ECC circuit 313 can obtain the number of failed bits in the read operation by counting the number of failed bits.

[0086] S902: Determine a voltage shift direction in a second operation phase according to a plurality of failed bit numbers.

[0087] The number of failed bits can be used to measure how many bits in the read result are wrong or inconsistent with the expected value. This indicator reflects the position relationship between the current reference voltage and the target read voltage. When the number of failed bits is high, it means that more data does not match the expected value, or the reference voltage used in the current operation stage is far away from the target read voltage.

[0088] On the contrary, when the number of failed bits is low, it means that the accuracy of the read operation is high, that is, the reference voltage used in the current operation phase is close to the target read voltage. Therefore, the number of failed bits is not only an indicator to measure the success of the read operation, but also reflects the relative position relationship between the reference voltage and the target read voltage in the operation phase. In practice, by monitoring and analyzing the changing trend of the number of failed bits, the reference voltage can be adjusted so that the reference voltage is constantly close to the target read voltage.

[0089] Therefore, by observing multiple read results in each operation stage, the number change trend of the number of failed bits can be determined. This trend reflects the impact of voltage settings on reading accuracy. By analyzing multiple read results in each operation stage, the number change trend of the number of failed bits can be determined. Subsequently, based on the number change trend of the number of failed bits, the offset direction of the reference voltage of the next operation stage relative to the reference voltage of the current operation stage is determined. These reference voltage offset direction options include reverse offset (adjusting the reference voltage in the opposite direction), same direction offset (adjusting the reference voltage in the same direction), and no offset (keeping the reference voltage unchanged).

[0090] S903: Determine a second reference voltage in the second operation phase according to the first reference voltage, the voltage offset in the second operation phase, and the voltage offset direction in the second operation phase.

[0091] After the first operation phase is completed, the second operation phase will be entered next. In the second operation phase, it is necessary to adjust based on the reference voltage of the first operation phase to obtain the second reference voltage required for the second operation phase, thereby further improving the accuracy of the reading operation. The voltage offset of the second operation phase is the voltage adjustment value relative to the first reference voltage. This voltage offset can be an increase in voltage or a decrease in voltage, depending on the voltage offset direction of the second operation phase determined in the previous step.

[0092] In the second operation stage, the voltage needs to be further adjusted based on the first reference voltage. This adjustment value can be determined according to the voltage offset direction determined previously. If the direction of voltage increase is selected in the first operation stage, then the second operation stage will continue to offset in the direction of voltage increase, and vice versa.

[0093] Next, according to the first reference voltage, the voltage offset in the second operation stage, and the voltage offset direction in the second operation stage, a second reference voltage in the second operation stage can be determined. The second reference voltage is a reference voltage value used when performing multiple read operations in the second operation stage. Specifically, the second reference voltage can be calculated by adding or subtracting the first reference voltage from the voltage offset in the second operation stage.

[0094] It should be emphasized that as the number of operation stages increases, the voltage offset corresponding to each operation stage gradually decreases. Gradually reducing the voltage offset makes it easier to distinguish the different states of the storage cell in each operation stage, thereby improving the accuracy of reading and reducing the occurrence of read errors. And a large voltage offset may cause data corruption or bit flipping of the storage cell. By gradually reducing the voltage offset, this risk can be reduced to ensure that the data will not be unnecessarily disturbed or damaged during the reading process.

[0095] Exemplarily, if the voltage offset in the first operation stage is the maximum voltage offset, then the voltage offset in the second operation stage may be 1 / 2 of the maximum voltage offset, 1 / 3 of the maximum voltage offset, and so on.

[0096] After the reference voltage of the second operation phase is obtained, it is used as the updated first reference voltage, and steps S901 to S903 are iteratively executed until the iteration exit condition is met, and the first reference voltage of the last iteration is used as the target read voltage as output.

[0097] For example, see Fig.10 , the detailed implementation process of S901 to S903 is explained. First, in the first operation stage, the reference voltage is the position corresponding to the dotted line 1, that is, the reference voltage of the first operation stage is L, and multiple read operations are performed based on the reference voltage L of the first operation stage to obtain multiple read results under the reference voltage.

[0098] According to multiple reading results of the first operation stage, it is determined that the voltage offset direction of the second operation stage is offset to the right, and the voltage offset amount of the second operation stage is max, then the reference voltage (L+max) of the second operation stage, that is, the reference voltage of the second operation stage is offset from the position of dotted line 1 to the position of dotted line 2, and multiple reading operations are performed based on the reference voltage (L+max) of the second operation stage to obtain multiple reading results under the reference voltage.

[0099] According to multiple reading results of the second operation stage, it is determined that the voltage offset direction of the third operation stage is offset to the left, and the voltage offset amount of the third operation stage is 1 / 2max, then the reference voltage of the third operation stage (L+max-1 / 2max), that is, the reference voltage of the third operation stage is offset from the position of dotted line 2 to the position of dotted line 3, and multiple reading operations are performed based on the reference voltage of the third operation stage (L+max-1 / 2max) to obtain multiple reading results under the reference voltage.

[0100] According to multiple reading results of the third operation stage, it is determined that the voltage offset direction of the fourth operation stage is offset to the left, and the voltage offset amount of the fourth operation stage is 1 / 4max, then the reference voltage of the third operation stage (L+max-1 / 2max+1 / 4max), that is, the reference voltage of the fourth operation stage is offset from the position of dotted line 3 to the position of dotted line 4, and multiple reading operations are performed based on the reference voltage of the fourth operation stage (L+max-1 / 2max+1 / 4max) to obtain multiple reading results under the reference voltage.

[0101] According to the multiple reading results of the fourth operation stage, it is determined that the voltage offset direction of the fifth operation stage is offset to the right, and the voltage offset amount of the fifth operation stage is 1 / 8max, then the reference voltage of the fifth operation stage is (L+max-1 / 2max+1 / 4max-1 / 8max), that is, the reference voltage of the fifth operation stage is offset from the position of dotted line 4 to the position of dotted line 5, and multiple read operations are performed based on the reference voltage of the fifth operation stage (L+max-1 / 2max+1 / 4max-1 / 8max) to obtain multiple read results under the reference voltage.

[0102] According to multiple read results of the fifth operation stage, it is determined that the voltage offset direction of the sixth operation stage is to the left, and the voltage offset amount of the sixth operation stage is 1 / 16max. The reference voltage of the sixth operation stage is (L+max-1 / 2max+1 / 4max-1 / 8max+1 / 16max), that is, the reference voltage of the third operation stage is offset from the position of dotted line 5 to the position of dotted line 6, and the position of dotted line 6 is the position of the target read voltage, because the read operation is performed based on the threshold voltage at this position, and the statistical result of the number of failed bits is the smallest.

[0103] In the present disclosure, the voltage offset size of the next operation phase is dynamically adjusted according to the read result of the previous operation phase, thereby reducing the number of read retries required to find the target read voltage and the read time required to find the target read voltage.

[0104] In a possible implementation, the second reference voltage, the first reference voltage, and the voltage offset in the second reading phase satisfy:

[0105] V n+1 =V n +(-1) m ·S n+1

[0106] Where V n+1 is the second reference voltage, V n is the first reference voltage, S n+1 is the voltage offset in the second reading stage. When the voltage offset direction in the second reading stage is the same as that in the first reading stage, m is an even number. When the voltage offset direction in the second reading stage is opposite to that in the first reading stage, m is an odd number.

[0107] To avoid multiple readings at unnecessary threshold voltage positions, in a possible implementation, before the first operation phase, the method includes:

[0108] S900: Acquire a target voltage interval, and determine a first reference voltage as an endpoint voltage of the target voltage interval.

[0109] The target voltage range is a voltage range given in advance through manual calibration, and the target read voltage is within the target voltage range. In order to reduce the number of read retries required to find the target read voltage, it is necessary to determine the first reference voltage as the endpoint voltage of the target voltage range. In this operation, the first reference voltage can be set at any endpoint of the target voltage range.

[0110] For example, see Fig.10 , the target voltage interval is [L, R], the L endpoint can be set to the first reference voltage, or the R endpoint can be set to the first reference voltage, which is not limited in the present disclosure. However, it should be noted that if one endpoint voltage of the target voltage interval is set to the first reference voltage, then in the next operation stage, the other endpoint voltage is set to the reference voltage of the operation stage, and then steps S901 to S903 are performed.

[0111] See also Fig.11 In a possible implementation, when multiple reading results are obtained, S901 includes the following sub-steps:

[0112] S9011: On the basis of the first reference voltage, increase or decrease in sequence to obtain a plurality of read voltages.

[0113] After the reference voltage is determined, multiple voltage offsets are performed based on the reference voltage to obtain multiple read voltage values ​​with a certain offset relative to the reference voltage. It should be noted that the method of obtaining the read voltage is similar in each operation stage. The following is a detailed description of obtaining the read voltage in the first operation stage.

[0114] Specifically, in the first operation stage, the first reference voltage is used as the starting point, and then the voltage is gradually increased or decreased according to the equal voltage offset to obtain a series of read voltage values ​​with a certain offset relative to the first reference voltage. This means that the voltage value is sequentially increased or decreased based on the reference voltage to generate a set of read voltages, which deviate from the first reference voltage to different degrees.

[0115] For example, see Fig.12 and Fig.13 , the voltage offset direction of the read voltage in the current operation stage needs to be the same as the offset direction of the reference voltage in the current operation stage. Since the first operation stage is the first operation stage, its voltage offset direction is predetermined. Therefore, taking the operation stage represented by the dotted line 3 as an example, four read operations are performed. When performing four read operations, the reference voltage V3 is first used as the starting point. Then, a series of read voltages with a certain offset relative to V2 are generated. These read voltages are Vrd1, Vrd2, Vrd3 and Vrd4, and Vrd1 is greater than Vrd2, Vrd2 is greater than Vrd3, and Vrd3 is greater than Vrd4. These read voltages are located on the left side of the reference voltage V3, and the offsets between them are equal, that is, they decrease by the same amplitude.

[0116] It should be noted that the above example is only one possibility, and in other possible examples, the read voltage is also located on the right side of the reference voltage and increases in sequence according to the same offset.

[0117] It should be noted that the offsets of the multiple read voltages generated based on the reference voltage may be equal or unequal.

[0118] For example, if the offset voltage value of the read voltage Vrd1 relative to the reference voltage is M, then the offset voltage value of the read voltage Vrd2 relative to Vrd1 can be M, or any other value different from M. This means that in different usage scenarios, the offset values ​​of the two read voltages can be the same or different, depending on the actual application requirements.

[0119] S9012: Perform a read operation based on a plurality of read voltages to obtain a plurality of read results, where the read results include a number of failed bits.

[0120] After obtaining multiple read voltages, a read operation is performed based on each read voltage. Each time a read operation is performed using a different read voltage, a read result is obtained, so multiple different read results are obtained. Then, based on the number of failed bits in the multiple read results, the voltage offset direction of the next operation stage can be determined.

[0121] Exemplarily, continuing with the above embodiment, in the second operation stage, after obtaining the read voltages Vrd1, Vrd2, Vrd3 and Vrd4, read operations are performed based on the read voltages Vrd1, Vrd2, Vrd3 and Vrd4, respectively, to obtain statistical results of the number of failed bits in each read result, i.e., Fbc1, Fbc2, Fbc3 and Fbc4, and then based on the change trends of Fbc1, Fbc2, Fbc3 and Fbc4, the voltage offset direction of the second operation stage is determined.

[0122] According to the variation trend of the number of failed bits in the read result, the relative position relationship between the reference voltage and the target read voltage is adjusted so that the reference voltage can quickly approach the target read voltage.

[0123] See also Fig.14 In a possible implementation, when determining the voltage offset direction in the second operation phase, S902 includes the following sub-steps:

[0124] S9021: When the number of the multiple failure bits increases sequentially, determine that the voltage offset direction of the second operation stage is the opposite direction of the voltage offset direction of the first operation stage.

[0125] When the number of failed bits in multiple read results increases successively, the change trend of the number of failed bits is an increasing trend, which means that the read voltage generated based on the reference voltage in this operation stage is increasingly deviating from the target read voltage, that is, the reference voltage is shifted away from the target read voltage in this operation stage. Therefore, in the next operation stage, the reference voltage needs to be moved in the opposite direction of the voltage shift direction in this operation stage, so that the reference voltage is shifted toward the target read voltage.

[0126] For example, continue to explain Fbc1, Fbc2, Fbc3 and Fbc4 obtained from four read operations. Assuming that Fbc1 is 10, Fbc2 is 12, Fbc3 is 15, and Fbc4 is 20, it can be seen that as the read voltage increases, the number of Fbcs gradually decreases, which means that the reference voltage in the current operation stage is offset away from the target read voltage. Therefore, in the next operation stage, the reference voltage needs to be moved in the opposite direction of the voltage offset direction in the current operation stage. The voltage offset direction in the current operation stage is left and right offset, so in the next operation stage, the reference voltage needs to be offset to the right.

[0127] S9022: When the number of the multiple failed bits decreases in sequence, determine that the voltage offset direction of the second operation phase is the same direction as the voltage offset direction of the first operation phase.

[0128] When the number of failed bits in multiple read results decreases successively, it indicates that the change trend of the number of failed bits is a decreasing trend, which means that the read voltage generated based on the reference voltage in this operation phase is getting closer and closer to the target read voltage, that is, the reference voltage is shifted in the direction close to the target read voltage in this operation phase. Therefore, in the next operation phase, the reference voltage needs to be moved in the same direction as the voltage shift direction in this operation phase, so that the reference voltage is shifted in the direction closer to the target read voltage.

[0129] Exemplarily, the operation stage represented by the dotted line 3 is continued to be described. Fbc1, Fbc2, Fbc3 and Fbc4 obtained by four read operations, assuming that Fbc1 is 10, Fbc2 is 6, Fbc3 is 4, and Fbc4 is 3. It can be seen that as the read voltage increases, the number of Fbcs gradually decreases, which means that the reference voltage in the current operation stage is shifted toward the direction close to the target read voltage. Therefore, in the next operation stage, the reference voltage needs to be moved in the same direction as the voltage shift direction in the current operation stage. The voltage shift direction in the current operation stage is to the left, so in the next operation stage, the reference voltage needs to be shifted to the left.

[0130] In a possible implementation manner, S902 further includes:

[0131] S9023: When the number of the multiple fail bits increases first and then decreases, determine that the voltage offset direction of the second operation phase is the opposite direction of the voltage offset direction of the first operation phase.

[0132] Exemplarily, Fbc1, Fbc2, Fbc3 and Fbc4 obtained from four read operations are used for illustration. Assuming that Fbc1 is 10, Fbc2 is 14, Fbc3 is 16, and Fbc4 is 10, it can be seen that with the increase of the read voltage, the change in the number of Fbc includes two stages, the first stage includes Fbc increasing from 10 to 16, and the second stage includes Fbc decreasing from 16 to 10. The first stage characterizes the increasing trend of the number of failed bits, indicating that the read voltage generated based on the reference voltage of this operation stage is increasingly deviating from the target read voltage, and the second stage characterizes the decreasing trend of the number of failed bits, indicating that the read voltage generated based on the reference voltage of this operation stage is increasingly approaching the target read voltage. Therefore, the positional relationship between the reference voltage and the target read voltage characterized by the two stages is contradictory, and therefore it is necessary to move the voltage offset direction of the next operation stage in the opposite direction of the voltage offset direction of this operation stage.

[0133] As the number of operation stages increases through iterations, the voltage offset of each operation stage gradually decreases, that is, the gap between the reference voltage of the current operation stage and the reference voltage of the previous operation stage gradually narrows. This means that as the number of iterations increases, the adjustment of the voltage offset operation will become smaller and smaller, making the reference voltage of the current operation stage gradually approach the reference voltage of the previous operation stage. However, when the voltage offset decreases below a minimum value where the voltage offset operation can no longer be performed, it is impossible to clearly determine the direction of the voltage offset in the next operation stage. Therefore, in order to ensure the effectiveness of the iteration and avoid falling into the dilemma of being unable to determine the next operation, the voltage offset needs to be used as one of the judgment conditions for exiting the iteration. In this way, when the voltage offset drops below the minimum value, the iteration can be automatically stopped to ensure the accuracy and stability of the voltage adjustment operation.

[0134] When the voltage offset in the second reading stage is smaller than a preset threshold, the first reference voltage is determined as the target reading voltage.

[0135] Exemplarily, assuming that the reference voltage of the first operation stage is A, the voltage offset of the first operation stage is B, and in each iteration, the voltage offset gradually decreases. The preset threshold is set to C, that is, when the voltage offset is less than or equal to C, the voltage offset operation cannot be continued, and it needs to be used as one of the judgment conditions for exiting the iteration.

[0136] The example iteration process is as follows:

[0137] First operation stage: voltage offset = B.

[0138] Second operation stage: voltage offset = 1 / 2B.

[0139] The third operation stage: voltage offset = 1 / 4B.

[0140] Fourth operation stage: voltage offset = 1 / 8B.

[0141] In the fourth operation stage, the voltage offset has been reduced to 1 / 8B, and the magnitude relationship between 1 / 8B and C is compared to determine that 1 / 8B is less than the preset threshold C. At this point, no more voltage offset operations can be performed, because further reducing the voltage offset may lead to uncertain results. Therefore, the voltage offset being less than or equal to the preset threshold can be used as a judgment condition for exiting the iteration, the iteration process is stopped, and the reference voltage of the fourth operation stage is output as the target read voltage.

[0142] The operating method of the storage controller provided by the present disclosure gradually reduces the voltage offset as the iteration of the operation stage increases, and stops the iteration when the voltage offset is less than a preset threshold value, ensuring that the voltage offset operation will not continue when the voltage offset is less than the preset threshold value, so as to maintain stability and reliability.

[0143] In addition to using the magnitude relationship between the voltage drift amount and the preset threshold as the judgment condition for exiting iteration, the change trend of the number of failed bits may also be used as the judgment condition for exiting iteration.

[0144] Exemplarily, when the number of the plurality of fail bits decreases first and then increases, the first reference voltage is determined as the target read voltage.

[0145] Exemplarily, the operation stage represented by the dotted line 3 is continued for explanation. Fbc1, Fbc2, Fbc3 and Fbc4 obtained by four read operations, assuming that Fbc1 is 10, Fbc2 is 6, Fbc3 is 4, and Fbc4 is 7, can be seen that with the increase of the read voltage, the change of the number of Fbc includes two stages, the first stage includes Fbc decreasing from 10 to 4, and the second stage includes Fbc decreasing from 4 to 7. The first stage represents the trend of the change of the number of failed bits as a decreasing trend, indicating that the read voltage generated based on the reference voltage of this operation stage is getting closer and closer to the target read voltage, and the second stage represents the trend of the change of the number of failed bits as an increasing trend, indicating that the read voltage generated based on the reference voltage of this operation stage is increasingly deviating from the target read voltage. Therefore, the positional relationship between the reference voltage and the target read voltage represented by the two stages has a relationship turning point, indicating that the target read voltage is near the relationship turning point. Therefore, the base voltage of this operation stage can be output as the target read voltage.

[0146] The operating method of the storage controller provided by the present disclosure dynamically adjusts the voltage offset of the next operating stage according to the reading result of the previous operating stage, so that the voltage offset of each operating stage is changing, thereby reducing the number of read retries required to find the target read voltage, thereby improving the reading performance of the memory and improving the user's experience. In addition, the operating method of the storage controller provided by the present disclosure does not require manual intervention by the user, and automatically finds the best reading position through internal iteration of the processor, reducing the workload of the user and reducing the complexity of operation.

[0147] The embodiment of the present disclosure further provides a storage controller, which can be Figure 8 The storage controller 111 shown includes a processor 311, a buffer 312, an error checking code (ECC) circuit 313, a host interface circuit 314, and a flash memory interface circuit 315, and the storage controller 111 is coupled to the memory 112. Exemplarily, the processor 311 is connected to the host 100 through the host interface circuit 314, and is connected to the memory 112 through the flash memory interface circuit 315.

[0148] The EcC circuit 313 is configured to perform multiple read operations according to the first reference voltage in the first operation phase to obtain multiple read results, wherein the read results include the number of failed bits, and the processor 311 is configured to determine the voltage shift direction in the second operation phase according to the multiple numbers of failed bits;

[0149] The processor 311 is also configured to determine a second reference voltage for the second operating stage based on the first reference voltage, a voltage offset for the second operating stage, and a voltage offset direction for the second operating stage, wherein the voltage offset for the second operating stage is smaller than the voltage offset for the first operating stage, and the voltage offset for the second operating stage is a voltage offset of the second reference voltage relative to the first reference voltage.

[0150] In some embodiments, the second reference voltage, the first reference voltage, and the voltage offset in the second reading phase satisfy:

[0151] V n+1 =V n +(-1) m ·S n+1

[0152] Where V n+1 is the second reference voltage, V n is the first reference voltage, S n+1 is the voltage offset in the second reading stage; when the voltage offset direction in the second reading stage is the same as that in the first reading stage, m is an even number; when the voltage offset direction in the second reading stage is opposite to that in the first reading stage, m is an odd number.

[0153] In some embodiments, the processor 311 is further configured to: obtain a target voltage interval, and determine the first reference voltage as an endpoint voltage of the target voltage interval.

[0154] In some embodiments, the processor 311 is specifically configured to: sequentially increase or decrease the first reference voltage to obtain multiple read voltages, and perform a read operation based on the multiple read voltages to obtain multiple read results, wherein the read results include the number of failed bits.

[0155] In some embodiments, the processor 311 is specifically configured to: when the number of fail bits increases successively, determine the voltage offset direction of the second operation stage to be the opposite direction of the voltage offset direction of the first operation stage; when the number of fail bits decreases successively, determine the voltage offset direction of the second operation stage to be the same direction as the voltage offset direction of the first operation stage.

[0156] In some embodiments, the processor 311 is specifically configured to: when the number of fail bits increases first and then decreases, determine that the voltage offset direction of the second operation phase is the opposite direction of the voltage offset direction of the first operation phase.

[0157] In some embodiments, the processor 311 is further configured to: when the number of the plurality of failed bits decreases first and then increases, determine the first reference voltage as the target read voltage.

[0158] In some embodiments, the processor 311 is further configured to: when the voltage offset in the second reading phase is less than a preset threshold, determine the first reference voltage as the target reading voltage.

[0159] The embodiment of the present disclosure also provides a storage system, for example, Figure 2 The storage system shown includes a memory 112 and the storage controller 111 provided in the above example. The storage controller 111 is coupled to the memory 112 via a flash memory interface circuit 315 to control the memory 112 to store data.

[0160] The embodiment of the present disclosure also provides an electronic device, which can be Figure 1 The electronic device shown includes a host 100 and a storage system 110 provided in the aforementioned embodiments. The host 100 is connected to the storage system 110 to write data to the storage system 110 or read data stored in the storage system 110 .

[0161] Those skilled in the art can clearly understand that, for the convenience and brevity of description, in the above embodiments, the description of each embodiment has different emphases, and the parts that are not described in detail in a certain embodiment can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0162] In the several embodiments provided in the present disclosure, it should be understood that the provided programming method and memory can be implemented in other ways. For example, the division of a module is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0163] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this disclosure.

[0164] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for operating a storage controller, characterized in that: The method comprises: In a first operation phase, performing multiple read operations according to a first reference voltage to obtain multiple read results, wherein the read results include the number of failed bits; Determining a voltage shift direction in a second operation phase according to the plurality of failed bit numbers; A second reference voltage of the second operating stage is determined according to the first reference voltage, a voltage offset of the second operating stage, and a voltage offset direction of the second operating stage. The voltage offset of the second operating stage is smaller than the voltage offset of the first operating stage. The voltage offset of the second operating stage is the voltage offset of the second reference voltage relative to the first reference voltage.

2. The method according to claim 1, characterized in that The second reference voltage, the first reference voltage, and the voltage offset in the second reading phase satisfy: V n+1 =V n +(-1) m ·S n+1 Where V n+1 is the second reference voltage, V n is the first reference voltage, S n+1 is the voltage offset of the second reading stage; when the voltage offset direction of the second reading stage is the same as that of the first reading stage, m is an even number; when the voltage offset direction of the second reading stage is opposite to that of the first reading stage, m is an odd number.

3. The method according to claim 1, characterized in that Prior to the first operating phase, the method comprises: A target voltage interval is acquired, and the first reference voltage is determined as an endpoint voltage of the target voltage interval.

4. The method according to claim 1, characterized in that The performing multiple read operations based on the first reference voltage to obtain multiple read results includes: On the basis of the first reference voltage, the voltage is increased or decreased in sequence to obtain a plurality of read voltages; A read operation is performed based on the plurality of read voltages to obtain a plurality of read results, wherein the read results include a number of failed bits.

5. The method according to claim 4, characterized in that Determining a voltage shift direction in a second operation phase according to the plurality of failed bit numbers includes: When the number of the plurality of failure bits increases sequentially, determining that the voltage offset direction of the second operation stage is the opposite direction of the voltage offset direction of the first operation stage; In a case where the number of the plurality of fail bits decreases sequentially, it is determined that the voltage offset direction of the second operation stage is the same direction as the voltage offset direction of the first operation stage.

6. The method according to claim 4, characterized in that The step of determining the voltage shift direction in the second operation phase according to the change trend of the number of failed bits further includes: In a case where the number of the plurality of fail bits increases first and then decreases, it is determined that the voltage offset direction of the second operation stage is the opposite direction of the voltage offset direction of the first operation stage.

7. The method according to claim 1, characterized in that The method further comprises: When the number of the plurality of fail bits decreases first and then increases, the first reference voltage is determined as the target read voltage.

8. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: When the voltage offset in the second reading stage is smaller than a preset threshold, the first reference voltage is determined as a target reading voltage.

9. A storage controller, characterized in that: The storage controller is coupled to the memory, and the storage controller includes a processor and an error checking code (ECC) circuit; The ECC circuit is configured to perform multiple read operations according to a first reference voltage in a first operation phase to obtain multiple read results, wherein the read results include the number of failed bits; The processor is configured to determine a voltage shift direction in a second operation phase according to the plurality of failed bit numbers; The processor is also configured to determine a second reference voltage for the second operating stage based on the first reference voltage, a voltage offset for the second operating stage, and a voltage offset direction for the second operating stage, wherein the voltage offset for the second operating stage is smaller than the voltage offset for the first operating stage, and the voltage offset for the second operating stage is a voltage offset of the second reference voltage relative to the first reference voltage.

10. The storage controller according to claim 9, characterized in that: The second reference voltage, the first reference voltage, and the voltage offset in the second reading phase satisfy: V n+1 =V n +(-1) m ·S n+1 Where V n+1 is the second reference voltage, V n is the first reference voltage, S n+1 is the voltage offset of the second reading stage; when the voltage offset direction of the second reading stage is the same as that of the first reading stage, m is an even number; when the voltage offset direction of the second reading stage is opposite to that of the first reading stage, m is an odd number.

11. The storage controller according to claim 9, characterized in that: The processor is further configured to: A target voltage interval is acquired, and the first reference voltage is determined as an endpoint voltage of the target voltage interval.

12. The storage controller according to claim 9, characterized in that: The processor is specifically configured to: On the basis of the first reference voltage, the voltage is increased or decreased in sequence to obtain a plurality of read voltages; A read operation is performed based on the plurality of read voltages to obtain a plurality of read results, wherein the read results include a number of failed bits.

13. The storage controller according to claim 12, characterized in that: The processor is specifically configured to: When the number of the plurality of failure bits increases sequentially, determining that the voltage offset direction of the second operation stage is the opposite direction of the voltage offset direction of the first operation stage; In a case where the number of the plurality of fail bits decreases sequentially, it is determined that the voltage offset direction of the second operation stage is the same direction as the voltage offset direction of the first operation stage.

14. The storage controller according to claim 12, wherein: The processor is specifically configured to: In a case where the number of the plurality of fail bits increases first and then decreases, it is determined that the voltage offset direction of the second operation stage is the opposite direction of the voltage offset direction of the first operation stage.

15. The storage controller according to claim 9, characterized in that: The processor is further configured to: When the number of the plurality of fail bits decreases first and then increases, the first reference voltage is determined as the target read voltage.

16. The storage controller according to any one of claims 9 to 15, characterized in that: The processor is further configured to: When the voltage offset in the second reading stage is smaller than a preset threshold, the first reference voltage is determined as a target reading voltage.

17. A storage system, characterized in that: The invention comprises a memory and a memory controller, wherein the memory controller is coupled to the memory, wherein the memory controller is the memory controller according to any one of claims 9 to 16.

18. An electronic device, characterized in that: The invention comprises a host and the storage system as claimed in claim 17, wherein the host is coupled to the storage system to write data to the storage system or read data stored in the storage system.

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