Trench etching method of semiconductor device

Abstract

The invention provides a groove etching method of a semiconductor device. The trench etching method of the semiconductor device comprises the following steps: sequentially superposing an etching stop layer, an insulating layer, a dielectric anti-reflection coating, an NFC layer, an oxide thin film layer, an anti-reflection layer and a photoresist layer on a substrate along a direction far away from the substrate, wherein the photoresist layer is provided with an etching pattern; etching the anti-reflection layer, the oxide thin film layer, the NFC layer, the dielectric anti-reflection coating and the insulating layer in sequence, so that part of the surface of the etching stop layer is exposed; and introducing a combination of a plurality of gases consisting of CxHyFz, CaFb, N2 and Ar, regulating and controlling the proportion of the plurality of gases, and etching the etching stop layer so as to form grooves with different shapes in the etching stop layer. According to the invention, the problem that the shape and size of the groove are difficult to adjust in the groove processing of the semiconductor device in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor processing, and in particular to a trench etching method for a semiconductor device. Background Art

[0002] In the back-end process of semiconductor manufacturing, groove processing is crucial to realize metal connections inside the chip. However, groove etching in the existing technology faces many challenges: insufficient etching selectivity makes it difficult to control the groove shape, poor stability of the mask layer affects pattern transfer, by-product deposition increases filling difficulty and contact resistance, ultra-fine groove size consistency is difficult to ensure, and when the via size is adjusted to reduce contact resistance, the risk of bridging increases significantly. These problems are directly related to the performance and reliability of the device. Therefore, developing a method that can accurately control the bottom morphology of the groove, effectively adjust the contact resistance and avoid the bridging effect has become a key technical problem that needs to be solved in the semiconductor manufacturing industry.

[0003] That is to say, the groove processing of semiconductor devices in the prior art has the problem that the groove shape and size are difficult to adjust. Summary of the invention

[0004] The main purpose of the present invention is to provide a groove etching method for a semiconductor device to solve the problem that the groove shape and size are difficult to adjust in the groove processing of the semiconductor device in the prior art.

[0005] In order to achieve the above-mentioned object, the present invention provides a trench etching method for a semiconductor device, comprising the following steps: stacking an etch stop layer, an insulating layer, a dielectric anti-reflective coating, an NFC layer, an oxide film layer, an anti-reflective layer and a photoresist layer in sequence on a substrate in a direction away from the substrate, wherein the photoresist layer has an etching pattern, the insulating layer and the dielectric anti-reflective coating have through holes corresponding to each other, the through holes are filled with NFC material, and the etch stop layer has a sink groove corresponding to the through hole, the sink groove is filled with NFC material; etching the anti-reflective layer, the oxide film layer, the NFC layer, the dielectric anti-reflective coating and the insulating layer in sequence, so that part of the surface of the etch stop layer is exposed; passing a C x H y F z , C a F b A combination of multiple gases consisting of N2 and Ar is used, the ratio of the multiple gases is adjusted and the etch stop layer is etched to form grooves of different shapes in the etch stop layer.

[0006] Further, the step of adjusting the ratio of the multiple gases and etching the etch stop layer to form grooves of different shapes in the etch stop layer includes: controlling C x H y F zThe ratio of the sum of the flow rates of N2 and N2 to the total flow rate of the multiple gases is within a range of greater than or equal to 9% and less than or equal to 12% to form a vertical groove having a width equal to that of the bottom through hole of the insulating layer; or controlling C x H y F z The ratio of the sum of the flow rates of N2 and N2 to the total flow rate of the multiple gases is within a range of greater than or equal to 22% and less than or equal to 25%, so as to form a deposited polymer on the side wall of the trench of the etch stop layer to form a tapered trench; or control C a F b The ratio of the flow rate of the gas to the total flow rate of the multiple gases is within a range of greater than or equal to 85% and less than or equal to 88%, and the etching pressure is controlled within a range of greater than or equal to 50mT and less than or equal to 70mT to form a vertical groove larger than the bottom through hole width of the insulating layer.

[0007] Further, the step of adjusting the ratio of the multiple gases and etching the etch stop layer to form grooves of different shapes in the etch stop layer includes: controlling C x H y F z The ratio of the flow rate of various gases to the total flow rate of various gases is within the range of greater than or equal to 0.1 and less than or equal to 0.2, and the ratio of the flow rate of N2 to the total flow rate of various gases is controlled within the range of 0.075 and less than or equal to 0.089, so as to form a deposited polymer on the side wall of the groove of the etch stop layer to form a tapered groove.

[0008] Furthermore, the step of adjusting the ratio of multiple gases and etching the etch stop layer to form grooves of different shapes in the etch stop layer includes: controlling the ratio of the flow rate of Ar to the total flow rate of multiple gases to be greater than or equal to 49% and less than or equal to 52%.

[0009] Further, the step of sequentially etching the anti-reflection layer, the oxide film layer, the NFC layer, the dielectric anti-reflection coating and the insulating layer to expose part of the surface of the etching stop layer includes: introducing a first mixed gas to etch the anti-reflection layer and the oxide film layer to expose part of the NFC layer; introducing a second mixed gas to etch the NFC layer, and etching the NFC material in the insulating layer and the dielectric anti-reflection coating to form corresponding through holes in the insulating layer and the dielectric anti-reflection coating, specifically exposing the corresponding through holes in the insulating layer and the dielectric anti-reflection coating; introducing a third mixed gas to etch the dielectric anti-reflection coating, thereby expanding the through hole width of the dielectric anti-reflection coating; introducing a fourth mixed gas to etch the insulating layer to a first preset depth, thereby expanding the through hole width of the insulating layer within the first preset depth.

[0010] Furthermore, in the process of introducing the first mixed gas to etch the anti-reflective layer and the oxide film layer, the first mixed gas is set to include CF4, CHF3 and O2, and the flow rate of CF4 in the first mixed gas is controlled to be within the range of greater than or equal to 170 ml / min and less than or equal to 220 ml / min; and / or the flow rate of CHF3 in the first mixed gas is controlled to be within the range of greater than or equal to 70 ml / min and less than or equal to 120 ml / min; and / or the flow rate of O2 in the first mixed gas is controlled to be within the range of greater than or equal to 10 ml / min and less than or equal to 25 ml / min.

[0011] Further, the step of introducing a second mixed gas to etch the NFC layer, and etching the NFC material in the insulating layer and the dielectric anti-reflective coating to form corresponding through holes in the insulating layer and the dielectric anti-reflective coating includes: introducing N2 and CO2 to etch the NFC layer to partially expose the dielectric anti-reflective coating; introducing N2 and H2 to etch the NFC material in the insulating layer and the dielectric anti-reflective coating to a second preset depth to form corresponding through holes in the insulating layer and the dielectric anti-reflective coating.

[0012] Furthermore, in the step of introducing N2 and H2 to etch the NFC material in the insulating layer and the dielectric anti-reflective coating to a second preset depth, the flow rate of N2 is controlled within a range of greater than or equal to 300 ml / min and less than or equal to 340 ml / min; the flow rate of H2 is controlled within a range of greater than or equal to 50 ml / min and less than or equal to 80 ml / min.

[0013] Furthermore, in the step of introducing the fourth mixed gas to etch the insulating layer to a first preset depth, the etching rate is controlled to be greater than or equal to 40 A / s and less than or equal to 50 A / s.

[0014] Furthermore, after the step of sequentially etching the anti-reflective layer, the oxide film layer, the NFC layer, the dielectric anti-reflective coating and the insulating layer to expose part of the surface of the etch stop layer, the method further includes: introducing O2 to remove the NFC material in the insulating layer and the etch stop layer and the remaining NFC material on the dielectric anti-reflective coating.

[0015] By applying the technical solution of the present invention, the present application reasonably sets the etching steps, firstly, the anti-reflection layer (BARC), the oxide thin film layer (LTO), the NFC layer, the dielectric anti-reflection coating (DARC) and the insulating layer (OX) are sequentially etched until part of the surface of the etch stop layer (NDC) is exposed. This series of etching steps ensures that the groove pattern can be accurately transferred to each layer, laying a solid foundation for the formation of the final groove. The key is that the last step of etching uses C x H y F z , Ca F b A combination of various gases consisting of N2 and Ar can be used to control the balance between polymer deposition, chemical etching and physical etching by reasonably controlling the proportion of these gases, thereby achieving control of the specific morphology of the bottom of the groove and controlling the realization of grooves of different shapes and sizes. This can achieve adjustment of the contact resistance without adjusting the size of the through hole, meeting the design performance requirements and process stability of the product and avoiding the risk of structural failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0017] Figure 1 A schematic flow chart of a trench etching method for a semiconductor device according to an optional embodiment of the present invention is shown;

[0018] Figure 2 A schematic diagram of the structure of the semiconductor device of the present invention before etching is shown;

[0019] Figure 3 A state diagram showing the semiconductor device of the present invention after etching the anti-reflection layer and the oxide film layer;

[0020] Figure 4 A state diagram showing the semiconductor device of the present invention after the NFC layer is etched;

[0021] Figure 5 A state diagram showing the semiconductor device of the present invention after etching the dielectric anti-reflection coating;

[0022] Figure 6 A state diagram showing the semiconductor device of the present invention after the insulating layer is etched;

[0023] Figure 7 A state diagram showing the semiconductor device of the present invention after the remaining NFC material is removed;

[0024] Figure 8 A schematic diagram showing a semiconductor device of the present invention forming a cone-shaped groove in an etch stop layer;

[0025] Fig. 9 A schematic diagram showing a semiconductor device of the present invention forming a vertical groove in an etch stop layer;

[0026] Fig.10 A schematic diagram showing a semiconductor device of the present invention forming a recessed trench in an etch stop layer.

[0027] The above drawings include the following reference numerals:

[0028] 10. Photoresist layer; 20. Anti-reflection layer; 30. Oxide film layer; 40. NFC layer; 41. NFC material; 50. Dielectric anti-reflection coating; 60. Insulation layer; 70. Through hole; 80. Etch stop layer; 81. Groove; 90. Substrate. DETAILED DESCRIPTION

[0029] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0030] It should be noted that, unless otherwise specified, all technical and scientific terms used in this application have the same meanings as commonly understood by ordinary technicians in the technical field to which this application belongs.

[0031] In the present invention, unless otherwise specified, the directional words used, such as "up, down, top, bottom", usually refer to the directions shown in the drawings, or to the components themselves in the vertical, perpendicular or gravity directions; similarly, for ease of understanding and description, "inside and outside" refer to the inside and outside relative to the outline of each component itself, but the above-mentioned directional words are not used to limit the present invention.

[0032] In order to solve the problem in the prior art that the shape and size of the groove 81 of the semiconductor device are difficult to adjust during processing of the groove 81, the present invention provides a groove etching method for the semiconductor device.

[0033] like Figures 1 to 10 As shown, the trench etching method of the semiconductor device comprises the following steps:

[0034] like Figure 2 As shown, an etch stop layer 80, an insulating layer 60, a dielectric anti-reflective coating 50, an NFC layer 40, an oxide film layer 30, an anti-reflective layer 20 and a photoresist layer 10 are sequentially stacked on a substrate 90 in a direction away from the substrate 90, the photoresist layer 10 has an etching pattern, and the insulating layer 60 and the dielectric anti-reflective coating 50 have through holes 70 corresponding to each other and connected, and the number of through holes 70 can be set according to actual conditions. Figure 2 There are three through holes 70 shown in the figure, and the three through holes of the insulating layer 60 correspond one to one to the three through holes of the dielectric anti-reflective coating 50. The three through holes in the two layers are filled with NFC material 41, and the NFC material 41 is the same as the material of the NFC layer 40. The etch stop layer 80 has a sink groove corresponding to the through hole 70 of the insulating layer 60, and the sink groove is filled with NFC material 41, and the depth of the sink groove is less than the thickness of the etch stop layer 80.

[0035] like Figures 2 to 7As shown, the anti-reflection layer 20, the oxide film layer 30, the NFC layer 40, the dielectric anti-reflection coating 50 and the insulating layer 60 are etched in sequence, so that part of the surface of the etch stop layer 80 is exposed.

[0036] like Figures 8 to 10 As shown, the input is from C x H y F z , C a F b A combination of multiple gases consisting of N 2 and Ar is used, the ratio of the multiple gases is adjusted, and the etch stop layer 80 is etched to form grooves 81 of different shapes in the etch stop layer 80.

[0037] The present application sets the etching steps reasonably, first etching the anti-reflection layer 20 (BARC), the oxide film layer 30 (LTO), the NFC layer 40, the dielectric anti-reflection coating 50 (DARC) and the insulating layer 60 (OX) in sequence, until the surface of the etching stop layer 80 (NDC) is partially exposed. This series of etching steps ensures that the groove 81 pattern can be accurately transferred to each layer, laying a solid foundation for the formation of the final groove 81. The key is that the last step of etching uses C x H y F z , C a F b A combination of various gases consisting of N2 and Ar can be used. By reasonably controlling the proportions of these gases, the balance between polymer deposition, chemical etching and physical etching can be controlled, thereby achieving control of the specific morphology of the bottom of the groove 81, and controlling the realization of grooves 81 of different shapes and sizes, thereby achieving contact resistance adjustment without adjusting the size of the through hole 70, thereby meeting the design performance requirements and process stability of the product and avoiding the risk of structural failure.

[0038] It should be noted that the etching pattern of the photoresist layer 10 can be designed according to actual conditions and is not limited to the form in this application. The etching pattern can refer to a plurality of holes penetrating the upper and lower surfaces formed after etching the photoresist layer 10, or can refer to the cross-sectional shape of the plurality of holes along a direction parallel to the substrate 90. The above-mentioned oxide film layer 30 is actually a low-temperature silicon oxide film.

[0039] Specifically, by increasing C x H y F z , C a F b , N2 and C in N2 and Ar x H y F zThe ratio of , increases the content of polymer precursor in the plasma, and promotes the polymer to deposit on the side wall of the groove 81 to form an inclined side wall (Taper), thereby forming a relatively gentle transition at the bottom of the groove 81, reducing the contact resistance, reference Figure 8 Adjust C x H y F z , C a F b , N2 and Ar ratio, so that polymer deposition, chemical etching and physical etching to achieve a balance, etching to form a vertical groove 81 bottom (Vertical), while maintaining structural stability while controlling the contact resistance, reference Fig. 9 As shown. x H y F z , C a F b , C in N2 and Ar a F b The ratio of and the etching pressure are reduced, the chemical etching ability is improved, and the concave morphology (Undercut) at the bottom of the groove 81 is etched to further reduce the contact resistance and avoid the risk of large-area metal bridging, such as Fig.10 shown.

[0040] The configuration of the present application not only solves the problem of the difficulty in controlling the bottom morphology of the groove 81 in the prior art, but also realizes the precise control of the bottom morphology of the groove 81 by flexibly adjusting the etching gas combination and ratio parameters, thereby effectively adjusting the contact resistance without increasing the risk of bridging, and significantly improving the switching speed and overall performance of the semiconductor device. This sophisticated etching control strategy provides a new technical approach for the processing of ultra-fine grooves 81, and meets the strict requirements for grooves 81 and contact resistance in the manufacture of high-density, high-performance integrated circuits.

[0041] Specifically, the step of adjusting the ratio of the multiple gases and etching the etch stop layer 80 to form grooves 81 of different shapes in the etch stop layer 80 includes:

[0042] In an optional embodiment, control C x H y F z The sum of the flow rates of N2 and C x H y F z , C a F b The ratio of the total flow rate of the multiple gases composed of N2 and Ar is within a range of greater than or equal to 9% and less than or equal to 12% to form a vertical groove 81 having a width equal to that of the bottom through hole of the insulating layer 60, such as Fig. 9As shown. By rationally regulating C x H y F z The ratio of N2 to all gases is beneficial to adjust the ratio of these four gases, so that polymer deposition, chemical etching and physical etching are in a relatively balanced position, and the etching forms a vertical bottom morphology. Fig. 9 As shown in C x H y F z The flow ratio of N2 directly affects the chemical reaction of the polymer during the deposition and etching process of the sidewall of the trench 81. The ratio range of 9% to 12% can ensure that a vertical bottom morphology of the trench 81 is formed in the etch stop layer 80, which accurately matches the width of the bottom through hole of the insulating layer 60, helps to improve the efficiency of metal filling and reduce voids and gaps during the filling process.

[0043] In addition, the bottom of the groove 81 with a vertical morphology can provide a stable contact area while reducing the risk of bridging between metal lines, which is crucial for controlling contact resistance. Compared with conical or concave morphologies, vertical morphology is more conducive to maintaining the consistency and minimization of contact resistance, thereby improving the switching speed and overall performance of semiconductor devices. By strictly controlling the ratio of CxHyFz and N2, highly selective etching can be achieved on the etch stop layer 80 while maintaining the uniformity of the etching process. This ensures that the side walls of the groove 81 remain straight and the bottom morphology is consistent, which is especially important for processing ultra-fine grooves 81. It is also possible to control the deposition of by-products during the etching process to avoid unnecessary polymer deposition at the bottom or side walls of the groove 81. In summary, controlling C x H y F z When the flow ratio of N2 is in the range of 9% to 12%, not only can the bottom morphology of the vertical groove 81 be formed with the same width as the bottom through hole of the insulating layer 60, but also the contact resistance can be optimized, the etching selectivity and uniformity can be enhanced, and the process stability and repeatability can be improved, thereby finally realizing a more efficient and stable semiconductor device manufacturing process.

[0044] In another optional embodiment, control C x H y F z The sum of the flow rates of N2 and C x H y F z , C a F b The total flow rate ratio of the multiple gases consisting of N2, Ar and N2 is within a range of greater than or equal to 22% and less than or equal to 25%, so that a polymer deposited on the side wall of the trench 81 of the etch stop layer 80 is formed to form a tapered trench 81. In this way, by increasing C x Hy F z The ratio of N2 to N2 increases the content of polymer precursor in the plasma, so that more polymer is deposited on the side wall of the groove 81, thereby accumulating and etching on the side wall of the groove 81 to form a tapered bottom morphology, referring to Figure 8 As shown in the figure, it can be seen that the side wall of the groove 81 finally formed in the etch stop layer 80 is inclined to the substrate 90, and the cross-sectional shape of a groove 81 along the direction perpendicular to the substrate 90 is an inverted trapezoid, that is, the bottom width of the groove 81 finally formed is smaller than the top width of the groove 81.

[0045] Specifically, the polymer deposited on the sidewall helps guide the metal filling material to flow smoothly into the groove 81, reducing the formation of voids and gaps, and improving the integrity and reliability of the metal filling. The tapered structure can avoid excessive stress concentration during the metal filling process and reduce the risk of metal wire breakage. x H y F z The increase of N2 promotes the chemical reaction in the etching process, forming more polymer precursors, while the presence of Ar ensures the necessary physical etching. In the ratio range of 22%-25%, chemical etching and physical etching reach a balance, ensuring the polymer deposition on the side wall of the groove 81 without affecting the verticality of the groove 81, thereby forming an ideal tapered structure. In this way, the C x H y F z The proportion of N2 and N2 can flexibly control the tapered angle of the sidewall of the groove 81 to meet different design requirements. This flexibility enables the processing of the groove 81 to adapt to various complex design requirements, improving the adaptability and control accuracy of the process. The design of the tapered groove 81 increases the contact area while reducing the direct contact between different metal wires and reducing the risk of bridging, which is important for ensuring the long-term stability and reliability of the device.

[0046] In summary, by controlling C in the etch stop layer 80 x H y F z The flow rate ratio of N2 is in the range of 22%-25%, forming a tapered groove 81, which not only optimizes the contact resistance and improves the metal filling process, but also ensures the chemical and physical balance of the etching process, effectively manages the by-products, improves the process flexibility, stability and device performance, and avoids the bridging effect, providing strong technical support for the manufacture of high-density and high-performance integrated circuits.

[0047] Furthermore, control C x H y F zThe ratio of the flow rate of N2 to the total flow rate of multiple gases is within a range of greater than or equal to 0.1 and less than or equal to 0.2, preferably 1 / 12; and the ratio of the flow rate of N2 to the total flow rate of multiple gases is controlled to be within a range of 0.075 and less than or equal to 0.089, preferably 1 / 6. This arrangement forms a deposited polymer on the side wall of the groove 81 of the etch stop layer 80 to form a tapered groove 81. By further refining the constraints, it is beneficial to ensure the stability of the formation of the tapered groove 81 and the process stability, and ensure the etching accuracy and reliability.

[0048] Or, Control C a F b The flow rate is related to the x H y F z , C a F b The ratio of the total flow rate of the multiple gases composed of N2, Ar and N2 is within the range of greater than or equal to 85% and less than or equal to 88%, and the etching pressure is controlled within the range of greater than or equal to 50mT and less than or equal to 70mT, and the etching temperature is controlled to be greater than or equal to 20°C and less than or equal to 60°C, so as to form a vertical trench 81 larger than the bottom through hole width of the insulating layer 60. By increasing C a F b The proportion of, and reduce the etching pressure, improve the chemical etching ability, so as to etch and form a vertical groove 81 larger than the bottom through hole width of the insulating layer 60, forming a bottom morphology of the concave Undercut, refer to Fig.10 By adjusting C a F b The flow ratio and etching pressure can accurately control the morphology of the groove 81, especially in the processing of ultra-fine grooves 81 with a feature size less than 150nm. The vertical groove 81 can provide a better sidewall right angle, which is beneficial to the uniformity and integrity of the subsequent metal filling. a F b Precise control of the gas ratio can enhance the selectivity of the etching process and reduce non-target etching of surrounding materials; at the same time, the appropriate pressure range ensures uniformity during the etching process and avoids inconsistencies in the size or morphology of the groove 81, which is particularly important for the manufacture of high-density integrated circuits. This setting can achieve reasonable regulation of the bottom width of the groove 81, forming a vertical, ultra-fine groove 81, thereby optimizing contact resistance, improving etching selectivity and uniformity, effectively managing by-products, ensuring process stability and repeatability, and also reducing the risk of bridging effects, providing a strong technical guarantee for the manufacture of high-density, high-performance integrated circuits. The setting of the specific ratio needs to be optimized according to the actual process conditions and target morphology to achieve the best effect.

[0049] In actual processing, control C x Hy F z The ratio of the flow rate of N2 to the total flow rate is increased from 0 to 10%, which can adjust the etching morphology of the groove 81 from undercut to vertical. x H y F z The ratio of the flow rate of N2 to the total flow rate is increased from 10% to 25%, thereby controlling the morphology of the etching of the groove 81 from vertical to inclined Taper.

[0050] Specifically, in the step of adjusting the ratio of multiple gases and etching the etch stop layer 80 to form grooves 81 of different shapes in the etch stop layer 80, the ratio of the flow rate of Ar to the total flow rate of multiple gases is controlled to be within a range of greater than or equal to 49% and less than or equal to 52%, preferably 50%. That is to say, in the process of etching the etch stop layer 80, whether it is necessary to form a conical, vertical or concave groove 81, it is necessary to ensure that the proportion of Ar is within this range, so that Ar gas can be used as a carrier gas to improve etching uniformity, which is suitable for the manufacture of semiconductor devices that require high uniformity etching, such as microstructures in integrated circuits, and can ensure the consistency of device performance.

[0051] Furthermore, Ar is a typical inert gas that performs physical etching mainly by ion bombardment, while C x H y F z , C a F b , N2 and other gases participate in chemical reactions and affect chemical etching. By controlling the flow ratio of Ar, the balance between physical etching and chemical etching can be finely adjusted, which is crucial for the regulation of the bottom morphology of the groove 81. At an Ar flow ratio of 49%-52%, it can not only maintain sufficient physical etching ability to maintain the side wall quality of the groove 81, but also ensure the effectiveness of chemical etching to avoid over-etching or under-etching. During the etching process, a reasonable proportion of Ar helps to control the amount of polymer deposition on the side wall of the groove 81. Too high or too low an Ar ratio will affect the polymer precursor content in the plasma, thereby affecting the formation of the bottom morphology of the groove 81. Specifically, by keeping the Ar ratio within the above range, polymer deposition, chemical etching and physical etching can reach an ideal balance point, ensuring that the bottom morphology of the groove 81 is the desired tapered (Taper), vertical (Vertical) or concave (Undercut) morphology without affecting the integrity of the side wall.

[0052] In addition, by rationally planning the proportion of Ar, the bottom morphology of the groove 81 can be precisely controlled, thereby optimizing the contact resistance. The tapered (Taper) morphology can reduce the contact area of ​​the metal filling, the vertical (Vertical) morphology minimizes the contact resistance while maintaining the right angle of the sidewall, and the undercut (Undercut) morphology can increase the contact area while avoiding the bridging effect and reducing the contact resistance. This strategy of controlling contact resistance through morphology improves the reliability of the process while ensuring device performance. Strict control of the Ar gas ratio helps to improve the stability and repeatability of the etching process. This is very important for quality control in a large-scale production environment, ensuring that the bottom morphology of the groove 81 of each device is consistent, thereby ensuring the consistency and stability of the performance of the semiconductor device. In summary, the precise control of the Ar gas flow ratio between 49% and 52% not only ensures the balance between physical and chemical etching during the etching process, but also optimizes the bottom morphology of the groove 81, thereby achieving effective adjustment of the contact resistance. At the same time, it improves the uniformity, selectivity and repeatability of the etching process, providing strong technical support for the manufacture of high-density, high-performance integrated circuits.

[0053] like Figure 2 As shown, in the step of sequentially etching the anti-reflection layer 20, the oxide film layer 30, the NFC layer 40, the dielectric anti-reflection coating 50 and the insulating layer 60 so that a portion of the surface of the etch stop layer 80 is exposed, the step includes:

[0054] Using the photoresist layer 10 as a mask, the first mixed gas is introduced to simultaneously etch the anti-reflection layer 20 and the oxide film layer 30, and the etching pattern is transferred to the NFC layer 40 to expose a portion of the NFC layer 40. The structure of the semiconductor device after this step is completed is shown in FIG. Figure 3 shown.

[0055] Then, the second mixed gas is introduced to etch the NFC layer 40, so that the etching pattern is transferred to the dielectric anti-reflection coating 50, and the NFC material 41 in the through hole 70 of the insulating layer 60 and the dielectric anti-reflection coating 50 is etched, so that the NFC material 41 filled in the through hole 70 of the insulating layer 60 retains an appropriate height. After the etching is completed, the corresponding through hole 70 is formed in the insulating layer 60 and the dielectric anti-reflection coating 50. The structure of the semiconductor device after completing this step is referred to Figure 4As shown, at this time, the anti-reflection layer 20 and the photoresist layer 10 on the oxide film layer 30 can be retained or removed. Ensuring that the etching pattern is accurately transferred from the photoresist layer 10 to the dielectric anti-reflection coating 50 and maintaining the integrity of the pattern is crucial for subsequent metal line connection. This setting can ensure the consistency of the NFC material 41 in the through hole 70 of the insulating layer 60, enhance the repeatability and stability of the process, and is beneficial to large-scale production. Provide an optimized through hole 70 environment for the subsequent metal filling step, reduce void formation, and improve the quality and reliability of metal filling.

[0056] Then, the third mixed gas is introduced to etch the dielectric anti-reflection coating 50, thereby expanding the width of the through hole 70 of the dielectric anti-reflection coating 50, and transferring the etched pattern to the surface of the insulating layer 60. The structure of the semiconductor device after etching is referenced to Figure 5 As shown. At this time, the oxide film layer 30 on the NFC layer 40 is also removed. Specifically, the third mixed gas includes CF4, CHF3, O2 and Ar. CF4 and CHF3 can effectively etch the dielectric anti-reflective coating 50, O2 enhances the selectivity and cleanliness of etching, and Ar provides physical etching assistance to ensure that the groove 81 pattern is accurately transferred to the lower layer and reduce over-etching. The physical etching effect of Ar combined with the chemical etching of CF4 and CHF3 can regulate the bottom morphology of the groove 81 to make it closer to the design requirements and improve the device performance. The synergistic effect of the mixed gas improves the predictability and stability of the etching process, which is conducive to maintaining consistent processing quality in large-scale production.

[0057] Specifically, it is also necessary to control the flow rate of CF4 in the third mixed gas to be within the range of greater than or equal to 180 ml / min and less than or equal to 210 ml / min; control the flow rate of CHF3 in the third mixed gas to be within the range of greater than or equal to 50 ml / min and less than or equal to 80 ml / min; control the flow rate of O2 in the third mixed gas to be within the range of greater than or equal to 10 ml / min and less than or equal to 20 ml / min; and control the flow rate of Ar in the third mixed gas to be within the range of greater than or equal to 450 ml / min and less than or equal to 500 ml / min.

[0058] Then, using the NFC layer 40 as a mask, the fourth mixed gas is introduced to etch the insulating layer 60 to a first preset depth, thereby expanding the width of the through hole 70 of the insulating layer 60 within the first preset depth. The etching depth is controlled by the etching time of this step to achieve the reserved depth required by the design. The first preset depth is less than the total thickness of the insulating layer 60, that is, in the process of etching the insulating layer 60, the etching depth is reasonably controlled by reasonably controlling the etching process parameters, so that only the width of the through hole 70 of the insulating layer 60 within the first preset depth is expanded. In other words, the width of the through hole 70 at the bottom of the insulating layer 60 remains unchanged, thereby forming a through hole 70 size that is larger at the top and smaller at the bottom.

[0059] Specifically, the fourth mixed gas includes CF4, CHF3, O2 and Ar. CF4 and CHF3 provide chemical etching ability, O2 enhances the selectivity and cleanliness of etching, and Ar assists physical etching. Under the joint action, the etching depth of the insulating layer 60 can be accurately controlled to meet the design requirements of OX remain. This setting helps to regulate the morphology of the groove 81, maintain the verticality of the side wall of the through hole 70, and reduce the non-uniformity of the bottom. The reasonable selection of the fourth mixed gas optimizes the etching process, realizes the precise control of the depth and morphology of the insulating layer 60, and maintains high process stability and cleanliness, which has a significant effect on improving the performance of semiconductor devices.

[0060] Specifically, it is also necessary to control the flow rate of CF4 in the fourth mixed gas to be within the range of greater than or equal to 200 ml / min and less than or equal to 240 ml / min; control the flow rate of CHF3 in the fourth mixed gas to be within the range of greater than or equal to 40 ml / min and less than or equal to 60 ml / min; control the flow rate of O2 in the fourth mixed gas to be within the range of greater than or equal to 8 ml / min and less than or equal to 15 ml / min; and control the flow rate of Ar in the fourth mixed gas to be within the range of greater than or equal to 700 ml / min and less than or equal to 1000 ml / min.

[0061] Then, O2 is introduced to remove the remaining NFC material 41 in the through hole 70 of the insulating layer 60 and the etch stop layer 80 and the remaining NFC material on the dielectric anti-reflective coating 50, so that the groove of the etch stop layer 80 is exposed. x H y F z , C a F b A combination of multiple gases consisting of N2 and Ar, adjusting the ratio of the multiple gases and etching the etch stop layer 80 to form grooves 81 of different shapes in the etch stop layer 80" is performed to form grooves 81 of desired morphology. In this step, the dielectric anti-reflective coating 50 on the top of the insulating layer 60 is removed.

[0062] Finally, H2 and N2 may be introduced to remove the polymer, thereby completing the trench etching method of the present application.

[0063] Through the above process, a trench 81 with a characteristic size less than or equal to 120 nm is formed, where the characteristic size includes the depth and width of the trench 81 .

[0064] like Figure 3 As shown, in the process of introducing the first mixed gas to etch the anti-reflection layer 20 and the oxide film layer 30, the first mixed gas is set to consist of CF4, CHF3 and O2. In this step, the flow rate of CF4 in the first mixed gas is controlled to be greater than or equal to 170 ml / min and less than or equal to 220 ml / min; the flow rate of CHF3 in the first mixed gas is controlled to be greater than or equal to 70 ml / min and less than or equal to 120 ml / min; the flow rate of O2 in the first mixed gas is controlled to be greater than or equal to 10 ml / min and less than or equal to 25 ml / min. By adjusting the flow rates of CF4, CHF3 and O2, the etching rate and selectivity can be accurately controlled to ensure that the etching pattern is accurately transferred from the photoresist layer 10 to the NFC layer 40, and the integrity and verticality of the groove 81 are maintained. CF4 and CHF3 are used as etching gases, and O2 is used as an oxidant. Their flow ratio affects the verticality and bottom smoothness of the sidewalls of the groove 81, which helps to form the desired morphology of the groove 81. The flow of CF4 and CHF3 can affect the etching depth, while O2 helps control the cleanliness of etching. The synergistic effect of the three helps to achieve the precise depth required by the design. Reasonable gas flow settings help to maximize the use of gas resources, reduce unnecessary waste, and thus reduce overall process costs.

[0065] like Figure 4 As shown, in the step of introducing the second mixed gas to etch the NFC layer 40, and etching the NFC material 41 in the insulating layer 60 and the dielectric anti-reflection coating 50 to form corresponding through holes 70 in the insulating layer 60 and the dielectric anti-reflection coating 50, two small steps are included, namely:

[0066] N2 and CO2 are introduced to etch the NFC layer 40 so that the dielectric anti-reflection coating 50 is partially exposed.

[0067] N2 and H2 are introduced to etch the NFC material 41 in the insulating layer 60 and the dielectric anti-reflection coating 50 to a second preset depth, so as to form corresponding through holes 70 in the insulating layer 60 and the dielectric anti-reflection coating 50 .

[0068] In the etching process of the groove 81 of the back-end process BEOL, N2 and CO2 are used to etch the NFC layer 40 in the first stage, and then N2 and H2 are used to etch the second stage. In this way, the NFC layer 40 can be effectively etched by N2 and CO2, while protecting the dielectric anti-reflection coating 50 below from being over-etched, ensuring that the dielectric anti-reflection coating 50 is partially exposed, and preparing a good interface for subsequent steps. The second stage uses N2 and H2 etching, which can accurately control the etching depth, avoid over-etching, and ensure that the depth and width of the through hole 70 consistent with the design are formed in the insulating layer 60 and the dielectric anti-reflection coating 50, which is crucial for controlling contact resistance and avoiding bridging effects. At the same time, the cleanliness of the groove 81 can be maintained, which is conducive to subsequent metal filling. In addition, N2 and H2 as etching gases can reduce damage to the insulating layer 60 and other sensitive layers, and protect the integrity and performance of the device structure.

[0069] Specifically, in the step of introducing N2 and H2 to etch the NFC material 41 in the insulating layer 60 and the dielectric anti-reflective coating 50 to a second preset depth, the flow rate of N2 is controlled within a range of greater than or equal to 300 ml / min and less than or equal to 340 ml / min; the flow rate of H2 is controlled within a range of greater than or equal to 50 ml / min and less than or equal to 80 ml / min. By properly controlling the flow rates of N2 and H2, it is beneficial to accurately control the etching depth, ensure that the NFC material 41 reserved in the insulating layer 60 maintains a reasonable height, and a reasonable flow range avoids excessive etching, protects the underlying layer from damage, and maintains the integrity of the groove 81 and the verticality of the sidewall.

[0070] Specifically, in the step of introducing the fourth mixed gas to etch the insulating layer 60 to a first preset depth, the etching rate is controlled to be greater than or equal to 40A / s and less than or equal to 50A / s. This rate range ensures the precise control of the etching depth, meets the residual thickness of the insulating layer 60 required by the design, and has a significant impact on the device performance. A higher etching rate improves manufacturing efficiency and shortens the process cycle. The control of the etching rate helps to maintain the morphology of the groove 81, prevents structural damage caused by excessive etching, maintains good sidewall verticality, and a stable and controllable etching rate ensures the consistency of the process. At the same time, it can reduce the deposition of by-products, keep the inside of the groove 81 clean, and facilitate subsequent metal filling. Through a reasonable etching rate, it is possible to achieve precise control of the depth, improve production efficiency, maintain the morphology of the groove 81, ensure process stability and product quality, and reduce internal contamination in the groove 81, which plays a key role in improving the electrical performance of semiconductor devices.

[0071] It should be noted that the first preset depth and the second preset depth can be set according to actual conditions and are not limited in this application.

[0072] Specifically, when entering thex H y F z , C a F b In the step of combining multiple gases consisting of N2 and Ar, C x H y F z Including CHF3, set C a F b Including CF4. CHF3 can increase the polymer precursor in the plasma, promote polymer deposition, help form protective side walls, and control the bottom morphology of the groove 81. CF4 can enhance chemical etching ability, especially under low pressure conditions, help form Undercut or Vertical morphology, and optimize contact resistance as needed. The addition of Ar provides physical etching action, assists in controlling the etching rate and morphology, keeps the side walls flat, and reduces damage. N2 helps stabilize the etching plasma, controls the amount of polymer deposition, and ensures the predictability and consistency of the etching process. By reasonably selecting the gas combination setting, the bottom morphology of the groove 81 can be effectively controlled, the flexibility and controllability of the process can be improved, and it has a significant effect on optimizing contact resistance and improving device performance.

[0073] Optionally, the substrate 90 of the present application is composed of a stacked OX layer and a NED layer, and the NED layer is located on the side of the OX layer away from the etching stop layer. Metal wiring corresponding to the groove 81 is provided in the OX layer and the NED layer. The OX layer is made of the same material as the above-mentioned insulating layer 60, and the NED layer is made of the same material as the above-mentioned etching stop layer 80.

[0074] The method of the present application is particularly suitable for processing ultrafine grooves 81 with a characteristic size greater than 0nm and less than 150nm. Grooves 81 within this size range are extremely critical in modern semiconductor manufacturing processes, especially in the back-end processes of high-performance integrated circuits and memory chips. The method can achieve precise adjustment of the bottom morphology of the groove 81 by precisely controlling the gas combination and proportion during the etching process and the environmental parameters of the etching chamber (such as pressure and temperature), which specifically includes the following points:

[0075] Morphology control: By adjusting the gas combination and parameters, the bottom of the groove 81 can be selectively controlled to form different morphologies such as tapered, vertical or undercut. This morphology control is crucial for ultra-fine grooves 81 because it directly affects the efficiency of metal filling, the size of contact resistance and the switching speed of the device.

[0076] Dimensional accuracy: The method of the present application can maintain the dimensional accuracy of the groove 81 within the ultra-micro size range, which is very important for ensuring the consistency and reliability of device performance. Especially when the feature size is less than 150nm, a slight change in size may have a significant impact on device performance.

[0077] Contact resistance adjustment: The contact resistance can be flexibly adjusted by adjusting the morphology of the bottom of the groove 81. For example, the tapered groove 81 can reduce the contact area and thus reduce the resistance, while the concave morphology can increase the contact area but avoid the bridging effect, and the vertical morphology provides a balance between contact resistance and structural stability.

[0078] Avoiding the bridging effect: In the processing of ultra-fine grooves 81, the bridging effect is a common problem, which will cause short circuits between metal lines. The method of the present application effectively avoids the bridging effect by controlling the morphology and size of the grooves 81, thereby ensuring the long-term stability and reliability of the device.

[0079] Process stability and repeatability: The method of the present application improves the stability and repeatability of the process by setting specific gas ratios and environmental parameters, which is crucial for quality control and cost management under large-scale production conditions.

[0080] Wide adaptability: Whether used for logic devices or memory devices, whether based on a silicon substrate 90 or a substrate 90 made of other materials, the method of the present application can provide a reliable solution for processing the groove 81 , showing wide adaptability and flexibility.

[0081] In summary, the method of the present application achieves precise control of the morphology of the groove 81 through a sophisticated etching control strategy in the processing of the ultra-fine groove 81, which not only solves the problem of size control, but also optimizes the contact resistance, avoids the bridging effect, and improves the process stability and repeatability, providing strong technical support for the manufacture of high-density, high-performance integrated circuits.

[0082] Obviously, the above-described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0083] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0084] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein.

[0085] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A trench etching method for a semiconductor device, characterized in that: The steps include: An etch stop layer (80), an insulating layer (60), a dielectric anti-reflective coating (50), an NFC layer (40), an oxide film layer (30), an anti-reflective layer (20) and a photoresist layer (10) are sequentially stacked on a substrate (90) in a direction away from the substrate (90); the photoresist layer (10) has an etched pattern; the insulating layer (60) and the dielectric anti-reflective coating (50) have through holes (70) corresponding to each other; the through holes (70) are filled with NFC material (41); and the etch stop layer (80) has a sink corresponding to the through hole (70); the sink is filled with the NFC material (41); The anti-reflection layer (20), the oxide thin film layer (30), the NFC layer (40), the dielectric anti-reflection coating (50) and the insulating layer (60) are sequentially etched so that a portion of the surface of the etch stop layer (80) is exposed; Access by C x H y F z , C a F b A combination of multiple gases consisting of N2 and Ar is used to adjust the ratio of the multiple gases and etch the etch stop layer (80) to form grooves (81) of different shapes in the etch stop layer (80).

2. The trench etching method of a semiconductor device according to claim 1, characterized in that: The step of adjusting the ratio of the plurality of gases and etching the etch stop layer (80) to form grooves (81) of different shapes in the etch stop layer (80) comprises: Control C x H y F z The ratio of the sum of the flow rates of N2 and N2 to the total flow rate of the plurality of gases is within a range of greater than or equal to 9% and less than or equal to 12%, so as to form a vertical groove (81) having a width equal to that of the bottom through hole of the insulating layer (60); or Control C x H y F z The ratio of the sum of the flow rates of N2 and N2 to the total flow rate of the plurality of gases is within a range of greater than or equal to 22% and less than or equal to 25%, so as to form a deposited polymer on the side wall of the groove (81) of the etch stop layer (80) to form a tapered groove (81); or Control C a F b The ratio of the flow rate of the plurality of gases to the total flow rate of the plurality of gases is within a range of greater than or equal to 85% and less than or equal to 88%, and the etching pressure is controlled within a range of greater than or equal to 50 mT and less than or equal to 70 mT to form a vertical groove (81) greater than the bottom through hole width of the insulating layer (60).

3. The trench etching method of a semiconductor device according to claim 1, characterized in that: The step of adjusting the ratio of the plurality of gases and etching the etch stop layer (80) to form grooves (81) of different shapes in the etch stop layer (80) comprises: Control C x H y F z The ratio of the flow rate of N2 to the total flow rate of the multiple gases is within a range of greater than or equal to 0.1 and less than or equal to 0.2, and the ratio of the flow rate of N2 to the total flow rate of the multiple gases is controlled within a range of 0.075 and less than or equal to 0.089, so as to form a deposited polymer on the side wall of the groove (81) of the etch stop layer (80) to form a tapered groove (81).

4. The trench etching method of a semiconductor device according to claim 1, characterized in that: The step of adjusting the ratio of the plurality of gases and etching the etch stop layer (80) to form grooves (81) of different shapes in the etch stop layer (80) comprises: The ratio of the flow rate of Ar to the total flow rate of the plurality of gases is controlled within a range of greater than or equal to 49% and less than or equal to 52%.

5. The trench etching method of a semiconductor device according to claim 1, characterized in that: The step of sequentially etching the anti-reflection layer (20), the oxide thin film layer (30), the NFC layer (40), the dielectric anti-reflection coating (50) and the insulating layer (60) so that a portion of the surface of the etching stop layer (80) is exposed comprises: Passing a first mixed gas to etch the anti-reflection layer (20) and the oxide thin film layer (30) to expose a portion of the NFC layer (40); Passing a second mixed gas to etch the NFC layer (40), and to etch the NFC material (41) in the insulating layer (60) and the dielectric anti-reflection coating (50), so as to form corresponding through holes (70) in the insulating layer (60) and the dielectric anti-reflection coating (50); Passing a third mixed gas to etch the dielectric anti-reflection coating (50), thereby expanding the through-hole width of the dielectric anti-reflection coating (50); A fourth mixed gas is introduced to etch the insulating layer (60) to a first preset depth, thereby expanding the width of the through hole of the insulating layer (60) within the first preset depth.

6. The trench etching method of a semiconductor device according to claim 5, characterized in that: In the process of introducing a first mixed gas to etch the anti-reflection layer (20) and the oxide film layer (30), the first mixed gas is set to include CF4, CHF3 and O2, Controlling the flow rate of CF4 in the first mixed gas to be within a range of greater than or equal to 170 ml / min and less than or equal to 220 ml / min; and / or Controlling the flow rate of CHF3 in the first mixed gas to be within a range of greater than or equal to 70 ml / min and less than or equal to 120 ml / min; and / or The flow rate of O2 in the first mixed gas is controlled within a range of greater than or equal to 10 ml / min and less than or equal to 25 ml / min.

7. The trench etching method of a semiconductor device according to claim 5, characterized in that: The step of introducing the second mixed gas to etch the NFC layer (40), and etching the NFC material (41) in the insulating layer (60) and the dielectric anti-reflection coating (50), so as to form corresponding through holes (70) in the insulating layer (60) and the dielectric anti-reflection coating (50) comprises: Passing N2 and CO2 to etch the NFC layer (40) so that the dielectric anti-reflection coating (50) is partially exposed; N2 and H2 are introduced to perform etching to a second preset depth on the NFC material (41) in the insulating layer (60) and the dielectric anti-reflection coating (50), so as to form corresponding through holes (70) in the insulating layer (60) and the dielectric anti-reflection coating (50).

8. The trench etching method of a semiconductor device according to claim 7, characterized in that: In the step of introducing N2 and H2 to etch the NFC material (41) in the insulating layer (60) and the dielectric anti-reflection coating (50) to a second preset depth, Control the flow rate of N2 within the range of 300 ml / min or more and 340 ml / min or less; The flow rate of H2 is controlled within the range of greater than or equal to 50 ml / min and less than or equal to 80 ml / min.

9. The trench etching method of a semiconductor device according to claim 5, characterized in that: In the step of introducing the fourth mixed gas to etch the insulating layer (60) to a first preset depth, The etching rate is controlled to be greater than or equal to 40 A / s and less than or equal to 50 A / s.

10. The trench etching method of a semiconductor device according to claim 1, characterized in that: After the step of sequentially etching the anti-reflection layer (20), the oxide thin film layer (30), the NFC layer (40), the dielectric anti-reflection coating (50) and the insulating layer (60) so that a portion of the surface of the etching stop layer (80) is exposed, the method further comprises: O2 is introduced to remove the NFC material (41) in the insulating layer (60) and the etch stop layer (80) and the remaining NFC material on the dielectric anti-reflective coating (50).

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