Method for preventing defects in integrated etching process and preparing metal interconnection structure

Abstract

The invention discloses a method for preventing defects in an integrated etching process and preparing a metal interconnection structure, which comprises the following steps of: manufacturing a multi-layer film structure on a target wafer with a first metal layer, and manufacturing a notch for exposing the first metal layer in the multi-layer film structure by using the integrated etching process; after etching is completed, CO / N2 combined gas is introduced as plasma gas in the electricity removal process, and a stable isolation protection layer is deposited on the surface of the notch so as to isolate residual polymers generated at the notch in the etching process; after electricity removal is completed, the wafer is jacked up and transferred into a wafer box; transferring the wafer in the wafer box to a wet cleaning process, and cleaning the deposited metal layer; removing the redundant metal layer and the multilayer film structure by adopting a CMP (Chemical Mechanical Polishing) process to complete the manufacturing of the metal interconnection structure; according to the method, the defect in the integrated etching process is prevented by improving the electricity removal procedure, an unexpected effect is achieved, high-purity nitrogen protection is not needed in the wafer box during transfer, and the limit waiting time is greatly prolonged.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and relates to an integrated etching process, and in particular to a method for preventing defects in the integrated etching process and preparing a metal interconnection structure. Background Art

[0002] The All in One (AIO) etching process is a method of simultaneous etching of trenches and vias, also known as metal hard mask Damascus integrated etching. When the hard mask is opened, the trench pattern is defined, and then the through-hole pattern is defined by exposure and development. Finally, the trench and through-hole are etched simultaneously, and the trench and through-hole patterns are completed in one step. After etching, the electrostatic chuck is used to release the wafer from the clamping of the wafer, and then the wafer is transferred to the front opening unified pod (Front Opening Unified Pod, Foup). The wafer needs to wait for a certain period of time in the wafer transfer box before entering the wet cleaning process (WET). After the wet cleaning process, the electrochemical copper plating process (Cu ECP) ​​is used to grow a certain thickness of Cu layer in the through-hole and trench. Finally, the chemical mechanical polishing process (CMP) is used to grind away the unnecessary Cu and metal hard mask to obtain a metal interconnect structure.

[0003] After the integrated etching is completed, due to the etching process problems, by-products will be generated. The by-products are residual polymers containing carbon and fluorine elements (C x F y When the wafer is transferred to the front-opening wafer transfer box, it will come into contact with air and water vapor. At this time, the residual polymer (C x F y polymer) will react with water vapor, TiN (metal hard mask is generally TiN), etc. to form titanium fluoride residue (Ti x F y The titanium fluoride residue covers the inner surface of the groove and the through hole (collectively referred to as the notch) and is removed in the subsequent wet cleaning process. The titanium fluoride residue is difficult to completely remove. The residual titanium fluoride makes it impossible to fill Cu during electrochemical copper plating. After the CMP process, the titanium fluoride residue is worn away to form a void, causing interconnection defects.

[0004] In addition, after etching is completed, before entering the wet cleaning process, the wafer often waits for several hours to dozens of hours in the wafer transfer box. During this process, the wafer will also be exposed to air or water vapor, which will react with residual polymer (Cx F y The reaction between the polymer and the titanium fluoride residue is difficult to remove.

[0005] In the prior art, the conventional solution is to add a post-etch treatment (PET) process after the integrated etching is completed, and use plasma gas (using N2 / H2) to remove the fluorinated polymer in the grooves formed by the integrated etching. However, the removal effect is limited, so it is necessary to replenish high-purity nitrogen in the wafer transfer box at intervals (usually 2 hours) to prevent the residual fluorinated polymer from reacting with water vapor in the air when the wafer stays for a long time to generate titanium fluoride residues that are difficult to remove by the subsequent wet cleaning process; even so, the waiting time of the wafer in the wafer transfer box cannot exceed 4 hours, which is not only costly and cumbersome to operate, but also seriously affects the flexible deployment of subsequent processes.

[0006] Prior art CN106206422A discloses a method for reducing the growth of metal hard mask Damascus integrated etching defects, the first step: performing metal hard mask Damascus integrated etching treatment; the second step: using etching equipment to clean off the polymer generated during the etching process on the wafer surface; the third step: using etching equipment to deposit a layer of relatively stable polymer on the wafer surface to prevent the device surface on the wafer from reacting with the air to produce polymers that block etching defects. The second step is actually the PET process mentioned above; in the third step, nitrogen and carbon monoxide are reacted to obtain carbon nitride and oxygen. Carbon nitride is a stable polymer that blocks the device surface on the wafer from reacting with the air to produce blocking etching defects; due to effective blocking, the waiting time of the metal hard mask Damascus integrated etching wafer before wet etching is extended; the process flexibility is increased, but the process still has the PET process in the second step. Without this step, the actual effect cannot achieve the ideal effect, and the de-electrification process (Dechuck) after the third step releases the clamping of the electrostatic chuck on the wafer, and an inert gas needs to be introduced. The commonly used inert gas Ar will bombard the stable polymer generated in the third step, causing the stable polymer to partially fail and affect the isolation effect of the stable polymer.

[0007] Therefore, further research and development is necessary to improve the efficiency of residue removal or isolation, and significantly extend the waiting time of the metal hard mask Damascus integrated etching wafer before wet etching without the need for nitrogen protection. Summary of the invention

[0008] One of the purposes of the present invention is to provide a method for preventing defects in an integrated etching process, thereby solving the problem of preventing defects caused by byproducts in the integrated etching process.

[0009] Another object of the present invention is to provide a method for preparing a metal interconnection structure, and the yield of the metal interconnection structure is improved by using the above method to prepare the metal interconnection structure.

[0010] In order to solve the above technical problems, the present invention adopts the following technical solutions: In one aspect, the present invention provides a method for preventing defects in an integrated etching process, comprising the following steps: The notch is formed by using an integrated etching process; After etching is completed, a CO / N2 gas combination is introduced as a plasma gas in the static removal process to allow the plasma gas to react and deposit a stable isolation protection layer on the surface of the notch to isolate the residual polymer generated in the notch during the etching process.

[0011] Furthermore, the static elimination process includes the following three stages: In the first stage, the conditions for removing static electricity are prepared. After the etching is completed, a CO / N2 gas combination is introduced into the etching chamber and maintained for a period of time after reaching the first pressure; The second stage: maintaining the first pressure, starting the RF power supply, dissociating the CO / N2 gas combination into plasma gas. Under the interaction of ions, the plasma gas reacts quickly on the notch surface to form a stable isolation protective layer. Stage 3: Apply reverse voltage to the electrostatic chuck to release the wafer.

[0012] Furthermore, in the first stage, the first pressure is 100mT-400mT, and the maintenance time after reaching the first pressure is 4-20s. During the pressure maintenance process, CO / N2 combined gas is continuously introduced for purging and replacement.

[0013] Furthermore, in the second stage, the pressure of the first stage is maintained, the radio frequency energy is set to 100-400W, the second stage is maintained for 2-8s, and the plasma gas is kept continuously present.

[0014] Furthermore, the third stage is maintained for 0.5-4s, and the plasma gas is kept continuously present.

[0015] In another aspect, the present invention provides a method for preparing a metal interconnect structure, comprising the following steps: Providing a target wafer having a first metal layer, wherein the first metal layer is a metal circuit on the target wafer; fabricating a multilayer film structure on the first metal layer; Using an integrated etching process to form a notch in the multi-layer film structure to expose the first metal layer; After etching is completed, a CO / N2 gas combination is introduced as a plasma gas in the de-electrification process, so that the plasma gas reacts and a stable isolation protection layer is deposited on the surface of the notch to isolate the residual polymer generated in the notch during the etching process; After the charge removal is completed, the wafer is lifted up and transferred to the wafer box; Transferring the wafers in the wafer box to a wet cleaning process to remove the stable isolation protective layer and residual polymer; depositing a metal layer within the notch; The CMP process is used to remove the redundant metal layers and multi-layer film structures to complete the production of the metal interconnection structure.

[0016] Furthermore, the multi-layer film structure includes a first etch stop layer, a low-k dielectric layer, a second etch stop layer, and a hard mask layer which are sequentially formed on the first metal layer.

[0017] Furthermore, when an integrated etching process is adopted, during the integrated etching, an anti-reflection coating is coated on the hard mask layer.

[0018] Furthermore, the first etch stop layer includes but is not limited to nitride-doped silicon carbide and silicon nitride; the second etch stop layer includes but is not limited to tetraethyl orthosilicate layer, silicon dioxide, and silicon nitride.

[0019] In another aspect, the present invention provides a metal interconnect structure prepared by a preparation method.

[0020] Compared with the prior art, the present invention has the following beneficial effects: The present invention eliminates the post-etch treatment (PET) process in the prior art, greatly reduces the cost after reducing the process, and improves the process controllability; on the basis of eliminating the post-etch treatment process, the present invention changes the original inert gas Ar into a CO / N2 combination gas in the de-electrification process (Dechuck), starts the radio frequency power supply during the de-electrification process, and dissociates the CO / N2 combination gas into plasma gas. Surprisingly, the plasma gas can react with each other while eliminating the charge on the surface of the wafer to generate a stable isolation protective layer, which removes the residual polymer (C x F y polymer) isolation cover to avoid residual polymer (C x F ypolymer) reacts with water vapor to produce titanium fluoride residues that are difficult to remove in a subsequent wet cleaning process; unexpectedly, due to the good isolation protection effect of the isolation protection layer of the present invention, during the transfer process of the wafer transfer box, the wafer transfer box of the present invention does not need high-purity nitrogen protection, and the maximum waiting time of the wafers in the wafer transfer box of the present invention is also extended from 4 hours in the prior art to 24 hours, which greatly improves the flexibility of the subsequent process and the yield of the semiconductor structure finally obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a flow chart of a method for preventing defects in an integrated etching process in Example 1 of the present invention.

[0022] Figure 2 This is a flow chart of the method for preparing the metal interconnect structure in Example 2 of the present invention.

[0023] Figure 3 Schematic diagram of a target wafer provided in step S210 of embodiment 2 of the present invention.

[0024] Figure 4 This is a schematic diagram of manufacturing a multilayer film structure in step S220 of Example 2 of the present invention.

[0025] Figure 5 This is a schematic diagram of completing the groove definition during the integrated etching in step S230 of embodiment 2 of the present invention.

[0026] Figure 6 This is a schematic diagram of completing the trench morphology etching during the integrated etching in step S230 of embodiment 2 of the present invention.

[0027] Figure 7 This is a schematic diagram of completing the through hole definition during the integrated etching in step S230 of embodiment 2 of the present invention.

[0028] Figure 8 This is a schematic diagram of making notches in a multi-layer film structure using an integrated etching process in step S230 of embodiment 2 of the present invention.

[0029] Fig. 9 This is a schematic diagram of generating an isolation protection layer in the static elimination process in step S240 of embodiment 2 of the present invention.

[0030] Fig.10 It is a schematic diagram of depositing a metal layer in the notch in step S270 of embodiment 2 of the present invention.

[0031] Fig.11 This is a schematic diagram of the metal interconnect structure obtained in step S280 of Example 2 of the present invention.

[0032] Fig.12This is a schematic diagram of connecting a second metal layer on the metal interconnect structure to realize interconnection between two semiconductor structures in Embodiment 2 of the present invention.

[0033] Fig.13 Schematic diagram of optimal key parameter control of the static elimination process in Example 2 of the present invention.

[0034] Fig.14 This is a comparison diagram of the effects of Example 2 of the present invention and the prior art.

[0035] Fig.15 This is a comparison diagram of the void defect in Example 2 of the present invention and the void defect in the prior art, wherein: Fig.15 A in the middle is an electron microscope image of a metal interconnect structure with void defects in the prior art. Fig.15 B is an electron microscope image of the void defect in Example 2 of the present invention.

[0036] 100-target wafer, 110-first metal layer, 120-dielectric layer; 200-multilayer film structure, 210-first etch stop layer, 220-low-k dielectric layer, 230-second etch stop layer, 240-hard mask layer, 250-organic anti-reflective coating, 260-inorganic anti-reflective coating, 270-PR layer; 310 - residual polymer, 320 - isolation protection layer; 400 - metal layer, 410 - metal interconnect structure, 500 - semiconductor structure, 510 - second metal layer. DETAILED DESCRIPTION

[0037] The following embodiments of the present invention are described in further detail in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0038] The de-electrification process (Dechuck) is a necessary process in the wafer processing process. In order to prevent the wafer from shifting in the etching chamber and ensure the wafer processing accuracy, an electrostatic chuck (ESC) is set in the etching chamber in the prior art. The electrostatic chuck (ESC) is used to apply an electric field to adsorb and fix the wafer. When one process is completed and it is necessary to transfer to the next process, plasma gas formed by inert gas will be introduced to neutralize the surface charge of the wafer, and then a reverse voltage will be applied to the electrostatic chuck (ESC) to release the wafer clamping. The wafer is transferred to a front-opening unified pod (FrontOpening Unified Pod, Foup) by a robot or other tool. The front-opening unified pod is transferred to the next station to proceed to the next process. In the present invention, integrated etching and wet cleaning are two processes, which need to be transferred through a wafer transfer box. During the transfer process, the wafer will be exposed to water vapor in the air, and the residual polymer (C x Fy polymer) will react with water vapor, TiN (metal hard mask is generally TiN), etc. to form titanium fluoride residue (Ti x F y Residue), titanium fluoride residue covers the inner surface of the groove and through hole (collectively referred to as notch), and is removed in the subsequent wet cleaning process. The titanium fluoride residue is difficult to completely remove, thus forming defects; in addition, the wafer transfer box needs to stay for a period of time during the transfer process, and the process needs to be flexibly adjusted. However, the longer the waiting time, the greater the probability that the wafer will be exposed to water vapor in the air, and the more titanium fluoride residue will be produced, and the greater the possibility of subsequent defects. The prior art sets a limit residence time in the center of high-purity nitrogen protection, which is generally set to about 4 hours. After the waiting time exceeds 4 hours, even with high-purity nitrogen protection, more defects will be generated, thereby affecting the yield of the semiconductor structure. The present invention has carried out relevant research and development to solve the above problems, and the present invention is illustrated below.

[0039] Example 1: Figure 1 As shown, this embodiment provides a method for preventing defects in an integrated etching process, comprising the following steps: S110, forming a notch by using an integrated etching process, wherein the notch includes a through hole and a groove; S120, after etching is completed, a CO / N2 gas combination is introduced as a plasma gas in the static removal process, so that the plasma gas reacts and a stable isolation protection layer is deposited on the surface of the notch to isolate the residual polymer generated in the notch during the etching process.

[0040] In this embodiment, the object of the integrated etching process can be any interconnect structure in the prior art, and the interconnect structure at least includes a lower metal line ( Fig.12 The first metal layer 110 in the wafer is formed by an integrated etching process, generally including a through hole and a groove, and the lower metal circuit is exposed in the through hole; this embodiment removes the post-etching treatment (PET) in the prior art, and directly changes the original inert gas Ar to a CO / N2 combination gas in the de-electrification process (Dechuck). The RF power supply is started during the de-electrification process to dissociate the CO / N2 combination gas into a plasma gas. The unexpected technical effect is that the plasma gas can react with each other while eliminating the surface charge of the wafer (the original function of the inert gas) to generate a stable isolation protection layer, which removes the residual polymer (C x F y polymer) isolation cover to prevent residual polymer (C x F yThe titanium fluoride polymer reacts with water vapor to produce titanium fluoride residues that are difficult to remove in the subsequent wet cleaning process. Since the isolation protection layer of the present invention has a good isolation protection effect, the wafer transfer box of the present invention does not need high-purity nitrogen protection during the transfer process of the wafer transfer box, and the maximum waiting time of the wafer in the wafer transfer box of the present invention is also extended from 4 hours in the prior art to 24 hours, which greatly improves the flexibility of the subsequent process and the yield of the final semiconductor structure.

[0041] In this embodiment, the reaction formula for generating a stable isolation protection layer is as follows:

[0042] In addition, in the process of powering on (starting the RF power supply), the electrostatic chuck needs to maintain a positive voltage all the time, so that under the action of static electricity, the plasma gas is highly close to the surface of the notch, and the polymer carbon nitride generated in a short time is efficiently gathered on the surface of the notch, forming a residual polymer (C x F y The invention provides a thin layer of isolation (which can be removed by a subsequent wet cleaning process) covering the polymer, which does not affect the normal de-electrification process (Dechuck), and avoids the damage to the stable polymer in the prior art CN106206422A caused by the inert gas (especially Ar) in the normal de-electrification process, thus achieving multiple goals at one stroke. Therefore, under the same conditions, the interconnection structure obtained by the invention has fewer defects than the prior art CN106206422A.

[0043] Example 2: Figure 2 As shown, the present invention provides a method for preparing a metal interconnect structure, comprising the following steps: S210, providing a target wafer 100 having a first metal layer 110, wherein the first metal layer 110 is a metal line on the target wafer 100, which is isolated by a dielectric layer 120, such as Figure 3 As shown; S220, fabricating a multilayer film structure 200 on the first metal layer 110, wherein the multilayer film structure 200 includes a first etch stop layer 210, a low-k dielectric layer 220, a second etch stop layer 230, and a hard mask layer 240, which are fabricated in sequence on the first metal layer 110. Figure 4 As shown; S230, such as Figures 5 to 8 As shown, an integrated etching process is used to make a notch in the multilayer film structure 200 to expose the first metal layer 110. The notch includes a groove and a through hole. The through hole is used to connect the first metal layer 110. The groove is a wire groove connected to the through hole. Figure 8 As shown, the prepared notch has residual polymer 310; S240, after the etching is completed, a CO / N2 gas combination is introduced as a plasma gas in the de-electrification process, so that the plasma gas reacts and a stable isolation protection layer 320 is deposited on the surface of the notch to isolate the residual polymer 310 generated in the notch during the etching process. Fig. 9 As shown; S250, after the charge removal is completed, lift up the target wafer 100 and transfer it to a wafer box; S260, transferring the wafers in the wafer box to a wet cleaning process to remove the stable isolation protection layer 320 and the residual polymer 310; S270, depositing a metal layer 400 in the notch, such as Fig.10 As shown; S280, using CMP process to remove the redundant metal layer 400 and the multilayer film structure 200, and completing the manufacture of the metal interconnection structure 410, such as Fig.11 shown.

[0044] A second metal layer 510 may be formed on the metal interconnection structure 410 or the semiconductor structure 500 having the second metal layer 510 may be bonded to the metal interconnection structure 410 to interconnect the two semiconductor structures. Fig.12 shown.

[0045] The metal interconnect structure is prepared by the method of this embodiment, and the post-etching treatment (PET) process is omitted. In the de-electrification process (Dechuck), the plasma gas that can react to generate a stable polymer is directly used to replace the original inert gas, and the residual polymer (C x F y The isolation protection layer 320 is used to isolate the polymer from the external environment, thereby avoiding residual polymer (C x F y The contact between the wafer and the water vapor can convert the titanium fluoride residue which is difficult to clean by wet cleaning. This eliminates the need for high-purity nitrogen protection during subsequent transfer through the wafer box, reducing costs and process complexity. At the same time, the maximum waiting time of the wafer in the wafer transfer box is extended to about 24 hours, which greatly improves process flexibility, reduces the probability of voids in the metal layer of the metal interconnect structure, and improves the yield of the semiconductor structure.

[0046] In step S210, Figure 3 As shown, the target wafer 100 provided in this embodiment has been prepared with the required semiconductor structure, and a first metal layer 110 is reserved on the upper surface for metal interconnection. Generally, the gaps between the first metal layer 110 are filled with a dielectric layer, which is an insulating material such as silicon dioxide.

[0047] The first etch stop layer 210 can be a common etch stop layer material in the prior art, including but not limited to nitride-doped silicon carbide and silicon nitride; in this embodiment, it is preferably a nitride-doped silicon carbide (nitride doped silicon carbide, NDC) layer; the low-k dielectric layer 220 is a low dielectric constant material layer, which can be made of silicon dioxide (SiO2) or BD layer. The BD (Black Diamond) layer is a low dielectric constant material based on chemical vapor deposition carbon-doped silicon oxide launched by Applied Materials (AMAT), and its electrical constant k=2.7; the second etch stop layer can be a common etch stop layer material in the prior art, including but not limited to tetraethyl orthosilicate layer, silicon dioxide, silicon nitride, and in this embodiment, tetraethyl orthosilicate (TEOS) is preferably used; the hard mask layer 240 plays a mask role, and the hard mask layer 240 generally uses a titanium nitride (TiN) layer.

[0048] In step S230, in order to improve the quality and efficiency of integrated etching, before integrated etching, an anti-reflection coating (ARC) is first coated on the hard mask layer 240, and a photoresist (PR) is coated to form a PR layer 270; Figure 5 As shown, the anti-reflection coating in this embodiment is a two-layer structure, which includes an organic anti-reflection coating 250 and an inorganic anti-reflection coating 260 from bottom to top. The organic anti-reflection coating 250 is a common bottom anti-reflection coating (BARC) in the prior art, and its main components are a cross-linkable resin, a thermal acid generator, a surfactant and a solvent; the inorganic anti-reflection coating 260 is silicon oxynitride (SiON), and the inorganic anti-reflection coating 260 mainly serves as a barrier layer in AIO etching to reduce bombardment damage to the hard mask layer 240 (TIN).

[0049] In step S230, during the integrated etching, a photolithography (exposure and development) is first performed to complete the trench definition, such as Figure 5 Then the hard mask layer 240 is etched, and the inorganic anti-reflective coating 260 and the organic anti-reflective coating 250 are sequentially stopped on the second etch stop layer 230 (tetraethyl orthosilicate (TEOS) layer) to complete the trench morphology etching, as shown Figure 6 As shown; then the secondary lithography (exposure, development) is performed to complete the definition of the through hole (via), as shown Figure 7As shown; then, a dry etching process is used to complete the etching of the trench and the via at one time. This step is completed in the same etching chamber, so it is called All in One (AIO). After the etching is completed, the first metal layer 110 is exposed at the bottom of the via. The trench and the via are collectively referred to as notches. Due to the etching process, residual polymers containing carbon and fluorine elements (C x F y polymer), residual polymer (C x F y polymer) mainly accumulates on the inner surface of the groove, such as Figure 8 As shown, these residual polymers (C x F y If the titanium fluoride polymer is not removed or isolated and covered, it will be exposed to water vapor and air during the subsequent wafer transfer process, and react with water vapor to generate titanium fluoride residues (residual particles) that are difficult to remove by subsequent wet cleaning.

[0050] In S240, after the etching is completed, the static elimination process includes the following three stages: In the first stage, the conditions for removing static electricity are prepared. After the etching is completed, a CO / N2 gas combination is introduced into the etching chamber and maintained for a period of time after reaching the first pressure; The second stage: maintaining the first pressure, starting the RF power supply for ignition, dissociating the CO / N2 gas combination into plasma gas, and under the interaction of ions, the plasma gas reacts quickly on the notch surface to form a stable isolation protection layer 320; Phase 3: Reverse voltage is applied to the electrostatic chuck to release the wafer clamp and the RF power is turned off.

[0051] In the first stage, the first pressure is 100mT-400mT. For example, a more suitable pressure is 250mT. After reaching the first pressure, the maintenance time T1 is 4-20s, and a suitable time is 8s. During the pressure maintenance process, CO / N2 combined gas is continuously introduced for purging and replacement. The longer the maintenance time T1 after the first pressure, the better the purging and replacement effect. Residual gas and some impurities can be removed by purging and replacement, but the time is too long, resulting in low energy efficiency.

[0052] In the second stage, the RF power supply power is set to 250-450W as the starting power. The greater the power supply power, the higher the gas dissociation degree, and the easier it is to form an isolation protective layer 320 to isolate water vapor. 250W is the lowest effective power verified by the production line. When it is lower than 250W, the obtained isolation protective layer 320 cannot produce an effective isolation effect. Of course, if the power supply power is too high, it will be limited by the total power of the equipment on the one hand, and the energy consumption will be high on the other hand, resulting in a large waste of energy. Therefore, a suitable power supply power is 350W.

[0053] In the second stage, the maintenance time after ignition determines the thickness of the isolation protection layer 320. If the maintenance time is too short, the generated isolation film cannot fully cover or the thickness is too small, and it cannot play an effective isolation role; if the maintenance time is too long, the thickness of the generated isolation film is too large, which makes it difficult to remove it in the subsequent wet cleaning process and causes waste of raw materials; therefore, the maintenance time T2 for starting the power supply to generate plasma gas is generally 2-8s. For example, a suitable time is 3s.

[0054] In the second stage, during the ignition process, the CO / N2 gas combination needs to be continuously introduced, and the flow ratio of CO gas and N2 gas in the CO / N2 gas combination has a great influence on the quality of the produced isolation protective layer 320; theoretically, the higher the CO gas ratio, the better the quality of the produced isolation protective layer 320, and the better the isolation effect, but too high a ratio will affect the static removal process; therefore, the appropriate N2 / CO ratio is 2:1-5:1 (molar ratio or volume flow ratio under the same pressure), and the optimal ratio is 3:1.

[0055] In the second stage, during the ignition process, if the CO gas flow rate is too small, the isolation protection film cannot be effectively generated. If the flow rate is too large, it will cause waste of raw materials and energy. Therefore, the CO gas flow rate must be no less than 100sccm (standard cubic centimeters per minute) to generate an effective isolation protection film. Generally speaking, a CO gas flow rate in the range of 100-250sccm is more appropriate.

[0056] In the second stage, the pressure and flow rate of the CO / N2 combination gas must be kept stable, and as in the first stage, stable flow rate and pressure can ensure a high-quality isolation layer.

[0057] In the third stage, when a reverse voltage is applied to the electrostatic chuck, there is generally no special requirement for the magnitude of the applied reverse voltage. For example, during adsorption, when the forward voltage is 2000V, the reverse voltage can be -100V. In addition, the applied reverse voltage needs to be maintained for a short time T3 to fully release the charge on the wafer so that it can be smoothly detached from the electrostatic chuck. This short time is generally 0.5-4s. For example, 1s is generally used.

[0058] A schematic diagram of a better key parameter control in the above-mentioned static elimination process is as follows: Fig.13 As shown, the interconnect structure is prepared by controlling the parameters, and the void defect count is performed after waiting in the wafer box for 24 hours (without high-purity nitrogen protection). The results are compared with the conventional post-etch treatment (PET) in the prior art and CN106206422A. Fig.14 As shown, Fig.14 The POR experimental conditions are: PET process removes the residual polymer containing fluorine in the integrated etching process (C x F y polymer); The experimental conditions of EXP are: PET process removes the residual polymer containing fluorine by integrated etching (C x F y polymer) and generate a layer of relatively stable polymer to isolate the residual polymer, that is, the technical solution conditions recorded in CN106206422A.

[0059] The CIP experimental conditions are as follows: the present invention removes charges and generates a protective film in a dechuck process. In the dechuck process, a CO / N2 gas combination is introduced as a plasma gas to allow the plasma gas to react and deposit a stable isolation protective layer 320 on the surface of the notch to isolate air and water vapor.

[0060] pass Fig.14 It can be seen that after 24 hours of waiting, the interconnection structure using only post-etch treatment (PET) in the prior art is all invalid voids and cannot be used; using the solution in the prior art CN106206422A, there are 13 invalid voids, which affect the yield. The microstructure of the invalid void defect is shown in the figure below. Fig.15 As shown in A, it can be seen that there is a void defect in the circuit at about the middle position, which affects the electrical performance of the circuit; the technical solution of the present invention has no defects and the yield is 100%. Fig.15 As shown in B, it can be seen that the edge of the interconnect structure is clear and has no defects; the present invention not only has a better yield than the prior art CN106206422A, but also saves the post-etch treatment (PET) process, greatly reducing the cost.

[0061] In step S250, the target wafer 100 does not need high-purity nitrogen protection in the wafer box, and the waiting limit time can reach about 24 hours, which is much longer than 4 hours in the prior art.

[0062] In step S260, the target wafer 100 is immersed or spray cleaned in a liquid cleaning agent to remove pollutants on the chip surface through chemical reaction and physical action. Common wet cleaning processes include immersion cleaning, spray cleaning and ultrasonic cleaning.

[0063] In step S270 , a Cu layer of a certain thickness is grown in the through hole and the trench by using an electrochemical copper plating process (Cu ECP) ​​as an interconnection layer metal.

[0064] In step S280, a CMP process is used to remove the redundant Cu layer, the tetraethyl orthosilicate layer 230, and the hard mask layer 240, remaining at the low-k dielectric layer 220, to obtain a metal interconnect structure 410. A second metal layer 510 can be fabricated on the metal interconnect structure 410, or the second metal layer 510 and the metal interconnect structure 410 can be bonded to realize the interconnection of subsequent semiconductor processes.

[0065] The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Although the present invention is described in detail with reference to the embodiments, it should be understood by those skilled in the art that various combinations, modifications or equivalent substitutions of the technical solutions of the present invention do not depart from the spirit and scope of the technical solutions of the present invention, and should be included in the scope of the claims of the present invention.

Claims

1. A method for preventing defects in an integrated etching process, characterized in that: The following steps are involved: The notch is formed by using an integrated etching process; After etching is completed, a CO / N2 gas combination is introduced as a plasma gas in the static removal process to allow the plasma gas to react and deposit a stable isolation protection layer on the surface of the notch to isolate the residual polymer generated in the notch during the etching process.

2. The method for preventing defects in an integrated etching process according to claim 1, characterized in that: The static elimination process includes the following three stages: In the first stage, the conditions for removing static electricity are prepared. After the etching is completed, a CO / N2 gas combination is introduced into the etching chamber and maintained for a period of time after reaching the first pressure; The second stage: maintain the first pressure, start the RF power supply, dissociate the CO / N2 gas combination into plasma gas, and under the interaction of ions, the plasma gas reacts quickly at the notch and surface to form a stable isolation protective layer; Stage 3: Apply reverse voltage to the electrostatic chuck to release the wafer.

3. The method for preventing defects in an integrated etching process according to claim 2, characterized in that: In the first stage, the first pressure is 100mT-400mT, and the maintenance time after reaching the first pressure is 4-20s. During the pressure maintenance process, CO / N2 combined gas is continuously introduced for purging and replacement.

4. The method for preventing defects in an integrated etching process according to claim 2, characterized in that: In the second stage, the pressure of the first stage is maintained, the RF energy is set to 100-400W, the second stage is maintained for 2-8s, and the plasma gas is kept continuously present.

5. The method for preventing defects in an integrated etching process according to claim 2, characterized in that: The third stage lasts for 0.5-4s and the plasma gas is kept continuously present.

6. A method for preparing a metal interconnect structure, characterized in that: The following steps are involved: Providing a target wafer having a first metal layer, wherein the first metal layer is a metal circuit on the target wafer; fabricating a multilayer film structure on the first metal layer; Using an integrated etching process to form a notch in the multi-layer film structure to expose the first metal layer; After etching is completed, a CO / N2 gas combination is introduced as a plasma gas in the de-electrification process, so that the plasma gas reacts and a stable isolation protection layer is deposited on the surface of the notch to isolate the residual polymer generated in the notch during the etching process; After the charge removal is completed, the wafer is lifted up and transferred to the wafer box; Transferring the wafers in the wafer box to a wet cleaning process to remove the stable isolation protective layer and residual polymer; depositing a metal layer within the notch; The CMP process is used to remove the redundant metal layers and multi-layer film structures to complete the production of the metal interconnection structure.

7. The method for preparing a metal interconnect structure according to claim 6, characterized in that: The multi-layer film structure comprises a first etch stop layer, a low-k dielectric layer, a second etch stop layer and a hard mask layer which are sequentially formed on a first metal layer.

8. The method for preparing a metal interconnect structure according to claim 7, characterized in that: During integrated etching, the hard mask layer is coated with an anti-reflection coating.

9. The method for preparing a metal interconnect structure according to claim 6, characterized in that: The static elimination process includes the following three stages: In the first stage, the conditions for removing static electricity are prepared. After the etching is completed, a CO / N2 gas combination is introduced into the etching chamber and maintained for a period of time after reaching the first pressure; The second stage: maintaining the first pressure, starting the RF power supply, dissociating the CO / N2 gas combination into plasma gas. Under the interaction of ions, the plasma gas reacts quickly on the notch surface to form a stable isolation protective layer. Stage 3: Apply reverse voltage to the electrostatic chuck to release the wafer.

10. The method for preparing a metal interconnect structure according to claim 6, characterized in that: At least in the second stage, in the CO / N2 combined gas, the flow ratio of N2 gas to CO gas is 2:1-5:1.

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