Main control module of battery management system

Abstract

The invention discloses a main control module of a battery management system, a module external interface circuit is an interface between the main control module of the battery management system and external equipment, and the main control module of the battery management system outputs a driving signal to the external equipment through the module external interface circuit. External equipment inputs a signal to the module through a module external interface circuit, and meanwhile, the battery management system master control module communicates with the external equipment through a CAN interface; the power supply circuit is used for converting a 24V power supply signal in the slave module external interface circuit into a 5V power supply signal required by the module; the switching value acquisition circuit is used for filtering, isolating and converting a 24V switching value signal in the module external interface circuit into a 5V switching value signal and inputting the 5V switching value signal to the singlechip circuit; the analog quantity acquisition circuit is used for carrying out filtering and voltage division processing on an analog quantity signal in the slave module external interface circuit to obtain a 0-4V voltage signal and inputting the 0-4V voltage signal to the singlechip circuit; the CAN interface circuit completes physical conversion of CAN bus signals between the single-chip microcomputer and the external environment. The single-chip microcomputer circuit analyzes and processes the switching value signal, the analog quantity signal and the CAN bus signal, then outputs a control signal to the drive circuit, and outputs the CAN bus signal to an external device. The main control module is high in hardware integration level and low in total hardware cost.

Description

Technical Field

[0001] The present invention relates to battery management, and in particular to a main control module design of a battery management system. Background Art

[0002] Power battery systems with larger capacities will adopt a multi-branch battery subsystem parallel mode, and the battery management system main control unit usually adopts a hierarchical design, namely: each branch has a first-level master control, which is responsible for collecting and processing the single cell battery information sent by each branch slave control module; the first-level master control then forwards the information to the second-level master control. The entire system has a second-level master control, which is responsible for collecting the total voltage, total current, insulation resistance and other information of the battery system, controlling the contactor status, fault judgment and processing, and communicating with the vehicle controller and charger to complete the charging and discharging management of the entire battery system.

[0003] This design has the following disadvantages:

[0004] A. The number of master control modules is large, and the total hardware cost is high;

[0005] B. There are many software in the main control module, and the software maintenance cost is high;

[0006] C. There are many main control modules, the total working power consumption is high, the total installation space is large, and the total weight is large. Summary of the invention

[0007] The purpose of the present invention is to provide a main control module of a battery management system.

[0008] The technical solution to achieve the purpose of the present invention is: a battery management system main control module, including: module external interface circuit, power supply circuit, single-chip circuit, CAN interface circuit, switch quantity acquisition circuit, analog quantity acquisition circuit and drive circuit, wherein:

[0009] The module external interface circuit is the interface between the main control module of the battery management system and the external device. The main control module of the battery management system outputs the driving signal to the external device through the module external interface circuit, and the external device inputs the signal to the module through the module external interface circuit. At the same time, the main control module of the battery management system and the external device communicate through the CAN interface;

[0010] The power circuit converts the 24V power signal from the module's external interface circuit into the 5V power signal required by the module;

[0011] The switch quantity acquisition circuit filters and isolates the 24V switch quantity signal in the module's external interface circuit and converts it into a 5V switch quantity signal, which is then input to the single-chip microcomputer circuit.

[0012] The analog quantity acquisition circuit filters and divides the analog quantity signal from the external interface circuit of the module into a voltage signal of 0 to 4V and inputs it to the single-chip microcomputer circuit;

[0013] The CAN interface circuit completes the physical conversion of CAN bus signals between the microcontroller and the external environment;

[0014] The single-chip microcomputer circuit analyzes and processes the switch signal, analog signal and CAN bus signal, and then outputs the control signal to the drive circuit and outputs the CAN bus signal to the external device.

[0015] Furthermore, in the external interface circuit of the module, a 1318384-240 core connector is used for the external connector JP1;

[0016] Connect pins 1 and 2 of the external connector JP1 to the positive electrode network BAT+ of the diode D1 of the power circuit;

[0017] Pins 21, 22, 33, 34, 35, 36 and 37 of the external connector JP1 are connected to pin 4 of the inductor L1 of the power circuit and the network DGND;

[0018] Connect pin 3 of external connector JP1 to pin 2 of inductor L11_0 of CAN interface circuit and network CANH0;

[0019] Connect pin 4 of external connector JP1 to pin 1 of inductor L11_0 of CAN interface circuit and network CANL0;

[0020] Connect pin 23 of external connector JP1 to the network 0S of the CAN interface circuit;

[0021] Connect pin 5 of external connector JP1 to pin 2 of inductor L11_1 of CAN interface circuit and network CANH1;

[0022] Connect pin 6 of external connector JP1 to pin 1 of inductor L11_1 of CAN interface circuit and network CANL1;

[0023] Connect pin 24 of external connector JP1 to network 1S of CAN interface circuit;

[0024] Connect the 25th pin of the external connector JP1 to the 2nd pin of the inductor L11_2 of the CAN interface circuit and the network CANH2;

[0025] Connect the 26th pin of the external connector JP1 to the 1st pin of the inductor L11_2 of the CAN interface circuit and the network CANL2;

[0026] Connect pin 27 of external connector JP1 to network 2S of CAN interface circuit;

[0027] Connect pin 7 of external connector JP1 to pin 2 of inductor L11_3 of CAN interface circuit and network CANH3;

[0028] Connect the 8th pin of the external connector JP1 to the 1st pin of the inductor L11_3 of the CAN interface circuit and the network CANL3;

[0029] Connect pin 28 of external connector JP1 to network 3S of CAN interface circuit;

[0030] Connect pin 9 of external connector JP1 to pin 2 of inductor L11_4 of CAN interface circuit and network CANH4;

[0031] Connect the 10th pin of the external connector JP1 to the 1st pin of the inductor L11_4 of the CAN interface circuit and the network CANL4;

[0032] Connect pin 29 of external connector JP1 to network 4S of CAN interface circuit;

[0033] Connect the 11th pin of the external connector JP1 to the 2nd pin of the inductor L11_5 of the CAN interface circuit and the network CANH5;

[0034] Connect the 12th pin of the external connector JP1 to the 1st pin of the inductor L11_5 of the CAN interface circuit and the network CANL5;

[0035] Connect pin 30 of external connector JP1 to network 5S of CAN interface circuit;

[0036] The 13-pin network DOH1, 14-pin network DOH2, 15-pin network DOH3, and 16-pin network DOH4 of the external connector JP1 are respectively connected to the 18-pin network DOH1, 17-pin network DOH2, 14-pin network DOH3, and 13-pin network DOH4 of the chip U4 in the drive circuit;

[0037] The 17-pin network DOH5, 18-pin network DOH6 and 19-pin network DOH7 of the external connector JP1 are respectively connected to the 18-pin network DOH5, 17-pin network DOH6 and 14-pin network DOH7 of the chip U5 in the drive circuit;

[0038] Connect the 31-pin network ON of the external connector JP1 to the 1-pin network ON of the capacitor C20 of the switch quantity acquisition circuit;

[0039] Connect the 32-pin network A+ of the external connector JP1 to the 1-pin network A+ of the capacitor C21 of the switch quantity acquisition circuit;

[0040] Connect the 20-pin network AI1 of the external connector JP1 to the 1-pin network AI1 of the capacitor C22 of the analog acquisition circuit;

[0041] Connect the 40-pin network AI2 of the external connector JP1 to the 1-pin network AI2 of the capacitor C26 of the analog acquisition circuit;

[0042] Connect the 38-pin network AGND of the external connector JP1 to the network AGND of the power circuit;

[0043] Connect the 39-pin network A5V of the external connector JP1 to the network A5V of the power circuit.

[0044] Further, the power supply circuit includes a diode D1, a diode D2, a diode D3, a diode D4, a diode D18, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, an inductor L1, an inductor L2, a magnetic bead L3, an inductor L5, a magnetic bead L6, a magnetic bead L7, a magnetic bead L8, a magnetic bead L9, a magnetic bead L10, a magnetic bead L12, a resistor R1, a resistor R2, a resistor R50, a resistor R51, and a chip U3, wherein:

[0045] The chip U3 model is LN5016PHMR-G, the positive pole of the diode D1 is connected to the network BAT+, the negative pole of the diode D1 is connected to the negative pole of the diode D2, the output network P101 signal is used to power the drive circuit, the capacitor C1 is connected in parallel with the diode D2, the pin 1 of the inductor L1 is connected to the network P101; the capacitor C2 is connected between the pins 2 and 3 of the inductor L1, the pin 2 of the inductor L1 is connected to the pin 1 of the inductor L2, the pin 2 of the inductor L2 is connected to the pin 5 of the chip U3, the pin 4 of the inductor L1 is connected to the network DGND, the pin 3 of the inductor L1 is connected to the network GND, the pin 1 of the capacitor C3 is connected to the pin 5 of the chip U3, the capacitor Pin 2 of C3 is connected to network GND, pin 1 of capacitor C4 is connected to pin 5 of chip U3, pin 2 of capacitor C4 is connected to network GND, pin 1 of capacitor C5 is connected to pin 1 of chip U3, pin 2 of capacitor C5 is connected to pin 6 of chip U3, pin 1 of inductor L5 is connected to pin 6 of chip U3, pin 2 of inductor L5 is connected to network +5V, pin 1 of resistor R51 is connected to pin 3 of chip U3, pin 2 of resistor R51 is connected to pin 2 of chip U3 network GND, the positive pole of capacitor C6 is connected to network +5V, the negative pole of capacitor C6 is connected to network GND, pin 1 of capacitor C7 is connected to network +5V, and pin 2 of capacitor C7 is connected to network GND , Pin 1 of resistor R50 is connected to pin 3 of U3, Pin 2 of resistor R50 is connected to network +5V, Pin 1 of magnetic bead L6 is connected to network +5V, Pin 2 of magnetic bead L6 is connected to network +5V-B1, Pin 1 of magnetic bead L7 is connected to network +5V, Pin 2 of magnetic bead L7 is connected to network +5V-B2, Pin 1 of magnetic bead L8 is connected to network +5V, Pin 2 of magnetic bead L8 is connected to network VCC, Pin 1 of magnetic bead L9 is connected to network +5V, Pin 2 of magnetic bead L9 is connected to network A5V, Pin 1 of magnetic bead L10 is connected to network GND, Pin 2 of magnetic bead L10 is connected to network AGND, Pin 31 of external connector JP1 is connected to magnetic bead L3 Pin 1, pin 2 of magnetic bead L3 is connected to the positive electrode of diode D3, the negative electrode of diode D3 is connected to pin 1 of resistor R1, pin 2 of resistor R1 is connected to pin 1 of resistor R2, pin 2 of resistor R2 is connected to network GND, capacitor C8 is connected in parallel with resistor R2, pin 1 of resistor R2 is connected to pin 4 of U3, the negative electrode of diode D4 is connected to pin 4 of U3, the positive electrode of diode D4 is connected to pin 88 of microcontroller U1A, network BMU_LOCK, pin 32 of external connector JP1 is connected to pin 1 of magnetic bead L12, pin 2 of magnetic bead L12 is connected to the positive electrode of diode D18, and the negative electrode of diode D18 is connected to pin 1 of resistor R1.

[0046] Further, the single chip microcomputer circuit includes chip U1, chip U2, chip U8, internal connector J1, crystal oscillator Y1, capacitor C37, capacitor C38, capacitor C39, capacitor C40, capacitor C41, capacitor C42, capacitor C43, capacitor C44, capacitor C45, capacitor C46, ​​capacitor C47, capacitor C48, capacitor C49, capacitor C50, capacitor C51, capacitor C52, resistor R37, resistor R38, resistor R39, resistor R40, resistor R41, resistor R42, resistor R43, diode D17, wherein:

[0047] Chip U1 and chip U2 are 32-bit Arm Cortex-M4F processors FS32K144HFT0MLLT with a main frequency of up to 112MHz; chip U8 uses LM4040BIM-4.1; internal connector J1 uses DC3-2.54-10PAS;

[0048] Pin 1 of chip U1 is connected to pin 100 of chip U2, pin 2 of chip U1 is connected to pin 2 of chip U2, pin 99 of chip U1 is connected to pin 99 of chip U2, and pin 100 of chip U1 is connected to pin 1 of chip U2;

[0049] Pin 8 of chip U1 is connected to pin 5 of CAN interface circuit U9_0, pin 9 of chip U1 is connected to pin 4 of CAN interface circuit chip U9_0, pin 89 of chip U1 is connected to pin 5 of CAN interface circuit chip U9_1, pin 90 of chip U1 is connected to pin 4 of CAN interface circuit chip U9_1, pin 43 of chip U1 is connected to pin 5 of CAN interface circuit chip U9_2, and pin 44 of chip U1 is connected to pin 4 of CAN interface circuit chip U9_2;

[0050] Pin 8 of chip U2 is connected to pin 5 of CAN interface circuit chip U9_3, pin 9 of chip U2 is connected to pin 4 of CAN interface circuit chip U9_3, pin 89 of chip U2 is connected to pin 5 of CAN interface circuit chip U9_4, pin 90 of chip U2 is connected to pin 4 of CAN interface circuit chip U9_4, pin 43 of chip U2 is connected to pin 5 of CAN interface circuit chip U9_5, and pin 44 of chip U2 is connected to pin 4 of CAN interface circuit chip U9_5;

[0051] Pin 62 of chip U1 is connected to pin 3 of drive output circuit chip U4, pin 59 of chip U1 is connected to pin 5 of drive output circuit chip U4, pin 58 of chip U1 is connected to pin 7 of drive output circuit chip U4, pin 57 of chip U1 is connected to pin 9 of drive output circuit chip U4, pin 62 of chip U2 is connected to pin 3 of drive output circuit chip U5, pin 59 of chip U2 is connected to pin 5 of drive output circuit chip U5, and pin 58 of chip U2 is connected to pin 7 of drive output circuit chip U5;

[0052] Pin 45 of chip U1 is connected to pin 1 of resistor R29 of analog quantity acquisition circuit, network AI_HALL1; pin 46 of chip U1 is connected to pin 1 of resistor R33 of analog quantity acquisition circuit, network AI_HALL2;

[0053] Pin 82 of chip U1 is connected to pin 1 network CHK1 of resistor R3 of the switch quantity acquisition circuit, and pin 83 of chip U1 is connected to pin 1 network CHK2 of resistor R4 of the switch quantity acquisition circuit;

[0054] Pin 15 of chip U1 is connected to pin 3 of crystal oscillator Y1, pin 16 of chip U1 is connected to pin 1 of crystal oscillator Y1, resistor R38 is connected in parallel between pins 15 and 16 of chip U1, pin 1 of capacitor C38 is connected to pin 3 of crystal oscillator Y1, pin 2 of capacitor C38 is connected to pin 4 of crystal oscillator Y1 and network GND, pin 1 of capacitor C37 is connected to pin 1 of crystal oscillator Y1, pin 2 of capacitor C37 is connected to network GND, pin 97 of chip U1 is connected to pin 1 of capacitor C52, pin 2 of capacitor C52 is connected to network GND, pin 97 of chip U1 is connected to network +5V-B1 through resistor R39, the cathode of diode D17 is connected to network +5V-B1, and the anode of diode D17 is connected to pin 97 of chip U1;

[0055] Pin 1 and Pin 2 of the internal connector J1 are connected to the network +5V-B1, Pin 3 and Pin 4 of the internal connector J1 are connected to Pin 97 of the chip U1, Pin 5 of the internal connector J1 is connected to Pin 95 of the chip U1, Pin 6 of the internal connector J1 is connected to Pin 92 of the chip U1, Pin 7 of the internal connector J1 is connected to Pin 98 of the chip U1, Pin 9 of the internal connector J1 is connected to Pin 96 of the chip U1, Pin 8 and Pin 10 of the internal connector J1 are connected to the network GND, Pin 95 of the chip U1 is connected to the network +5V-B1 through resistor R40, and Pin 92 of the chip U1 is connected to the network +5V-B1 through resistor R41;

[0056] The 98th pin of chip U1 is connected to the network +5V-B1 through resistor R42, and the 96th pin of chip U1 is connected to the network GND through resistor R43.

[0057] Pin 11 of chip U1 is connected to network A5V, pin 13 of chip U1 is connected to network AGND, capacitor C40 of capacitor C39 is connected in parallel between pins 11 and 13 of chip U1;

[0058] The 38th, 61st, 87th and 10th pins of chip U1 are connected to the network +5V-B1, and the 37th, 60th, 86th and 14th pins of chip U1 are connected to the network GND. Capacitors C41 and C42 are connected in parallel between the 38th and 37th pins of chip U1, capacitors C43 and C44 are connected in parallel between the 61st and 60th pins of chip U1, capacitors C45 and C46 are connected in parallel between the 87th and 86th pins of chip U1, and capacitors C47 and C48 are connected in parallel between the 10th and 14th pins of chip U1;

[0059] Capacitors C49, C50 and C51 are connected in parallel between pins 12 and 13 of chip U1. Pin 12 of chip U1 is pulled up to network A5V through resistor R37. Pin 1 of chip U8 is connected to pin 12 of chip U1, and pin 2 of chip U8 is connected to network AGND of pin 13 of chip U1.

[0060] The peripheral circuit of part B of chip U2 has the same principles as part B of chip U1 except that the power supply is changed from +5V-B1 to +5V-B2.

[0061] Further, the CAN interface circuit is composed of 6 identical circuits, including chip U9_m, capacitor C29_m, capacitor C30_m, capacitor C31_m, capacitor C32_m, capacitor C33_m, capacitor C34_m, capacitor C35_m, capacitor C36_m, resistor R34_m, resistor R35_m, resistor R36_m, inductor L11_m, diode D16_m, m=0,1,2,3,4,5;

[0062] Chip U9_m uses CAN isolation chip TDH541SCANH with isolated DCDC. Pins 1, 3, 7, 9, and 10 of chip U9_0 are connected to network GND, pins 6 and 8 of chip U9_0 are connected to network VCC, capacitors C29_0 and C30_0 are connected in parallel between pins 8 and 10 of chip U9_0, pins 11, 13, 16, 18, and 20 of chip U9_0 are connected to network CAN_GND0, pins 12 and 19 of chip U9_0 are connected to network CAN_5V0, capacitor C31_0 is connected between pins 20 and 19 of chip U9_0, capacitor C32_0 is connected between pins 13 and 12 of chip U9_0, resistor R34_0 and capacitor C One end of 33_0 is connected in parallel to the network CAN_GND0, and the other end is connected to the network 0S, pin 1 of capacitor C34_0 is connected to pin 1 of L11_0, pin 2 of capacitor C34_0 is connected to the network 0S, pin 3 of diode D16_0 is connected to 0S, pin 1 of diode D16_0 is connected to pin 1 of L11_0, pin 2 of diode D16_0 is connected to pin 2 of L11_0, pin 1 of capacitor C35_0 is connected to pin 2 of L11_0, pin 2 of capacitor C35_0 is connected to the network 0S, pin 1 of resistor R35_0 is connected to pin 2 of L11_0, pin 2 of resistor R35_0 is connected to pin 1 of capacitor C36_0, pin 1 of resistor R36_0 is connected to pin 1 of L11_0, pin 2 of resistor R36_0 is connected to pin 1 of capacitor C36_0, and pin 2 of capacitor C36_0 is connected to the network 0S.

[0063] Further, the switch quantity acquisition circuit includes resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, chip U7, chip U10, diode D5, diode D6, diode D7, diode D8, capacitor C18, capacitor C19, capacitor C20, capacitor C21, wherein:

[0064] The chip U7 uses IS3H7C, and the chip U10 uses IS3H7C;

[0065] In the external interface circuit of the module, the 31-pin network ON of the external connector JP1 is connected to the 1-pin of the capacitor C20 and the 2-pin of the resistor R11, the 2-pin of the capacitor C20 is connected to the network DGND, the 1-pin of the resistor R11 is connected to the positive electrode of the diode D7, the negative electrode of the diode D7 is connected to the 1-pin of the capacitor C18, the 1-pin of the resistor R9, the negative electrode of the diode D5 and the 2-pin of the resistor R7, the 2-pin of the capacitor C18, the 2-pin of the resistor R9 and the positive electrode of the diode D5 are connected to the 2-pin network DGND of the chip U7, the 1-pin of the resistor R7 is connected to the 1-pin of the chip U7, the 3-pin of the chip U7 is connected to the network GND, the 4-pin of the chip U7 is connected to the network +5V-B1 through the pull-up resistor R5, the 4-pin of the chip U7 is connected to the 2-pin of the resistor R3, and the 1-pin of the resistor R3 is connected to the 83-pin network CHK1 of the chip U1;

[0066] In the external interface circuit of the module, the 32-pin network A+ of the external connector JP1 is connected to the 1-pin of the capacitor C21 and the 2-pin of the resistor R12, the 2-pin of the capacitor C21 is connected to the network DGND, the 1-pin of the resistor R12 is connected to the positive electrode of the diode D8, the negative electrode of the diode D8 is connected to the 1-pin of the capacitor C19, the 1-pin of the resistor R10, the negative electrode of the diode D6 and the 2-pin of the resistor R8, the 2-pin of the capacitor C19, the 2-pin of the resistor R10 and the positive electrode of the diode D6 are connected to the 2-pin network DGND of the chip U10, the 1-pin of the resistor R8 is connected to the 1-pin of the chip U10, the 3-pin of the chip U10 is connected to the network GND, the 4-pin of the chip U10 is connected to the network +5V-B1 through the pull-up resistor R6, the 4-pin of the chip U10 is connected to the 2-pin of the resistor R4, and the 1-pin of the resistor R4 is connected to the 82-pin network CHK2 of the chip U1.

[0067] Further, the analog quantity acquisition circuit includes capacitor C22, capacitor C23, capacitor C24, capacitor C25, capacitor C26, capacitor C27, capacitor C28, resistor R26, resistor R27, resistor R28, resistor R29, resistor R30, resistor R31, resistor R32, resistor R33, and chip U6, wherein:

[0068] Chip U6 uses MCP6002T / I / SN. In the module's external interface circuit, the 20-pin network AI1 of the external connector JP1 is connected to pin 1 of capacitor C22, pin 1 of capacitor C23, and pin 1 of resistor R26. Pin 2 of capacitor C22 is connected to network DGND, pin 2 of capacitor C23 is connected to network AGND, pin 2 of resistor R26 is connected to pin 3 of chip U6, pin 1 of resistor R27 is connected to pin 3 of chip U6, pin 2 of resistor R27 is connected to network AGND, and pin 1 of capacitor C24 is connected to network DGND. Connect to pin 3 of chip U6, pin 2 of capacitor C24 to network AGND, pin 1 of resistor R28 to network AGND, pin 2 of resistor R28 to pin 2 of chip U6, pin 2 of chip U6 and pin 1 of chip U6 are short-circuited, pin 8 of chip U6 to network A5V, pin 4 of chip U6 to network AGND, pin 1 of capacitor C25 to between pin 8 of chip U6 and pin 4 of U6, pin 2 of resistor R29 to pin 1 of chip U6, and pin 1 of resistor R29 to pin 45 of chip U1;

[0069] In the external interface circuit of the module, the 40-pin network AI2 of the external connector JP1 is connected to the 1-pin of capacitor C26, the 1-pin of capacitor C27, and the 1-pin of resistor R30, the 2-pin of capacitor C26 is connected to the network DGND, the 2-pin of capacitor C27 is connected to the network AGND, the 2-pin of resistor R30 is connected to the 5-pin of chip U6, the 1-pin of resistor R31 is connected to the 5-pin of chip U6, the 2-pin of resistor R31 is connected to the network AGND, the 1-pin of capacitor C28 is connected to the 5-pin of chip U6, the 2-pin of capacitor C28 is connected to the network AGND, the 1-pin of resistor R32 is connected to the network AGND, the 2-pin of resistor R32 is connected to the 6-pin of chip U6, the 6-pin of chip U6 is short-circuited with the 7-pin of chip U6, the 2-pin of resistor R33 is connected to the 7-pin of chip U6, and the 1-pin of resistor R33 is connected to the 46-pin of chip U1.

[0070] Further, the driving circuit includes a chip U4, a chip U5, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a resistor R25, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17, a diode D9, a diode D10, a diode D11, a diode D12, a diode D13, a diode D14, and a diode D15, wherein:

[0071] Chip U4 and chip U5 use the intelligent high-drive chip BTS724G; Pin 1, Pin 10, Pin 11, Pin 12, Pin 15, Pin 16, Pin 19 and Pin 20 of chip U4 are connected to the network P101 output by the power circuit, Pin 4 of chip U4 is connected to Pin 1 of resistor R13, Pin 2 of resistor R13 is connected to the network VCC, Pin 8 of chip U4 is connected to Pin 1 of resistor R15, Pin 2 of resistor R15 is connected to the network VCC, Pin 2 and Pin 6 ...2 and Pin 6 of chip U4 are connected to the network P101 output by the power circuit, Pin 4 of chip U4 is connected to Pin 1 of resistor R13, Pin 2 of resistor R13 is connected to the network VCC, Pin 2 and Pin 6 of chip U4 are connected to the network P101 output by the power circuit, Pin 4 of chip U4 is connected to Pin 1 of resistor R15, Pin 2 of resistor R15 is connected to the network VCC, Pin 2 and Pin 6 of chip U4 are connected to the network P101 output by the power circuit, Pin 4 of chip U4 is connected to Pin 1 of resistor R13, Pin 2 of resistor R13 is connected to the network VCC, Pin 2 and Pin 6 of chip U4 are connected to the network P101 output by Connect to pin 1 of resistor R14, pin 2 of resistor R14 to network DGND, pin 1 of capacitor C9 to network P101, pin 2 of capacitor C9 to network DGND, pin 1 of capacitor C10 to pin 13 of chip U4, pin 2 of capacitor C10 to network DGND, the cathode of diode D9 to pin 13 of chip U4, the anode of diode D9 to network GND, pin 1 of resistor R19 to pin 13 of chip U4, pin 2 of resistor R19 to network G ND, pin 1 of capacitor C11 is connected to pin 14 of chip U4, pin 2 of capacitor C11 is connected to network DGND, the cathode of diode D10 is connected to pin 14 of chip U4, the anode of diode D10 is connected to network GND, pin 1 of resistor R20 is connected to pin 14 of chip U4, pin 2 of resistor R20 is connected to network GND, pin 1 of capacitor C12 is connected to pin 17 of chip U4, pin 2 of capacitor C12 is connected to network DGND, the cathode of diode D11 is connected to pin 14 of chip U4 Pin 17, the positive electrode of diode D11 is connected to network GND, pin 1 of resistor R21 is connected to pin 17 of chip U4, pin 2 of resistor R21 is connected to network GND, pin 1 of capacitor C13 is connected to pin 18 of chip U4, pin 2 of capacitor C13 is connected to network DGND, the negative electrode of diode D12 is connected to pin 18 of chip U4, the positive electrode of diode D12 is connected to network GND, pin 1 of resistor R22 is connected to pin 18 of chip U4, and pin 2 of resistor R22 is connected to network GND;

[0072] Pin 1, 10, 11, 12, 15, 16, 19 and 20 of chip U5 are connected to the power circuit output network P101, pin 4 of chip U5 is connected to pin 1 of resistor R16, pin 2 of resistor R16 is connected to network VCC, pin 8 of chip U5 is connected to pin 1 of resistor R18, pin 2 of resistor R18 is connected to network VCC, pin 2 and pin 6 of chip U5 are connected to pin 1 of resistor R17, pin 2 of resistor R17 is connected to network DGND, pin 1 of capacitor C14 is connected to network P101, pin 2 of capacitor C14 is connected to network DGND, pin 1 of capacitor C15 is connected to pin 14 of chip U5, pin 2 of capacitor C11 is connected to network DGND, the cathode of diode D13 is connected to pin 14 of chip U5, diode D13 is connected to pin 14 of chip U5, The positive electrode of the chip is connected to the network GND, the 1st pin of the resistor R23 is connected to the 14th pin of the chip U5, the 2nd pin of the resistor R23 is connected to the network GND, the 1st pin of the capacitor C16 is connected to the 17th pin of the chip U5, the 2nd pin of the capacitor C16 is connected to the network DGND, the negative electrode of the diode D14 is connected to the 17th pin of the chip U5, the positive electrode of the diode D14 is connected to the network GND, the 1st pin of the resistor R24 ​​is connected to the 17th pin of the chip U5, the 2nd pin of the resistor R24 ​​is connected to the network GND, the 1st pin of the capacitor C17 is connected to the 18th pin of the chip U5, the 2nd pin of the capacitor C17 is connected to the network DGND, the negative electrode of the diode D15 is connected to the 18th pin of the chip U5, the positive electrode of the diode D15 is connected to the network GND, the 1st pin of the resistor R25 is connected to the 18th pin of the chip U5, and the 2nd pin of the resistor R25 is connected to the network GND. The 9th pin of the chip U5 and the 13th pin of the chip U5 are not used and are left floating.

[0073] Compared with the prior art, the present invention has the following significant advantages: 1) the hardware integration of the main control module is high and the total hardware cost is low; 2) the core algorithms or logics are all completed by the main single-chip microcomputer, and the functions completed by the slave single-chip microcomputer are simple and fixed, so only one software of the main single-chip microcomputer needs to be maintained, and the software maintenance cost is low; 3) the number of modules is small, the total working power consumption is small, the total installation space is small, and the total weight is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] Figure 1 It is the schematic diagram of the module's external interface circuit.

[0075] Figure 2 It is the power supply circuit schematic.

[0076] Figure 3 It is the schematic diagram of the microcontroller circuit.

[0077] Figure 4 This is the schematic diagram of the CAN interface circuit.

[0078] Figure 5 It is the schematic diagram of the switch quantity acquisition circuit.

[0079] Figure 6 It is the schematic diagram of analog quantity acquisition circuit.

[0080] Figure 7 This is the schematic diagram of the driving circuit.

[0081] Figure 8 This is a simplified diagram of the electrical principle of the battery system.

[0082] Component code description: D stands for diode, C stands for capacitor, L stands for inductor or magnetic bead, U stands for chip, R stands for resistor, J stands for internal connector, JP stands for external connector, and Y stands for crystal oscillator.

[0083] In the seven circuit diagrams that make up the module, the component pins with the same labeled network are actually connected together even if they are not directly connected by wires on the circuit diagram. For example, all component pins marked with network DGND are connected together, component pins marked with network P101 are connected together, and so on. DETAILED DESCRIPTION

[0084] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0085] A battery management system main control module, such as Figures 1 to 7 As shown, it includes: module external interface circuit, power supply circuit, single-chip circuit, CAN interface circuit, switch quantity acquisition circuit, analog quantity acquisition circuit, and drive circuit. The module external interface circuit is the only interface between the module and the external device. The module outputs the drive signal to the external device through the interface, and the external device inputs the signal to the module through the interface. At the same time, the module and the external device communicate through the CAN interface. The power supply circuit converts the 24V power supply signal from the module external interface circuit into the 5V power supply signal required by the module. The switch quantity acquisition circuit filters and isolates the 24V switch quantity signal in the module external interface circuit and converts it into a 5V switch quantity signal, which is input to the single-chip circuit. The analog quantity acquisition circuit filters and divides the analog quantity signal from the module external interface circuit into a voltage signal of 0 to 4V, which is input to the single-chip circuit. The CAN interface circuit completes the physical conversion of the CAN bus signal between the single-chip and the external environment. The single-chip circuit is the acquisition and control center of the module, which analyzes and processes the switch quantity signal, analog quantity signal and CAN bus signal, and then outputs the control signal to the drive circuit and the CAN bus signal to the external device.

[0086] 1. Module introduction:

[0087] 1. Module external interface circuit

[0088] Connect pins 1 and 2 of the external connector JP1 to the positive electrode network BAT+ of the diode D1 of the power circuit;

[0089] Connect pins 21, 22, 33, 34, 35, 36 and 37 of external connector JP1 to pin 4 of power circuit L1, network DGND;

[0090] Connect pin 3 of external connector JP1 to pin 2 (m=0) of inductor L11_0 of CAN interface circuit, network CANH0;

[0091] Connect the 4th pin of the external connector JP1 to the 1st pin of the inductor L11_0 of the CAN interface circuit (m=0), network CANL0;

[0092] Connect pin 23 of external connector JP1 to network 0S (m=0) of CAN interface circuit;

[0093] Connect pin 5 of external connector JP1 to pin 2 of inductor L11_1 of CAN interface circuit (m=1), network CANH1;

[0094] Connect the 6th pin of the external connector JP1 to the 1st pin of the inductor L11_1 of the CAN interface circuit (m=1), network CANL1;

[0095] Connect pin 24 of external connector JP1 to network 1S (m=1) of CAN interface circuit;

[0096] Connect the 25th pin of the external connector JP1 to the 2nd pin of the inductor L11_2 of the CAN interface circuit (m=2), network CANH2;

[0097] Connect the 26th pin of the external connector JP1 to the 1st pin of the inductor L11_2 of the CAN interface circuit (m=2), network CANL2;

[0098] Connect pin 27 of external connector JP1 to network 2S (m=2) of CAN interface circuit;

[0099] Connect the pin 7 of the external connector JP1 to the pin 2 (m=3) of the inductor L11_3 of the CAN interface circuit, network CANH3;

[0100] Connect the 8th pin of the external connector JP1 to the 1st pin of the inductor L11_3 of the CAN interface circuit (m=3), network CANL3;

[0101] Connect pin 28 of external connector JP1 to network 3S (m=3) of CAN interface circuit;

[0102] Connect the 9th pin of the external connector JP1 to the 2nd pin (m=4) of the inductor L11_4 of the CAN interface circuit, network CANH4;

[0103] Connect the 10th pin of the external connector JP1 to the 1st pin of the inductor L11_4 of the CAN interface circuit (m=4), network CANL4;

[0104] Connect pin 29 of external connector JP1 to network 4S (m=4) of CAN interface circuit;

[0105] Connect the 11th pin of the external connector JP1 to the 2nd pin (m=5) of the inductor L11_5 of the CAN interface circuit, network CANH5;

[0106] Connect the 12th pin of the external connector JP1 to the 1st pin of the inductor L11_5 of the CAN interface circuit (m=5), network CANL5;

[0107] Connect pin 30 of external connector JP1 to network 5S (m=5) of CAN interface circuit;

[0108] The 13-pin network DOH1, 14-pin network DOH2, 15-pin network DOH3, and 16-pin network DOH4 of the external connector JP1 are respectively connected to the 18-pin network DOH1, 17-pin network DOH2, 14-pin network DOH3, and 13-pin network DOH4 of the chip U4 in the drive circuit;

[0109] The 17-pin network DOH5, 18-pin network DOH6 and 19-pin network DOH7 of the external connector JP1 are respectively connected to the 18-pin network DOH5, 17-pin network DOH6 and 14-pin network DOH7 of the chip U5 in the drive circuit;

[0110] Connect the 31-pin network ON of the external connector JP1 to the 1-pin network ON of the capacitor C20 of the switch quantity acquisition circuit;

[0111] Connect the 32-pin network A+ of the external connector JP1 to the 1-pin network A+ of the capacitor C21 of the switch quantity acquisition circuit;

[0112] Connect the 20-pin network AI1 of the external connector JP1 to the 1-pin network AI1 of the capacitor C22 of the analog acquisition circuit;

[0113] Connect the 40-pin network AI2 of the external connector JP1 to the 1-pin network AI2 of the capacitor C26 of the analog acquisition circuit;

[0114] Connect the 38-pin network AGND of the external connector JP1 to the network AGND of the power circuit;

[0115] Connect the 39-pin network A5V of the external connector JP1 to the network A5V of the power circuit;

[0116] 2. Power circuit

[0117] The power supply circuit includes a diode D1, a diode D2, a diode D3, a diode D4, a diode D18, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, an inductor L1, an inductor L2, a magnetic bead L3, an inductor L5, a magnetic bead L6, a magnetic bead L7, a magnetic bead L8, a magnetic bead L9, a magnetic bead L10, a magnetic bead L12, a resistor R1, a resistor R2, a resistor R50, a resistor R51, and a chip U3 (model LN5016PHMR-G), wherein:

[0118] The positive pole of diode D1 is connected to network BAT+, the negative pole of diode D1 is connected to the negative pole of diode D2, the output network P101 signal is used to power the drive circuit, capacitor C1 is connected in parallel with diode D2, and pin 1 of inductor L1 is connected to network P101; capacitor C2 is connected in parallel between pins 2 and 3 of inductor L1, pin 2 of inductor L1 is connected to pin 1 of inductor L2, pin 2 of inductor L2 is connected to pin 5 of chip U3, pin 4 of inductor L1 is connected to network DGND, pin 3 of inductor L1 is connected to network GND, pin 1 of capacitor C3 is connected to pin 5 of chip U3, pin 2 of capacitor C3 is connected to network GND, capacitor C Pin 1 of capacitor C4 is connected to pin 5 of chip U3, pin 2 of capacitor C4 is connected to network GND, pin 1 of capacitor C5 is connected to pin 1 of chip U3, pin 2 of capacitor C5 is connected to pin 6 of chip U3, pin 1 of inductor L5 is connected to pin 6 of chip U3, pin 2 of inductor L5 is connected to network +5V, pin 1 of resistor R51 is connected to pin 3 of chip U3, pin 2 of resistor R51 is connected to pin 2 of chip U3 network GND, the positive electrode of capacitor C6 is connected to network +5V, the negative electrode of capacitor C6 is connected to network GND, pin 1 of capacitor C7 is connected to network +5V, pin 2 of capacitor C7 is connected to network GND, pin 1 of resistor R50 is connected Pin 3 of U3 and pin 2 of resistor R50 are connected to the network +5V, pin 1 of ferrite bead L6 is connected to the network +5V, pin 2 of ferrite bead L6 is connected to the network +5V-B1, pin 1 of ferrite bead L7 is connected to the network +5V, pin 2 of ferrite bead L7 is connected to the network +5V-B2, pin 1 of ferrite bead L8 is connected to the network +5V, pin 2 of ferrite bead L8 is connected to the network VCC, pin 1 of ferrite bead L9 is connected to the network +5V, pin 2 of ferrite bead L9 is connected to the network A5V, pin 1 of ferrite bead L10 is connected to the network GND, pin 2 of ferrite bead L10 is connected to the network AGND, pin 31 of the external connector JP1 is connected to pin 1 of ferrite bead L3, and ferrite bead Pin 2 of L3 is connected to the positive electrode of diode D3, the negative electrode of diode D3 is connected to pin 1 of resistor R1, pin 2 of resistor R1 is connected to pin 1 of resistor R2, pin 2 of resistor R2 is connected to network GND, capacitor C8 is connected in parallel with resistor R2, pin 1 of resistor R2 is connected to pin 4 of U3, the negative electrode of diode D4 is connected to pin 4 of U3, the positive electrode of diode D4 is connected to pin 88 of microcontroller U1A, network BMU_LOCK, pin 32 of external connector JP1 is connected to pin 1 of ferrite bead L12, pin 2 of ferrite bead L12 is connected to the positive electrode of diode D18, and the negative electrode of diode D18 is connected to pin 1 of resistor R1.

[0119] 3. Single chip microcomputer circuit

[0120] The single-chip computer circuit includes chip U1, chip U2, chip U8, internal connector J1, crystal oscillator Y1, capacitor C37, capacitor C38, capacitor C39, capacitor C40, capacitor C41, capacitor C42, capacitor C43, capacitor C44, capacitor C45, capacitor C46, ​​capacitor C47, capacitor C48, capacitor C49, capacitor C50, capacitor C51, capacitor C52, resistor R37, resistor R38, resistor R39, resistor R40, resistor R41, resistor R42, resistor R43, diode D17, among which:

[0121] Chip U1 and chip U2 are 32-bit Arm Cortex-M4F processors FS32K144HFT0MLLT with a main frequency of up to 112MHz; for the convenience of circuit description, chip U1 is divided into two parts, U1A and U1B, in the circuit diagram; chip U2 is divided into two parts, U2A and U2B, in the circuit diagram.

[0122] Pin 1 of chip U1 is connected to pin 100 of chip U2, pin 2 of chip U1 is connected to pin 2 of chip U2, pin 99 of chip U1 is connected to pin 99 of chip U2, and pin 100 of chip U1 is connected to pin 1 of chip U2;

[0123] Pin 8 of chip U1 is connected to pin 5 of CAN interface circuit U9_0, pin 9 of chip U1 is connected to pin 4 of CAN interface circuit chip U9_0, pin 89 of chip U1 is connected to pin 5 of CAN interface circuit chip U9_1, pin 90 of chip U1 is connected to pin 4 of CAN interface circuit chip U9_1, pin 43 of chip U1 is connected to pin 5 of CAN interface circuit chip U9_2, and pin 44 of chip U1 is connected to pin 4 of CAN interface circuit chip U9_2;

[0124] Pin 8 of chip U2 is connected to pin 5 of CAN interface circuit chip U9_3, pin 9 of chip U2 is connected to pin 4 of CAN interface circuit chip U9_3, pin 89 of chip U2 is connected to pin 5 of CAN interface circuit chip U9_4, pin 90 of chip U2 is connected to pin 4 of CAN interface circuit chip U9_4, pin 43 of chip U2 is connected to pin 5 of CAN interface circuit chip U9_5, and pin 44 of chip U2 is connected to pin 4 of CAN interface circuit chip U9_5;

[0125] Pin 62 of chip U1 is connected to pin 3 of drive output circuit chip U4, pin 59 of chip U1 is connected to pin 5 of drive output circuit chip U4, pin 58 of chip U1 is connected to pin 7 of drive output circuit chip U4, pin 57 of chip U1 is connected to pin 9 of drive output circuit chip U4, pin 62 of chip U2 is connected to pin 3 of drive output circuit chip U5, pin 59 of chip U2 is connected to pin 5 of drive output circuit chip U5, and pin 58 of chip U2 is connected to pin 7 of drive output circuit chip U5;

[0126] Pin 45 of chip U1 is connected to pin 1 of resistor R29 of analog quantity acquisition circuit, network AI_HALL1; pin 46 of chip U1 is connected to pin 1 of resistor R33 of analog quantity acquisition circuit, network AI_HALL2;

[0127] Pin 82 of chip U1 is connected to pin 1 network CHK1 of resistor R3 of the switch quantity acquisition circuit, and pin 83 of chip U1 is connected to pin 1 network CHK2 of resistor R4 of the switch quantity acquisition circuit;

[0128] Pin 15 of chip U1 is connected to pin 3 of crystal oscillator Y1, pin 16 of chip U1 is connected to pin 1 of crystal oscillator Y1, resistor R38 is connected in parallel between pins 15 and 16 of chip U1, pin 1 of capacitor C38 is connected to pin 3 of crystal oscillator Y1, pin 2 of capacitor C38 is connected to pin 4 of crystal oscillator Y1 and network GND, pin 1 of capacitor C37 is connected to pin 1 of crystal oscillator Y1, pin 2 of capacitor C37 is connected to network GND, pin 97 of chip U1 is connected to pin 1 of capacitor C52, pin 2 of capacitor C52 is connected to network GND, pin 97 of chip U1 is connected to network +5V-B1 through resistor R39, the cathode of diode D17 is connected to network +5V-B1, and the anode of diode D17 is connected to pin 97 of chip U1;

[0129] Pin 1 and Pin 2 of the internal connector J1 are connected to the network +5V-B1, Pin 3 and Pin 4 of the internal connector J1 are connected to Pin 97 of the chip U1, Pin 5 of the internal connector J1 is connected to Pin 95 of the chip U1, Pin 6 of the internal connector J1 is connected to Pin 92 of the chip U1, Pin 7 of the internal connector J1 is connected to Pin 98 of the chip U1, Pin 9 of the internal connector J1 is connected to Pin 96 of the chip U1, Pin 8 and Pin 10 of the internal connector J1 are connected to the network GND, Pin 95 of the chip U1 is connected to the network +5V-B1 through resistor R40, and Pin 92 of the chip U1 is connected to the network +5V-B1 through resistor R41;

[0130] The 98th pin of chip U1 is connected to the network +5V-B1 through resistor R42, and the 96th pin of chip U1 is connected to the network GND through resistor R43.

[0131] Pin 11 of chip U1 is connected to network A5V, pin 13 of chip U1 is connected to network AGND, capacitor C40 of capacitor C39 is connected in parallel between pins 11 and 13 of chip U1;

[0132] The 38th, 61st, 87th and 10th pins of chip U1 are connected to the network +5V-B1, and the 37th, 60th, 86th and 14th pins of chip U1 are connected to the network GND. Capacitors C41 and C42 are connected in parallel between the 38th and 37th pins of chip U1, capacitors C43 and C44 are connected in parallel between the 61st and 60th pins of chip U1, capacitors C45 and C46 are connected in parallel between the 87th and 86th pins of chip U1, and capacitors C47 and C48 are connected in parallel between the 10th and 14th pins of chip U1;

[0133] Capacitors C49, C50 and C51 are connected in parallel between pins 12 and 13 of chip U1. Pin 12 of chip U1 is pulled up to network A5V through resistor R37. Pin 1 of chip U8 is connected to pin 12 of chip U1, and pin 2 of chip U8 is connected to network AGND of pin 13 of chip U1.

[0134] The peripheral circuit of part B of chip U2 has the same principles as part B of chip U1 except that the power supply is changed from +5V-B1 to +5V-B2, and will not be described in detail.

[0135] 4. CAN interface circuit

[0136] This part contains 6 identical circuits, including chip U9_m, capacitor C29_m, capacitor C30_m, capacitor C31_m, capacitor C32_m, capacitor C33_m, capacitor C34_m, capacitor C35_m, capacitor C36_m, resistor R34_m, resistor R35_m, resistor R36_m, inductor L11_m, diode D16_m, m=0, 1, 2, 3, 4, 5, and the following description is based on m=0.

[0137] Pins 1, 3, 7, 9, and 10 of chip U9_0 are connected to the network GND, pins 6 and 8 of chip U9_0 are connected to the network VCC, capacitors C29_0 and C30_0 are connected in parallel and connected between pins 8 and 10 of chip U9_0, pins 11, 13, 16, 18, and 20 of chip U9_0 are connected to the network CAN_GND0, pins 12 and 19 of chip U9_0 are connected to the network CAN_5V0, capacitor C31_0 is connected between pins 20 and 19 of chip U9_0, capacitor C32_0 is connected between pins 13 and 12 of chip U9_0, resistor R34_0 and capacitor C33_0 are connected in parallel and one end is connected to the network CAN_GND 0, and the other end is connected to the network 0S, pin 1 of capacitor C34_0 is connected to pin 1 of L11_0, pin 2 of capacitor C34_0 is connected to the network 0S, pin 3 of diode D16_0 is connected to 0S, pin 1 of diode D16_0 is connected to pin 1 of L11_0, pin 2 of diode D16_0 is connected to pin 2 of L11_0, pin 1 of capacitor C35_0 is connected to pin 2 of L11_0, pin 2 of capacitor C35_0 is connected to the network 0S, pin 1 of resistor R35_0 is connected to pin 2 of L11_0, pin 2 of resistor R35_0 is connected to pin 1 of capacitor C36_0, pin 1 of resistor R36_0 is connected to pin 1 of L11_0, pin 2 of resistor R36_0 is connected to pin 1 of capacitor C36_0, and pin 2 of capacitor C36_0 is connected to the network 0S.

[0138] 5. Switching quantity acquisition circuit

[0139] The switch quantity acquisition circuit includes resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, chip U7, chip U10, diode D5, diode D6, diode D7, diode D8, capacitor C18, capacitor C19, capacitor C20, capacitor C21, wherein:

[0140] The 31-pin network ON of JP1 is connected to the 1-pin of capacitor C20 and the 2-pin of resistor R11, the 2-pin of capacitor C20 is connected to the network DGND, the 1-pin of resistor R11 is connected to the positive electrode of diode D7, the negative electrode of diode D7 is connected to the 1-pin of capacitor C18, the 1-pin of resistor R9, the negative electrode of diode D5 and the 2-pin of resistor R7, the 2-pin of capacitor C18, the 2-pin of resistor R9 and the positive electrode of diode D5 are connected to the 2-pin network DGND of chip U7, the 1-pin of resistor R7 is connected to the 1-pin of chip U7, the 3-pin of chip U7 is connected to the network GND, the 4-pin of chip U7 is connected to the network +5V-B1 through the pull-up resistor R5, the 4-pin of chip U7 is connected to the 2-pin of resistor R3, the 1-pin of resistor R3 is connected to the 83-pin network CHK1 of chip U1;

[0141] The 32-pin network A+ of JP1 is connected to the 1-pin of capacitor C21 and the 2-pin of resistor R12, the 2-pin of capacitor C21 is connected to the network DGND, the 1-pin of resistor R12 is connected to the positive electrode of diode D8, the negative electrode of diode D8 is connected to the 1-pin of capacitor C19, the 1-pin of resistor R10, the negative electrode of diode D6 and the 2-pin of resistor R8, the 2-pin of capacitor C19, the 2-pin of resistor R10 and the positive electrode of diode D6 are connected to the 2-pin network DGND of chip U10, the 1-pin of resistor R8 is connected to the 1-pin of chip U10, the 3-pin of chip U10 is connected to the network GND, the 4-pin of chip U10 is connected to the network +5V-B1 through the pull-up resistor R6, the 4-pin of chip U10 is connected to the 2-pin of resistor R4, the 1-pin of resistor R4 is connected to the 82-pin network CHK2 of chip U1.

[0142] 6. Analog quantity acquisition circuit

[0143] The analog quantity acquisition circuit includes capacitor C22, capacitor C23, capacitor C24, capacitor C25, capacitor C26, capacitor C27, capacitor C28, resistor R26, resistor R27, resistor R28, resistor R29, resistor R30, resistor R31, resistor R32, resistor R33, and chip U6 (divided into U6A and U6B in the circuit diagram), where:

[0144] JP1's 20-pin network AI1 is connected to pin 1 of capacitor C22, pin 1 of capacitor C23, and pin 1 of resistor R26. Pin 2 of capacitor C22 is connected to network DGND, pin 2 of capacitor C23 is connected to network AGND, pin 2 of resistor R26 is connected to pin 3 of chip U6, pin 1 of resistor R27 is connected to pin 3 of chip U6, pin 2 of resistor R27 is connected to network AGND, pin 1 of capacitor C24 is connected to pin 3 of chip U6, and pin 2 of capacitor C24 is connected to pin 3 of chip U6. Connect to network AGND, pin 1 of resistor R28 connects to network AGND, pin 2 of resistor R28 connects to pin 2 of chip U6, pin 2 of chip U6 is short-circuited with pin 1 of chip U6, pin 8 of chip U6 connects to network A5V, pin 4 of chip U6 connects to network AGND, pin 1 of capacitor C25 connects between pin 8 of chip U6 and pin 4 of U6, pin 2 of resistor R29 connects to pin 1 of chip U6, and pin 1 of resistor R29 connects to pin 45 of chip U1;

[0145] The 40-pin network AI2 of JP1 is connected to the 1-pin of capacitor C26, the 1-pin of capacitor C27, and the 1-pin of resistor R30. The 2-pin of capacitor C26 is connected to the network DGND, the 2-pin of capacitor C27 is connected to the network AGND, the 2-pin of resistor R30 is connected to the 5-pin of chip U6, the 1-pin of resistor R31 is connected to the 5-pin of chip U6, the 2-pin of resistor R31 is connected to the network AGND, the 1-pin of capacitor C28 is connected to the 5-pin of chip U6, the 2-pin of capacitor C28 is connected to the network AGND, the 1-pin of resistor R32 is connected to the network AGND, the 2-pin of resistor R32 is connected to the 6-pin of chip U6, the 6-pin of chip U6 is short-circuited with the 7-pin of chip U6, the 2-pin of resistor R33 is connected to the 7-pin of chip U6, and the 1-pin of resistor R33 is connected to the 46-pin of chip U1.

[0146] 7. Driving circuit

[0147] The driving circuit includes chip U4, chip U5, resistor R13, resistor R14, resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, resistor R22, resistor R23, resistor R24, resistor R25, capacitor C9, capacitor C10, capacitor C11, capacitor C12, capacitor C13, capacitor C14, capacitor C15, capacitor C16, capacitor C17, diode D9, diode D10, diode D11, diode D12, diode D13, diode D14, diode D15, wherein:

[0148] Pin 1, 10, 11, 12, 15, 16, 19 and 20 of chip U4 are connected to the power circuit output network P101, pin 4 of chip U4 is connected to pin 1 of resistor R13, pin 2 of resistor R13 is connected to network VCC, pin 8 of chip U4 is connected to pin 1 of resistor R15, pin 2 of resistor R15 is connected to network VCC, pin 2 and pin 6 of chip U4 are connected to pin 1 of resistor R14, pin 2 of resistor R14 is connected to pin 3 of resistor R15, and pin 4 of resistor R15 is connected to network VCC. Connect to network DGND, pin 1 of capacitor C9 connects to network P101, pin 2 of capacitor C9 connects to network DGND, pin 1 of capacitor C10 connects to pin 13 of chip U4, pin 2 of capacitor C10 connects to network DGND, the cathode of diode D9 connects to pin 13 of chip U4, the anode of diode D9 connects to network GND, pin 1 of resistor R19 connects to pin 13 of chip U4, pin 2 of resistor R19 connects to network GND, pin 1 of capacitor C11 connects to chip Pin 14 of chip U4, pin 2 of capacitor C11 connected to network DGND, the cathode of diode D10 connected to pin 14 of chip U4, the anode of diode D10 connected to network GND, pin 1 of resistor R20 connected to pin 14 of chip U4, pin 2 of resistor R20 connected to network GND, pin 1 of capacitor C12 connected to pin 17 of chip U4, pin 2 of capacitor C12 connected to network DGND, the cathode of diode D11 connected to pin 17 of chip U4, diode The positive electrode of D11 is connected to the network GND, the 1st pin of the resistor R21 is connected to the 17th pin of the chip U4, the 2nd pin of the resistor R21 is connected to the network GND, the 1st pin of the capacitor C13 is connected to the 18th pin of the chip U4, the 2nd pin of the capacitor C13 is connected to the network DGND, the negative electrode of the diode D12 is connected to the 18th pin of the chip U4, the positive electrode of the diode D12 is connected to the network GND, the 1st pin of the resistor R22 is connected to the 18th pin of the chip U4, the 2nd pin of the resistor R22 is connected to the network GND;

[0149] Pin 1, 10, 11, 12, 15, 16, 19 and 20 of chip U5 are connected to the power circuit output network P101, pin 4 of chip U5 is connected to pin 1 of resistor R16, pin 2 of resistor R16 is connected to network VCC, pin 8 of chip U5 is connected to pin 1 of resistor R18, pin 2 of resistor R18 is connected to network VCC, pin 2 and pin 6 of chip U5 are connected to pin 1 of resistor R17, pin 2 of resistor R17 is connected to network DGND, pin 1 of capacitor C14 is connected to network P101, pin 2 of capacitor C14 is connected to network DGND, pin 1 of capacitor C15 is connected to pin 14 of chip U5, pin 2 of capacitor C11 is connected to network DGND, the cathode of diode D13 is connected to pin 14 of chip U5, diode D13 is connected to pin 14 of chip U5, The positive electrode of the chip is connected to the network GND, the 1st pin of the resistor R23 is connected to the 14th pin of the chip U5, the 2nd pin of the resistor R23 is connected to the network GND, the 1st pin of the capacitor C16 is connected to the 17th pin of the chip U5, the 2nd pin of the capacitor C16 is connected to the network DGND, the negative electrode of the diode D14 is connected to the 17th pin of the chip U5, the positive electrode of the diode D14 is connected to the network GND, the 1st pin of the resistor R24 ​​is connected to the 17th pin of the chip U5, the 2nd pin of the resistor R24 ​​is connected to the network GND, the 1st pin of the capacitor C17 is connected to the 18th pin of the chip U5, the 2nd pin of the capacitor C17 is connected to the network DGND, the negative electrode of the diode D15 is connected to the 18th pin of the chip U5, the positive electrode of the diode D15 is connected to the network GND, the 1st pin of the resistor R25 is connected to the 18th pin of the chip U5, and the 2nd pin of the resistor R25 is connected to the network GND. The 9th pin of the chip U5 and the 13th pin of the chip U5 are not used and are left floating.

[0150] 2. Working principle of each circuit:

[0151] 1. Power supply circuit

[0152] The BAT+ and DGND power signals are input from the external interface, passing through the anti-reverse connection design of diode D1, and then through the overvoltage absorption protection of diode D2, and then through capacitor C1, inductor L1, capacitor C2 to form a common-mode filter circuit, and then through inductor L2, capacitor C3 to form a differential-mode filter circuit, and finally through further filtering by capacitor C4, the relatively clean power signal is input to the switching power supply chip U3. Magnetic bead L3, diode D3, magnetic bead L12, diode D18, resistor R1, resistor R2, capacitor C8 form a power wake-up circuit. When the voltage of ON or A+ is greater than or equal to 5.7V, U3 works and outputs a voltage of +5V. After filtering by magnetic bead L6, network +5V-B1 is generated to power chip U1 and switch quantity acquisition circuit; after filtering by magnetic bead L7, network +5V-B2 is generated to power chip U2; after filtering by magnetic bead L8, network VCC is generated to power the drive output circuit and CAN interface circuit; after filtering by magnetic bead L9, network A5V is generated to power the external interface and analog quantity acquisition circuit; magnetic bead L10 is a bridge for the single-point connection of network GND and network AGND. Inductor L5, capacitor C5, capacitor C6, capacitor C7, resistor R50, and resistor R51 form the peripheral circuit of chip U1.

[0153] 2. Single chip microcomputer circuit

[0154] For the convenience of circuit description, chip U1 is divided into two parts, U1A and U1B, in the circuit diagram; chip U2 is divided into two parts, U2A and U2B, in the circuit diagram.

[0155] Chip U1 and chip U2 are 32-bit Arm Cortex-M4F processors FS32K144HFT0MLLT with a main frequency of up to 112MHz, 512KB Flash, 64KB System RAM, and other rich resources;

[0156] Crystal oscillator Y1, capacitor C37, capacitor C38, and resistor R38 form the crystal oscillator circuit of the single-chip microcomputer. Crystal oscillator Y1 uses 16MHz, and the frequency multiplication is set inside the single-chip microcomputer to generate a maximum main frequency of 112MHz.

[0157] Resistor R39, capacitor C52, and diode D17 form the reset circuit of chip U1. When the 97th pin of chip U1 is powered on, it is initially 0V. As +5V-B1 charges capacitor C52 through resistor R39, the voltage of the 97th pin of chip U1 gradually rises to 5V, and the reset of the single-chip microcomputer is completed.

[0158] Internal connector J1, resistor R40, resistor R41, resistor R42, and resistor R43 constitute a program download interface circuit;

[0159] Capacitor C49, capacitor C50, capacitor C51, chip U8, and resistor R37 constitute the analog reference voltage 4.096V power supply circuit of chip U1;

[0160] After chip U1 is powered on and reset, the Hall sensor zero point calibration function is first executed in the self-test phase, and the fault calibration threshold is read from the Flash. Then, the analog quantity acquisition function, charge and discharge current conversion function, switch quantity acquisition function, switch quantity output function, CAN0 bus transceiver function, CAN1 bus transceiver function, CAN2 bus transceiver function, SPI bus transceiver function, SOC estimation function, fault handling function, high drive output function, etc. are cyclically executed in the main program.

[0161] After chip U2 is powered on and reset, the CAN3 bus receiving function, CAN4 bus receiving function, CAN5 bus receiving function, single cell voltage processing function, single cell temperature processing function, and SPI bus transceiver function are executed cyclically in the main program;

[0162] 3. CAN interface circuit

[0163] Chip U9_m uses CAN isolation chip TDH541SCANH with isolated DCDC, inductor L11 is CAN common mode inductor for filtering, resistor R35 and resistor R36 form 120Ω CAN bus matching resistor, capacitor C34 and capacitor C35 form CAN interface matching capacitor, diode D16 is used for electrostatic protection;

[0164] Chip U9_m is the physical layer chip of the CAN bus interface, which converts the TTL level signal of the microcontroller into the differential signal of the CAN bus of the external device;

[0165] 4. Switching quantity acquisition circuit

[0166] This part of the circuit converts the 0V~32V voltage signal of the external input switch signal into a 0V / 5V TTL signal for collection by the single-chip microcomputer circuit;

[0167] When the network ON signal input at pin 31 of JP1 is higher than 12V, the diode inside chip U7 (IS3H7C) turns on and emits light, making pins 3 and 4 of chip U7 turned on, and the single-chip microcomputer chip U1 collects the low level L; when the network ON signal input voltage is lower than 12V, the diode inside chip U7 is cut off, pins 3 and 4 of chip U7 are not turned on, and the single-chip microcomputer chip U1 collects the high level H;

[0168] Capacitor C20 is an EMC filter capacitor that filters out input interference signals. Diode D7 utilizes the unidirectional conduction characteristics of the component. Resistors R7 and R11 play a role in current limiting and voltage reduction to prevent chip U7 from being damaged by overcurrent. Diode D5, resistor R9 and capacitor C18 form a protection circuit to prevent chip U7 from being damaged by overvoltage due to instantaneous overvoltage of the input signal.

[0169] The collection principle of the 32-pin network A+ of the external connector JP1 is the same as that of the network ON.

[0170] Note: When the voltage of the MCU input pin is below 1.5V, it is recognized as a low level L. When the voltage of the MCU pin is above 3.5V, it is recognized as a high level H.

[0171] 5. Analog quantity acquisition circuit

[0172] The function of this part of the circuit is to filter and convert the network AI1 and network AI2 signals input by JP1 into relatively clean analog signals of 0~4V and input them to chip U1 for collection and processing. Take the AI1 signal as an example: C22 is an EMC filter capacitor, which filters out the interference signal, and then converts the input 0~5VDC voltage signal into a 0~4VDC signal through the voltage divider circuit composed of R26 and R27. The reason for the conversion is that the analog reference voltage chip U8 of U1 uses LM4040BIM-4.1, that is, the reference voltage is 4.096V, and the input voltage must be less than or equal to the reference voltage. Otherwise, the input microcontroller higher than the reference voltage will be processed according to the reference voltage, resulting in inaccurate collection. Chip U6 uses MCP6002T / I / SN, which is a 2-channel op amp. It plays the role of a follower in this circuit to increase the input impedance. Capacitors C23 and C24 play a filtering role, and resistor R29 plays a current limiting role.

[0173] 6. Drive output circuit

[0174] U4 and U5 use Infineon's intelligent high-drive chip BTS724G, which is a high-drive chip with integrated 4-way output. The single-way drive capability can reach 3A, and the total of the four-way output can reach 7A. Figure 8In the battery system application, JP1's 13-pin DOH1 and JP1's 33-pin DGND are connected to the main positive contactor coil, JP1's 14-pin DOH2 and JP1's 34-pin DGND are connected to the main negative contactor coil, JP1's 15-pin DOH3 and JP1's 35-pin DGND are connected to the charging positive contactor coil, JP1's 16-pin DOH1 and JP1's 36-pin DGND are connected to the charging negative contactor coil, JP1's 17-pin DOH5 and JP1's 37-pin DGND are connected to the BMS slave control module power supply of branch one, JP1's 18-pin DOH6 and JP1's 37-pin DGND are connected to the BMS slave control module power supply of branch two, and JP1's 19-pin DOH7 and JP1's 37-pin DGND are connected to the BMS slave control module power supply of branch three. Take the network DOH1 output as an example: when the microcontroller controls the network IO_DO1 to be high level, DOH1 outputs the same level signal as P101, capacitor C13 filters out the interference signal of JP113 pin, and diode D12 and resistor R22 provide a discharge circuit for the reverse voltage generated when the inductive load is turned off.

[0175] Description of low voltage power-on working process:

[0176] like Figure 8 As shown, the BMS main control module has a 24V power input, and the wake-up signal ON or A+ inputs a 24V valid signal. The power circuit of the BMS main control module works, and the power circuit outputs +5V-B1, +5V-B2, VCC, and A5V power signals. After the power-on of each part of the circuit is completed, the chip U1 outputs a BMU_LOCK high-level signal to the positive electrode of the power circuit diode D4 after power-on, completing the power-on self-locking function, which is used to prevent the power circuit from being accidentally powered off due to interference with the ON or A+ signal. It also has the function of delaying power-off.

[0177] After the chip U2 is powered on, it outputs high-level signals of IO_BSU1 on pin 62, IO_BSU2 on pin 59, and IO_BSU3 on pin 58, and drives the output circuit chip U5 to output three 24V power supply signals DOH5, DOH6, and DOH7 to power the BSU slave control modules of the three branches.

[0178] The voltage and temperature of each cell of the branch 1 battery are transmitted by the slave control module BSU1 to the 7-pin CANH3, 8-pin CANL3, and 28-pin 3S of the external connector JP1 of the master control module via the CAN bus differential signal. Then, the chip U9_3 converts the CAN3 bus differential signal into a TTL signal and sends it to the 8-pin and 9-pin of the chip U2. U2 completes the calculation of the extreme value information of the voltage and temperature of the branch 1 battery.

[0179] The voltage and temperature of each cell of the battery in branch 2 are transmitted by the slave control module BSU2 via the CAN bus differential signal to the 9-pin CANH4, 10-pin CANL4, and 29-pin 4S of the external connector JP1 of the master control module. Then, the chip U9_4 converts the CAN4 bus differential signal into a TTL signal and sends it to the 89-pin and 90-pin of the chip U2. U2 completes the calculation of the extreme value information of the voltage and temperature of the battery in branch 2.

[0180] The voltage and temperature of each cell of the three-battery branch are transmitted by the slave control module BSU3 to the 11-pin CANH5, 12-pin CANL5, and 30-pin 5S of the external connector JP1 of the master control module via the CAN bus differential signal. Then, the chip U9_5 converts the CAN5 bus differential signal into a TTL signal and sends it to the 43-pin and 44-pin of the chip U2. U2 completes the calculation of the extreme value information of the voltage and temperature of the three-battery branch.

[0181] Chip U2 then calculates the extreme value information of the entire battery system: the highest cell voltage and number, the lowest cell voltage and number, the highest cell temperature and number, and the lowest cell temperature and number. Chip U2 sends the extreme value information of the battery system to chip U1 via the SPI bus consisting of pins 1, 2, 99, and 100.

[0182] The vehicle control unit sends the total voltage and insulation resistance value of the battery system to the chip U9_1 through the CAN1 bus via differential signals. The chip U9_1 converts the differential signals into TTL signals and sends them to pins 89 and 90 of the chip U1.

[0183] Pins 38 and 39 of the JP1 connector are the 5V power supply provided by the module to the Hall sensor DHAB S124 of the battery system. The Hall sensor senses and outputs two 0-5V voltage signals, which are connected to pins 20 AI1 and 40 AI2 of the external connector JP1. These two voltage signals are processed by the analog quantity acquisition circuit and then connected to the chip U1. According to the characteristic formula of the Hall sensor DHAB S124, the chip U1 corresponds the voltage signal to the charge and discharge current value of the battery system. The chip U1 then integrates the current in ampere hours to update the SOC value of the current battery system.

[0184] Chip U1 collects the ON signal and A+ signal processed by the switch quantity acquisition circuit.

[0185] U1 processes the collected and received information about the battery system for fault diagnosis, bus communication and charge and discharge control.

[0186] Chip U1 performs fault diagnosis: The calibration function of chip U1 provides threshold calibration for single cell overvoltage, single cell undervoltage, overtemperature, undertemperature, excessive charging current, excessive discharging current, overvoltage, undervoltage, SOC, and insulation fault. Chip U1 compares the relevant actual values ​​of the battery system with the calibration values ​​in real time.

[0187] Charging failures include:

[0188] 1. The single cell voltage is too high (the highest single cell voltage is higher than the single cell overvoltage threshold value and lasts for 5S)

[0189] 2. Temperature is too high (the highest monomer temperature is higher than the temperature threshold for 5 seconds)

[0190] 3. Temperature is too low (the lowest monomer temperature is lower than the low temperature threshold for 5 seconds)

[0191] 4. Large charging current (charging current is greater than the charging current excessive threshold, lasting for 5S)

[0192] 5. Total voltage is too high (total voltage is higher than total voltage threshold for 5 seconds)

[0193] 6. Insulation fault (insulation resistance is lower than the insulation fault threshold and lasts for 15S)

[0194] Discharge faults include:

[0195] 1. The cell voltage is too low (the lowest cell voltage is lower than the cell undervoltage threshold value and lasts for 5S)

[0196] 2. Temperature is too high (the highest monomer temperature is higher than the temperature threshold for 5 seconds)

[0197] 3. Temperature is too low (the lowest monomer temperature is lower than the low temperature threshold for 5 seconds)

[0198] 4. High charging current (charging current is greater than the charging current threshold, lasting for 5S) - Feedback

[0199] 5. Discharge current is too large (discharge current is greater than the discharge current threshold value and lasts for 5S)

[0200] 6. Total voltage is too low (total voltage is lower than the total voltage threshold for 5 seconds)

[0201] 7. Insulation fault (insulation resistance is lower than the insulation fault threshold and lasts for 15S)

[0202] During the discharge process, when there is a discharge fault, chip U1 reports the fault information to the vehicle control unit through CAN1, and requests the vehicle to issue a high-voltage power-off command; during the charging process, when there is a charging fault, chip U1 reports the fault information to the charging pile through CAN2, and requests the charging pile to stop charging and disconnect the negative charging contactor and the positive charging contactor;

[0203] The 89th and 90th pins of chip U1 output TTL level to chip U9_1, and chip U9_1 converts TTL signal into CAN1 differential signal and sends it to vehicle control unit. Chip U1 sends the following information to vehicle control unit through CAN1 bus: total current, SOC value, highest cell voltage and number, lowest cell voltage and number, highest temperature and number, lowest temperature and number, DOH1 status, DOH2 status, DOH3 status, DOH4 status, A+ status, ON status, fault flag.

[0204] Chip U1 communicates with the charging pile through the CAN2 bus and is implemented in accordance with the national standard charging protocol "GB / T27930-2023 Digital Communication Protocol between Non-Onboard Conductive Chargers and Electric Vehicles".

[0205] Description of the charging high voltage power-up process:

[0206] The DC charging pile outputs A+24V signal input, the power circuit wakes up, and the chip U1 self-checks. After determining that the battery system has no charging fault, it interacts with the charging pile through the CAN2 interface. After a successful handshake, it controls DOH3 and DOH4 to output 24V, and DOH1 and DOH2 to output 0V. At this time, the charging positive contactor and the charging negative contactor are closed, the main positive contactor and the main negative contactor are disconnected, and the battery system starts to be charged.

[0207] Description of the discharge high voltage power-up process:

[0208] There is no 24V input to the A+ signal, and there is 24V input to ON. After the chip U1 determines that there is no discharge fault, it first sends the high-voltage flag through the CAN1 interface, and then waits to receive the high-voltage power-on command issued by the vehicle. When the high-voltage power-on command is valid, the chip U1 controls IO_DO1 and IO_DO2 to output 5V high level, and the chip U1 controls IO_DO3 and IO_DO4 to output 0V low level. The chip U4 controls DOH1 and DOH2 to output 24V, and DOH3 and DOH4 to output 0V. At this time, the main positive contactor and the main negative contactor are closed, the charging positive contactor and the charging negative contactor are disconnected, and the battery system discharges the vehicle.

[0209] Description of charging and discharging process:

[0210] When chip U1 detects a single cell overvoltage or total voltage overvoltage, chip U1 sends a BMS charging end instruction to the charging pile through CAN2, and the charging pile stops outputting. Then, chip U1 controls chip U4 to turn off the outputs of DOH1, DOH2, DOH3, and DOH4. At this time, the main positive contactor, main negative contactor, charging positive contactor, and charging negative contactor are all disconnected, and the battery system stops charging.

[0211] Description of the discharge process:

[0212] The vehicle sends a high-voltage power-off command through the CAN1 bus, and chip U1 controls DOH1 and DOH2 to output 0V, while DOH3 and DOH4 remain in their original state. At this time, the main positive contactor and the main negative contactor are disconnected, and the battery system stops discharging.

[0213] Description of low voltage power-on process:

[0214] After the high voltage power-off is completed, when the chip U1 determines that the switch signals of ON and A+ inputs have no 24V input for 10S, the chip U1 controls the chip U5 to stop the 24V output of DOH5, DOH6, and DOH7. At this time, the BSU slave control modules of the three branches are all powered off and dormant. Then, the chip U1 controls BMU_LOCK to output a low level of 0V, and the 4th pin of the power circuit chip U3 is lower than the wake-up voltage of 1.2V. The chip U3 stops outputting +5V, and the circuits of each part of the module lose the 5V power supply, and the circuit stops working. At this time, the main control module enters a low power consumption state, and the power consumption is less than 1mA.

[0215] In summary, the present invention uses two single-chip microcomputers, master (U1) and slave (U2), which communicate via the SPI bus in the module. The two single-chip microcomputers work in parallel, and each single-chip microcomputer controls three CAN buses. The CAN bus of the master single-chip microcomputer is used for bus communication of charging CAN2, vehicle CAN1, and maintenance CAN0, and the CAN interface of the slave single-chip microcomputer is used for the collection and processing of the BMS slave control module data of battery branch 1, battery branch 2, and battery branch 3. The signal acquisition, contactor control, slave control module power supply, low power consumption, fault diagnosis and calibration of the battery management system of the battery system are all completed by the master single-chip microcomputer, and the slave single-chip microcomputer is responsible for processing the extreme value data of the single cell voltage and single cell temperature, and sends it to the master single-chip microcomputer through the SPI bus. By adopting the master-slave MCU mode, the design of the main control module of the multi-branch battery management system is simplified, the software and hardware development costs of the battery management main control module are reduced, and the pressure of after-sales maintenance is reduced. The module has obvious improvements in terms of volume, weight and power saving. In addition, the function allocation of the master and slave MCUs is reasonable, the task volume of the master MCU has not increased, and the MCU software response speed will only be better than that of multiple main control modules. For battery systems with more parallel battery branches, the MCU can be replaced with a chip with more CAN controller resources, such as the S32K348 MCU with an 8-way CAN controller.

[0216] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0217] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A battery management system main control module, characterized in that: include: The module includes external interface circuit, power supply circuit, single-chip microcomputer circuit, CAN interface circuit, switch quantity acquisition circuit, analog quantity acquisition circuit and drive circuit, among which: The module external interface circuit is the interface between the main control module of the battery management system and the external device. The main control module of the battery management system outputs the driving signal to the external device through the module external interface circuit, and the external device inputs the signal to the module through the module external interface circuit. At the same time, the main control module of the battery management system and the external device communicate through the CAN interface; The power circuit converts the 24V power signal from the module's external interface circuit into the 5V power signal required by the module; The switch quantity acquisition circuit filters and isolates the 24V switch quantity signal in the module's external interface circuit and converts it into a 5V switch quantity signal, which is then input to the single-chip microcomputer circuit. The analog quantity acquisition circuit filters and divides the analog quantity signal from the external interface circuit of the module into a voltage signal of 0 to 4V and inputs it to the single-chip microcomputer circuit; The CAN interface circuit completes the physical conversion of CAN bus signals between the microcontroller and the external environment; The single-chip microcomputer circuit analyzes and processes the switch signal, analog signal and CAN bus signal, and then outputs the control signal to the drive circuit and outputs the CAN bus signal to the external device.

2. The battery management system main control module according to claim 1, characterized in that: In the module's external interface circuit, the external connector JP1 uses a 1318384-240 core connector; Connect pins 1 and 2 of the external connector JP1 to the positive electrode network BAT+ of the diode D1 of the power circuit; Pins 21, 22, 33, 34, 35, 36 and 37 of the external connector JP1 are connected to pin 4 of the inductor L1 of the power circuit and the network DGND; Connect pin 3 of external connector JP1 to pin 2 of inductor L11_0 of CAN interface circuit and network CANH0; Connect pin 4 of external connector JP1 to pin 1 of inductor L11_0 of CAN interface circuit and network CANL0; Connect pin 23 of external connector JP1 to the network 0S of the CAN interface circuit; Connect pin 5 of external connector JP1 to pin 2 of inductor L11_1 of CAN interface circuit and network CANH1; Connect pin 6 of external connector JP1 to pin 1 of inductor L11_1 of CAN interface circuit and network CANL1; Connect pin 24 of external connector JP1 to network 1S of CAN interface circuit; Connect the 25th pin of the external connector JP1 to the 2nd pin of the inductor L11_2 of the CAN interface circuit and the network CANH2; Connect the 26th pin of the external connector JP1 to the 1st pin of the inductor L11_2 of the CAN interface circuit and the network CANL2; Connect pin 27 of external connector JP1 to network 2S of CAN interface circuit; Connect pin 7 of external connector JP1 to pin 2 of inductor L11_3 of CAN interface circuit and network CANH3; Connect the 8th pin of the external connector JP1 to the 1st pin of the inductor L11_3 of the CAN interface circuit and the network CANL3; Connect pin 28 of external connector JP1 to network 3S of CAN interface circuit; Connect pin 9 of external connector JP1 to pin 2 of inductor L11_4 of CAN interface circuit and network CANH4; Connect the 10th pin of the external connector JP1 to the 1st pin of the inductor L11_4 of the CAN interface circuit and the network CANL4; Connect pin 29 of external connector JP1 to network 4S of CAN interface circuit; Connect the 11th pin of the external connector JP1 to the 2nd pin of the inductor L11_5 of the CAN interface circuit and the network CANH5; Connect the 12th pin of the external connector JP1 to the 1st pin of the inductor L11_5 of the CAN interface circuit and the network CANL5; Connect pin 30 of external connector JP1 to network 5S of CAN interface circuit; The 13-pin network DOH1, 14-pin network DOH2, 15-pin network DOH3, and 16-pin network DOH4 of the external connector JP1 are respectively connected to the 18-pin network DOH1, 17-pin network DOH2, 14-pin network DOH3, and 13-pin network DOH4 of the chip U4 in the drive circuit; The 17-pin network DOH5, 18-pin network DOH6 and 19-pin network DOH7 of the external connector JP1 are respectively connected to the 18-pin network DOH5, 17-pin network DOH6 and 14-pin network DOH7 of the chip U5 in the drive circuit; Connect the 31-pin network ON of the external connector JP1 to the 1-pin network ON of the capacitor C20 of the switch quantity acquisition circuit; Connect the 32-pin network A+ of the external connector JP1 to the 1-pin network A+ of the capacitor C21 of the switch quantity acquisition circuit; Connect the 20-pin network AI1 of the external connector JP1 to the 1-pin network AI1 of the capacitor C22 of the analog acquisition circuit; Connect the 40-pin network AI2 of the external connector JP1 to the 1-pin network AI2 of the capacitor C26 of the analog acquisition circuit; Connect the 38-pin network AGND of the external connector JP1 to the network AGND of the power circuit; Connect the 39-pin network A5V of the external connector JP1 to the network A5V of the power circuit.

3. The main control module of the battery management system according to claim 1, characterized in that: The power supply circuit includes a diode D1, a diode D2, a diode D3, a diode D4, a diode D18, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, an inductor L1, an inductor L2, a magnetic bead L3, an inductor L5, a magnetic bead L6, a magnetic bead L7, a magnetic bead L8, a magnetic bead L9, a magnetic bead L10, a magnetic bead L12, a resistor R1, a resistor R2, a resistor R50, a resistor R51, and a chip U3, wherein: The chip U3 model is LN5016PHMR-G, the positive pole of the diode D1 is connected to the network BAT+, the negative pole of the diode D1 is connected to the negative pole of the diode D2, the output network P101 signal is used to power the drive circuit, the capacitor C1 is connected in parallel with the diode D2, the pin 1 of the inductor L1 is connected to the network P101; the capacitor C2 is connected between the pins 2 and 3 of the inductor L1, the pin 2 of the inductor L1 is connected to the pin 1 of the inductor L2, the pin 2 of the inductor L2 is connected to the pin 5 of the chip U3, the pin 4 of the inductor L1 is connected to the network DGND, the pin 3 of the inductor L1 is connected to the network GND, the pin 1 of the capacitor C3 is connected to the pin 5 of the chip U3, the capacitor Pin 2 of C3 is connected to network GND, pin 1 of capacitor C4 is connected to pin 5 of chip U3, pin 2 of capacitor C4 is connected to network GND, pin 1 of capacitor C5 is connected to pin 1 of chip U3, pin 2 of capacitor C5 is connected to pin 6 of chip U3, pin 1 of inductor L5 is connected to pin 6 of chip U3, pin 2 of inductor L5 is connected to network +5V, pin 1 of resistor R51 is connected to pin 3 of chip U3, pin 2 of resistor R51 is connected to pin 2 of chip U3 network GND, the positive pole of capacitor C6 is connected to network +5V, the negative pole of capacitor C6 is connected to network GND, pin 1 of capacitor C7 is connected to network +5V, and pin 2 of capacitor C7 is connected to network GND , Pin 1 of resistor R50 is connected to pin 3 of U3, Pin 2 of resistor R50 is connected to network +5V, Pin 1 of magnetic bead L6 is connected to network +5V, Pin 2 of magnetic bead L6 is connected to network +5V-B1, Pin 1 of magnetic bead L7 is connected to network +5V, Pin 2 of magnetic bead L7 is connected to network +5V-B2, Pin 1 of magnetic bead L8 is connected to network +5V, Pin 2 of magnetic bead L8 is connected to network VCC, Pin 1 of magnetic bead L9 is connected to network +5V, Pin 2 of magnetic bead L9 is connected to network A5V, Pin 1 of magnetic bead L10 is connected to network GND, Pin 2 of magnetic bead L10 is connected to network AGND, Pin 31 of external connector JP1 is connected to magnetic bead L3 Pin 1, pin 2 of magnetic bead L3 is connected to the positive electrode of diode D3, the negative electrode of diode D3 is connected to pin 1 of resistor R1, pin 2 of resistor R1 is connected to pin 1 of resistor R2, pin 2 of resistor R2 is connected to network GND, capacitor C8 is connected in parallel with resistor R2, pin 1 of resistor R2 is connected to pin 4 of U3, the negative electrode of diode D4 is connected to pin 4 of U3, the positive electrode of diode D4 is connected to pin 88 of microcontroller U1A, network BMU_LOCK, pin 32 of external connector JP1 is connected to pin 1 of magnetic bead L12, pin 2 of magnetic bead L12 is connected to the positive electrode of diode D18, and the negative electrode of diode D18 is connected to pin 1 of resistor R1.

4. The main control module of the battery management system according to claim 1, characterized in that: The single-chip computer circuit includes chip U1, chip U2, chip U8, internal connector J1, crystal oscillator Y1, capacitor C37, capacitor C38, capacitor C39, capacitor C40, capacitor C41, capacitor C42, capacitor C43, capacitor C44, capacitor C45, capacitor C46, ​​capacitor C47, capacitor C48, capacitor C49, capacitor C50, capacitor C51, capacitor C52, resistor R37, resistor R38, resistor R39, resistor R40, resistor R41, resistor R42, resistor R43, diode D17, among which: Chip U1 and chip U2 are 32-bit Arm Cortex-M4F processors FS32K144HFT0MLLT with a main frequency of up to 112MHz; chip U8 uses LM4040BIM-4.1; internal connector J1 uses DC3-2.54-10PAS; Pin 1 of chip U1 is connected to pin 100 of chip U2, pin 2 of chip U1 is connected to pin 2 of chip U2, pin 99 of chip U1 is connected to pin 99 of chip U2, and pin 100 of chip U1 is connected to pin 1 of chip U2; Pin 8 of chip U1 is connected to pin 5 of CAN interface circuit U9_0, pin 9 of chip U1 is connected to pin 4 of CAN interface circuit chip U9_0, pin 89 of chip U1 is connected to pin 5 of CAN interface circuit chip U9_1, pin 90 of chip U1 is connected to pin 4 of CAN interface circuit chip U9_1, pin 43 of chip U1 is connected to pin 5 of CAN interface circuit chip U9_2, and pin 44 of chip U1 is connected to pin 4 of CAN interface circuit chip U9_2; Pin 8 of chip U2 is connected to pin 5 of CAN interface circuit chip U9_3, pin 9 of chip U2 is connected to pin 4 of CAN interface circuit chip U9_3, pin 89 of chip U2 is connected to pin 5 of CAN interface circuit chip U9_4, pin 90 of chip U2 is connected to pin 4 of CAN interface circuit chip U9_4, pin 43 of chip U2 is connected to pin 5 of CAN interface circuit chip U9_5, and pin 44 of chip U2 is connected to pin 4 of CAN interface circuit chip U9_5; Pin 62 of chip U1 is connected to pin 3 of drive output circuit chip U4, pin 59 of chip U1 is connected to pin 5 of drive output circuit chip U4, pin 58 of chip U1 is connected to pin 7 of drive output circuit chip U4, pin 57 of chip U1 is connected to pin 9 of drive output circuit chip U4, pin 62 of chip U2 is connected to pin 3 of drive output circuit chip U5, pin 59 of chip U2 is connected to pin 5 of drive output circuit chip U5, and pin 58 of chip U2 is connected to pin 7 of drive output circuit chip U5; Pin 45 of chip U1 is connected to pin 1 of resistor R29 of analog quantity acquisition circuit, network AI_HALL1, and pin 46 of chip U1 is connected to pin 1 of resistor R33 of analog quantity acquisition circuit, network AI_HALL2; The 82nd pin of the chip U1 is connected to the 1st pin network CHK1 of the resistor R3 of the switch quantity acquisition circuit, and the 83rd pin of the chip U1 is connected to the 1st pin network CHK2 of the resistor R4 of the switch quantity acquisition circuit; Pin 15 of chip U1 is connected to pin 3 of crystal oscillator Y1, pin 16 of chip U1 is connected to pin 1 of crystal oscillator Y1, resistor R38 is connected in parallel between pins 15 and 16 of chip U1, pin 1 of capacitor C38 is connected to pin 3 of crystal oscillator Y1, pin 2 of capacitor C38 is connected to pin 4 of crystal oscillator Y1 and network GND, pin 1 of capacitor C37 is connected to pin 1 of crystal oscillator Y1, pin 2 of capacitor C37 is connected to network GND, pin 97 of chip U1 is connected to pin 1 of capacitor C52, pin 2 of capacitor C52 is connected to network GND, pin 97 of chip U1 is connected to network +5V-B1 through resistor R39, the cathode of diode D17 is connected to network +5V-B1, and the anode of diode D17 is connected to pin 97 of chip U1; Pin 1 and Pin 2 of the internal connector J1 are connected to the network +5V-B1, Pin 3 and Pin 4 of the internal connector J1 are connected to Pin 97 of the chip U1, Pin 5 of the internal connector J1 is connected to Pin 95 of the chip U1, Pin 6 of the internal connector J1 is connected to Pin 92 of the chip U1, Pin 7 of the internal connector J1 is connected to Pin 98 of the chip U1, Pin 9 of the internal connector J1 is connected to Pin 96 of the chip U1, Pin 8 and Pin 10 of the internal connector J1 are connected to the network GND, Pin 95 of the chip U1 is connected to the network +5V-B1 through resistor R40, and Pin 92 of the chip U1 is connected to the network +5V-B1 through resistor R41; The 98th pin of chip U1 is connected to the network +5V-B1 through resistor R42, and the 96th pin of chip U1 is connected to the network GND through resistor R43. Pin 11 of chip U1 is connected to network A5V, pin 13 of chip U1 is connected to network AGND, capacitor C40 of capacitor C39 is connected in parallel between pins 11 and 13 of chip U1; The 38th, 61st, 87th and 10th pins of chip U1 are connected to the network +5V-B1, and the 37th, 60th, 86th and 14th pins of chip U1 are connected to the network GND. Capacitors C41 and C42 are connected in parallel between the 38th and 37th pins of chip U1, capacitors C43 and C44 are connected in parallel between the 61st and 60th pins of chip U1, capacitors C45 and C46 are connected in parallel between the 87th and 86th pins of chip U1, and capacitors C47 and C48 are connected in parallel between the 10th and 14th pins of chip U1; Capacitors C49, C50 and C51 are connected in parallel between pins 12 and 13 of chip U1. Pin 12 of chip U1 is pulled up to network A5V through resistor R37. Pin 1 of chip U8 is connected to pin 12 of chip U1, and pin 2 of chip U8 is connected to network AGND of pin 13 of chip U1. The peripheral circuit of part B of chip U2 has the same principles as part B of chip U1 except that the power supply is changed from +5V-B1 to +5V-B2.

5. The main control module of the battery management system according to claim 1, characterized in that: The CAN interface circuit is composed of 6 identical circuits, including chip U9_m, capacitor C29_m, capacitor C30_m, capacitor C31_m, capacitor C32_m, capacitor C33_m, capacitor C34_m, capacitor C35_m, capacitor C36_m, resistor R34_m, resistor R35_m, resistor R36_m, inductor L11_m, diode D16_m, m=0,1,2,3,4,5; Chip U9_m uses CAN isolation chip TDH541SCANH with isolated DCDC. Pins 1, 3, 7, 9, and 10 of chip U9_0 are connected to network GND, pins 6 and 8 of chip U9_0 are connected to network VCC, capacitors C29_0 and C30_0 are connected in parallel between pins 8 and 10 of chip U9_0, pins 11, 13, 16, 18, and 20 of chip U9_0 are connected to network CAN_GND0, pins 12 and 19 of chip U9_0 are connected to network CAN_5V0, capacitor C31_0 is connected between pins 20 and 19 of chip U9_0, capacitor C32_0 is connected between pins 13 and 12 of chip U9_0, resistor R34_0 and capacitor C One end of 33_0 is connected in parallel to the network CAN_GND0, and the other end is connected to the network 0S, pin 1 of capacitor C34_0 is connected to pin 1 of L11_0, pin 2 of capacitor C34_0 is connected to the network 0S, pin 3 of diode D16_0 is connected to 0S, pin 1 of diode D16_0 is connected to pin 1 of L11_0, pin 2 of diode D16_0 is connected to pin 2 of L11_0, pin 1 of capacitor C35_0 is connected to pin 2 of L11_0, pin 2 of capacitor C35_0 is connected to the network 0S, pin 1 of resistor R35_0 is connected to pin 2 of L11_0, pin 2 of resistor R35_0 is connected to pin 1 of capacitor C36_0, pin 1 of resistor R36_0 is connected to pin 1 of L11_0, pin 2 of resistor R36_0 is connected to pin 1 of capacitor C36_0, and pin 2 of capacitor C36_0 is connected to the network 0S.

6. The battery management system main control module according to claim 1, characterized in that: The switch quantity acquisition circuit includes resistor R3, resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, resistor R12, chip U7, chip U10, diode D5, diode D6, diode D7, diode D8, capacitor C18, capacitor C19, capacitor C20, capacitor C21, wherein: The chip U7 uses IS3H7C, and the chip U10 uses IS3H7C; In the external interface circuit of the module, the 31-pin network ON of the external connector JP1 is connected to the 1-pin of the capacitor C20 and the 2-pin of the resistor R11, the 2-pin of the capacitor C20 is connected to the network DGND, the 1-pin of the resistor R11 is connected to the positive electrode of the diode D7, the negative electrode of the diode D7 is connected to the 1-pin of the capacitor C18, the 1-pin of the resistor R9, the negative electrode of the diode D5 and the 2-pin of the resistor R7, the 2-pin of the capacitor C18, the 2-pin of the resistor R9 and the positive electrode of the diode D5 are connected to the 2-pin network DGND of the chip U7, the 1-pin of the resistor R7 is connected to the 1-pin of the chip U7, the 3-pin of the chip U7 is connected to the network GND, the 4-pin of the chip U7 is connected to the network +5V-B1 through the pull-up resistor R5, the 4-pin of the chip U7 is connected to the 2-pin of the resistor R3, and the 1-pin of the resistor R3 is connected to the 83-pin network CHK1 of the chip U1; In the external interface circuit of the module, the 32-pin network A+ of the external connector JP1 is connected to the 1-pin of the capacitor C21 and the 2-pin of the resistor R12, the 2-pin of the capacitor C21 is connected to the network DGND, the 1-pin of the resistor R12 is connected to the positive electrode of the diode D8, the negative electrode of the diode D8 is connected to the 1-pin of the capacitor C19, the 1-pin of the resistor R10, the negative electrode of the diode D6 and the 2-pin of the resistor R8, the 2-pin of the capacitor C19, the 2-pin of the resistor R10 and the positive electrode of the diode D6 are connected to the 2-pin network DGND of the chip U10, the 1-pin of the resistor R8 is connected to the 1-pin of the chip U10, the 3-pin of the chip U10 is connected to the network GND, the 4-pin of the chip U10 is connected to the network +5V-B1 through the pull-up resistor R6, the 4-pin of the chip U10 is connected to the 2-pin of the resistor R4, and the 1-pin of the resistor R4 is connected to the 82-pin network CHK2 of the chip U1.

7. The battery management system main control module according to claim 1, characterized in that: The analog quantity acquisition circuit includes capacitor C22, capacitor C23, capacitor C24, capacitor C25, capacitor C26, capacitor C27, capacitor C28, resistor R26, resistor R27, resistor R28, resistor R29, resistor R30, resistor R31, resistor R32, resistor R33, and chip U6, wherein: Chip U6 uses MCP6002T / I / SN. In the module's external interface circuit, the 20-pin network AI1 of the external connector JP1 is connected to pin 1 of capacitor C22, pin 1 of capacitor C23, and pin 1 of resistor R26. Pin 2 of capacitor C22 is connected to network DGND, pin 2 of capacitor C23 is connected to network AGND, pin 2 of resistor R26 is connected to pin 3 of chip U6, pin 1 of resistor R27 is connected to pin 3 of chip U6, pin 2 of resistor R27 is connected to network AGND, and pin 1 of capacitor C24 is connected to network DGND. Connect to pin 3 of chip U6, pin 2 of capacitor C24 to network AGND, pin 1 of resistor R28 to network AGND, pin 2 of resistor R28 to pin 2 of chip U6, pin 2 of chip U6 and pin 1 of chip U6 are short-circuited, pin 8 of chip U6 to network A5V, pin 4 of chip U6 to network AGND, pin 1 of capacitor C25 to between pin 8 of chip U6 and pin 4 of U6, pin 2 of resistor R29 to pin 1 of chip U6, and pin 1 of resistor R29 to pin 45 of chip U1; In the external interface circuit of the module, the 40-pin network AI2 of the external connector JP1 is connected to the 1-pin of capacitor C26, the 1-pin of capacitor C27, and the 1-pin of resistor R30, the 2-pin of capacitor C26 is connected to the network DGND, the 2-pin of capacitor C27 is connected to the network AGND, the 2-pin of resistor R30 is connected to the 5-pin of chip U6, the 1-pin of resistor R31 is connected to the 5-pin of chip U6, the 2-pin of resistor R31 is connected to the network AGND, the 1-pin of capacitor C28 is connected to the 5-pin of chip U6, the 2-pin of capacitor C28 is connected to the network AGND, the 1-pin of resistor R32 is connected to the network AGND, the 2-pin of resistor R32 is connected to the 6-pin of chip U6, the 6-pin of chip U6 is short-circuited with the 7-pin of chip U6, the 2-pin of resistor R33 is connected to the 7-pin of chip U6, and the 1-pin of resistor R33 is connected to the 46-pin of chip U1.

8. The battery management system main control module according to claim 1, characterized in that: The driving circuit includes chip U4, chip U5, resistor R13, resistor R14, resistor R15, resistor R16, resistor R17, resistor R18, resistor R19, resistor R20, resistor R21, resistor R22, resistor R23, resistor R24, resistor R25, capacitor C9, capacitor C10, capacitor C11, capacitor C12, capacitor C13, capacitor C14, capacitor C15, capacitor C16, capacitor C17, diode D9, diode D10, diode D11, diode D12, diode D13, diode D14, diode D15, wherein: Chip U4 and chip U5 use the intelligent high-drive chip BTS724G; Pin 1, Pin 10, Pin 11, Pin 12, Pin 15, Pin 16, Pin 19 and Pin 20 of chip U4 are connected to the network P101 output by the power circuit, Pin 4 of chip U4 is connected to Pin 1 of resistor R13, Pin 2 of resistor R13 is connected to the network VCC, Pin 8 of chip U4 is connected to Pin 1 of resistor R15, Pin 2 of resistor R15 is connected to the network VCC, Pin 2 and Pin 6 ...2 and Pin 6 of chip U4 are connected to the network P101 output by the power circuit, Pin 4 of chip U4 is connected to Pin 1 of resistor R13, Pin 2 of resistor R13 is connected to the network VCC, Pin 2 and Pin 6 of chip U4 are connected to the network P101 output by the power circuit, Pin 4 of chip U4 is connected to Pin 1 of resistor R15, Pin 2 of resistor R15 is connected to the network VCC, Pin 2 and Pin 6 of chip U4 are connected to the network P101 output by the power circuit, Pin 4 of chip U4 is connected to Pin 1 of resistor R13, Pin 2 of resistor R13 is connected to the network VCC, Pin 2 and Pin 6 of chip U4 are connected to the network P101 output by Connect to pin 1 of resistor R14, pin 2 of resistor R14 to network DGND, pin 1 of capacitor C9 to network P101, pin 2 of capacitor C9 to network DGND, pin 1 of capacitor C10 to pin 13 of chip U4, pin 2 of capacitor C10 to network DGND, the cathode of diode D9 to pin 13 of chip U4, the anode of diode D9 to network GND, pin 1 of resistor R19 to pin 13 of chip U4, pin 2 of resistor R19 to network G ND, pin 1 of capacitor C11 is connected to pin 14 of chip U4, pin 2 of capacitor C11 is connected to network DGND, the cathode of diode D10 is connected to pin 14 of chip U4, the anode of diode D10 is connected to network GND, pin 1 of resistor R20 is connected to pin 14 of chip U4, pin 2 of resistor R20 is connected to network GND, pin 1 of capacitor C12 is connected to pin 17 of chip U4, pin 2 of capacitor C12 is connected to network DGND, the cathode of diode D11 is connected to pin 14 of chip U4 Pin 17, the positive electrode of diode D11 is connected to network GND, pin 1 of resistor R21 is connected to pin 17 of chip U4, pin 2 of resistor R21 is connected to network GND, pin 1 of capacitor C13 is connected to pin 18 of chip U4, pin 2 of capacitor C13 is connected to network DGND, the negative electrode of diode D12 is connected to pin 18 of chip U4, the positive electrode of diode D12 is connected to network GND, pin 1 of resistor R22 is connected to pin 18 of chip U4, and pin 2 of resistor R22 is connected to network GND; Pin 1, 10, 11, 12, 15, 16, 19 and 20 of chip U5 are connected to the power circuit output network P101, pin 4 of chip U5 is connected to pin 1 of resistor R16, pin 2 of resistor R16 is connected to network VCC, pin 8 of chip U5 is connected to pin 1 of resistor R18, pin 2 of resistor R18 is connected to network VCC, pin 2 and pin 6 of chip U5 are connected to pin 1 of resistor R17, pin 2 of resistor R17 is connected to network DGND, pin 1 of capacitor C14 is connected to network P101, pin 2 of capacitor C14 is connected to network DGND, pin 1 of capacitor C15 is connected to pin 14 of chip U5, pin 2 of capacitor C11 is connected to network DGND, the cathode of diode D13 is connected to pin 14 of chip U5, diode D13 is connected to pin 14 of chip U5, The positive electrode of the chip is connected to the network GND, the 1st pin of the resistor R23 is connected to the 14th pin of the chip U5, the 2nd pin of the resistor R23 is connected to the network GND, the 1st pin of the capacitor C16 is connected to the 17th pin of the chip U5, the 2nd pin of the capacitor C16 is connected to the network DGND, the negative electrode of the diode D14 is connected to the 17th pin of the chip U5, the positive electrode of the diode D14 is connected to the network GND, the 1st pin of the resistor R24 ​​is connected to the 17th pin of the chip U5, the 2nd pin of the resistor R24 ​​is connected to the network GND, the 1st pin of the capacitor C17 is connected to the 18th pin of the chip U5, the 2nd pin of the capacitor C17 is connected to the network DGND, the negative electrode of the diode D15 is connected to the 18th pin of the chip U5, the positive electrode of the diode D15 is connected to the network GND, the 1st pin of the resistor R25 is connected to the 18th pin of the chip U5, and the 2nd pin of the resistor R25 is connected to the network GND. The 9th pin of the chip U5 and the 13th pin of the chip U5 are not used and are left floating.

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