Type-C interface power supply surge protection design method

Abstract

The invention relates to the technical field of anti-electromagnetic interference, and provides a Type-C interface power supply surge protection design method. Comprising a Type-C interface power supply, and the Type-C interface power supply is composed of a Type-C interface, a transient suppression diode D4 and a chip end. The design method comprises the steps of obtaining an initial circuit schematic diagram and a surge protection requirement of a Type-C interface, and determining rated voltage, rated power and response time of the Type-C interface; determining a first electrical characteristic that the Type-C interface generates low-voltage surge interference according to the rated voltage and the rated power, and configuring multiple TVS transient voltage suppressor diodes at the output end of the Type-C interface to generate a first circuit schematic diagram; acquiring a second electrical characteristic after the configuration of the multiple TVS transient voltage suppressor diodes, and configuring a plurality of common-mode inductance filters at the output ends of the multiple TVS transient voltage suppressor diodes to generate a second circuit schematic diagram; and according to the second circuit schematic diagram, generating a Type-C interface to be verified, and performing a low-voltage surge test.

Description

Technical Field

[0001] The present invention relates to the technical field of Type-C interface, and in particular to a Type-C interface power surge protection design method. Background Art

[0002] With the continuous development of electronic devices, Type-C interface has been widely used in various electronic devices due to its advantages such as high-speed data transmission and fast charging. However, electronic devices may be affected by power surges during use, especially in the current fast charging application field. As the fast charging power is getting higher and higher (currently up to 240W), the corresponding Type-C interface will generate a greater surge when plugged in and unplugged, which is more likely to cause damage to the device.

[0003] At present, the common Type-C interface power surge protection method is to add protection devices to the power network and signal network at the interface. Although this method can provide surge protection to a certain extent, its protection capability for low-voltage surges is limited. It can usually only provide surge voltage protection of about 30V for the power network and 20V for the signal network, and cannot effectively protect against higher surge voltages. Summary of the invention

[0004] The present invention proposes a Type-C interface power surge protection design method, which is used to solve the problem that the Type-C interface power surge protection method in the prior art is to add protection devices on the power network and signal network at the interface. Although this method can provide surge protection to a certain extent, its protection capability for low-voltage surges is limited. It can usually only provide surge voltage protection of about 30V for the power network and about 20V for the signal network, and cannot effectively protect against higher surge voltages.

[0005] The present invention proposes a Type-C interface power supply surge protection design method, including a Type-C interface power supply, the Type-C interface power supply consists of a Type-C interface, a transient suppression diode D4 and a chip end; wherein the input end of the Type-C interface is connected to the transient suppression diode D4, and the output end of the Type-C interface is connected to the chip end, and the design method includes: Obtain the initial circuit schematic and surge protection requirements of the Type-C interface, and determine the rated voltage, rated power, and response time of the Type-C interface; Determine a first electrical characteristic of low-voltage surge interference generated by the Type-C interface according to the rated voltage and the rated power, configure multiple TVS transient voltage suppression diodes at the output end of the Type-C interface, and generate a first circuit schematic diagram; Acquire a second electrical characteristic after configuring multiple TVS transient voltage suppression diodes, and configure multiple common-mode inductor filters at output ends of the multiple TVS transient voltage suppression diodes to generate a second circuit schematic; According to the second circuit schematic, a Type-C interface to be verified is generated, and a low-voltage surge test is performed; When the test result meets the surge protection requirements, the Type-C interface corresponding to the second circuit schematic is used as the target Type-C interface.

[0006] Furthermore, when configuring multiple TVS transient voltage suppression diodes at the output end of the Type-C interface, it also includes: Configure multiple linear resistors before the TVS transient voltage suppression diode.

[0007] Furthermore, when configuring multiple TVS transient voltage suppression diodes at the output end of the Type-C interface, it also includes: An inductive filter L6 is arranged before the TVS diode D4, and a target TVS diode D5 is arranged before the inductive filter L6.

[0008] Furthermore, the first electrical characteristic is an original electrical characteristic of the Type-C interface before any surge protection design is performed; Wherein, the first electrical characteristic includes: Voltage level when the Type-C interface is working normally; The maximum power that the Type-C port can handle under normal operating conditions; The response speed of the Type-C interface to voltage changes; Abnormal behavior of the Type-C interface under low-voltage surge interference, including voltage spikes and current changes.

[0009] Furthermore, the second electrical characteristic refers to the electrical characteristic after multiple TVS transient voltage suppression diodes are configured at the output end of the Type-C interface; The second electrical characteristics include: a breakdown voltage characteristic of a TVS diode, a power characteristic of a TVS diode, a response time of a TVS diode, an impedance characteristic of a circuit, and a filtering strength of a circuit.

[0010] Furthermore, the obtaining of the initial circuit schematic diagram and surge protection requirements of the Type-C interface also includes: Analyze the initial circuit schematic diagram of the Type-C interface circuit, divide it into multiple circuit function groups, and determine the electrical utility characteristics of each circuit function group; wherein the electrical utility characteristics include the connection type defined by the interface electrical characteristics; Determining electrical similarities of multiple circuit functional groups based on electrical utility characteristics; Based on electrical similarity, electrical function groups with electrical similarity above a preset threshold are divided into electrical collection groups; Determine electrical correlation information of each electrical combination group according to electrical utility characteristics and electrical similarity; Technically associate the electrical association information with the corresponding circuit function group to determine the electrical association data of the Type-C interface; According to the electrical related data and surge protection requirements of the Type-C interface, low-voltage surge interference is introduced, and circuit components of the initial circuit schematic diagram of the Type-C interface to be modified are determined.

[0011] Further, the circuit components of the initial circuit schematic diagram of the Type-C interface to be modified are determined, further comprising: Create an analog auxiliary cell library containing TVS diodes, common mode inductors, and filter capacitors; In the RTL design stage, the digital standard cell library and analog auxiliary cell library are called to design the digital-analog mixed circuit of the Type-C interface; According to the mixed digital-analog circuit, the TVS diode is used on the power input terminal and signal line of the Type-C interface to determine the surge protection status of the Type-C interface, and the interference intensity under different component configurations is determined; the interference intensity includes differential mode interference intensity and common mode interference intensity; Based on the interference intensity, the digital backend tool is used to automatically generate the initial layout of the Type-C interface circuit based on the RTL design; Physical verification and simulation are performed on the generated initial layout to simulate surge voltage events and ensure the protection strength of the TVS diode.

[0012] Further, generating a Type-C interface to be verified according to the second circuit schematic diagram and performing a low-voltage surge test includes: Set the surge generator to output a surge waveform that meets actual application conditions; Connect the Type-C port to be verified to the surge generator; Start the surge generator and apply a surge signal to the Type-C interface to be verified in blocking mode and conduction mode; Use an oscilloscope and voltage and current probes to monitor the operating data of the device under test during the surge process; Based on the operating data, the voltage and current stress waveforms in the blocking mode and the conduction mode are compared, and the response characteristics of the Type-C interface to be verified in different states are analyzed.

[0013] Furthermore, in the blocking mode: Setting a controllable power supply system so that it outputs a first voltage stress waveform that meets actual application conditions; Put the Type-C interface to be verified into a blocked state; Start the controllable power system and apply a first voltage stress to the Type-C interface to be verified; Use an oscilloscope and a voltage probe to monitor the voltage waves at both ends of the Type-C interface to be verified and obtain blocking operation data.

[0014] Furthermore, in the conduction mode: Setting a controllable power supply system so that it outputs a second current stress waveform that meets actual application conditions; Put the Type-C interface to be verified into the on state; Start the controllable power system and apply a second current stress to the Type-C interface to be verified; Use an oscilloscope and current probe to monitor the current waveform at both ends of the Type-C interface to be verified and obtain the conduction operation data.

[0015] The beneficial effects of the present invention are: This application only uses TVS as the core protection device, which simplifies the traditional three-level protection structure and reduces costs. The current capacity is improved by connecting multiple TVS in parallel, and the common-mode inductor is combined to suppress high-frequency noise, avoiding the defects of MOV / GDT in low-voltage, high-power Type-C scenarios. Reliable parallel connection is achieved through TVS selection (low dynamic resistance), layout-optimized symmetrical routing, and active current sharing control, which can break through the current limitation of traditional single TVS and replace some functions of MOV. In addition, the common-mode inductor can play a decoupling role in the surge path, delay the surge rise time, reduce the transient pressure of TVS, and form a collaborative protection mechanism of "inductor buffering + TVS clamping". Therefore, the TYPE-C interface obtained under the design method of this application can not only suppress noise, but also assist in surge energy distribution, which may reduce the number or specification requirements of TVS, reduce costs, and realize the current sharing control of TVS parallel connection on the chip side.

[0016] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description and the accompanying drawings.

[0017] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0019] In the attached picture: Figure 1 This is a method flow chart of a Type-C interface power surge protection design method in an embodiment of the present invention; Figure 2 This is a schematic diagram of a first surge protection design circuit for a Type-C interface power supply according to an embodiment of the present invention; Figure 3 This is a schematic diagram of a second surge protection design circuit for a Type-C interface power supply in an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0021] Through theoretical analysis, experimental comparison, and combined with actual design rectification experience, the present invention determines the low-voltage surge voltage level (100V) directly injected into the Type-C port to ensure the normal use of the conventional fast charging mode (≤100W); at the same time, the protection circuit of the Type-C port is optimized to improve the protection capability of the Type-C port; Based on the mechanism of surge interference, while utilizing the discharge and clamping functions of TVS transient voltage suppression diode, a universal protection device, an inductive filter's de-energizing mechanism and secondary clamping discharge measures are additionally added to the power supply end. Since the signal end has to take into account the signal integrity issue, only a small resistor is connected in series as an additional transient suppression measure, thereby improving the protection capability of the Type-C port at a low cost. The power supply end has low anti-interference performance, which causes abnormal charging function when the initial 30V surge is injected, and it can still charge normally when the surge injection is increased to 100V. The signal end may cause data link disconnection when the initial 20V surge injection is increased, and it can still communicate normally when the surge injection is increased to 50V.

[0022] The purpose of the present invention is to provide a Type-C interface power supply surge protection design method proposed by the present invention, including a Type-C interface power supply, the Type-C interface power supply consists of a Type-C interface, a transient suppression diode D4 and a chip end; wherein the input end of the Type-C interface is connected to the transient suppression diode D4, and the output end of the Type-C interface is connected to the chip end, and the design method includes: Obtain the initial circuit schematic and surge protection requirements of the Type-C interface, and determine the rated voltage, rated power, and response time of the Type-C interface; Determine a first electrical characteristic of low-voltage surge interference generated by the Type-C interface according to the rated voltage and the rated power, configure multiple TVS transient voltage suppression diodes at the output end of the Type-C interface, and generate a first circuit schematic diagram; Acquire a second electrical characteristic after configuring multiple TVS transient voltage suppression diodes, and configure multiple common-mode inductor filters at output ends of the multiple TVS transient voltage suppression diodes to generate a second circuit schematic; According to the second circuit schematic, a Type-C interface to be verified is generated, and a low-voltage surge test is performed; a PCB layout of the Type-C interface to be verified is generated through an EDA tool, and then converted and simulated into the Type-C interface to be verified.

[0023] When the test result meets the surge protection requirements, the Type-C interface corresponding to the second circuit schematic is used as the target Type-C interface.

[0024] like Figure 1 and Figure 2 As shown, Figure 2 This is the figure obtained after the design of the present invention is completed. Based on the characteristics of surge interference - transient pulse interference signal, it is directly injected into the Type-C port through CDN (coupling / decoupling network) during testing; C1 and C2 are filter capacitors of the power port; the signal line at the port has TVS transient voltage suppression diodes D1~D3 to the ground (for easy installation, 2-way and 4-way TVS group devices are used, each device contains 2 or 4 independent TVS tubes), which can be used to bypass and discharge transient interference and clamp the voltage on the signal line at a lower level; At the same time, the common-mode inductor filters L1~L5 at the back end can further suppress the residual common-mode interference; a junction capacitor and a high-power transient suppression diode D4 are added to the power supply end for surge protection. This design can ensure the 50V surge protection capability of the Type-C power port (low-voltage surge direct injection) and the 30V surge protection capability of the signal port.

[0025] TVS is usually used as the last level of protection and needs to be used in conjunction with MOV and gas discharge tube. This solution only uses TVS as the core protection device, which simplifies the traditional three-level protection structure and reduces costs. MOV is a voltage-sensitive resistor. When the voltage exceeds its threshold (varistor voltage), the impedance drops sharply and can discharge large currents. The gas discharge tube is ionized and turned on by the internal gas, which can withstand a surge current of tens of kiloamperes, and presents extremely low impedance (close to short circuit) after conduction. In this application, the current capacity is improved by connecting multiple TVS in parallel, and the high-frequency noise is suppressed by combining common-mode inductors to avoid the defects of MOV / GDT in low-voltage, high-power Type-C scenarios. Reliable parallel connection can be achieved through TVS selection (low dynamic resistance), layout-optimized symmetrical routing, and active current sharing control, which can break through the current limit of a traditional single TVS and replace some functions of MOV. In addition, the common-mode inductor can play a decoupling role in the surge path, delay the surge rise time, reduce the transient pressure of the TVS, and form a collaborative protection mechanism of "inductor buffer + TVS clamp". Therefore, the TYPE-C interface obtained by the design of the present application can not only suppress noise, but also assist in the distribution of surge energy, which may reduce the number or specification requirements of TVS and reduce costs. In the present application, the chip side realizes the current sharing control of TVS parallel connection.

[0026] As an embodiment of the present invention: when configuring multiple TVS transient voltage suppression diodes at the output end of the Type-C interface, it also includes: Configure multiple linear resistors before the TVS transient voltage suppression diode (such as Figure 3 (in Chinese: R1, R2, R3).

[0027] In actual implementation, in the traditional solution, MOV / GDT as the front stage bears most of the surge energy, while this embodiment achieves similar hierarchical protection through the combination of resistor + TVS: the resistor realizes primary energy absorption by coarse current limiting, and the TVS acts as a fine clamp to protect the subsequent circuit. In actual implementation, the resistance and power of the resistor need to be customized according to the current of Type-C (such as 5A / 20V) to avoid excessive voltage drop or temperature rise during normal operation. Potentiometers or digitally controlled resistors can also be used to achieve automatic resistance adjustment and automatically adapt to dynamic current.

[0028] As an embodiment of the present invention: when configuring multiple TVS transient voltage suppression diodes at the output end of the Type-C interface, it also includes: An inductive filter L6 is arranged before the TVS diode D4, and a target TVS diode D5 is arranged before the inductive filter L6.

[0029] like Figure 3, first add linear resistors R1~R3 ​​on the signal line at the port (for easy installation, a resistor array is used, each resistor array has 2~4 resistors), the resistance value of R1~R3 ​​is 2.2Ω, and the transient large current surge interference can be effectively reduced after the current limiting effect of the resistor, and then through the transient suppression diodes D1~D3 at the next stage of the port, the transient interference can be further bypassed and discharged, and the voltage on the signal line can be clamped at a lower level; the common mode inductor filter L1~L5 at the last end can also further suppress the residual common mode interference; so that the surge protection at the signal network end can be increased from 30V to 50V; As for the power signal network, on the basis of the original D4, an inductive filter L6 is first added to play a decoupling role. At the same time, due to its high-frequency and high-impedance characteristics, it also has a certain inhibitory effect on transient surges. Then a protection device D5 is added to the back stage of this device to further clamp and discharge the surge, thereby increasing the surge protection capability of the power port from 50V to 100V.

[0030] As an embodiment of the present invention: the first electrical characteristic is the original electrical characteristic of the Type-C interface before any surge protection design is performed; Wherein, the first electrical characteristic includes: Voltage level when the Type-C interface is working normally; The maximum power that the Type-C port can handle under normal operating conditions; The response speed of the Type-C interface to voltage changes; Abnormal behavior of the Type-C interface under low-voltage surge interference, including voltage spikes and current changes.

[0031] In the existing technology, the existing surge protection solutions (such as MOV+TVS combination) usually select devices based on standard surge models (such as 8 / 20μs waveform, 2Ω coupling impedance), without considering the differences in electrical characteristics of specific interfaces. For example: the high power (100W PD) and high-frequency signal transmission of the Type-C interface will cause the parasitic parameters (such as inductance and capacitance) of the surge path to be different from those of the traditional power interface, but the traditional solution has not been optimized in a targeted manner.

[0032] This application provides a customized basis for the design through the first electrical characteristics (original electrical characteristics). The traditional solution directly quotes the standard surge parameters just to meet the standards. This application is based on the actual dynamic characteristics of the interface and makes dynamic adjustments to better adapt to the high-power and high-frequency scenarios of Type-C, that is, high-power scenarios. Then, the second improvement is implemented according to the actual first electrical characteristics to determine the specific structure of the target Type-C interface. Dynamic iterative feature comparison and dynamic update are achieved to reduce the cost in the design process.

[0033] As an embodiment of the present invention: the second electrical characteristic refers to the electrical characteristic after multiple TVS transient voltage suppression diodes are configured at the output end of the Type-C interface; The second electrical characteristics include: a breakdown voltage characteristic of a TVS diode, a power characteristic of a TVS diode, a response time of a TVS diode, an impedance characteristic of a circuit, and a filtering strength of a circuit.

[0034] In actual implementation, existing solutions usually only focus on the independent parameters of TVS (such as breakdown voltage and peak power), and ignore the dynamic synergy effect of multiple TVS in parallel (such as impedance superposition and response time difference). The response time of a single TVS is 1ns, but the overall response delay of multiple TVS in parallel may be up to 5ns due to parasitic parameters. Uneven power distribution of TVS may cause local overheating, but traditional designs do not quantify such risks.

[0035] This application considers the comprehensive electrical characteristics when connected in parallel. Therefore, through a variety of electrical characteristic parameters, the gradient breakdown voltage design of multiple TVS (such as 24V, 24.5V, 25V) is realized to achieve graded discharge of surge energy and avoid current concentration caused by simultaneous conduction. For example: when the surge voltage reaches 24V, the first TVS is turned on first; when the voltage continues to rise to 24.5V, the second TVS joins the diversion, and so on. Reduce the instantaneous pressure of a single TVS and extend the life of the device. Distributed optimization of power characteristics: According to the power distribution data in the second electrical characteristic (such as each TVS bears 30% of the total energy), the TVS layout is dynamically adjusted (such as high-power branches close to the interface pins) to reduce the risk of heat concentration. Through the junction capacitance of multiple TVS (such as 50pF per piece) and the PCB trace inductance (such as 2nH), a controllable LC filter network is formed to provide impedance matching within the surge frequency band (1MHz-100MHz). In response to the delay, this application designs a step-by-step response mechanism by controlling the timing of multiple TVSs on the chip side and taking advantage of the slight difference in TVS response time (such as a 0.5ns step difference): the first TVS (fastest response) handles the initial surge spike, and the subsequent TVSs respond in sequence to cover the long tail of the surge waveform. Although the response time is increased, the surge tolerance of the Type-C interface is improved.

[0036] As an embodiment of the present invention: the obtaining of the initial circuit schematic diagram and surge protection requirements of the Type-C interface further includes: Analyze the initial circuit schematic diagram of the Type-C interface circuit, divide it into multiple circuit function groups, and determine the electrical utility characteristics of each circuit function group; wherein the electrical utility characteristics include the connection type defined by the interface electrical characteristics; Determining electrical similarities of multiple circuit functional groups based on electrical utility characteristics; Based on electrical similarity, electrical function groups with electrical similarity above a preset threshold are divided into electrical collection groups; Determine electrical correlation information of each electrical combination group according to electrical utility characteristics and electrical similarity; Technically associate the electrical association information with the corresponding circuit function group to determine the electrical association data of the Type-C interface; According to the electrical related data and surge protection requirements of the Type-C interface, low-voltage surge interference is introduced, and circuit components of the initial circuit schematic diagram of the Type-C interface to be modified are determined.

[0037] In the above technical solution: In existing technologies, surge protection design usually relies on the experience of engineers, manually adding TVS or MOV at key nodes (such as VBUS, CC lines), and lacks systematic circuit analysis and protection planning. This may lead to over-design and protection loopholes, such as redundant configuration of protection devices in low-risk areas, increasing costs and volume, and ignoring surge risks in atypical paths (such as ESD coupling to data lines). Moreover, traditional technologies mostly design circuits based on demand, optimize protection designs from the perspective of circuit functional group division and electrical similarity, resulting in insufficient matching between device layout and interface characteristics. For example: the electrical characteristics of the power supply group (VBUS) and signal group (CC / SBU) of the Type-C interface are significantly different, but traditional solutions have not designed differentiated protection strategies in a targeted manner.

[0038] This application aims to decompose the Type-C interface circuit into multiple functional groups (such as power supply group, signal group, grounding group), and perform similarity clustering based on electrical utility characteristics (such as voltage level, impedance, noise sensitivity), and uniformly configure protection devices only for high-similarity functional groups (such as multiple VBUS power supply branches) to avoid repeated design. According to electrical correlation information (such as common ground loop coupling path), insert common-mode inductors or TVS at key nodes to block surge propagation. Combine electrical correlation data with surge protection requirements to dynamically generate protection plans. For example: if the electrical similarity of a functional group is high and the surge coupling risk is high, a multi-channel TVS parallel solution is automatically allocated; if there is strong electromagnetic coupling between functional groups (such as high-frequency signal lines and power lines are adjacent), a shielding layer or a common-mode filter is inserted. The electrical similarity calculation uses Euclidean distance or cosine similarity to calculate the electrical characteristic differences of functional components. A preset similarity threshold (such as 0.8) is set, and functional groups above this value are classified into the same electrical set group. In actual implementation, electrical related information such as: power supply group and ground group are coupled through PCB layer, impedance difference between functional groups and layout distance calculation are required.

[0039] As an embodiment of the present invention: the circuit components of the initial circuit schematic diagram of the Type-C interface to be modified are determined, further comprising: Create an analog auxiliary cell library containing TVS diodes, common mode inductors, and filter capacitors; In the RTL design stage, the digital standard cell library and analog auxiliary cell library are called to design the digital-analog mixed circuit of the Type-C interface; According to the mixed digital-analog circuit, determine the surge protection status of the Type-C interface on the power input terminal and signal line of the Type-C interface by using the TVS diode, and determine the differential mode interference strength under different component configurations; the interference strength includes differential mode interference strength and common mode interference strength; Based on the interference intensity, the digital backend tool is used to automatically generate the initial layout of the Type-C interface circuit based on the RTL design; Physical verification and simulation are performed on the generated initial layout to simulate surge voltage events and ensure the protection strength of the TVS diode.

[0040] The technical effects of the above technical solution are: In existing solutions, analog protection devices (TVS, common-mode inductors) and digital circuit design are usually completed in independent stages (e.g., digital logic design is completed first, and protection devices are added manually later), which makes it difficult to optimize the layout of protection devices (e.g., the distance between TVS and high-speed signal lines affects impedance matching). Every time the protection scheme is modified, the layout needs to be redrawn, and automated verification cannot be achieved. Traditional methods rely on later experimental tests (such as surge gun injection) to verify the protection effect, and cannot predict performance through simulation in the early stages of the design, resulting in long development cycles and high costs.

[0041] The present invention constructs an analog auxiliary cell library containing specific circuit components (such as TVS diodes, common-mode inductors, and filter capacitors). These components are key components for power surge protection. In the register transfer level (RTL) design stage, the digital standard cell library and the analog auxiliary cell library are combined to design the digital-analog hybrid circuit of the Type-C interface. This ensures that the circuit contains both a digital logic part and an analog part for surge protection. According to the designed digital-analog hybrid circuit, the surge protection effect of the TVS diode on the power input end and signal line of the Type-C interface, as well as the protection state of the interface under differential mode interference, are analyzed. By analyzing the circuit performance under different component configurations, the intensity of differential mode interference is determined, which is crucial to evaluating the effectiveness of surge protection.

[0042] Use digital backend tools to automatically generate the initial layout of the Type-C interface circuit based on the RTL design. The key to converting circuit design into physical layout. Physical verification and simulation verification are performed on the generated initial layout to ensure that the circuit layout meets the design rules, and the protection strength of the TVS diode is tested by simulating surge voltage events. In the above process, a multi-objective optimization function is introduced using a digital backend tool. In the layout generation stage, the following optimization goals are defined, such as electrical goals, physical goals, and thermal goals; then based on machine learning, the neural network model is trained, with the input being the circuit function group division results, electrical similarity data, and interference strength, and the output being the optimal layout constraints (such as the spacing rules between TVS and data lines). Finally, an adaptive genetic algorithm is used to encode the location coordinates and connection relationship of TVS and common-mode inductors into a gene sequence. In the simulation test, that is, in the process of simulating surge voltage, a surge source is superimposed between VBUS and GND or between the data line (D+ / D-) and the metal casing, and then a hybrid simulation is performed, including building a nonlinear model of TVS and common-mode inductance, extracting the S parameter model of the layout parasitic parameters (wiring inductance, capacitance), calculating the TVS clamping response through time domain simulation (SPICE), and verifying the high-frequency resonance point through frequency domain simulation (EM) to prevent self-oscillation. Finally, a dynamic correction is performed. If the simulation results show that the residual voltage exceeds the standard, the number of TVS or the common-mode inductance value is automatically adjusted, and the layout is regenerated. If the resonant frequency is detected to fall in the surge frequency band, damping is inserted.

[0043] By using analog auxiliary cell libraries and digital standard cell libraries, you can quickly design and implement mixed analog and digital circuits to improve design efficiency. By accurately judging the surge protection status of components such as TVS diodes, you can optimize circuit design and improve protection effects.

[0044] In actual implementation, the analog auxiliary cell library (TVS, common-mode inductor, etc.) is called in the RTL design stage, and the protection device is used as a native part of the circuit design rather than a later patch. The calling method is based on hardware description language instructions or pre-set API interfaces. For example: Instantiate the TVS module in the Verilog code and define its electrical parameters (such as clamping voltage and junction capacitance). Optimize the physical distance between the signal path and the protection device through the mixed layout of digital standard cell libraries (such as logic gates, IO cells) and analog cells. Dynamically adjust the component configuration based on the differential mode / common mode interference strength to form a closed-loop design process: inject the surge model into the digital-analog hybrid circuit to calculate the interference strength. If the differential mode interference exceeds the standard, increase the number of TVS or reduce its dynamic resistance; if the common mode interference exceeds the standard, insert a common mode inductor or adjust the grounding strategy. According to the optimization results, the physical layout containing the protection device is automatically generated through the digital back-end tool (such as Cadence Innovus). Simulate surge events (such as 8 / 20μs waveforms) in the physical verification stage, and directly evaluate the clamping effect of TVS through simulation, replacing traditional experimental tests and shortening the development cycle.

[0045] As an embodiment of the present invention: generating a Type-C interface to be verified according to the second circuit schematic diagram and performing a low-voltage surge test includes: Set the surge generator to output a surge waveform that meets actual application conditions; Connect the Type-C port to be verified to the surge generator; Start the surge generator and apply a surge signal to the Type-C interface to be verified in blocking mode and conduction mode; Use an oscilloscope and voltage and current probes to monitor the operating data of the device under test during the surge process; Based on the operating data, the voltage and current stress waveforms in the blocking mode and the conduction mode are compared, and the response characteristics of the Type-C interface to be verified in different states are analyzed.

[0046] In this application, a surge generator is configured to output the working conditions of the Type-C interface in actual application (surge events of the Type-C interface in real scenarios (hot plug, protocol switching, load mutation) are collected by a high-speed oscilloscope, the instantaneous current is monitored, the characteristic parameters are determined, and then a dynamic waveform is formed by superposition of multiple pulses), and the surge waveform that may be encountered is determined by integrating the frequency, amplitude and number of pulses of the Type-C interface to be verified on the time axis to ensure that the test conditions are consistent with the actual working conditions. Connect the Type-C interface to be tested to the surge generator and prepare for the surge test. Start the surge generator in blocking mode (PD protocol not completed, power supply not activated, high impedance state, simulating surge events at the moment of device plugging and unplugging, protocol negotiation failure or standby state) and conduction mode (handshake protocol completed, power supply activated, low impedance state, simulating surge events when the device is working at full load, data transmission or dynamic power adjustment (such as 20V→5V switching)), apply surge signals to the Type-C interface to be verified, and simulate surge events in actual use; use an oscilloscope and voltage and current probes to monitor the voltage and current changes of the Type-C interface in real time during the surge process, record the operating data and compare the voltage and current stress waveforms in the blocking mode and the conduction mode, and determine the response characteristics of the Type-C interface in different states through joint analysis of the spectrum and time domain, and evaluate its protection effect.

[0047] Existing surge tests are usually based on standard waveforms, but the surge waveforms in the actual working conditions of the Type-C interface (such as hot plugging and fast charging) may contain high-frequency oscillations or multiple pulse superpositions, resulting in a disconnect between the test results and the real scene. Traditional methods only test in a single working mode (such as the on state), ignoring the differences in surge response of the device in the blocking mode (such as standby, protocol handshake), resulting in incomplete coverage of the protection design. This application captures the real working scenarios of the Type-C interface (such as voltage transients during PD protocol switching and VBUS hot plug jitter), builds a multi-dimensional surge waveform library (such as a composite waveform with superimposed high-frequency noise), replaces a single standard waveform, and improves the authenticity of the test. For example, a surge model triggered by the USB PD protocol is preset in the surge generator (such as a voltage drop superimposed with a 1MHz oscillation when switching from 20V to 5V). Surges are injected in the blocking mode (such as CC line without handshake) and the on mode (such as full load power supply), and the protection blind area is identified by comparing the voltage stress waveforms (such as peak value, rise time) and current path distribution of the two modes. For example, in blocking mode, surge energy may be coupled to the data line through parasitic capacitance, and in conduction mode, the low impedance of the VBUS path causes surge current concentration. Based on the comparative analysis results, the protection strategy is dynamically adjusted. For example, if the residual voltage of the data line exceeds the standard in blocking mode, increase the number of TVS of the data line; if the common-mode noise is significant in conduction mode, optimize the layout of the common-mode inductor.

[0048] As an embodiment of the present invention: in the blocking mode: Setting a controllable power supply system so that it outputs a first voltage stress waveform that meets actual application conditions; Put the Type-C interface to be verified into a blocked state; Start the controllable power system and apply a first voltage stress to the Type-C interface to be verified; Use an oscilloscope and a voltage probe to monitor the voltage waves at both ends of the Type-C interface to be verified and obtain blocking operation data.

[0049] In the actual implementation process, the controllable power supply needs to output the first voltage stress waveform to simulate the complex voltage changes in the real scene (such as plug-in surge, power transient, EFT group pulse, etc.). Then, the Type-C interface is put into blocking mode through logical control (such as CC pin configuration) or physical disconnection, and the controllable power supply is connected to the VBUS (or CC / SBU pin) of the interface to be tested, and a dynamic voltage waveform is applied. Finally, the real-time voltage waveform at both ends of the interface is captured by an oscilloscope to analyze the characteristics such as overshoot, oscillation, and clamping response. Determine the peak voltage tolerance value, voltage drop time, waveform distortion, and leakage current (need to cooperate with a current probe). Traditional tests mostly use static voltage (such as withstand voltage test), while this solution simulates the dynamic stress of the real scene through a programmable voltage waveform, which is closer to the actual failure mode (such as cumulative damage caused by repeated plugging and unplugging). By focusing on the reliability of the Type-C interface in the non-working state, it makes up for the shortcomings of traditional testing that only focuses on the conduction mode (for example, avoiding damage caused by accidental voltage intrusion when the device is in standby). By capturing transient responses, voltage waveform characteristics can be correlated with physical damage (such as insulation breakdown and FET breakdown), providing a direct basis for failure analysis.

[0050] As an embodiment of the present invention: in the conduction mode: Setting a controllable power supply system so that it outputs a second current stress waveform that meets actual application conditions; Put the Type-C interface to be verified into the on state; Start the controllable power system and apply a second current stress to the Type-C interface to be verified; Use an oscilloscope and current probe to monitor the current waveform at both ends of the Type-C interface to be verified and obtain the conduction operation data.

[0051] In actual implementation, the controllable power supply system is configured to output the second current stress waveform (e.g., waveform shape, amplitude range, time characteristics). The second current stress waveform is not a standard pulse, but a complex waveform designed according to the actual application scenario (e.g., current jump and load step in the PD protocol). The waveform generation is based on the PD protocol state machine trigger. In the prior art, because the current measurement may involve factors such as large current rapid switching and impedance matching between the current source and the load, the current measurement and monitoring are difficult, and the voltage is monitored. However, the present application simulates the working condition, so the current monitoring can be realized. The Type-C interface is placed in the on state, and the current waveform details (e.g., overshoot, oscillation, recovery time) are captured in real time in combination with the interface on state (e.g., VBUS active power supply, CC pin negotiation completed) to prepare for the current stress test. The controllable power supply system is started to apply the second current stress to the Type-C interface to be verified. The current waveform at both ends of the Type-C interface is monitored using an oscilloscope and a current probe to obtain the operating data in the on mode. The traditional current test method cannot reflect the impact of dynamic current stress in actual working conditions (e.g., current mutation caused by PD protocol negotiation, load competition when multiple devices are connected in parallel). The above solution has more realistic failure mode coverage (such as current overshoot causing MOSFET burning and inductor saturation), and can also perform data-driven optimization and guide the selection of protection devices through waveform analysis, such as matching the fuse blowing characteristics with the current rise rate.

[0052] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A Type-C interface power surge protection design method, characterized in that: The invention comprises a Type-C interface power supply, wherein the Type-C interface power supply comprises a Type-C interface, a transient suppression diode D4 and a chip end; wherein the input end of the Type-C interface is connected to the transient suppression diode D4, and the output end of the Type-C interface is connected to the chip end, and the design method comprises: Obtain the initial circuit schematic and surge protection requirements of the Type-C interface, and determine the rated voltage, rated power, and response time of the Type-C interface; Determine a first electrical characteristic of low-voltage surge interference generated by the Type-C interface according to the rated voltage and the rated power, configure multiple TVS transient voltage suppression diodes at the output end of the Type-C interface, and generate a first circuit schematic diagram; Acquire a second electrical characteristic after configuring multiple TVS transient voltage suppression diodes, and configure multiple common-mode inductor filters at output ends of the multiple TVS transient voltage suppression diodes to generate a second circuit schematic; According to the second circuit schematic, a Type-C interface to be verified is generated, and a low-voltage surge test is performed; When the test result meets the surge protection requirements, the Type-C interface corresponding to the second circuit schematic is used as the target Type-C interface.

2. A Type-C interface power surge protection design method as claimed in claim 1, characterized in that: When configuring multiple TVS transient voltage suppression diodes at the output end of the Type-C interface, it also includes: Configure multiple linear resistors before the TVS transient voltage suppression diode.

3. A Type-C interface power surge protection design method as claimed in claim 1, characterized in that: When configuring multiple TVS transient voltage suppression diodes at the output end of the Type-C interface, it also includes: An inductive filter L6 is arranged before the TVS diode D4, and a target TVS diode D5 is arranged before the inductive filter L6.

4. A Type-C interface power surge protection design method as claimed in claim 1, characterized in that: The first electrical characteristic is the original electrical characteristic of the Type-C interface before any surge protection design is performed; Wherein, the first electrical characteristic includes: Voltage level when the Type-C interface is working normally; The maximum power that the Type-C port can handle under normal operating conditions; The response speed of the Type-C interface to voltage changes; Abnormal behavior of the Type-C interface under low-voltage surge interference, including voltage spikes and current changes.

5. A Type-C interface power surge protection design method as claimed in claim 1, characterized in that: The second electrical characteristic refers to the electrical characteristic after multiple TVS transient voltage suppression diodes are configured at the output end of the Type-C interface; The second electrical characteristics include: a breakdown voltage characteristic of a TVS diode, a power characteristic of a TVS diode, a response time of a TVS diode, an impedance characteristic of a circuit, and a filtering strength of a circuit.

6. A Type-C interface power surge protection design method as claimed in claim 1, characterized in that: The obtaining of the initial circuit schematic diagram and surge protection requirements of the Type-C interface also includes: Analyze the initial circuit schematic diagram of the Type-C interface circuit, divide it into multiple circuit function groups, and determine the electrical utility characteristics of each circuit function group; wherein the electrical utility characteristics include the connection type defined by the interface electrical characteristics; Determining electrical similarities of multiple circuit functional groups based on electrical utility characteristics; Based on electrical similarity, electrical function groups with electrical similarity above a preset threshold are divided into electrical collection groups; Determine electrical correlation information of each electrical combination group according to electrical utility characteristics and electrical similarity; Technically associate the electrical association information with the corresponding circuit function group to determine the electrical association data of the Type-C interface; According to the electrical related data and surge protection requirements of the Type-C interface, low-voltage surge interference is introduced, and circuit components of the initial circuit schematic diagram of the Type-C interface to be modified are determined.

7. A Type-C interface power surge protection design method as claimed in claim 6, characterized in that: The circuit components of the initial circuit schematic diagram of the Type-C interface to be modified are determined, and further include: Create an analog auxiliary cell library containing TVS diodes, common mode inductors, and filter capacitors; In the RTL design stage, the digital standard cell library and analog auxiliary cell library are called to design the digital-analog mixed circuit of the Type-C interface; According to the mixed digital-analog circuit, the TVS diode is used on the power input terminal and signal line of the Type-C interface to determine the surge protection status of the Type-C interface, and the interference intensity under different component configurations is determined; the interference intensity includes differential mode interference intensity and common mode interference intensity; Based on the interference intensity, the digital backend tool is used to automatically generate the initial layout of the Type-C interface circuit based on the RTL design; Physical verification and simulation are performed on the generated initial layout to simulate surge voltage events and ensure the protection strength of the TVS diode.

8. A Type-C interface power surge protection design method as claimed in claim 1, characterized in that: The method of generating a Type-C interface to be verified according to the second circuit schematic diagram and performing a low-voltage surge test includes: Set the surge generator to output a surge waveform that meets actual application conditions; Connect the Type-C port to be verified to the surge generator; Start the surge generator and apply a surge signal to the Type-C interface to be verified in blocking mode and conduction mode; Use an oscilloscope and voltage and current probes to monitor the operating data of the device under test during the surge process; Based on the operating data, the voltage and current stress waveforms in the blocking mode and the conduction mode are compared, and the response characteristics of the Type-C interface to be verified in different states are analyzed.

9. A Type-C interface power surge protection design method as claimed in claim 8, characterized in that: In the blocking mode: Setting a controllable power supply system so that it outputs a first voltage stress waveform that meets actual application conditions; Put the Type-C interface to be verified into a blocked state; Start the controllable power system and apply a first voltage stress to the Type-C interface to be verified; Use an oscilloscope and a voltage probe to monitor the voltage waves at both ends of the Type-C interface to be verified and obtain blocking operation data.

10. A Type-C interface power surge protection design method as claimed in claim 8, characterized in that: In the conduction mode: Setting a controllable power supply system so that it outputs a second current stress waveform that meets actual application conditions; Put the Type-C interface to be verified into the on state; Start the controllable power system and apply a second current stress to the Type-C interface to be verified; Use an oscilloscope and current probe to monitor the current waveform at both ends of the Type-C interface to be verified and obtain the conduction operation data.

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