Miller clamp circuit for driving wide band gap high voltage power devices

Abstract

A Miller clamp circuit for driving a wide band gap (WBG) device is provided. In one embodiment, a Miller clamp circuit includes a semiconductor switching device having a high level terminal and a low level terminal, the high level terminal being connected to a gate of the wide band gap device and the low level terminal being connected to a source of the wide band gap device; a first diode having an anode connected to a ground terminal of a driver chip and a cathode connected to a control terminal of the semiconductor switching device; the first resistor is connected in parallel with the first diode; a second resistor having a first end connected to a ground terminal of the driving chip; a second diode having an anode connected to a low level terminal of the semiconductor switching device and a cathode connected to a second terminal of the second resistor; and a third resistor connected in parallel with the second diode. The Miller clamp circuit is configured to simultaneously suppress misturn-on and gate loop oscillation of a wide band gap high voltage power device.

Description

Technical Field

[0001] The present invention relates to a voltage clamping technology, and more particularly to a Miller clamping circuit for simultaneously suppressing mis-turn-on and gate loop oscillation of a wide bandgap high voltage power device. Background Art

[0002] Widebandgap (WBG) power devices, such as silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) and gallium nitride (GaN) high-electron-mobility transistors (HEMTs), can operate at higher frequencies and temperatures than traditional silicon-based power devices with similar voltage and current ratings, making them the devices of choice for many high-efficiency and high-power-density converters. However, for widebandgap power devices to operate at appropriately high speeds, parasitic inductances, especially in the gate loop, must be carefully managed.

[0003] First, parasitic inductance hinders gate current during switching transients, slowing down switching and increasing switching losses. Second, parasitic inductance in series with gate capacitance can cause gate loop oscillations, which can cause false turn-on during switching given the relatively low threshold voltages of some commercial wide bandgap power devices. Third, parasitic inductance can also cause sizable positive and negative gate voltage pulses (also known as crosstalk) on the off device when adjacent devices switch. Since mainstream wide bandgap power devices (especially SiC MOSFETs) have a limited minimum gate voltage allowed, typically between -3 and -10V, positive pulses can also cause false turn-on, while negative pulses can cause excessive stress on the gate.

[0004] One solution to suppress false turn-on is to use a gate driver with a Miller clamp function to suppress gate pulses caused by crosstalk. However, Miller clamping cannot solve the other two problems caused by parasitic inductance, namely, reduced switching speed and false turn-on caused by ringing. In addition, the performance of Miller clamping can be affected by parasitic inductance during fast switching transients of wide bandgap power devices.

[0005] Another solution is to use a negative OFF-state gate voltage to turn off the device. The negative OFF-state gate voltage leaves a wider margin below the threshold voltage to accommodate gate voltage pulses / oscillations caused by crosstalk and ringing, thereby suppressing false turn-on. However, negative gate bias can increase reverse conduction losses in SiC MOSFETs and GaN high electron mobility transistors, which has an adverse effect. Most importantly, from a reliability perspective, negative OFF-state gate voltage may cause the gate bias to enter an unsafe range, especially when a negative gate pulse occurs. Negative gate overstress and increased reverse conduction losses can be mitigated by adopting a two-phase turn-off scheme, that is, first turning off the wide bandgap high-voltage power device with a negative OFF gate voltage, and then actively shifting the negative OFF gate voltage back to zero before the negative pulse occurs. However, this comes at the cost of complex drive circuits. Some methods use passive components for level shifting, but this has an adverse effect on the on-state conduction losses due to the reduction of the on-state gate voltage. Summary of the invention

[0006] An object of the present invention is to provide a clamping circuit that can be used with a unipolar gate driver with a gate turn-off voltage of 0 volts (Volt, V). The clamping circuit is intended to achieve Miller clamping and negative gate voltage spike clamping for wide bandgap high voltage power devices, thereby simultaneously suppressing mis-turn-on and protecting the gate of the wide bandgap high voltage power device from overstress.

[0007] According to a first aspect of the present invention, a Miller clamp circuit for driving a wide bandgap high voltage power device is provided. The wide bandgap device may be a silicon carbide metal oxide semiconductor field effect transistor (MOSFET) having a gate, a drain and a source. The Miller clamp circuit includes a semiconductor switch device, a first diode, a first resistor, a second resistor, a second diode and a third resistor. The semiconductor switch device has a high level end and a low level end, the high level end is connected to the gate of the wide bandgap device, and the low level end is connected to the source of the wide bandgap device. The first diode has an anode and a cathode, the anode is connected to the ground terminal of the driving chip, and the cathode is connected to the control terminal of the semiconductor switch device. The first resistor is connected in parallel with the first diode. The second resistor has a first end connected to the ground terminal of the driving chip. The second diode has an anode and a cathode, the anode is connected to the low level end of the semiconductor switch device, and the cathode is connected to the second end of the second resistor. The third resistor is connected in parallel with the second diode. The Miller clamp circuit is configured to simultaneously suppress mis-turn-on and gate loop oscillation of the wide bandgap power device.

[0008] According to a second aspect of the present invention, a gate clamp driving circuit is provided for driving the wide bandgap device. The Miller clamp driving circuit comprises a driving chip and the Miller clamp circuit according to the first aspect of the present invention. The driving chip has at least a driving terminal, a power supply terminal and a ground terminal.

[0009] In one embodiment, the semiconductor switching device is a high-electron-mobility-transistor (HEMT), whose drain is the high-level end of the semiconductor switching device, the source is the low-level end of the semiconductor switching device, and the gate is the control terminal of the semiconductor switching device.

[0010] In one embodiment, the high electron mobility transistor is a gallium nitride (GaN) high electron mobility transistor.

[0011] In one embodiment, the GaN high electron mobility transistor is a low voltage GaN high electron mobility transistor. The GaN high electron mobility transistor has a rated voltage, and the rated voltage is higher than the on-gate voltage for driving the wide bandgap device. The GaN high electron mobility transistor has a threshold voltage, and the threshold voltage is lower than the threshold voltage for driving the wide bandgap device.

[0012] In one embodiment, the GaN high electron mobility transistor is an enhancement mode GaN high electron mobility transistor.

[0013] In one embodiment, the resistance value of the first resistor is between 0.1 ohms (Ω) and 10,000 ohms.

[0014] In one embodiment, the resistance value of the second resistor is between 0.1 ohms (Ω) and 10,000 ohms.

[0015] In one embodiment, the resistance value of the third resistor is between 0.1 ohms (Ω) and 10000 ohms.

[0016] The provided Miller clamp drive circuit uses low voltage GaN HEMTs to implement two functions - negative gate voltage pulse clamping and Miller clamping. Thanks to the fast switching speed of low voltage GaN HEMTs, the gate voltage of high voltage power devices can be well clamped within positive and negative safety thresholds. The gate turn-off voltage V GS-offThe unipolar driving scheme is not only simpler, but also reduces the reverse conduction loss of high-voltage power devices. In addition, since the low-voltage GaN high-electron-mobility transistor can bypass part of the gate loop parasitic inductance, it can also suppress the gate loop oscillation and the resulting mis-conduction, thereby increasing the switching speed and further reducing the switching loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The specific implementation modes of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0018] Figure 1 FIG. 1 is a schematic diagram of a Miller clamp driving circuit 100 for driving a wide bandgap high voltage power device according to an embodiment of the present invention.

[0019] Figures 2A to 2D The operating mechanism of the Miller clamp driving circuit in one embodiment of the present invention is illustrated.

[0020] Figure 3 A half-bridge circuit is shown for verifying the Miller clamping and negative pulse clamping performance of the Miller clamping driver circuit disclosed in the present application.

[0021] FIG. 4A to FIG. 4C The conventional unipolar driver (i.e., gate turn-off voltage V GS-off =0V), gate turn-off voltage V GS-off = -4V bipolar driver and the Miller clamp drive circuit disclosed in this application, the gate-source positive voltage (V GS )pulse.

[0022] FIG. 5A to FIG. 5C The conventional unipolar driver (i.e., gate turn-off voltage V GS-off =0V), gate turn-off voltage V GS-off =-4V bipolar driver and the crosstalk of the Miller clamp drive circuit disclosed in this application cause the gate-source negative voltage (V GS )pulse.

[0023] Figure 6 A half-bridge test circuit is shown for evaluating the switching process and switching loss of a device under test with different gate drive circuits.

[0024] Fig. 7A and 7B The waveforms of the device under test during the turn-off process of a conventional unipolar driver with two different gate resistance values ​​are respectively shown. Figure 7C The waveforms of the device under test using the Miller clamp driver circuit disclosed in the present application during the turn-off process are shown.

[0025] Fig. 8A and 8B The turn-on loss and turn-off loss of the LS DUT with different gate drivers are shown respectively. DETAILED DESCRIPTION

[0026] In the following description, the details of the present invention will be described as preferred embodiments. It will be apparent to those skilled in the art that modifications, including additions and / or substitutions, may be made without departing from the scope and spirit of the present invention. Specific details may be omitted so as not to obscure the present invention; however, the present disclosure is written to enable those skilled in the art to practice what the present invention teaches without undue experimentation.

[0027] Figure 1 A circuit diagram of a Miller clamp driving circuit 100 for driving a wide bandgap high voltage power device in one embodiment of the present invention is shown. The wide bandgap high voltage power device may be a silicon carbide (SiC) metal oxide semiconductor field effect transistor (metal-oxide-semiconductor field-effect transistor, MOSFET) or a gallium nitride (gallium nitride, GaN) high electron mobility transistor (high-electron-mobility-transistor, HEMT). As shown in the figure, the Miller clamp driving circuit 100 includes a driving chip 101 and a Miller clamp circuit 102.

[0028] The driver chip 101 has at least a driving terminal, a power supply terminal and a ground terminal. The driver chip is a simple unipolar gate driver. When the driver chip is controlled / commanded to turn off the wide bandgap high voltage power device, a 0-VV GS-off Voltage.

[0029] The Miller clamp circuit 102 has a first terminal T1, a second terminal T2 and a third terminal T3. The first terminal T1 is connected to the ground terminal of the driving chip 101, the second terminal T2 is connected to the gate of the wide bandgap device, and the third terminal T3 is connected to the source of the wide bandgap device.

[0030] The Miller clamp circuit 102 is configured to suppress both mis-turn-on and gate loop oscillation of a wide bandgap device.

[0031] In one embodiment, the Miller clamp circuit 102 includes a semiconductor switch device Q1, a first diode D1, and a first resistor R1. The semiconductor switch device Q1 has a high level end and a low level end, the high level end is connected to the second terminal T2 (i.e., the gate of the wide bandgap device), and the low level end is connected to the third terminal T3 (i.e., the source of the wide bandgap device). The first diode D1 has an anode and a cathode, the anode is connected to the first terminal T1 (i.e., the ground terminal of the driving chip 101), and the cathode is connected to the control terminal of the semiconductor switch device Q1. The first resistor R1 is connected in parallel with the first diode D1.

[0032] The Miller clamp circuit 102 further includes a second resistor R2, a second diode D2, and a third resistor R3. The second resistor R2 has an anode connected to the first diode (i.e., the first terminal T1), the second diode D2 has an anode connected to the low level end of the semiconductor switching device Q1 (i.e., the third terminal T3), and the third resistor R3 is connected in parallel with the second diode D2.

[0033] In a preferred embodiment, the resistance value of the first resistor R1 is between 0.1 ohms (Ω) and 10,000 ohms, the resistance value of the second resistor R2 is between 0.1 ohms (Ω) and 10,000 ohms, and the resistance value of the third resistor R3 is between 0.1 ohms (Ω) and 10,000 ohms.

[0034] In a preferred embodiment, the semiconductor switch device Q1 is a low voltage high electron mobility transistor. The low voltage high electron mobility transistor has a drain, a source and a gate. The drain is the high level end of the semiconductor switch device Q1, the source is the low level end of the semiconductor switch device Q1, and the gate is the control terminal of the semiconductor switch device Q1.

[0035] In a preferred embodiment, the high electron mobility transistor Q1 is an enhancement-mode (E-mode) gallium nitride high electron mobility transistor, whose rated voltage is higher than the on-gate voltage of the driving wide bandgap device, for example, 20 volts (V), and whose rated current is higher than the maximum current flowing through the driving circuit, for example, 2 amperes (Ampere, A).

[0036] Figures 2A to 2D The operation mechanism of the Miller clamp driving circuit in one embodiment of the present invention is illustrated. In the detailed description of the present invention below, a high voltage SiC MOSFET is used as an example to illustrate the high voltage power device that needs to be driven, although the Miller clamp driving circuit can also be applied to a high voltage GaN high electron mobility transistor.

[0037] like Figure 2A As shown in the figure, during the conduction process, the low voltage GaN high electron mobility transistor Q1 is stabilized in the off state, while the driver chip provides current to charge the gate source capacitance of the SiC MOS field effect transistor, thereby turning on the high voltage power device. The conduction speed can be adjusted by the gate resistor R2.

[0038] like Figure 2B As shown in the figure, during the shutdown process, the gate loop current can be shunted to the gate-source capacitance of the low-voltage GaN high-electron-mobility transistor Q1 through the electrical path (i). Therefore, the high-electron-mobility transistor Q1 can be turned on and provide an additional discharge path (ii) for the gate charge of the SiC MOSFET, thereby accelerating the shutdown process. At the same time, due to the parasitic inductance L p It will be bypassed by the discharge path (ii) provided by the high electron mobility transistor Q1, and the gate loop oscillation can also be suppressed.

[0039] like Figure 2C As shown in FIG. 1 , the positive gate voltage pulse caused by the Miller effect also undergoes a similar clamping process. Compared with the high voltage SiC MOSFET to be driven, the gate-source capacitance of the lateral low voltage GaN high electron mobility transistor Q1 is much smaller and the switching speed is much faster. Therefore, before the high voltage SiC MOSFET to be driven is mis-turned on, the low voltage GaN high electron mobility transistor Q1 can be turned on. Thus, an electrical path (ii) is provided to clamp the positive gate pulse of the high voltage power device, effectively suppressing the mis-turned on caused by crosstalk.

[0040] like Figure 2D As shown in FIG. 1 , the Miller clamp drive circuit also provides protection for the gate of the high voltage power device by suppressing the negative gate voltage pulse. The reverse conduction of the low voltage GaN high electron mobility transistor Q1 suppresses the amplitude of the negative gate voltage pulse through the electrical path (iii), thereby protecting the gate of the high voltage power device from negative gate overstress.

[0041] Figure 3A half-bridge circuit is shown for verifying the Miller clamp and negative pulse clamp performance of the Miller clamp driver circuit disclosed in the present application. The half-bridge circuit uses two identical high voltage silicon carbide metal oxide semiconductor field effect transistors, and both are driven by a driver circuit. Due to the crosstalk between the high-side (HS) device under test (DUT) and the low-side (LS) device under test, the turn-on process of the high-side device will generate a gate voltage positive pulse on the low-side DUT, which may cause false turn-on. The turn-off process of the high-side device will generate a gate voltage negative pulse on the low-side DUT, which may cause excessive stress on the gate of the DUT.

[0042] FIG. 4A to FIG. 4C The conventional unipolar driver (V GS-off =0V), gate turn-off voltage V GS- The gate-source positive voltage (V GS ) pulse. Figure 4A As shown in Figure 1, with a conventional unipolar driver, the gate-source voltage positive pulse exceeds the V TH , which can lead to misleading communication. Figure 4B As shown, with a V of -4V GS-off The bipolar driver at V TH The following produces a wider margin to accommodate the positive pulse. However, the gate voltage oscillates beyond V GS-min , which can lead to undesirable gate overstress. Figure 4C As shown in Figure 1, when the Miller clamp drive circuit is used, the gate-source voltage positive pulse is well clamped at the V of the SiC MOSFET. TH below, thus effectively suppressing false turn-on without the need for a negative turn-off voltage V GS-off .

[0043] FIG. 5A to FIG. 5C The conventional unipolar driver (i.e., gate turn-off voltage V GS-off =0V), gate turn-off voltage V GS The crosstalk between the bipolar driver with -off=-4V and the Miller clamp driver circuit disclosed in this application causes the gate-source voltage (V GS ) negative pulse. Figure 5A As shown, even with a medium V SiC MOSFET, the DSAt the slew rate (i.e., 45V / ns), the gate of the SiC MOSFET will also experience a slight overvoltage. Figure 5B As shown, with a V of -4V GS-off The bipolar driver of the current-carrier-type gate driver exhausts the margin for accommodating negative gate voltage pulses, resulting in severe gate overstress when negative pulses occur. Figure 5C As shown, in contrast, the 0V V GS-off The driver retains the negative gate voltage margin, while the reverse conduction of the low-voltage GaN high-electron-mobility transistor helps to suppress the gate negative pulse. Therefore, the gate of the SiC MOSFET can be effectively protected from negative gate overstress.

[0044] Figure 6 The following diagram shows a half-bridge test circuit used to characterize the switching process and switching loss of a low-voltage side DUT under different gate drive circuits.

[0045] Fig. 7A and 7B The waveforms of the low-side DUT during the turn-off process of a conventional unipolar driver with two different gate resistor values ​​(i.e., R3) are depicted respectively. As shown in the figure, reducing the gate resistor of the conventional unipolar gate driver can accelerate C GS However, the gate loop oscillation will intensify, resulting in false turn-on, which will affect the reduction of switching losses.

[0046] Figure 7C The waveform of the low-voltage side device under test using the Miller clamp driver circuit disclosed in this application during the turn-off process is shown in the figure. As shown in the figure, the large current discharge capability of the low-voltage GaN high electron mobility transistor helps to accelerate the C of the metal oxide semiconductor field effect transistor. GS At the same time, since the low-voltage GaN high-electron-mobility transistor can bypass part of the parasitic inductance of the gate loop, it can also suppress the gate loop oscillation and the resulting misconduction.

[0047] Fig. 8A and 8B The turn-on and turn-off losses of the low-side DUT with different gate drivers are plotted separately.

[0048] like Fig. 8A As shown, compared with the traditional unipolar driver, the -4V V GS-offThe proposed bipolar driver can suppress false turn-on, thus eliminating the associated additional switching losses. However, the bipolar driver undesirably increases reverse conduction losses in the circuit and overstresses the gate of the SiC MOSFET. Due to the effective Miller clamping function provided by the low voltage GaN high electron mobility transistor, the presented driver exhibits similar turn-on losses as the bipolar driver at all current levels, indicating that false turn-on is also successfully suppressed.

[0049] like Figure 8B As shown, the turn-off losses of silicon carbide metal oxide semiconductor field effect transistors using traditional unipolar drivers and the provided drivers are compared. For the traditional unipolar driver, reducing the gate resistance value (i.e., R3) from 5.6 ohms to 2 ohms can speed up the turn-off process and reduce switching losses. However, further reducing the gate resistance value will increase switching losses at moderate current levels because the gate loop oscillation will intensify, resulting in mis-conduction and related additional switching losses. By using the driver provided by the present invention, the turn-off loss is significantly reduced, which is a direct benefit of accelerating the turn-off process and suppressing the gate loop oscillation.

[0050] Although the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not restrictive. The drawings are not necessarily drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the descriptions in the present disclosure and the actual devices. The present disclosure may also have other embodiments that are not specifically described. Modifications may be made to specific situations, materials, material compositions, methods or processes to comply with the objectives and scope of protection of the present disclosure. All these modifications are within the scope of the claims attached hereto. Although the methods disclosed herein are described with reference to specific operations performed in a specific order, it is understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations are not limited.

Claims

1. A Miller clamp circuit for driving a wide bandgap high voltage power device, characterized in that: include: A semiconductor switch device having a high level end and a low level end, wherein the high level end is connected to the gate of the wide bandgap device, and the low level end is connected to the source of the wide bandgap device; A first diode having an anode and a cathode, wherein the anode is connected to a ground terminal of the driving chip, and the cathode is connected to a control terminal of the semiconductor switch device; A first resistor is connected in parallel with the first diode; a second resistor having a first end connected to a ground terminal of the driving chip; a second diode having an anode and a cathode, wherein the anode is connected to the low level end of the semiconductor switch device, and the cathode is connected to the second end of the second resistor; as well as A third resistor is connected in parallel with the second diode; as well as The Miller clamp circuit is configured to simultaneously suppress mis-turn-on and gate loop oscillation of a wide bandgap high voltage power device.

2. The Miller clamp circuit according to claim 1, characterized in that: The semiconductor switching device is a high-electron-mobility-transistor (HEMT), which has a drain, a source and a gate, the drain is the high-level end of the semiconductor switching device, the source is the low-level end of the semiconductor switching device, and the gate is the control terminal of the semiconductor switching device.

3. The Miller clamp circuit according to claim 2, characterized in that: The high electron mobility transistor is a gallium nitride (GaN) high electron mobility transistor.

4. The Miller clamp circuit according to claim 3, characterized in that: The GaN high electron mobility transistor is a low voltage GaN high electron mobility transistor having a rated voltage and a threshold voltage, wherein the rated voltage is higher than an on-state gate voltage of a wide bandgap high voltage power device, and the threshold voltage is lower than a threshold voltage of the wide bandgap device.

5. The Miller clamp circuit according to claim 4, characterized in that: The GaN high electron mobility transistor is an enhancement mode GaN high electron mobility transistor.

6. The Miller clamp circuit according to claim 1, characterized in that: The resistance value of the first resistor is between 0.1 ohm (Ω) and 10000 ohm.

7. The Miller clamp circuit according to claim 1, characterized in that: The resistance value of the second resistor is between 0.1 ohms and 10000 ohms.

8. The Miller clamp circuit according to claim 1, characterized in that: The resistance value of the third resistor is between 0.1 ohm and 10000 ohm.

9. A Miller clamp driving circuit for driving a wide bandgap high voltage power device, characterized in that: include: A driving chip, comprising at least a driving terminal, a power supply terminal and a ground terminal; as well as The Miller clamp circuit of claim 1.

10. The Miller clamp driving circuit according to claim 9, characterized in that: The semiconductor switching device is a high-electron-mobility-transistor (HEMT), which has a drain, a source and a gate, the drain is the high-level end of the semiconductor switching device; the source is the low-level end of the semiconductor switching device, and the gate is the control terminal of the semiconductor switching device.

11. The Miller clamp driving circuit according to claim 10, characterized in that: The high electron mobility transistor is a gallium nitride (GaN) high electron mobility transistor.

12. The Miller clamp driving circuit according to claim 11, characterized in that: The GaN high electron mobility transistor is a low voltage GaN high electron mobility transistor having a rated voltage and a threshold voltage, wherein the rated voltage is higher than an on-state gate voltage of the wide bandgap device, and the threshold voltage is lower than a threshold voltage of the wide bandgap device.

13. The Miller clamp driving circuit according to claim 12, characterized in that: The low voltage gallium nitride high electron mobility transistor is an enhancement mode gallium nitride high electron mobility transistor.

14. The Miller clamp circuit according to claim 9, characterized in that: The resistance value of the first resistor is between 0.1 ohm (Ω) and 10000 ohm.

15. The Miller clamp circuit according to claim 9, characterized in that: The resistance value of the second resistor is between 0.1 ohms and 10000 ohms.

16. The Miller clamp circuit according to claim 9, characterized in that: The resistance value of the third resistor is between 0.1 ohm and 10000 ohm.

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