Hybrid buck converter and method of operation thereof

Abstract

There is provided a hybrid buck converter including: a first PMOS transistor and a second PMOS transistor electrically connecting a supply voltage node with a first switching node; a first NMOS transistor and a second NMOS transistor electrically connecting a ground node and the first switch node; an inductor electrically connecting the first switching node and the second switching node; a third NMOS transistor electrically connecting the second switch node and the first output node; a third PMOS transistor electrically connecting the second switch node and the second output node; a shunt regulator driven based on a second output voltage of the second output node; a first PWM controller adjusting the magnitude of the inductive current based on pulse width control of the first PMOS transistor and the first NMOS transistor; and a second PWM controller adjusting a magnitude of the second output voltage based on pulse width control of the third PMOS transistor and the third NMOS transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0135395 filed on October 11, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0186295 filed on December 19, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0003] Embodiments of the inventive concept relate to a hybrid buck converter, and more particularly, to a hybrid buck converter for high-speed transient response and high dynamic efficiency and an operating method thereof. Background Art

[0004] High-performance parallel processing technologies such as artificial intelligence and machine learning have become common and are expanding into various fields beyond image and speech recognition. Due to the nature of having to process large amounts of data at high speed, processors that perform high-performance computing are required, and technical requirements to be overcome are constantly emerging. For example, the amount of power required by processors to perform high-performance computing is constantly increasing. In proportion to the increasing power requirements, high thermal design power and high heat consumption costs may be incurred, and many resources may be consumed for heat dissipation.

[0005] Dynamic voltage scaling techniques may be used in high performance computing processors where power varies according to processing throughput to effectively control power utilization, and to achieve higher efficiency, it may be necessary to increase the tracking speed of dynamic voltage scaling. A hybrid buck converter has been proposed that adds a shunt regulator in parallel with the buck converter to increase the tracking speed of dynamic voltage scaling.

[0006] However, compared to a buck converter with 100% ideal power conversion efficiency, the efficiency of the proposed hybrid buck converter decreases exponentially due to the frequent operation of the shunt regulator resulting in power loss. Therefore, it may be necessary to reduce this efficiency reduction in a hybrid buck converter supporting dynamic voltage scaling. Summary of the invention

[0007] The inventive concept provides a hybrid buck converter having high dynamic efficiency while maintaining a high-speed transient response, and a method of operating the hybrid buck converter.

[0008] According to one aspect of the present invention, a hybrid buck converter is provided, comprising: a buck converter, comprising a first P-channel metal oxide semiconductor (PMOS) transistor and a second PMOS transistor electrically connecting a power supply voltage node to a first switch node, a first N-channel metal oxide semiconductor (NMOS) transistor and a second NMOS transistor electrically connecting a ground node to the first switch node, and an inductor electrically connecting the first switch node to the second switch node; a third NMOS transistor electrically connecting the second switch node to the first output node; a third PMOS transistor electrically connecting the second switch node to the second output node; a shunt regulator driven based on a second output voltage corresponding to the second output node; a first pulse width modulation (PWM) controller, adjusting the magnitude of an inductor current flowing through the inductor based on pulse width control of the first PMOS transistor and the first NMOS transistor; and a second PWM controller, adjusting the magnitude of the second output voltage based on pulse width control of the third PMOS transistor and the third NMOS transistor.

[0009] According to another aspect of the present invention, there is provided an operating method of a hybrid buck converter, the operating method comprising: determining whether an inductor current flowing through an inductor of the buck converter is N times the shunt current output from a shunt regulator; performing pulse width control between a high-side switch element and a low-side switch element of the buck converter according to the determination; and performing pulse width control between a third NMOS transistor and a third PMOS transistor based on a comparison result of a second output voltage with a second reference voltage, wherein the high-side switch element may electrically connect a power supply voltage to a first switch node corresponding to a first end of the inductor, the low-side switch element may electrically connect a ground node to the first switch node, the third PMOS transistor may electrically connect a second output node corresponding to a second output voltage to a second switch node corresponding to a second end of the inductor, and the third NMOS transistor may electrically connect the second switch node to a first output node corresponding to the first output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram showing an electronic device and an external power supply according to an embodiment;

[0012] Figure 2 is a detailed block diagram of a power management integrated circuit (PMIC) according to an embodiment;

[0013] Figure 3A is a circuit diagram of a hybrid buck converter according to a comparative example;

[0014] Figure 3B is a diagram showing the operation of a hybrid buck converter according to a comparative example;

[0015] Figure 4 is a circuit diagram of a hybrid buck converter according to an embodiment;

[0016] Figure 5A is a circuit diagram of a hybrid buck converter including a push-pull controller according to an embodiment;

[0017] Figure 5B is a flow chart illustrating a method of operating a hybrid buck converter according to an embodiment;

[0018] Fig. 6A is a circuit diagram of a hybrid buck converter including a first pulse width modulation (PWM) controller according to an embodiment;

[0019] Figure 6B is a flow chart illustrating a method of operating a hybrid buck converter according to an embodiment;

[0020] Fig. 7A is a circuit diagram of a hybrid buck converter including a second PWM controller according to an embodiment;

[0021] Figure 7B is a flow chart illustrating a method of operating a hybrid buck converter according to an embodiment;

[0022] Figure 7C An example of power loss reduction according to an embodiment is shown;

[0023] Fig.7D is a diagram showing an example in which a second reference voltage is changed according to an embodiment;

[0024] Fig. 8A is a circuit diagram of a hybrid buck converter including a hysteretic controller according to an embodiment;

[0025] Figure 8B shows an example of a third reference voltage according to an embodiment;

[0026] Figure 8C is a flow chart illustrating a method of operating a hybrid buck converter according to an embodiment; and

[0027] Fig. 9 is a pair of graphs illustrating the efficiency improvement of a hybrid buck converter according to an embodiment. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same components in the figure are marked with the same reference numerals, and their repeated description is omitted. The term "and / or" used herein includes any and all combinations of one or more of the associated listed items. It should be noted that the various aspects described for an embodiment can be incorporated into different embodiments, although not specifically described in this regard. That is, the features of all embodiments and / or any embodiment can be combined in any manner and / or combination. In this specification, although terms such as first, second, etc. are used to describe various elements or components, it is self-evident that these elements or components are not limited by these terms. These terms are only used to distinguish a single element or component from other elements or components.

[0029] Figure 1 is a block diagram illustrating an electronic device 100 and an external power source 110 according to an embodiment.

[0030] refer to Figure 1 , an electronic device 100 and an external power source 110 are shown. In order to charge a battery 103 included in the electronic device 100, the electronic device 100 and the external power source 110 may be electrically connected to each other in a wired or wireless manner.

[0031] In various embodiments, the electronic device 100 may include various electronic devices that can be carried by a user. For example, the electronic device 100 may be a mobile device, such as a smart phone, a tablet personal computer PC, a mobile phone, a personal digital assistant (PDA), a notebook computer, a wearable device, a global positioning system (GPS) device, an e-book terminal, a digital broadcast terminal, an MP3 player, a digital camera, etc. For another example, the electronic device 100 may be an electric vehicle.

[0032] According to an embodiment, the electronic device 100 may include a power management integrated circuit (PMIC) 101. The PMIC 101 may be implemented as an integrated circuit chip and may be mounted on a printed circuit board (PCB). The PMIC 101 may charge the battery 103 by receiving power from an external power source 110 and transmitting the received power to the battery 103, and may transmit power to the system load 102 to control the electronic device 100 to perform various functions. Figure 2 The detailed configuration of the PMIC 101 is described in FIG.

[0033] In addition, the electronic device 100 may include a battery 103. The battery 103 may include at least one battery cell. For example, the battery 103 may correspond to a multi-cell battery including a plurality of battery cells electrically connected in series with each other. As another example, the battery 103 may correspond to a single-cell battery including one battery cell. When the electronic device 100 is electrically connected to the external power source 110, the battery 103 may receive power through the PMIC 101. When the electronic device 100 is not connected to the external power source 110, the battery 103 may provide power to the system load 102 to control the electronic device 100 to perform various functions.

[0034] In addition, the electronic device 100 may include a system load 102. Although not shown, the system load 102 may include components other than the PMIC 101 and the battery 103 in the electronic device 100. For example, the system load 102 may include a display, an application processor, a communication processor, a speaker, a memory, etc. That is, the system load 102 may represent a chip, a module, an operation block, a functional block, and an intellectual property (IP) block included in the electronic device 100. The system load 102 may receive power from the external power source 110 or the battery 103 and provide various functions to the user. For example, a monitor in the system load 102 may provide visual recognition to the user by displaying an object on a display, a communication processor may send and receive data by exchanging wireless signals with an external device, and an application processor may perform various operations.

[0035] In addition, the electronic device 100 may include a socket interface 104. The socket interface 104 may electrically connect the electronic device 100 to an external power source 110 via a universal serial bus (USB) cable. In an embodiment, the socket interface 104 may correspond to a USB type-C interface, and the USB cable may correspond to a USB type-C cable. The USB Type-C interface may be implemented based on the definition of USB 2.0, USB 3.1, or USB 3.2. The socket interface 104 may include a plurality of pins. The plurality of pins may include a pin for power supply, a pin for data transmission, and a configuration channel (CC) pin.

[0036] The external power source 110 may supply power to the electronic device 100. According to various embodiments, the external power source 110 may include a travel adapter (TA) 111 and a wireless charger 112. Instead of supplying power through a wire, the wireless charger 112 may wirelessly transmit power through the air to charge the electronic device 100. According to various embodiments, the wireless charger 112 may transmit power based on various wireless charging methods, such as a magnetic induction method, a magnetic resonance method, and an electromagnetic induction method, and a non-radioactive wireless charging method (WiTricity).

[0037] The TA 111 may be powered by a wire connected to the PMIC 101 of the electronic device 100. The TA 111 may convert power provided from an alternating current (AC) 110V to 220V (which may be a household power source or other power supply device (e.g., a computer)) into direct current (DC) power required to charge the battery 103, and provide the converted DC power to the electronic device 100. According to various embodiments, the socket interface 104 may be electrically connected to an output terminal of the auxiliary battery.

[0038] Figure 2 is a detailed block diagram of a power management integrated circuit (PMIC) 200 according to an embodiment.

[0039] Figure 2 The PMIC 200 may correspond to Figure 1 The electronic device 100 includes a PMIC 101. Figure 2 , the PMIC 200 may include a control circuit 220 , a direct charger 230 , a switching charger 240 , an input current limiter (ICL) 210 , a fuel meter 260 , and a power meter 250 .

[0040] The ICL 210 may adjust the magnitude of the input current. For example, when the system load 102 is also operating while the battery 103 is being charged, the magnitude of the input current input to the PMIC 200 may correspond to the sum of the charging current for charging the battery and the load current transmitted to the system load 102. When the magnitude of the input current increases, the overload of the PMIC 200 may increase the risk of fire. Therefore, the ICL 210 may control the magnitude of the input current not to exceed a predetermined magnitude. Although not shown, the ICL 210 may include an internal transistor resistor. When the magnitude of the input current exceeds a predetermined magnitude, the magnitude of the internal transistor resistor may increase according to a control signal received from the control circuit 220. Since the magnitude of the external power supply voltage is constant, the magnitude of the input current may be reduced by increasing the magnitude of the internal transistor resistor.

[0041] The control circuit 220 may control the overall operation of the PMIC 200. The control circuit 220 may communicate with the TA 111 through the socket interface 104. For example, the control circuit 220 may control the output voltage and output current of the TA 111 by transmitting control information to the TA 111.

[0042] The switching charger 240 includes a buck converter and can reduce the input voltage and adjust the charging current by adjusting the cycle of the buck converter. Since the switching charger 240 includes an inductor, the switching loss and the conduction loss caused by the resistance component of the inductor itself may not be eliminated. Therefore, the charging efficiency of the switching charger 240 may be lower than the charging efficiency of the direct charger 230.

[0043] The direct charger 230 can directly transmit the input voltage to the battery 103 through the capacitive voltage divider. Since the direct charger 230 only includes a transistor and a capacitor, the switching loss and the conduction loss caused by the resistance component of the inductor itself can be saved. Since the input voltage can be directly transmitted to the node of the battery 103 through the capacitive voltage divider, the direct charger 230 can be suitable for a high-efficiency charging system.

[0044] The fuel gauge 260 may sense the state of the battery 103. For example, the fuel gauge 260 may sense the state of charge (SoC), charging voltage, charging current, and battery temperature of the battery 103. The SoC is a ratio of the current capacity of the battery 103 to the maximum capacity and may be defined in units of percentage (%).

[0045] Although not shown, the fuel gauge 260 may include an analog-to-digital converter (ADC). The fuel gauge 260 may digitally convert the analog information of the sensed voltage, current, and temperature through the ADC, and transmit the digital information to the direct charger 230, the switching charger 240, and / or the system load 102. The fuel gauge 260 may be implemented as part of an integrated circuit chip and may be mounted on a printed circuit board. However, the embodiment is not limited thereto, and the fuel gauge 260 and the PMIC 200 may be implemented as different integrated circuits or integrated circuit chips.

[0046] The power meter 250 can obtain information of input / output voltage and current. The power meter 250 can sense the magnitude of the voltage and current input to the PMIC 200 and the magnitude of the voltage and current transmitted to the system load 102.

[0047] Although not shown, the power meter 250 includes an ADC, and the sensed voltage, current, and power information may be digitally converted using the ADC, and the digital information may be transmitted to the direct charger 230, the switch charger 240, and / or the system load 102. The power meter 250 may be implemented as part of an integrated circuit chip and may be mounted on a printed circuit board. However, the embodiment is not limited thereto, and the power meter 250 and the PMIC 200 may be implemented as different integrated circuits or integrated circuit chips.

[0048] Although not shown, the PMIC 200 may further include a circuit or block supporting at least one of various functions such as an undervoltage lockout (UVLO) function, an overcurrent protection (OCP) function, an overvoltage protection (OVP) function, a soft start function for reducing inrush current, a foldback current limiting function, a hiccup mode function for short circuit protection, an overtemperature protection (OTP) function, etc., so as to operate normally even under power saving conditions.

[0049] According to an embodiment, the switching charger 240 may include a DC-DC converter. For example, the DC-DC converter may correspond to a hybrid buck converter. The hybrid buck converter is a heterogeneous parallel converter and may represent, for example, a DC-DC converter in which different buck converters and shunt regulators are connected in parallel. Hereinafter, a hybrid buck converter according to a comparative example and a hybrid buck converter according to an embodiment of the inventive concept will be described.

[0050] Figure 3A is a circuit diagram of a hybrid buck converter 300 according to a comparative example, and Figure 3B is a graph showing efficiency loss as a function of operating voltage scaling frequency according to a comparative example.

[0051] refer to Figure 3A , the hybrid buck converter 300 according to the comparative example may include a buck converter 310 and a shunt regulator 320 connected to each other in parallel.

[0052] The buck converter 310 may include a PMOS transistor M P , NMOS transistor M N , inductor L and capacitor C OUT . PMOS transistor M P and NMOS transistor M N For example, if it is necessary to increase the load current I input to the system load 102 LOAD , the PMOS transistor M can be turned on alternately P and NMOS transistor M N , so that the PMOS transistor M P The conduction time increases, and the NMOS transistor M N As another example, if it is necessary to reduce the load current I input to the system load 102 LOAD , the PMOS transistor M can be turned on alternately P and NMOS transistor M N , so that the PMOS transistor M P The conduction time of the NMOS transistor M is reduced. N The on time increases.

[0053] The shunt regulator 320 may include a PMOS transistor M PH and NMOS transistor M NH The shunt regulator 320 can control the PMOS transistor M PH and NMOS transistor M NH , to achieve high-speed transient response. For example, if it is necessary to increase the load current I input to the system load 102 LOAD, the shunt regulator 320 can control the PMOS transistor M PH is turned on to transfer the charging current I CH Added to the transient load current I LOAD , so that the load current I LOAD As another example, if it is necessary to reduce the load current I input to the system load 102 LOAD , the shunt regulator 320 can control the NMOS transistor M NH turn-on, to take the transient load current I LOAD Subtract the discharge current I DCH , so that the load current I LOAD Quickly enter a stable state.

[0054] refer to Figure 3B , the X-axis of the graph represents the frequency of dynamic voltage scaling, and the Y-axis of the graph represents the efficiency loss. For example, whenever dynamic voltage scaling occurs, the hybrid buck converter 300 according to the comparative example operates to reduce the charging current I CH Added to the load current I LOAD Or from the load current I LOAD Subtract the discharge current I DCH However, power loss occurs every time the shunt regulator 320 operates, and the power loss may be proportional to the magnitude of the voltage drop (eg, the supply voltage V DD With the output voltage V OUT ) and may also be proportional to the shunt current (e.g., the charging current I CH With the discharge current I DCH That is, the reference Figure 3B , it can be confirmed that the efficiency loss increases rapidly as the frequency of dynamic voltage scaling increases.

[0055] Figure 4 is a circuit diagram of a hybrid buck converter 400 according to an embodiment.

[0056] refer to Figure 4 , the hybrid buck converter 400 may include a buck converter 410 and a shunt regulator 420. In addition, in addition to the hybrid buck converter 300 according to the comparative example, the hybrid buck converter 400 may further include a third NMOS transistor M N3 , the third PMOS transistor M P3 , the fourth NMOS transistor M N4 , coupling capacitor C C , the second output capacitor C OUT2 and the third output capacitor C OUT3 .

[0057] According to an embodiment, the first NMOS transistor M of the hybrid buck converter 400 is N1 and the second NMOS transistor M N2 The first PMOS transistor M of the hybrid buck converter 400 is P1 and the second PMOS transistor M P2 Can be called a high-side switching element.

[0058] According to an embodiment, the hybrid buck converter 400 may further include a third NMOS transistor M N3 , the third PMOS transistor M P3 and the second output capacitor C OUT2 The coupling capacitor C C The third NMOS transistor M N3 can be electrically connected to the second switch node L X2 and the first output node OUT 1 The third PMOS transistor M P3 can be electrically connected to the second switch node L X2 and the second output node OUT 2 According to an embodiment, the third NMOS transistor M N3 and the third PMOS transistor M P3 The third NMOS transistor M N3 and the third PMOS transistor M P3 Alternating conduction can control the second output node OUT 2 The voltage level of the second output node OUT 2 The voltage may correspond to the second output voltage V OUT2 The second output node OUT 2 may be a node for driving the shunt regulator 420. That is, the shunt regulator 420 may be based on the second output voltage V OUT2 The coupling capacitor C C The first output node OUT 1 The second output node OUT 2 Coupling capacitor C C can correspond to the first output node OUT 1 The first output voltage V OUT1 The second output node OUT 2 The second output voltage V OUT2 The AC current flows through the electrical path between. That is, the first output voltage V OUT1 and the second output voltage V OUT2 Based on the third PMOS transistor M P3 and the third NMOS transistor M N3The duty cycle of the first output capacitor C OUT1 , the second output capacitor C OUT2 , and coupling capacitor C C Make adjustments.

[0059] According to an embodiment, the hybrid buck converter 400 may further include a fourth NMOS transistor M N4 and the third output capacitor C OUT3 The fourth NMOS transistor M N4 The first switch node L X1 The third output node OUT 3 The fourth NMOS transistor M N4 The third output capacitor C OUT3 For example, when the third output capacitor C OUT3 is charged and the third output node OUT 3 When the voltage level exceeds the first threshold, the fourth NMOS transistor M N4 When the fourth NMOS transistor M N4 When turned on, a third output capacitor C OUT3 The charge stored in the inductor generates the inductor current I IND That is, the fourth NMOS transistor M N4 The third output capacitor C OUT3 stores the discharge current, and when the third output capacitor C OUT3 When the charge stored in the fourth NMOS transistor M exceeds a predetermined reference value, the fourth NMOS transistor M N4 can be turned on to reuse the stored charge as the inductor current I IND The following will refer to FIG. 8A to FIG. 8C This is described in detail.

[0060] According to an embodiment, the shunt regulator 420 may include a coarse regulator 421 and a fine regulator 423. The coarse regulator 421 may include a second output node OUT 2 The first output node OUT 1 Connect the rough PMOS transistor M CP And the first output node OUT 1 The third output node OUT 3 Connect the rough NMOS transistor M CN . Rough PMOS transistor M CP The charging current can be adjusted to adjust the first output node OUT 1 For example, a rough PMOS transistor M CP 32 PMOS transistors may be included.CP The input to the first output node OUT can be controlled based on the on or off of the 32 PMOS transistors. 1 The shunt current I SHUNT For example, as the number of on transistors among the 32 PMOS transistors increases, the input to the first output node OUT 1 The charging current increases, causing the shunt current I SHUNT The size increases.

[0061] Rough NMOS transistor M CN The discharge current can be adjusted to adjust the first output node OUT 1 For example, a rough NMOS transistor M CN 32 NMOS transistors may be included. CN The input to the first output node OUT can be controlled based on the on or off of the 32 NMOS transistors. 1 The shunt current I SHUNT For example, as the number of on transistors among the 32 NMOS transistors increases, the first output node OUT 1 Discharge to the third output node OUT 3 The discharge current increases, and the shunt current I SHUNT The size can be reduced.

[0062] The fine adjuster 423 may include a second output node OUT 2 The first output node OUT 1 Connect the fine PMOS transistor M FP . Fine PMOS transistor M FP The charging current can be adjusted to adjust the first output node OUT 1 For example, the fine PMOS transistor M FP 128 PMOS transistors may be included. FP The input to the first output node OUT can be controlled based on the on or off of the 128 PMOS transistors. 1 The shunt current I SHUNT For example, as the number of on transistors among the 128 PMOS transistors increases, the input to the first output node OUT 1 The charging current increases, causing the shunt current I SHUNT Due to the fine PMOS transistor M FP Rougher PMOS transistor M CP More transistors are included so that the charging current can be regulated more finely or precisely.

[0063] In the above embodiment, the rough PMOS transistor M CP and a rough NMOS transistor M CN Each includes 32 power MOSFETs, and the fine PMOS transistor M FP 128 power MOSFETs are included, but the embodiment is not limited thereto. According to various embodiments, the rough PMOS transistor M may be variably set. CP , coarse NMOS transistor M CN and fine PMOS transistor M FP However, in some embodiments, the fine PMOS transistor M FP The number of power MOSFETs in the CP The number of power MOSFETs in the

[0064] Figure 5A is a circuit diagram of a hybrid buck converter 500 including a push-pull controller 510 according to an embodiment.

[0065] refer to Figure 5A ,Apart from Figure 4 In addition to the hybrid buck converter 400 , the hybrid buck converter 500 may further include a push-pull controller 510 .

[0066] According to an embodiment, the push-pull controller 510 may control the on or off of the shunt regulator 420. The push-pull controller 510 may be referred to by various terms, such as a shunt controller, a transient controller, etc. The push-pull controller 510 may receive a first output voltage V OUT1 , that is, the first output node OUT 1 The push-pull controller 510 can be from ( Figure 2 The power meter 250 of the PMIC 200 receives the first output voltage V OUT1 The push-pull controller 510 can receive a first reference voltage V REF1 The push-pull controller 510 can be operated from ( Figure 2 The control circuit 220 of the PMIC 200 receives a first reference voltage V REF1 . The first reference voltage V REF1 can be changed by the control circuit 220. For example, the control circuit 220 can determine to perform dynamic voltage scaling. The control circuit 220 can increase or decrease the first reference voltage V REF1 The value of the first output node OUT is changed 1 The first output voltage V OUT1 , thereby changing the load current I LOAD .

[0067] According to an embodiment, the push-pull controller 510 may not generate the control signal PG32 or NG32 of the coarse regulator 421. For example, the hybrid buck converter 500 may be in a stable state. The stable state may refer to that as the first output voltage V OUT1 becomes close to the first reference voltage V REF1 , the first output node OUT 1 and load current I LOAD When the hybrid buck converter 500 is in a stable state, there is no need to quickly reduce or increase the shunt current I by driving the rough regulator 421. SHUNT Therefore, the push-pull controller 510 may not generate the control signal PG 32 or NG 32 for driving the coarse regulator 421. However, even in the stable state, the hybrid buck converter 500 may generate the control signal PG 128 of the fine regulator 423 to make the first output voltage V OUT1 Successfully track the first reference voltage V REF1 .

[0068] According to an embodiment, the push-pull controller 510 may simultaneously generate the control signal PG32 or NG32 of the coarse regulator 421 and the control signal PG128 of the fine regulator 423. For example, the hybrid buck converter 500 may be in a transient state. The transient state may refer to the first output voltage V OUT1 With the first reference voltage V REF1 That is, the transient state may correspond to the first output voltage V OUT1 and the first reference voltage V REF1 For example, the control circuit 220 can change the first reference voltage V by determining the dynamic voltage scaling. REF1 In this case, it may be necessary to change the shunt current I SHUNT , so that the first output voltage V OUT1 and load current I LOAD The push-pull controller 510 can quickly enter a stable state. REF1 With the first output voltage V OUT1 The control signal PG_32 or NG_32 for driving the coarse regulator 421 is compared, and based on the comparison result, the control signal PG_32 or NG_32 for driving the coarse regulator 421 is generated. However, even in this case, the control signal PG_128 for the fine regulator 423 may be generated. For example, the control signal PG_128 may be generated together with the control signal PG_32 or NG_32 for the coarse regulator 421. For example, the first reference voltage V REF1 The push-pull controller 510 can increase the first reference voltage V REF1 Increase the shunt current I SHUNTThe size of the first output voltage V OUT1 To this end, the push-pull controller 510 can increase the rough PMOS transistor M CP As another example, the first reference voltage V REF1 The push-pull controller 510 can be reduced according to the first reference voltage V REF1 Reduce the shunt current I SHUNT The size of the first output voltage V OUT1 To this end, the push-pull controller 510 can add a rough NMOS transistor M CN The number of NMOS transistors that are turned on among the 32 NMOS transistors included in .

[0069] Figure 5B is a flow chart illustrating a method of operating the hybrid buck converter 500 according to an embodiment.

[0070] refer to Figure 5B In operation S510, the hybrid buck converter 500 may receive a first output voltage V OUT1 The push-pull controller 510 of the hybrid buck converter 500 can set the first output voltage V OUT1 With the first reference voltage V REF1 Make a comparison.

[0071] In operation S520, the hybrid buck converter 500 may determine the first output voltage V OUT1 Is it in a stable state? For example, when the first output voltage V OUT1 With the first reference voltage V REF1 When the difference between is less than or equal to the threshold, it can be determined that the push-pull controller 510 of the hybrid buck converter 500 is in a stable state. As another example, in response to receiving a signal from the control circuit 220 for changing the first reference voltage V based on dynamic voltage scaling, REF1 The push-pull controller 510 of the hybrid buck converter 500 may determine that it is a transient state rather than a steady state.

[0072] In operation S530, the hybrid buck converter 500 may control the shunt current I by simultaneously adjusting the fine regulator 423 and the coarse regulator 421. SHUNT In operation S520, the push-pull controller 510 may determine that the hybrid buck converter 500 is currently in a transient state. The push-pull controller 510 may increase or decrease the shunt current I SHUNT , so that the first output voltage V OUT1 Converge to the first reference voltage V as quickly as possible REF1 For example, when the first output voltage VOUT1 Greater than the first reference voltage V REF1 When the coarse NMOS transistor M is driven CN The control signal NG_32 is used to reduce the first output voltage V OUT1 As another example, when the first output voltage V OUT1 Lower than the first reference voltage V REF1 When the rough PMOS transistor M is driven PN The control signal PG_32 and the control signal PG_32 for driving the fine PMOS transistor M FP The control signal PG_128 is used to increase the first output voltage V OUT1 .

[0073] In operation S540, the hybrid buck converter 500 may control the shunt current I by adjusting only the fine regulator 423. SHUNT In operation S520, the push-pull controller 510 may determine that the hybrid buck converter 500 is currently in a stable state. OUT1 It is already in a stable state, so the push-pull controller 510 does not need to quickly increase or decrease the shunt current I SHUNT Therefore, the push-pull controller 510 only generates the power for driving the fine PMOS transistor M FP The control signal PG_128 is used to control the shunt current I SHUNT , so that the first output voltage V OUT1 Can successfully track the first reference voltage V REF1 .

[0074] Fig. 6A is a circuit diagram of a hybrid buck converter 600 including a first PWM controller 610 according to an embodiment.

[0075] refer to Fig. 6A ,Apart from Figure 4 In addition to the hybrid buck converter 400 , the hybrid buck converter 600 may further include a transconductance (GM) unit 601 , a compensation network 603 , a comparator 605 and a first PWM controller 610 .

[0076] According to an embodiment, the GM unit 601 may correspond to an operational amplifier. The GM unit 601 may receive a differential input voltage and output a first regulated voltage V C1 The first PWM controller 610 can be based on the first regulation voltage V C1 To control the duty cycle. One of the differential input voltages can correspond to the shunt voltage V SHUNT . Shunt voltage V SHUNT It can be achieved by sensing the shunt current I SHUNTThe other of the differential input voltages can correspond to the inductor voltage V IND . Inductor voltage V IND It can be achieved by sensing the inductor current I IND And the inductor current I IND According to the embodiment, the inductor current I IND Converts the voltage ratio to the shunt current I SHUNT The conversion ratio to voltage can be different. According to an embodiment, the inductor current I IND It can be converted to the inductor voltage V based on a 1:1 ratio IND . Shunt current I SHUNT It can be converted to a shunt voltage V based on a ratio of 1:β SHUNT That is, the inductor current I can be adjusted IND and the shunt current I SHUNT to satisfy the following formula 1.

[0077] [Formula 1]

[0078] I IND =β*I SHUNT

[0079] The hybrid buck converter 600 can convert the inductor current I IND The size of the shunt current I SHUNT β times the size of , thereby reducing the size of the power loss generated by the shunt regulator 420. The power loss PL generated by the shunt regulator 420 is shown in the following formula 2.

[0080] [Formula 2]

[0081] PL=I SHUNT *(V OUT2 -V OUT1 )

[0082] That is, the hybrid buck converter 600 converts most of the load current I LOAD (For example, ) is processed as the inductor current I IND , and only a small part of the load current I LOAD (For example, ) is processed as the shunt current I SHUNT , to reduce the shunt current I SHUNT The value of β can be set to be smaller than 100, or larger than 100, depending on the operating environment. The value of β can be set to be smaller than 100, or larger than 100, depending on the user's preferences. Figure 1 The configuration of the electronic device 100 may vary.

[0083] According to an embodiment, the compensation network 603 can determine the first regulation voltage V C1 The compensation network 603 may include a first compensation capacitor C P1 , the second compensation capacitor C P2 and the first compensation resistor R P1 .

[0084] The comparator 605 may compare the input signals with each other to generate an output signal indicating the comparison result. The comparator 605 may receive differential inputs. One of the differential inputs may be an AC waveform. For example, the AC waveform may be a sawtooth waveform, but is not limited thereto. According to various embodiments, the AC waveform may also include a triangular waveform, a square waveform, etc. According to an embodiment, the comparator 605 may compare the first regulated voltage V C1 The voltage V of the AC waveform SAW1 and provides the comparison result to the first PWM controller 610.

[0085] According to an embodiment, the first PWM controller 610 may control the first PMOS transistor M P1 and the first NMOS transistor M N1 For example, when the inductor current I IND Less than the shunt current I SHUNT When the first PWM controller 610 increases the first PMOS transistor M P1 That is, the first PWM controller 610 can increase the on-time of the first NMOS transistor M N1 and the first PMOS transistor M P1 During a period of alternating conduction, the first PMOS transistor M P1 The conduction time increases the inductor current I IND As another example, when the inductor current I IND Greater than the shunt current I SHUNT When the first PWM controller 610 reduces the first PMOS transistor M P1 That is, the first PWM controller 610 can reduce the on-time of the first NMOS transistor M N1 and the first PMOS transistor M P1 During a period of alternating conduction, the first PMOS transistor M P1 conduction time to reduce the inductor current I IND size.

[0086] Figure 6B is a flow chart illustrating a method of operating the hybrid buck converter 600 according to an embodiment.

[0087] refer to Figure 6BIn operation S610, the hybrid buck converter 600 can sense the shunt current I SHUNT and the inductor current I IND To generate the shunt voltage V SHUNT and the inductor voltage V IND For example, the hybrid buck converter 600 may further include a first current-voltage converter and a second current-voltage converter. The first current-voltage converter may convert the inductor current I IND Converted to inductor voltage V IND In this case, the conversion ratio of the first current-to-voltage converter may be 1:1. The second current-to-voltage converter may convert the shunt current I SHUNT Converted to shunt voltage V SHUNT In this case, the conversion ratio of the second current-to-voltage converter may be 1:β. That is, the second current-to-voltage converter may convert the shunt current I SHUNT Multiply by β to generate the shunt voltage V SHUNT .

[0088] In operation S620, the GM unit 601 of the hybrid buck converter 600 may be configured based on the shunt voltage V SHUNT and the inductor voltage V IND Generate a first regulation voltage V C1 For example, the GM unit 601 of the hybrid buck converter 600 may receive the shunt voltage V obtained in operation S610. SHUNT and the inductor voltage V IND As input, and output the first regulated voltage V C1 .

[0089] In operation S630, the hybrid buck converter 600 may adjust the voltage V C1 and AC waveform voltage V SAW1 The comparison between the first PMOS transistor M P1 and the first NMOS transistor M N1 For example, when the first regulation voltage V C1 Exceeding AC waveform voltage V SAW1 When the inductor current I IND Greater than the shunt current I SHUNT β times), the first PWM controller 610 can control the pulse width ratio so that the first PMOS transistor M P1 As another example, when the first regulation voltage V C1 Less than AC waveform voltage V SAW1 When the inductor current I IND Less than the shunt current I SHUNTβ times), the first PWM controller 610 can control the pulse width ratio so that the first PMOS transistor M P1 The on-time increases.

[0090] Fig. 7A is a circuit diagram of a hybrid buck converter 700 including a second PWM controller 710 according to an embodiment.

[0091] refer to Fig. 7A ,Apart from Figure 4 In addition to the hybrid buck converter 400 , the hybrid buck converter 700 may further include a GM unit 701 , a compensation network 703 , a comparator 705 and a second PWM controller 710 .

[0092] According to an embodiment, the GM unit 701 may correspond to an operational amplifier. The GM unit 701 may receive a differential input voltage and output a second regulated voltage V C2 The second PWM controller 710 can be based on the second regulation voltage V C2 Control the third PMOS transistor M P3 and the third NMOS transistor M N3 One of the differential inputs may correspond to a second output voltage V OUT2 The second output voltage V OUT2 can be achieved by sensing the second output node OUT 2 The other of the differential inputs can be a second reference voltage V REF2 The second reference voltage V REF2 can be used as a control device for controlling the second output voltage V OUT2 The voltage level of the reference voltage. The second reference voltage V REF2 Can be Figure 2 For example, the control circuit 220 may change the second reference voltage V based on the frequency of dynamic voltage scaling. REF2 Set to close to the power supply voltage V DD or close to the first output voltage V OUT1 The following will refer to Fig.7D The second reference voltage V REF2 .

[0093] According to an embodiment, the compensation network 703 can determine the second regulation voltage V c2 The compensation network 703 may include a third compensation capacitor C P3 .

[0094] The comparator 705 may compare the input signals with each other to generate an output signal indicating the comparison result. The comparator 705 may receive differential inputs. One of the differential inputs may be an AC waveform. For example, the AC waveform may be a sawtooth waveform, but is not limited thereto. According to various embodiments, the AC waveform may also include a triangular waveform, a square waveform, etc. According to an embodiment, the comparator 705 may compare the second regulated voltage V C2 The voltage V of the AC waveform SAW2 and provide the comparison result to the second PWM controller 710.

[0095] According to an embodiment, the second PWM controller 710 may control the third PMOS transistor M P3 and the third NMOS transistor M N3 For example, when the second regulation voltage V C2 Less than the voltage V of the AC waveform SAW2 When the second PWM controller 710 can add a third PMOS transistor M P3 That is, the second PWM controller 710 can increase the conduction time of the third NMOS transistor M N3 and the third PMOS transistor M P3 During one cycle of alternating conduction, the third PMOS transistor M P3 The conduction time of the second output voltage V OUT2 As another example, when the second regulation voltage V C2 Greater than the voltage V of the AC waveform SAW2 When the second PWM controller 710 can reduce the third PMOS transistor M P3 That is, the second PWM controller 710 can reduce the on-time of the third NMOS transistor M N3 and the third PMOS transistor M P3 During one cycle of alternating conduction, the third PMOS transistor M P3 The conduction time of the second output voltage V OUT2 voltage level.

[0096] Figure 7B is a flow chart illustrating a method of operating the hybrid buck converter 700 according to an embodiment.

[0097] refer to Figure 7B In operation S710, the hybrid buck converter 700 may receive a second output voltage V OUT2 For example, the GM unit 701 can receive the voltage level of the second output node OUT 2 The second output voltage V OUT2 The sensed value is input to one of the differential inputs.

[0098] In operation S720, the GM unit 701 of the hybrid buck converter 700 may be configured based on the second output voltage V OUT2 and the second reference voltage V REF2 Generate a second regulation voltage V c2 For example, the GM unit 701 of the hybrid buck converter 700 may be based on the second output voltage V received in operation S710. OUT2 and the second reference voltage V REF2 Output the second regulated voltage V C2 The second reference voltage V REF2 can be used to control the second output voltage V OUT2 The voltage level is set close to the power supply voltage V DD Still close to the first output voltage V OUT1 The reference voltage.

[0099] In operation S730, the hybrid buck converter 700 may adjust the voltage V c2 With AC waveform voltage V SAW2 The comparison between the third PMOS transistor M P3 and the third NMOS transistor M N3 For example, when the second regulation voltage V C2 Greater than the voltage V of the AC waveform SAW2 When the second PWM controller 710 can control the pulse width ratio to reduce the third PMOS transistor M P3 Accordingly, the second regulation voltage V C2 can be gradually reduced to converge to the voltage V of the AC waveform SAW2 As another example, when the second regulation voltage V C2 Less than the voltage V of the AC waveform SAW2 When the second PWM controller 710 can control the pulse width ratio to increase the third PMOS transistor M P3 Accordingly, the second regulation voltage V C2 can be gradually increased to converge to the voltage V of the AC waveform SAW2 The middle value of .

[0100] Figure 7C An example of power loss reduction according to an embodiment is shown.

[0101] refer to Figure 7C , shows the second output node OUT 2 According to the voltage level of Figure 3A The shunt regulator of the comparative example is based on the power supply voltage V DDTherefore, the power loss of the hybrid buck converter 300 according to the comparative example is as follows.

[0102] [Formula 3]

[0103] PL=I SHUNT *V DROP1 =I SHUNT *(V DD -V OUT1 )

[0104] refer to Figure 4 , when the shunt regulator 420 regulates the second output node OUT based on the embodiments disclosed herein 2 When driven, the driving voltage of the shunt regulator 420 can be DD The output voltage V OUT2 Therefore, the power loss of the hybrid buck converter 700 according to the embodiment is as follows.

[0105] [Formula 4]

[0106] PL=I SHUNT *V DROP2 =I SHUNT *(V OUT2 -V OUT1 )

[0107] Here, it can be seen that since the second output voltage V OUT2 Less than the power supply voltage V DD , so the voltage drop is reduced, and thus the power loss is also reduced. That is, the hybrid buck converter 700 can be operated by reducing the voltage driving the shunt regulator 420 from the power supply voltage V DD Change to the second output voltage V OUT2 To reduce power loss.

[0108] Fig.7D is a diagram showing a second reference voltage V according to an embodiment REF2 Diagram of the example that has undergone changes.

[0109] refer to Fig.7D , the second reference voltage V REF2 The frequency can be changed to a first voltage V based on dynamic voltage scaling 1 To the third voltage V 3 According to an embodiment, Figure 2 The control circuit 220 of the PMIC 200 may generate a first control signal at the first time T1. The first control signal may be an instruction to set the second reference voltage V REF2 The magnitude of the first voltage V 1 signal. Figure 2The control circuit 220 may track the number of occurrences of dynamic voltage scaling within a predetermined time period. The control circuit 220 may generate a first control signal when the dynamic voltage scaling occurs an appropriate number of times. For example, the control circuit 220 may generate a first control signal when the number of occurrences of dynamic voltage scaling within a specific time period is greater than a first value and less than a second value. The second value may be greater than the first value.

[0110] According to an embodiment, Figure 2 The control circuit 220 of the PMIC 200 may generate a second control signal at the second time T2. The second control signal may be an instruction to set the second reference voltage V REF2 The magnitude of the second voltage V 2 The second voltage V 2 The magnitude can be greater than the first voltage V 1 That is, the second control signal may be used to set the second output node OUT 2 The second output voltage V OUT2 The control circuit 220 can identify whether dynamic voltage scaling occurs frequently after the first time T1. For example, when the number of occurrences of dynamic voltage scaling within a specific time period exceeds a second value, the control circuit 220 can generate a second control signal to increase the second output voltage V OUT2 The voltage level changes to close to the power supply voltage V DD When dynamic voltage scaling occurs frequently, the number of times the shunt regulator 420 is driven will also increase. OUT2 is set to low (eg, with the first output voltage V OUT1 similar value), when dynamic voltage scaling occurs, the second output voltage V OUT2 is not high enough to drive the shunt regulator 420, so the first output voltage V OUT1 and load current I LOAD The transient state may last for a long time, which may be regarded as a defect. To prevent or reduce the possibility of this happening, the control circuit 220 may set the second output voltage V OUT2 Set high so that the shunt regulator 420 can always be driven.

[0111] According to an embodiment, the control circuit 220 of the PMIC 200 may generate a third control signal at the third time T3. The third control signal may be an instruction to set the second reference voltage V REF2 The magnitude of the third voltage V 3 The third voltage V 3 The magnitude may be smaller than the first voltage V 1 and the second voltage V 2That is, the third control signal may be to set the second output node OUT 2 The second output voltage V OUT2 The voltage level is set to a low level (eg, very close to the first output voltage V OUT1 ) signal. The control circuit 220 can identify whether dynamic voltage scaling hardly occurs after the second time T2. For example, when the number of occurrences of dynamic voltage scaling within the predetermined time period is less than the first value, the control circuit 220 can generate a third control signal to increase the second output voltage V OUT2 The voltage level changes to be close to the first output voltage V OUT1 When dynamic voltage scaling hardly occurs, the number of driving times of the shunt regulator 420 will also be reduced. OUT2 Set to high (for example, with supply voltage V DD , the power loss generated by the shunt regulator 420 will increase. Therefore, in order to improve power efficiency by reducing the power loss generated by the shunt regulator 420, the control circuit 220 can set the second output voltage V OUT2 Set to Low.

[0112] Fig. 8A is a circuit diagram of a hybrid buck converter 800 including a hysteretic controller 810 according to an embodiment, and Figure 8B shows a third reference voltage V according to an embodiment REF3 .

[0113] refer to Fig. 8A ,Apart from Figure 4 In addition to the hybrid buck converter 400 , the hybrid buck converter 800 may further include a hysteresis controller 810 .

[0114] According to an embodiment, the hysteresis controller 810 may control the fourth NMOS transistor M N4 For example, the hysteresis controller 810 may receive a third reference voltage V REF3 and the third output voltage V OUT3 The hysteresis controller 810 can respond to the third output voltage V OUT3 exceeds the third reference voltage V REF3 The fourth NMOS transistor M N4 On or off.

[0115] Also refer to Figure 8B and Fig. 8A , when the third output voltage V OUT3 Exceeding the window voltage by placing V WDNDOW and the third reference voltage V REF3When the obtained value is added, the fourth NMOS transistor M N4 Can be turned on. Since the third output capacitor C OUT3 is charged enough to exceed the window voltage V WINDOW and the third reference voltage V REF3 Therefore, the hysteresis controller 810 can turn on the fourth NMOS transistor M N4 , to utilize the power stored in the third output capacitor C OUT3 The charge in the inductor generates the inductor current I IND The hysteresis controller 810 may turn on the fourth NMOS transistor M N4 At the same time, the first NMOS transistor M N1 That is, the fourth NMOS transistor M N4 and the first NMOS transistor M N1 Can be turned on alternately.

[0116] Also refer to Figure 8B and Fig. 8A , when the third output voltage V OUT3 is less than the third reference voltage V REF3 Subtract the window voltage V WINDOW The value obtained is that the fourth NMOS transistor M N4 When the third output voltage V OUT3 is reduced to less than the third reference voltage V REF3 Subtract the window voltage V WINDOW The value obtained is that the third output capacitor C OUT3 Most of the charge stored in the hysteresis controller 810 may have been used. N4 cut-off, so that the third output node OUT 3 The first switch node L X1 The hysteresis controller 810 can make the fourth NMOS transistor M N4 The first NMOS transistor M is turned off and turned on at the same time N1 After that, the rough NMOS transistor M CN From the first output node OUT 1 The discharge current of the third output capacitor C OUT3 is charged, and when the third output voltage V OUT3 exceeds the third reference voltage V REF3 With the window voltage V WINDOW When the sum of N4 .

[0117] According to various embodiments, the hysteresis controller 810 may be based on the fourth NMOS transistor M N4The on or off control history of the third output capacitor C can be variably set to reuse the third output capacitor C OUT3 The optimal window voltage V for the charge stored in WINDOW .

[0118] Figure 8C is a flow chart illustrating a method of operating the hybrid buck converter 800 according to an embodiment.

[0119] refer to Figure 8C In operation S810, the hybrid buck converter 800 may receive a third output voltage V OUT3 For example, the hysteresis controller 810 may receive a voltage level of the third output node OUT 3 The third output voltage V OUT3 The sensed value is used as an input.

[0120] In operation S820, the hybrid buck converter 800 may generate a voltage based on the third output voltage V OUT3 , the third reference voltage V REF3 and the window voltage V WDNDOW To control the first NMOS transistor M N1 and the fourth NMOS transistor M N4 For example, when the third output voltage V OUT3 Exceeding the window voltage by placing V WINDOW and the third reference voltage V REF3 When the obtained value is added, the hysteresis controller 810 may turn on the fourth NMOS transistor M N4 The first NMOS transistor M N1 As another example, when the third output voltage V OUT3 is less than the third reference voltage V REF3 Subtract the window voltage V WINDOW When the value obtained is N4 The first NMOS transistor M is turned off and turned on. N1 .

[0121] According to the above embodiment, Figure 5A FIG. 4 shows a push-pull controller 510 for controlling the shunt regulator 420. Fig. 6A The circuit for controlling the inductor current I IND The first PWM controller 610, Fig. 7A The circuit for controlling the second output voltage V OUT2 The second PWM controller 710, and Fig. 8A The circuit for controlling the third output voltage V OUT3However, the push-pull controller 510, the first PWM controller 610, the second PWM controller 710 and the hysteresis controller 810 do not operate separately but can operate simultaneously. That is, Figure 4 The hybrid buck converter 400 can be composed of Figure 5A Push-pull controller 510, Fig. 6A The first PWM controller 610, Fig. 7A The second PWM controller 710 or Fig. 8A The hysteresis controller 810 controls simultaneously and / or independently.

[0122] Fig. 9 is a pair of graphs illustrating the efficiency improvement of a hybrid buck converter according to an embodiment.

[0123] refer to Fig. 9 , the first figure on the left shows the first output voltage V OUT1 , how much the efficiency is improved. For example, in the case of the hybrid buck converter according to the comparative example, when the first output voltage V OUT1 When the output voltage is 1V, the efficiency is about 70%, and in the case of the hybrid buck converter according to the embodiment, the efficiency can be confirmed to exceed about 85%. This efficiency improvement can be based on driving the shunt regulator to drive the first output voltage V OUT1 The regulated second output voltage V OUT2 , rather than based on the power supply voltage V DD drives the shunt regulator, thereby reducing the magnitude of the voltage drop that causes power loss and by always keeping the inductor current I IND is the shunt current I SHUNT The current in the shunt-based regulator is reduced by a factor of β.

[0124] The second figure on the right shows how much the efficiency loss is improved according to the frequency of dynamic voltage scaling. For example, when the frequency of dynamic voltage scaling is 10KHz, it can be confirmed that in the case of the hybrid buck converter according to the comparative example, the efficiency loss is about 3%. However, in the case of the hybrid buck converter according to the embodiment, it can be confirmed that the efficiency loss is reduced to about 0.7%. This reduction in efficiency loss can be based on driving the shunt regulator to the first output voltage V OUT1 The regulated second output voltage V OUT2 , rather than based on the power supply voltage V DD drives the shunt regulator, thereby reducing the magnitude of the voltage drop that causes power loss by always keeping the inductor current I IND is the shunt current I SHUNT The discharge current discharged from the shunt regulator is stored in the third output capacitor C OUT3and reuses the stored charge to generate the inductor current I IND .

[0125] While embodiments of the inventive concept have been particularly shown and described with reference thereto, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A hybrid buck converter comprising: a buck converter comprising a first P-channel metal oxide semiconductor (PMOS) transistor, a second PMOS transistor, a first N-channel metal oxide semiconductor (NMOS) transistor, a second NMOS transistor, and an inductor, wherein the first PMOS transistor and the second PMOS transistor electrically connect a power supply voltage node with a first switch node, the first NMOS transistor and the second NMOS transistor electrically connect a ground node with the first switch node, and the inductor electrically connects the first switch node with a second switch node; a third NMOS transistor, electrically connecting the second switch node to the first output node; a third PMOS transistor, electrically connecting the second switch node to a second output node; a shunt regulator driven based on a second output voltage corresponding to the second output node; a first pulse width modulation (PWM) controller configured to adjust the magnitude of the inductor current flowing through the inductor based on pulse width control of the first PMOS transistor and the first NMOS transistor; and The second PWM controller is configured to adjust the magnitude of the second output voltage based on pulse width control of the third PMOS transistor and the third NMOS transistor.

2. The hybrid buck converter according to claim 1, wherein: The shunt regulator comprises: a fine PMOS transistor electrically connected to the second output node and the first output node; a coarse PMOS transistor electrically connected in parallel with the fine PMOS transistor; and a coarse NMOS transistor electrically connected to the first output node and a third output node, and The hybrid buck converter also includes a push-pull controller, which is configured to control the magnitude of the shunt current provided to the first output node from the shunt regulator by generating a first control signal for the coarse PMOS transistor, a second control signal for the fine PMOS transistor, and a third control signal for the coarse NMOS transistor based on a result of comparing a first output voltage corresponding to the first output node with a first reference voltage.

3. The hybrid buck converter according to claim 2, wherein: The first PWM controller is configured to adjust a pulse width ratio between the first PMOS transistor and the first NMOS transistor so that the inductor current becomes equal to N times the shunt current, where N is a natural number.

4. The hybrid buck converter according to claim 3, wherein: The first PWM controller is configured to: increase the duty cycle of the first PMOS transistor when the inductor current is greater than N times the shunt current; and reduce the duty cycle of the first PMOS transistor when the inductor current is less than N times the shunt current, and The first NMOS transistor and the first PMOS transistor are turned on alternately.

5. The hybrid buck converter according to claim 2, wherein: The first reference voltage varies based on dynamic voltage scaling.

6. The hybrid buck converter according to claim 1, wherein: The second PWM controller is configured to adjust a pulse width ratio between the third PMOS transistor and the third NMOS transistor based on a result of comparing the second output voltage with a second reference voltage so that the second output voltage becomes equal to the second reference voltage.

7. The hybrid buck converter according to claim 6, wherein: The second PWM controller is configured to: reduce the duty cycle of the third PMOS transistor when the second output voltage exceeds the second reference voltage; and increase the duty cycle of the third PMOS transistor when the second output voltage is less than the second reference voltage, and The third NMOS transistor and the third PMOS transistor are turned on alternately.

8. The hybrid buck converter according to claim 6, wherein: The second reference voltage varies based on a frequency of dynamic voltage scaling.

9. The hybrid buck converter of claim 2, further comprising: a third output capacitor between the third output node and the ground node; a fourth NMOS transistor, electrically connecting the third output node to the first switch node; as well as A hysteresis controller is configured to turn on the fourth NMOS transistor based on a result of comparing a third output voltage corresponding to the third output node with a third reference voltage.

10. The hybrid buck converter according to claim 9, wherein: The hysteresis controller is also configured to: When the third output voltage exceeds the sum of the third reference voltage and the window voltage, turning on the fourth NMOS transistor and turning off the first NMOS transistor; and When the third output voltage is less than a value obtained by subtracting the window voltage from the third reference voltage, the fourth NMOS transistor is turned off and the first NMOS transistor is turned on.

11. A method for operating a hybrid buck converter, the hybrid buck converter comprising a buck converter and a shunt regulator, the method comprising: determining whether an inductor current flowing through an inductor of the buck converter is N times a shunt current output from the shunt regulator, where N is a natural number; performing pulse width control between a high-side switching element and a low-side switching element of the buck converter based on the determination; and Based on the result of comparing the second output voltage with the second reference voltage, pulse width control is performed between the third NMOS transistor and the third PMOS transistor, wherein The high-side switch element electrically connects a power supply voltage to a first switch node corresponding to a first end of the inductor, The low-side switch element electrically connects a ground node to the first switch node, The third PMOS transistor electrically connects a second output node corresponding to the second output voltage and a second switch node corresponding to the second end of the inductor, and The third NMOS transistor electrically connects the second switch node to a first output node corresponding to a first output voltage.

12. The operating method according to claim 11, wherein The shunt regulator comprises: a fine PMOS transistor electrically connected to the second output node and the first output node; a coarse PMOS transistor electrically connected in parallel with the fine PMOS transistor; and a coarse NMOS transistor electrically connected to the first output node and the third output node, and The operating method further includes: comparing the first output voltage with a first reference voltage; Based on the result of the comparison, a first control signal for the coarse PMOS transistor, a second control signal for the fine PMOS transistor, and a third control signal for the coarse NMOS transistor are generated; and the magnitude of the shunt current is controlled based on the control signals.

13. The operating method according to claim 12, wherein: Performing pulse width control between the high-side switch element and the low-side switch element further comprises: identifying that the inductor current is greater than N times the shunt current; and Based on the identification, a duty cycle of the high-side switching element is increased.

14. The operating method according to claim 12, wherein: Performing pulse width control between the high-side switch element and the low-side switch element further comprises: identifying that the inductor current is less than N times the shunt current; and Based on the identifying, a duty cycle of the high-side switching element is reduced.

15. The operating method according to claim 12, wherein: The first reference voltage varies based on dynamic voltage scaling.

16. The operating method according to claim 11, wherein: Performing pulse width control between the third NMOS transistor and the third PMOS transistor further includes: identifying that the second output voltage exceeds the second reference voltage; and Based on the identifying, a duty cycle of the third PMOS transistor is reduced.

17. The operating method according to claim 11, wherein: Performing pulse width control between the third NMOS transistor and the third PMOS transistor further includes: identifying that the second output voltage is less than the second reference voltage; and Based on the identifying, a duty cycle of the third PMOS transistor is increased.

18. The operating method according to claim 11, wherein: The second reference voltage varies based on a frequency of dynamic voltage scaling.

19. The operating method according to claim 12, further comprising: comparing the third output voltage with a third reference voltage; and turning on or off the fourth NMOS transistor based on the comparison, wherein The third output voltage is based on a third output capacitor electrically connecting the third output node with the ground node, and the fourth NMOS transistor electrically connects the third output node with the first switch node.

20. The operating method according to claim 19, further comprising: When the third output voltage exceeds the sum of the third reference voltage and the window voltage, turning on the fourth NMOS transistor; as well as When the third output voltage is less than a value obtained by subtracting the window voltage from the third reference voltage, the fourth NMOS transistor is turned off.

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