Large delay chip based on CMOS (Complementary Metal Oxide Semiconductor)

Abstract

The invention provides a CMOS-based large time delay chip, which comprises a substrate and a time delay circuit, the time delay circuit comprises at least one time delay unit, the plurality of time delay units are sequentially connected by adopting a binary weight cascade structure, a low noise amplifier is connected between a target time delay unit and a next time delay unit, and the target time delay unit and the next time delay unit are arranged on the substrate. The delay unit comprises four transistors, a delay state and a reference state, the reference state comprises a first inductor, and two ends of the reference state are respectively connected with a first transistor and a second transistor; the delay state comprises a delay line, and two ends are respectively connected with the third transistor and the fourth transistor; the first transistor is connected with the third transistor, and the second transistor is connected with the fourth transistor. In the delay units, the delay line of the low delay unit is arranged in the low delay unit body, and the delay line of the high delay unit is arranged on the substrate. The delay time can be increased, the loss in a working frequency band is reduced, and the problems of short delay time and large loss fluctuation of a delayer chip are solved.

Description

Technical Field

[0001] The present application relates to the technical field of delay devices, and in particular to a large delay chip based on CMOS. Background Art

[0002] True-Time Delay (TTD) is widely used in electronic communications and other fields. For example, phased array radar needs to control the delay of the signal transmitted by each array element to achieve the purpose of controlling the beam pointing. The main delay technologies of delay devices include non-silicon delay and silicon delay. Compared with non-silicon technologies such as gallium arsenide (GaAs), silicon-based delay device chips have the advantages of mature technology, low cost, high integration, and strong compatibility. However, due to its disadvantages such as relatively low electron mobility, higher insertion loss and power consumption are generated when implementing TTD circuits.

[0003] For example, in some delay device structures based on complementary metal oxide semiconductor (CMOS) technology, the signal delay is mainly adjusted by introducing a single-pole double-throw switch or a trombone line structure, and the delay unit is mostly composed of an artificial transmission line (ATL). One of the inherent disadvantages of the trombone line structure is that the loss increases with the selection of a longer delay state, resulting in a change in the loss under different delay states. Therefore, each state switch needs to be composed of an amplifier, resulting in an increase in the chip area and power consumption of the delay device. In addition, the TTD delay is small, and the ATL structure will bring more operating frequency band limitation problems and greater in-band loss fluctuations when facing greater delay requirements. Summary of the invention

[0004] The present application provides a large delay chip based on CMOS to solve the problem that the delay time of the delay device chip is short and the loss fluctuation is large.

[0005] The present application provides a CMOS-based large delay chip, comprising: a substrate and a delay circuit, wherein the delay circuit comprises at least one delay unit, and a plurality of the delay units are sequentially connected using a binary weight cascade structure, wherein a low-noise amplifier is connected between a target delay unit and the next delay unit, and the target delay unit is the delay unit whose loss reaches a loss threshold, and the delay unit and the low-noise amplifier are arranged on the substrate;

[0006] The delay unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a delay state and a reference state, wherein the reference state includes a first inductor, and two ends of the first inductor are respectively connected to the drain end of the first transistor and the source end of the second transistor; the delay state includes a delay line, and two ends of the delay line are respectively connected to the drain end of the third transistor and the source end of the fourth transistor; the source end of the first transistor is connected to the source end of the third transistor, and the drain end of the second transistor is connected to the drain end of the fourth transistor;

[0007] The delay unit includes a low delay unit and a high delay unit. The delay line of the low delay unit is arranged in the low delay unit body, and the delay line of the high delay unit is arranged on the substrate.

[0008] By setting the delay line of the low-delay unit in the body of the low-delay unit, a smaller loss can be achieved in the chip. By setting the delay line of the high-delay unit on the substrate, the delay time can be increased, thereby generating different delays. By connecting multiple delay units using a binary weight cascade structure, a longer delay time can be obtained. By setting the low-noise amplifier between the delay units, the overall loss of the delay circuit can be reduced. The problem of short delay time and large loss fluctuation of the delay chip can be solved.

[0009] In some feasible implementations, the number of the delay units is seven, the target delay unit is the fourth delay unit, and the low noise amplifier is arranged between the fourth delay unit and the fifth delay unit. When the number of the delay units in the delay circuit is seven, a longer delay time can be achieved while minimizing signal loss, and at the same time, the large delay chip can maintain a smaller size.

[0010] In some feasible implementations, the delay time of the low-delay unit is less than or equal to 24 ps, and the delay time of the high-delay unit is greater than or equal to 48 ps.

[0011] In some feasible implementations, the delay line includes a microstrip line and a stripline, the delay line of the low-delay unit is the microstrip line, and the delay line of the high-delay unit is the stripline.

[0012] In some feasible implementations, the microstrip line in the low-delay unit is arranged on a high-layer metal in a chip. By arranging the microstrip line on a high-layer metal in a chip, the loss of the delay line in the chip can be reduced.

[0013] In some feasible implementations, the thickness of the substrate is 300 μm to 310 μm, the line width of the stripline on the substrate is 30 μm to 40 μm, and the spacing between two adjacent striplines is 30 μm to 40 μm. By reducing the thickness of the substrate, reducing the line width and line spacing of the stripline, the loss of the delay circuit can be reduced, and the area of ​​the large delay chip can also be reduced.

[0014] In some feasible implementations, the substrate is made of a low-loss dielectric material, and the low-loss dielectric material is HL972LFG-LD, so as to further reduce the loss of the delay circuit.

[0015] In some feasible implementations, the reference state further includes a resistor and a first capacitor, the first capacitor is connected in parallel to both ends of the first inductor, the resistor is also connected in parallel to both ends of the first inductor, one end of the resistor is connected to the first inductor, the other end of the resistor is connected to one end of the first capacitor, and the other end of the first capacitor is grounded. By connecting the first capacitor in parallel to both ends of the first inductor to form a π-shaped balancing circuit, the loss within the working frequency band can be adjusted while ensuring impedance matching, and the parallel first capacitor can also fix the DC working level of the delay unit circuit and reduce the conduction loss of the transistor. And due to the reduction in the use of inductance, the area of ​​the large delay chip can also be reduced.

[0016] In some feasible implementations, the input and output ends of the delay unit and the two ends of the delay line are impedance matched respectively; the delay state also includes a second inductor, and the two ends of the delay line are respectively connected to the second inductor, one end of one of the second inductors is connected to the drain end of the third transistor, and the other end is connected to the input end of the delay line; one end of the other second inductor is connected to the output end of the delay line, and the other end is connected to the source end of the fourth transistor, and the second inductor is used for impedance matching.

[0017] In some feasible implementations, the delay circuit further includes a second capacitor, and the second capacitor is provided between the input end of the delay circuit and the first delay unit and between the output end of the delay circuit and the last delay unit.

[0018] The present application provides a large delay chip based on CMOS, including: a substrate and a delay circuit, the delay circuit includes at least one delay unit, multiple delay units are connected in sequence using a binary weight cascade structure, a low noise amplifier is connected between the target delay unit and the next delay unit, and the delay unit and the low noise amplifier are arranged on the substrate. The delay unit includes four transistors, a delay state and a reference state, the reference state includes a first inductor, and the two ends are respectively connected to the drain end of the first transistor and the source end of the second transistor; the delay state includes a delay line, and the two ends are respectively connected to the drain end of the third transistor and the source end of the fourth transistor; the source end of the first transistor is connected to the source end of the third transistor, and the drain end of the second transistor is connected to the drain end of the fourth transistor. The delay unit includes a low delay unit and a high delay unit, the delay line of the low delay unit is arranged in the low delay unit body, and the delay line of the high delay unit is arranged on the substrate. By cascading multiple delay units, setting the delay line of the high delay unit on the substrate, and setting a low noise amplifier between the target delay unit and the next delay unit, the delay time can be increased and the loss within the working frequency band can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 A schematic diagram of the structure of a CMOS-based large-delay chip provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of a delay unit circuit provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of the delay fluctuations caused by different gears provided in the embodiment of the present application;

[0023] Figure 4 A schematic diagram of the structure of a delay device chip based on GaAs technology provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of the structure of a delay chip based on 28nm CMOS technology provided in an embodiment of the present application;

[0025] Figure 6 Schematic diagram of the delay chip structure based on 40nm bulk CMOS technology provided in an embodiment of the present application.

[0026] Illustration Description:

[0027] Among them, 100-substrate; 201-low delay unit; 202-high delay unit; 203-delay line; 300-low noise amplifier. DETAILED DESCRIPTION

[0028] The following embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following embodiments do not represent all implementations consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application as detailed in the claims.

[0029] In some delay device structures based on CMOS technology, signal delay is adjusted mainly by introducing single-pole double-throw switches or trombone line structures, and the delay units are mostly composed of ATL. One of the inherent disadvantages of the trombone line structure is that the loss increases with the selection of a longer delay state, resulting in changes in loss under different delay states. Therefore, each state switch needs to be composed of an amplifier, resulting in an increase in the chip area and power consumption of the delay device. In addition, the TTD delay is small, and the ATL structure will bring more operating frequency band limitation problems and greater in-band loss fluctuations when facing greater delay requirements.

[0030] In order to solve the problem that the delay time of the delay device chip is short and the loss fluctuation is large, the embodiment of the present application provides a large delay chip based on CMOS, see Figure 1 , Figure 1 Taking seven delay units as an example, a large delay chip is illustrated. The large delay chip includes: a substrate 100 and a delay circuit. The delay circuit includes at least one delay unit. Multiple delay units are connected in sequence using a binary weight cascade structure, wherein a low-noise amplifier 300 is connected between a target delay unit and the next delay unit, and the delay unit and the low-noise amplifier 300 are arranged on the substrate 100.

[0031] Since each delay unit will cause signal loss during the delay process, when the loss reaches the loss threshold, compensation amplification is required, that is, the target delay unit is the delay unit when the loss reaches the loss threshold. The low-noise amplifier (Low-Noise Amplifier, LNA) is used to amplify weak signals and minimize the input and output signal-to-noise ratio. Therefore, a low-noise amplifier 300 is set between the target delay unit and the next delay unit to compensate for the loss generated by each delay unit and reduce the loss of the overall delay circuit.

[0032] The binary weight cascade structure refers to a structure in which multiple delay units with different delay times are connected in sequence, and the output of each delay unit is connected to the input of the next delay unit, thereby forming a total structure with multiple delay times. The delay times of these delay units are arranged in a binary manner, such as 6ps, 12ps, 24ps, 48ps, 96ps..., and the cascade refers to connecting these delay units in a certain order to add up the delay times of these delay units. It can be understood that the first delay unit, namely delay unit 1, is a first-level delay unit, the second delay unit, namely delay unit 2, is a second-level delay unit, and the Nth delay unit is an Nth-level delay unit.

[0033] In some embodiments, the delay unit may be a delay chip, see Figure 2 The delay unit includes a first transistor Sr1, a second transistor Sr2, a third transistor Sr3, a fourth transistor Sr4, a delay state and a reference state. Figure 2 As shown in the dotted box in , the reference state includes a first inductor L1, and the two ends of the first inductor L1 are respectively connected to the drain end of the first transistor Sr1 and the source end of the second transistor Sr2. The delay state includes a delay line 203, and the lengths of the delay lines 203 in different delay units are different, which are used to provide different levels of delay time. The two ends of the delay line 203 are respectively connected to the drain end of the third transistor Sr3 and the source end of the fourth transistor Sr4; the source end of the first transistor Sr1 is connected to the source end of the third transistor Sr3, and the drain end of the second transistor Sr2 is connected to the drain end of the fourth transistor Sr4. In some embodiments, the first transistor Sr1, the second transistor Sr2, the third transistor Sr3 and the fourth transistor Sr4 can be MOS switch tubes based on 65nm CMOS process.

[0034] Figure 2 In the figure, Vc is the control signal of the transistor switch, the low level reference state is on, and the high level delay state is on. The delay state or reference state can be turned on or off by turning on different transistors. Different delay times can be obtained by turning on the delay states of delay units of different levels. When the delay states of all delay units are turned on, the delay time of the large delay chip reaches the maximum value.

[0035] The delay unit includes a low delay unit 201 and a high delay unit 202. The delay line 203 of the low delay unit 201 is arranged in the body of the low delay unit 201, and the delay line 203 of the high delay unit 202 is arranged on the substrate 100. Figure 1The delay line 1 of the first delay unit, the delay line 2 of the second delay unit, and the delay line 3 of the third delay unit are all arranged in the body of the low delay unit 201, that is, inside the chip. The delay line 4 of the fourth delay unit to the delay line 7 of the seventh delay unit are arranged on the substrate 100, that is, outside the chip.

[0036] The large delay chip provided in the embodiment of the present application can achieve smaller losses in the chip by setting the delay line 203 of the low delay unit 201 in the body of the low delay unit 201, and can increase the delay time by setting the delay line 203 of the high delay unit 202 on the substrate 100, thereby generating different delays. By connecting multiple delay units using a binary weight cascade structure, when the delay states of all delay units are turned on, the delay time can be maximized. By arranging a low noise amplifier 300 between the delay units, the loss of the overall delay circuit can be reduced. The problem of short delay time and large loss fluctuation of the delay chip can be solved.

[0037] In some embodiments, the number of delay units is seven, and the delay units are connected in a seven-level binary weight cascade structure. Among them, the delay time of the first-level delay unit is 6ps, the delay time of the second-level delay unit is 12ps, the delay time of the third-level delay unit Delay3 is 24ps, and the delay times of the fourth-level delay unit, the fifth-level delay unit, the sixth-level delay unit, and the seventh-level delay unit are 48ps, 96ps, 192ps, and 384ps, respectively. The total delay time is 762ps when the delay time from the first-level delay unit to the seventh-level delay unit is added.

[0038] Since a delay time greater than 6ps cannot meet the minimum requirement of the radar phased array angular resolution, and a delay time less than 6ps will not be enough to achieve a delay time of 6ps×127=762ps at the minimum level of seven (a total of 127 levels), the delay time of the first-level delay unit is 6ps. At a delay time of 762ps, the electromagnetic wave can travel 2.286m, which meets the maximum size of the radar antenna that can be manufactured in the target specific application scenario. Therefore, the level of the delay unit is at least seven, and the total delay time is 762ps. When the level is greater than seven, although the total delay time will increase, it will also cause the number of transistors used in the control delay unit below to be too large, resulting in excessive signal loss. According to the experimental data, when the number of delay units in the delay circuit is seven, the signal loss can be minimized while achieving a longer delay time, and at the same time, the large delay chip can maintain a smaller size.

[0039] When the number of delay units is seven, for the setting position of the low noise amplifier 300, since amplification too early will make the signal too large and distorted in the middle, amplification too late will make the signal attenuate to too small and more easily interfered by noise, therefore, the low noise amplifier 300 is placed after the delay unit when the loss reaches the loss threshold. In some embodiments, a low noise amplifier 300 with a gain of 25dB from 17GHz to 22GHz can be used to compensate for the loss of each delay unit to reduce the impact on the noise performance of the circuit, and at the same time, the 27GHz to 32GHz frequency band can be suppressed. After simulation testing, the performance of the low noise amplifier 300 can just meet the loss (20dB) caused by the first four delay units, so the low noise amplifier 300 is placed between the fourth delay unit and the fifth delay unit, that is, the target delay unit is the fourth delay unit.

[0040] In some embodiments, the delay time of the low delay unit 201 is less than or equal to 24 ps, and the delay time of the high delay unit 202 is greater than or equal to 48 ps. It can be understood that in the embodiment of the present application, the first-level delay unit, the second-level delay unit, and the third-level delay unit are low-delay units 201, and the fourth-level delay unit to the seventh-level delay unit are high-delay units 202.

[0041] The delay line 203 includes a microstrip line and a stripline. The delay line 203 of the low-delay unit 201 is a microstrip line, that is, the on-chip delay line 203 is a microstrip line. Compared with the stripline, the loss of the microstrip line is large. By setting the microstrip line in the body of the low-delay unit 201, the required delay time can be obtained while reducing the loss. The microstrip line in the low-delay unit 201 is set on the high-level metal in the chip. The high-level metal is the high-level metal of the delay chip wafer. By setting the microstrip line on the high-level metal in the chip, the loss of the delay line 203 in the chip can be reduced. The delay line 203 of the high-delay unit 202 is a stripline, that is, the off-chip delay line 203 is a stripline. Compared with the microstrip line, the stripline can provide better signal transmission performance, so the stripline can be set on the substrate 100 to provide a longer delay time.

[0042] Since the stripline disposed on the substrate 100 will increase the loss, in order to reduce the loss of the delay line of the high delay unit 202, the thickness of the substrate 100 can be reduced to 300μm-310μm, the line width of the stripline on the substrate 100 can be reduced to 30μm-40μm, the spacing between two adjacent striplines can be reduced to 30μm-40μm, and the center distance of the pins can be reduced. Since the thickness of the substrate 100 is reduced, the line width and line spacing are also reduced, thereby reducing the area of ​​the large delay chip.

[0043] In some embodiments, a low-loss dielectric material HL972LFG-LD may be used as the material of the substrate 100 to achieve a greater delay time while maintaining a lower insertion loss and a better in-band loss flatness.

[0044] See again Figure 2 , the input and output ends of the delay unit and the two ends of the delay line 203 are impedance matched respectively, so as to reduce the loss value and loss fluctuation. In some embodiments, the impedance matching resistance is 50Ω. Impedance matching is performed at both ends of the delay line 203 to reduce the loss and loss fluctuation caused by the delay line itself; impedance matching is performed at the input and output ends of the delay unit to reduce the reflection of the signal in the delay unit circuit, for example, the input reflection coefficient S11 and the output reflection coefficient S22 can be made less than or equal to -15dB, improve the signal quality and transmission efficiency, reduce the loss and loss fluctuation within the working frequency band, and at the same time improve the DC working level of the delay unit circuit. Since the external input is adjustable, the conduction loss of the first transistor, the second transistor, the third transistor and the fourth transistor can also be reduced.

[0045] In some embodiments, the reference state further includes a resistor R and a first capacitor C1, the first inductor L1 is connected in parallel with the first capacitor C1 at both ends, the first inductor L1 is also connected in parallel with a resistor R at both ends, one end of the resistor R is connected to the first inductor L1, the other end of the resistor R is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is grounded. By connecting the first capacitor C1 in parallel at both ends of the first inductor L1, a π-shaped balancing circuit is formed, and the loss within the working frequency band can be adjusted while ensuring 50Ω impedance matching, so that it is equivalent to the loss size of the delay state within the working frequency band. The parallel first capacitor C1 can also fix the DC working level of the delay unit circuit and reduce the conduction loss of the transistor. In addition, due to the reduction in the use of inductance, the area of ​​the large delay chip can also be reduced.

[0046] The delay state also includes a second inductor L2, and the two ends of the delay line 203 are respectively connected to the second inductor L2, wherein one end of one of the second inductors L2 is connected to the drain end of the third transistor Sr3, and the other end is connected to the input end of the delay line 203; one end of the other second inductor L2 is connected to the output end of the delay line 203, and the other end is connected to the source end of the fourth transistor Sr4. It can be seen from the above embodiments that the delay line 203 of the high delay unit 202 is arranged on the substrate 100. In some embodiments, the delay line 203 and the second inductor L2 can be connected by metal wire bonding. It can be understood that the second inductor L2 is used for impedance matching, and the impedance matching resistance is 50Ω. It should also be noted that the values ​​of the second inductor L2, the resistor R and the first capacitor C1 are all obtained through electromagnetic modeling simulation.

[0047] See again Figure 1The delay circuit further includes a second capacitor C2, and the second capacitor C2 is disposed between the input end of the delay circuit and the first delay unit, and between the output end of the delay circuit and the last delay unit. The second capacitor C2 may be a voltage stabilizing capacitor for maintaining the stability of the input and output voltages. In some embodiments, a third inductor L3 may be disposed at both ends of the second capacitor C2, respectively, to more effectively filter out noise and fluctuations in the input and output voltages.

[0048] See Table 1, which shows the delay fluctuation values ​​of the large delay chip under different frequencies and different switching states. The numbers 0000000 or 1111111 in each column of the first row in Table 1 represent the switching state from the seventh-level delay unit to the first-level delay unit from left to right, where 0 represents the reference state on and 1 represents the delay state on. Table 1 shows 9 typical switching states, 0000000 means that the delay state of all delay units is closed, 0000001 means that only the delay state of the first-level delay unit is turned on, 0000010 means that only the delay state of the second-level delay unit is turned on, and 1111111 means that the delay state of the first-level delay unit to the seventh-level delay unit is turned on. Therefore, it can be understood that the number 0000000 means the minimum delay time, and 1111111 means the maximum delay time.

[0049] Table 1 Delay fluctuation values ​​of large delay chips at different frequencies and in different switching states

[0050]

[0051] It can be seen from Table 1 that the maximum delay fluctuation of the large delay chip provided in the embodiment of the present application is 3.5ps. Figure 3 , Figure 3 This is a schematic diagram of the delay fluctuations caused by different gears. Figure 3 In the figure, G0-G127 correspond to the 9 switch states in Table 1, G0 corresponds to 0000000, G127 corresponds to 1111111, and G8, G16, G32, and G64 correspond to the delay states of only turning on the fourth, fifth, sixth, and seventh delay units, respectively. Figure 3 It can be seen that the large delay chip of the present application can produce a relatively small delay fluctuation when the delay time is large. The smaller the delay fluctuation, the higher the delay accuracy and the more accurate the delay time obtained.

[0052] See also Figure 4-Figure 6 , Figure 4 The delay chip structure is based on GaAs technology and consists of a TTD delay unit, a broadband amplifier, and a cascaded programmable attenuator. It achieves a 255ps delay with a step size of 1ps at 6 to 18GHz, and provides 8-bit delay control. The high-order delay path in the TTD unit is formed by a cascaded ATL. Figure 5The delay device chip structure is based on 28nm CMOS technology. A 4-bit broadband switch line TTD operating at 3-30GHz is proposed, achieving a delay of 4.6-68.5ps. Cascade coupled all-pass network (CAPN) and non-coupled all-pass network (NCAPN) are used as delay elements. Figure 6 The delay chip structure is based on 40nm bulk CMOS technology, and uses a trombone line structure to design a TTD circuit with a working frequency band of 5 to 23GHz, a delay range of 125ps, a resolution of 3 bits, and each delay unit is composed of two sections of ATL. Figure 4 As comparative example 1, Figure 5 As comparative example 2, Figure 6 The structure is used as comparative example 3, and compared with the large delay chip of the present application. See Table 2, which is a comparison between a large delay chip containing 7 delay units and delay chips with different structures.

[0053] Table 2 Comparison of large delay chips and delay chips with different structures

[0054] Large delay chip Comparative Example 1 Comparative Example 2 Comparative Example 3 Frequency (GHz) 17-22 6-18 3-30 5-23 Delay range / step (ps) 762 / 6 255 / 1 68.5 / * 125 / 17.85 <![CDATA[Chip area (mm 2 )]]> 1.44 20 0.34 0.85

[0055] The large delay chip provided in the embodiment of the present application, when the number of delay units is seven, in the frequency range of 17GHz to 22GHz of the working frequency band, the delay step is 6ps / step, and the delay accuracy is ≤±1.75ps in the full state and full bandwidth, including the 0 gear, the number of gears can reach 128 gears, and the total delay time is about 762ps. Through simulation tests, the loss in the full-gear working frequency band is in the range of -17 to -22.5dB, the loss error is <±3dB in the full state and full bandwidth, the input reflection coefficient S11 and the output reflection coefficient S22 are both less than -14dB, and the overall bare chip size of the chip is 2mm×0.72mm (the size after packaging is 3.3mm×2.9mm). It can be seen from Table 2 that compared with the delay chip structure in the comparative example, the large delay chip provided in the embodiment of the present application can maintain a smaller size of the large delay chip while greatly improving the delay time.

[0056] It can be seen from the above technical solutions that the embodiment of the present application provides a large delay chip based on CMOS, including: a substrate 100 and a delay circuit, the delay circuit includes at least one delay unit, multiple delay units are connected in sequence using a binary weight cascade structure, a low noise amplifier 300 is connected between the target delay unit and the next delay unit, and the delay unit and the low noise amplifier 300 are arranged on the substrate 100. The delay unit includes four transistors, a delay state and a reference state, the reference state includes a first inductor, and the two ends are respectively connected to the drain end of the first transistor and the source end of the second transistor; the delay state includes a delay line, and the two ends are respectively connected to the drain end of the third transistor and the source end of the fourth transistor; the source end of the first transistor is connected to the source end of the third transistor, and the drain end of the second transistor is connected to the drain end of the fourth transistor. The delay unit includes a low delay unit 201 and a high delay unit 202, the delay line of the low delay unit 201 is arranged in the low delay unit body, and the delay line of the high delay unit 202 is arranged on the substrate 100. By cascading multiple delay units, setting the delay line of the high delay unit 202 on the substrate 100, and setting a low noise amplifier 300 between the target delay unit and the next delay unit, the delay time can be increased and the loss in the working frequency band can be reduced.

[0057] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. A CMOS-based long-delay chip, characterized in that: include: A substrate and a delay circuit, wherein the delay circuit comprises at least one delay unit, wherein a plurality of the delay units are sequentially connected using a binary weight cascade structure, wherein a low noise amplifier is connected between a target delay unit and a next delay unit, wherein the target delay unit is the delay unit whose loss reaches a loss threshold, and the delay unit and the low noise amplifier are arranged on the substrate; The delay unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a delay state and a reference state, wherein the reference state includes a first inductor, and two ends of the first inductor are respectively connected to the drain end of the first transistor and the source end of the second transistor; the delay state includes a delay line, and two ends of the delay line are respectively connected to the drain end of the third transistor and the source end of the fourth transistor; the source end of the first transistor is connected to the source end of the third transistor, and the drain end of the second transistor is connected to the drain end of the fourth transistor; The delay unit includes a low delay unit and a high delay unit. The delay line of the low delay unit is arranged in the low delay unit body, and the delay line of the high delay unit is arranged on the substrate.

2. The CMOS-based long-delay chip according to claim 1, characterized in that: The number of the delay units is seven, the target delay unit is the fourth delay unit, and the low noise amplifier is arranged between the fourth delay unit and the fifth delay unit.

3. The CMOS-based long-delay chip according to claim 1, characterized in that: The delay time of the low-delay unit is less than or equal to 24 ps, and the delay time of the high-delay unit is greater than or equal to 48 ps.

4. The CMOS-based long-delay chip according to claim 1, characterized in that: The delay line includes a microstrip line and a stripline. The delay line of the low delay unit is the microstrip line, and the delay line of the high delay unit is the stripline.

5. The CMOS-based long-delay chip according to claim 4, characterized in that: The microstrip line in the low-delay unit is arranged on a high-layer metal in the chip.

6. The CMOS-based long-delay chip according to claim 4, characterized in that: The thickness of the substrate is 300 μm to 310 μm, the line width of the strip lines on the substrate is in the range of 30 μm to 40 μm, and the distance between two adjacent strip lines is in the range of 30 μm to 40 μm.

7. The CMOS-based long-delay chip according to claim 1, characterized in that: The substrate is made of a low-loss dielectric material, and the low-loss dielectric material is HL972LFG-LD.

8. The CMOS-based long-delay chip according to claim 1, characterized in that: The reference state also includes a resistor and a first capacitor, the first capacitor is connected in parallel to both ends of the first inductor, the resistor is also connected in parallel to both ends of the first inductor, one end of the resistor is connected to the first inductor, the other end of the resistor is connected to one end of the first capacitor, and the other end of the first capacitor is grounded.

9. The CMOS-based long-delay chip according to claim 1, characterized in that: The input and output ends of the delay unit and the two ends of the delay line are impedance matched respectively; the delay state also includes a second inductor, and the two ends of the delay line are respectively connected to the second inductor, one end of one of the second inductors is connected to the drain end of the third transistor, and the other end is connected to the input end of the delay line; one end of the other second inductor is connected to the output end of the delay line, and the other end is connected to the source end of the fourth transistor, and the second inductor is used for impedance matching.

10. The CMOS-based long-delay chip according to claim 1, characterized in that: The delay circuit further includes a second capacitor, and the second capacitor is arranged between the input end of the delay circuit and the first delay unit and between the output end of the delay circuit and the last delay unit.

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