Latch for solving output failure
By introducing two latch components with different failure input signals into the latch, and using the cooperation of logic gate circuit and switch components, the output stability of the latch under specific input conditions is achieved, solving the problem of the output failure of the existing latch.
Patent Information
- Application Number
- CN202510021960.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-07
- Publication Date
- 2025-04-11
AI Technical Summary
Existing latches will have an issue of output failure under specific input conditions. For example, when both inputs are 0 or both are 1, the output is unstable and may oscillate between the two states.
A latch consisting of two latch components with different failure input signals (first latch components and second latch components) are designed, and automatically switch to another latch component through the cooperation of the logic gate circuit and the switch components to ensure effective output.
By introducing two latch components with different failure input signals, the latch can automatically switch to the other when one latch component fails, solving the problem of latch output failure and ensuring the stability of the output.
Smart Images
Figure CN119814023A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of latches, and in particular to a latch for solving output failure problems. Background Art
[0002] Latch is a storage unit circuit that is sensitive to pulse level. It can change state under the action of specific input pulse level. Latching is to temporarily store the signal to maintain a certain level state. The main function of latch is cache, followed by completing the synchronization problem between high-speed controller and slow peripherals, then solving the problem of driver, and finally solving the problem of an I / O port being able to output and input.
[0003] In the prior art, latches have the problem of invalid output. For example, according to the truth table of a latch with active low input, when both inputs are 0, the output will be invalid. In this case, the output of the trigger is unstable and may oscillate between two states. Similarly, for a latch with active high input, when both inputs are 1, the output will also be invalid.
[0004] Therefore, it is necessary to provide a latch that can solve the problem of output failure, so as to solve the problem of latch output failure. Summary of the invention
[0005] The present invention provides a latch for solving output failure, comprising a first input end, a second input end, a first latch component, a second latch component, a logic gate circuit, a switch component and a latch output end, wherein the first input end and the second input end are electrically connected to the two input ends of the first latch component respectively, the first input end and the second input end are electrically connected to the two input ends of the second latch component respectively, the output ends of the first latch component and the second latch component are both electrically connected to the input end of the logic gate circuit, the switch component is electrically connected to the first latch component, the second latch component and the output end of the logic gate circuit, the latch output end is electrically connected to the switch component, the switch component is used to connect the latch output end and the latch component with valid output in the first latch component and the second latch component according to the input signals of the first input end and the second input end, and the failure input signal corresponding to the first latch component is different from the failure input signal corresponding to the second latch component.
[0006] Furthermore, the first latch component is composed of a NOR gate, and the second latch component is composed of a NAND gate.
[0007] Furthermore, the switch component is used to connect the latch output terminal and the second latch component when a low level is input to both the first input terminal and the second input terminal, and the switch component is also used to connect the latch output terminal and the first latch component when a high level is input to at least one of the first input terminal and the second input terminal.
[0008] Furthermore, the logic gate circuit includes a first logic gate sub-circuit and a second logic gate sub-circuit, wherein the input end of the first logic gate sub-circuit is electrically connected to the output end of the first latch component, and the input end of the second logic gate sub-circuit is electrically connected to the output end of the second latch component.
[0009] Further, the first latch component includes a first NOR gate and a second NOR gate, the first input end is electrically connected to an input end of the first NOR gate and an input end of the second NOR gate, the other input end of the first NOR gate is electrically connected to the output end of the second NOR gate, and the other input end of the second NOR gate is electrically connected to the output end of the first NOR gate.
[0010] Further, the second latch component includes a first NAND gate and a second NAND gate, the first input end is electrically connected to an input end of the first NAND gate and an input end of the second NAND gate, the other input end of the first NAND gate is electrically connected to the output end of the second NAND gate, and the other input end of the second NAND gate is electrically connected to the output end of the first NAND gate.
[0011] Furthermore, the first logic gate sub-circuit and the second logic gate sub-circuit have the same structure.
[0012] Furthermore, the first logic gate sub-circuit includes a first XOR gate and a first inverter, wherein one input terminal of the first XOR gate is electrically connected to the output terminal of the first NOR gate, the other input terminal of the first XOR gate is electrically connected to the output terminal of the second NOR gate, and the output terminal of the first XOR gate is electrically connected to the input terminal of the first inverter.
[0013] Furthermore, the second logic gate sub-circuit includes a second XOR gate and a second inverter, wherein an output terminal of the second XOR gate is electrically connected to the output terminal of the first NAND gate, an output terminal of the second XOR gate is electrically connected to the output terminal of the second NAND gate, and the output terminal of the second XOR gate is electrically connected to the input terminal of the second inverter.
[0014] Further, the switch component includes a first switch, a second switch and a third switch, wherein the first switch and the third switch are connected in series between the first latch component and the latch output end, the second switch is connected in series between the second latch component and the latch output end, the first control end of the first switch is electrically connected to the output end of the first XOR gate, the second control end of the first switch is electrically connected to the output end of the first inverter, the first control end of the second switch is electrically connected to the output end of the second XOR gate, the second control end of the second switch is electrically connected to the output end of the second inverter, the second control end of the third switch is electrically connected to the output end of the second XOR gate, and the first control end of the third switch is electrically connected to the output end of the second inverter.
[0015] Compared with the prior art, the latch for solving output failure provided by the present invention has at least the following beneficial effects:
[0016] By introducing two latch components (a first latch component and a second latch component) with different failure input signals, the latch can automatically switch to another latch component when one latch component fails, thereby solving the technical problem of latch output failure. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] This specification will be further described in the form of exemplary embodiments, which will be described in detail by the accompanying drawings. These embodiments are not restrictive, and in these embodiments, the same number represents the same structure, wherein:
[0018] Figure 1 It is a module schematic diagram of a latch for solving output failure according to some embodiments of this specification;
[0019] Figure 2 It is a circuit structure diagram of a latch for solving output failure according to some embodiments of this specification. DETAILED DESCRIPTION
[0020] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of this specification. For ordinary technicians in this field, this specification can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.
[0021] Figure 1 is a schematic diagram of a module of a latch for solving output failure according to some embodiments of this specification, such as Figure 1As shown, a latch for solving output failure may include a first input terminal, a second input terminal, a first latch component, a second latch component, a logic gate circuit, a switch component and a latch output terminal, wherein the first input terminal and the second input terminal are electrically connected to the two input terminals of the first latch component respectively, the first input terminal and the second input terminal are electrically connected to the two input terminals of the second latch component respectively, the output terminals of the first latch component and the second latch component are both electrically connected to the input terminal of the logic gate circuit, the switch component is electrically connected to the first latch component, the second latch component and the output terminal of the logic gate circuit, the latch output terminal is electrically connected to the switch component, the switch component is used to connect the latch output terminal and the first latch component and the second latch component according to the input signal of the first input terminal and the second input terminal. The failure input signal corresponding to the first latch component is different from the failure input signal corresponding to the second latch component. For example, when both inputs are 0, the output is invalid.
[0022] Specifically, by setting up logic gate circuits and switch components, the output end of the latch can be connected to the latch components with valid outputs in the first latch component and the second latch component, thereby achieving effective output of the latch, solving the problem of failure of the existing latch output.
[0023] Figure 2 is a schematic diagram of a circuit structure of a latch for solving output failure according to some embodiments of this specification, such as Figure 2 As shown, the first latch component is composed of a NOR gate, and the second latch component is composed of a NAND gate. Specifically, the first latch component includes a first NOR gate and a second NOR gate, the first input terminal IN1 is electrically connected to an input terminal of the first NOR gate and an input terminal of the second NOR gate, the other input terminal of the first NOR gate is electrically connected to the output terminal of the second NOR gate, and the other input terminal of the second NOR gate is electrically connected to the output terminal of the first NOR gate. The second latch component includes a first NAND gate and a second NAND gate, the first input terminal IN1 is electrically connected to an input terminal of the first NAND gate and an input terminal of the second NAND gate, the other input terminal of the first NAND gate is electrically connected to the output terminal of the second NAND gate, and the other input terminal of the second NAND gate is electrically connected to the output terminal of the first NAND gate.
[0024] Specifically, when the first input terminal IN1 and the second input terminal IN2 are both at low levels, the first latch component will maintain the current state unchanged, that is, the latch function. When the first input terminal IN1 and the second input terminal IN2 are both at high levels, the state of the first latch component is uncertain, that is, the output is invalid.
[0025] The working principle of the second latch component is similar to that of the first latch component, but the triggering condition is opposite. When the first input terminal IN1 and the second input terminal IN2 of the second latch component are both at a high level, the second latch component maintains the current state unchanged. When the first input terminal IN1 and the second input terminal IN2 are both at a low level, the state of the second latch component is also uncertain, that is, the output fails.
[0026] In some embodiments, the switch component is used to connect the latch output terminal and the second latch component when a low level is input to both the first input terminal IN1 and the second input terminal IN2, and the switch component is also used to connect the latch output terminal and the first latch component when at least one of the first input terminal IN1 and the second input terminal IN2 is input to a high level.
[0027] like Figure 2 As shown, the logic gate circuit includes a first logic gate subcircuit and a second logic gate subcircuit, wherein the input end of the first logic gate subcircuit is electrically connected to the output end of the first latch component, and the input end of the second logic gate subcircuit is electrically connected to the output end of the second latch component.
[0028] like Figure 2 As shown, the structures of the first logic gate subcircuit and the second logic gate subcircuit are consistent. The first logic gate subcircuit includes a first XOR gate X1 and a first inverter, wherein one input end of the first XOR gate X1 is electrically connected to the output end of the first NOR gate, the other input end of the first XOR gate X1 is electrically connected to the output end of the second NOR gate, and the output end of the first XOR gate is electrically connected to the input end of the first inverter. The second logic gate subcircuit includes a second XOR gate X2 and a second inverter, wherein one output end of the second XOR gate X2 is electrically connected to the output end of the first NAND gate, one output end of the second XOR gate X2 is electrically connected to the output end of the second NAND gate, and the output end of the second XOR gate X2 is electrically connected to the input end of the second inverter.
[0029] like Figure 2As shown, the switch component includes a first switch S1, a second switch S2 and a third switch S3, wherein the first switch S1 and the third switch S3 are connected in series between the first latch component and the latch output terminal OUT, the second switch S2 is connected in series between the second latch component and the latch output terminal, the first control terminal G of the first switch S1 is electrically connected to the output terminal of the first XOR gate X1, the second control terminal GB of the first switch S1 is electrically connected to the output terminal of the first inverter, the first control terminal G of the second switch S2 is electrically connected to the output terminal of the second XOR gate X2, the second control terminal GB of the second switch S2 is electrically connected to the output terminal of the second inverter, the second control terminal GB of the third switch S3 is electrically connected to the output terminal of the second XOR gate X2, and the first control terminal G of the third switch S3 is electrically connected to the output terminal of the second inverter. When the first control terminal G of the switch is 1, the switch is closed, and when the first control terminal G of the switch is 0, the switch is open. The second control terminal GB of the switch and the first control terminal G are mutually inverse signals, that is, when the first control terminal G of the switch is 0, the second control terminal GB of the switch is 1.
[0030] Specifically, Figure 2 The working process of a latch for solving output failure is shown as follows: when the inputs of the first input terminal IN1 and the second input terminal IN2 are 11 or 01 or 10, the output of the second latch component is valid, and the two outputs are different, then the output of the first XOR gate X1 is 1, the second switch S2 is closed, the third switch S3 is disconnected, and the latch output terminal OUT outputs the output of the second latch component; when the inputs of the first input terminal IN1 and the second input terminal IN2 are 00, the state of the second latch component is uncertain, that is, the output fails, the second switch S2 is disconnected, and the third switch S3 is closed. At this time, the output of the first latch component maintains the previous state, the first switch S1 is closed, and the latch output terminal OUT outputs the output of the first latch component.
[0031] Finally, it should be understood that the embodiments described in this specification are only used to illustrate the principles of the embodiments of this specification. Other variations may also fall within the scope of this specification. Therefore, as an example and not a limitation, alternative configurations of the embodiments of this specification may be considered consistent with the teachings of this specification. Accordingly, the embodiments of this specification are not limited to the embodiments explicitly introduced and described in this specification.
Claims
1. A latch for solving output failure, characterized in that: It includes a first input terminal, a second input terminal, a first latch component, a second latch component, a logic gate circuit, a switch component and a latch output terminal, wherein the first input terminal and the second input terminal are electrically connected to the two input terminals of the first latch component respectively, the first input terminal and the second input terminal are electrically connected to the two input terminals of the second latch component respectively, the output terminals of the first latch component and the second latch component are both electrically connected to the input terminal of the logic gate circuit, the switch component is electrically connected to the first latch component, the second latch component and the output terminal of the logic gate circuit, the latch output terminal is electrically connected to the switch component, and the switch component is used to connect the latch output terminal and the first latch component and the second latch component to output a valid latch component according to the input signals of the first input terminal and the second input terminal, and the failure input signal corresponding to the first latch component is different from the failure input signal corresponding to the second latch component.
2. A latch for solving output failure according to claim 1, characterized in that: The first latch component is composed of a NOR gate, and the second latch component is composed of a NAND gate.
3. A latch for solving output failure according to claim 2, characterized in that: The switch component is used to connect the latch output end and the second latch component when a low level is input to both the first input end and the second input end. The switch component is also used to connect the latch output end and the first latch component when a high level is input to at least one of the first input end and the second input end.
4. A latch for solving output failure according to claim 3, characterized in that: The logic gate circuit includes a first logic gate subcircuit and a second logic gate subcircuit, wherein the input end of the first logic gate subcircuit is electrically connected to the output end of the first latch component, and the input end of the second logic gate subcircuit is electrically connected to the output end of the second latch component.
5. A latch for solving output failure according to claim 4, characterized in that: The first latch component includes a first NOR gate and a second NOR gate, the first input end is electrically connected to an input end of the first NOR gate and an input end of the second NOR gate, the other input end of the first NOR gate is electrically connected to the output end of the second NOR gate, and the other input end of the second NOR gate is electrically connected to the output end of the first NOR gate.
6. A latch for solving output failure according to claim 5, characterized in that: The second latch component includes a first NAND gate and a second NAND gate, the first input end is electrically connected to an input end of the first NAND gate and an input end of the second NAND gate, the other input end of the first NAND gate is electrically connected to the output end of the second NAND gate, and the other input end of the second NAND gate is electrically connected to the output end of the first NAND gate.
7. A latch for solving output failure according to claim 6, characterized in that: The first logic gate sub-circuit and the second logic gate sub-circuit have the same structure.
8. A latch for solving output failure according to claim 7, characterized in that: The first logic gate sub-circuit includes a first XOR gate and a first inverter, wherein one input terminal of the first XOR gate is electrically connected to the output terminal of the first NOR gate, the other input terminal of the first XOR gate is electrically connected to the output terminal of the second NOR gate, and the output terminal of the first XOR gate is electrically connected to the input terminal of the first inverter.
9. A latch for solving output failure according to claim 8, characterized in that: The second logic gate sub-circuit includes a second XOR gate and a second inverter, wherein an output terminal of the second XOR gate is electrically connected to the output terminal of the first NAND gate, an output terminal of the second XOR gate is electrically connected to the output terminal of the second NAND gate, and the output terminal of the second XOR gate is electrically connected to the input terminal of the second inverter.
10. A latch for solving output failure problem according to claim 9, characterized in that: The switch component includes a first switch, a second switch and a third switch, wherein the first switch and the third switch are connected in series between the first latch component and the latch output end, the second switch is connected in series between the second latch component and the latch output end, the first control end of the first switch is electrically connected to the output end of the first XOR gate, the second control end of the first switch is electrically connected to the output end of the first inverter, the first control end of the second switch is electrically connected to the output end of the second XOR gate, the second control end of the second switch is electrically connected to the output end of the second inverter, the second control end of the third switch is electrically connected to the output end of the second XOR gate, and the first control end of the third switch is electrically connected to the output end of the second inverter.